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RF PLL Frequency Synthesizers Data Sheet ADF4110/ADF4111/ADF4112/ADF4113 Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
FEATURES
ADF4110: 550 MHz; ADF4111: 1.2 GHz; ADF4112: 3.0 GHz; ADF4113: 4.0 GHz 2.7 V to 5.5 V power supply Separate charge pump supply (VP) allows extended tuning voltage in 3 V systems Programmable dual-modulus prescaler 8/9, 16/17, 32/33, Programmable charge pump currents Programmable antibacklash pulse width 3-wire serial interface Analog and digital lock detect Hardware and software power-down mode
APPLICATIONS
Base stations for wireless radio (GSM, PCS, DCS, CDMA, WCDMA) Wireless handsets (GSM, PCS, DCS, CDMA, WCDMA) Wireless LANS Communications test equipment C AT V equipment GENERAL DESCRIPTION The ADF4110 family of frequency synthesizers can be used to implement local oscillators in the upconversion and downcon- version sections of wireless receivers and transmitters. They consist of a low noise digital PFD (phase frequency detector), a precision charge pump, a programmable reference divider, programmable A and B counters, and a dual-modulus prescaler (P/P + 1). The A (6-bit) and B (13-bit) counters, in conjunction with the dual-modulus prescaler (P/P + 1), implement an N divider (N = BP + A). In addition, the 14-bit reference counter (R counter) allows selectable REFIN frequencies at the PFD input. A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and voltage controlled oscillator (VCO). Control of all the on-chip registers is via a simple 3-wire interface. The devices operate with a power supply ranging from 2.7 V to 5.5 V and can be powered down when not in use. FUNCTIONAL BLOCK DIAGRAM N = BP + A FUNCTION LATCH PRESCALER P/P +1 13-BIT B COUNTER 6-BIT A COUNTER 14-BIT R COUNTER 24-BIT INPUT REGISTER R COUNTER LATCH A, B COUNTER LATCH PHASE FREQUENCY DETECTOR AVDD SDOUT SDOUT FROM FUNCTION LATCH DGNDAGNDCE RFINA RFINB LE DATA CLK REFIN CPGNDVPDVDDAVDD LOCK DETECT ADF4110/ADF4111 ADF4112/ADF41136 LOAD LOAD REFERENCE CHARGE PUMP M3 M2 M1 HIGH Z MUX MUXOUT CP RSET CURRENT SETTING 2 CPI3 CPI2 CPI1 CPI6 CPI5 CPI4 CURRENT SETTING 1 03496-0-001 Figure 1. Functional Block Diagram
ADF4110/ADF4111/ADF4112/ADF4113 Data Sheet Rev. F | Page 2 of 28 TABLE OF CONTENTS
REVISION HISTORY
1/13—Rev. E to Rev. F 8/12—Rev. D to Rev. E 5/12—Rev. C to Rev. D 3/04—Data sheet changed from Rev. B to Rev. C. 3/03—Data sheet changed from Rev. A to Rev. B. 1/01—Data sheet changed from Rev. 0 to Rev. A. Changes to DC Specifications in B Version, B Chips, Addition of New Material
Data Sheet ADF4110/ADF4111/ADF4112/ADF4113 Rev. F | Page 3 of 28 SPECIFICATIONS AVDD = DVDD = 3 V ± 10%, 5 V ± 10%; AVDD ≤VP ≤ 6.0 V; AGND = DGND = CPGND = 0 V; RSET = 4.7 kΩ; dBm referred to 50 Ω; TA = TMIN to TMAX, unless otherwise noted. Operating temperature range is as follows: B Version: −40°C to +85°C. Table 1. Parameter B Version B Chips1 Unit Test Conditions/Comments RF CHARACTERISTICS (3 V) See Figure 29 for input circuit. RF Input Sensitivity −15/0 −15/0 dBm min/max RF Input Frequency ADF4110 80/550 80/550 MHz min/max For lower frequencies, ensure slew rate (SR) > 30 V/µs. ADF4110 50/550 50/550 MHz min/max Input level = −10 dBm. ensure SR > 130 V/µs. Maximum Allowable Prescaler Output Frequency2 165 165 MHz max RF CHARACTERISTICS (5 V) RF Input Sensitivity −10/0 −10/0 dBm min/max RF Input Frequency ADF4110 80/550 80/550 MHz min/max For lower frequencies, ensure SR > 50 V/µs. Maximum Allowable Prescaler Output Frequency 2 200 200 MHz max REFIN CHARACTERISTICS REFIN Input Frequency 5/104 5/104 MHz min/max For f < 5 MHz, ensure SR > 100 V/µs. 3.0/AVDD 3.0/AVDD V p-p min/max AVDD = 5 V, biased at AVDD/2. See Note 3. REFIN Input Capacitance 10 10 pF max REFIN Input Current ±100 ±100 µA max PHASE DETECTOR FREQUENCY4 55 55 MHz max CHARGE PUMP ICP Sink/Source Programmable (see Table 9). High Value 5 5 mA typ With RSET = 4.7 kΩ. Low Value 625 625 µA typ Absolute Accuracy 2.5 2.5 % typ With RSET = 4.7 kΩ. RSET Range 2.7/10 2.7/10 kΩ typ See Table 9. ICP 3-State Leakage Current 1 1 nA typ Sink and Source Current Matching 2 2 % typ 0.5 V ≤ VCP ≤ VP – 0.5 V. ICP vs. Temperature 2 2 % typ VCP = VP/2. LOGIC INPUTS VINH, Input High Voltage 0.8 × DVDD 0.8 × DVDD V min VINL, Input Low Voltage 0.2 × DVDD 0.2 × DVDD V max IINH/IINL, Input Current ±1 ±1 µA max CIN, Input Capacitance 10 10 pF max LOGIC OUTPUTS VOH, Output High Voltage DVDD – 0.4 DVDD – 0.4 V min IOH = 500 µA. VOL, Output Low Voltage 0.4 0.4 V max IOL = 500 µA.
ADF4110/ADF4111/ADF4112/ADF4113 Data Sheet Rev. F | Page 4 of 28 Parameter B Version B Chips1 Unit Test Conditions/Comments POWER SUPPLIES AVDD 2.7/5.5 2.7/5.5 V min/V max DVDD AVDD AVDD IDD5 (AIDD + DIDD) ADF4110 5.5 4.5 mA max 4.5 mA typical. ADF4111 5.5 4.5 mA max 4.5 mA typical. ADF4112 7.5 6.5 mA max 6.5 mA typical. ADF4113 11 8.5 mA max 8.5 mA typical. IP 0.5 0.5 mA max TA = 25°C. Low Power Sleep Mode 1 1 µA typ NOISE CHARACTERISTICS ADF4113 Normalized Phase Noise Floor6 −215 −215 dBc/Hz typ Phase Noise Performance7 @ VCO output. ADF4110: 540 MHz Output8 −91 −91 dBc/Hz typ @ 1 kHz offset and 200 kHz PFD frequency. ADF4111: 900 MHz Output9 −87 −87 dBc/Hz typ @ 1 kHz offset and 200 kHz PFD frequency. ADF4112: 900 MHz Output9 −90 −90 dBc/Hz typ @ 1 kHz offset and 200 kHz PFD frequency. ADF4113: 900 MHz Output9 −91 −91 dBc/Hz typ @ 1 kHz offset and 200 kHz PFD frequency. ADF4111: 836 MHz Output10 −78 −78 dBc/Hz typ @ 300 Hz offset and 30 kHz PFD frequency. ADF4112: 1750 MHz Output11 −86 −86 dBc/Hz typ @ 1 kHz offset and 200 kHz PFD frequency. ADF4112: 1750 MHz Output12 −66 −66 dBc/Hz typ @ 200 Hz offset and 10 kHz PFD frequency. ADF4112: 1960 MHz Output13 −84 −84 dBc/Hz typ @ 1 kHz offset and 200 kHz PFD frequency. ADF4113: 1960 MHz Output13 −85 −85 dBc/Hz typ @ 1 kHz offset and 200 kHz PFD frequency. ADF4113: 3100 MHz Output14 −86 −86 dBc/Hz typ @ 1 kHz offset and 1 MHz PFD frequency. Spurious Signals ADF4110: 540 MHz Output9 −97/−106 −97/−106 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD frequency. ADF4111: 900 MHz Output9 −98/−110 −98/−110 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD frequency. ADF4112: 900 MHz Output9 −91/−100 −91/−100 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD frequency. ADF4113: 900 MHz Output9 −100/−110 −100/−110 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD frequency. ADF4111: 836 MHz Output10 −81/−84 −81/−84 dBc typ @ 30 kHz/60 kHz and 30 kHz PFD frequency. ADF4112: 1750 MHz Output11 −88/−90 −88/−90 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD frequency. ADF4112: 1750 MHz Output12 −65/−73 −65/−73 dBc typ @ 10 kHz/20 kHz and 10 kHz PFD frequency. ADF4112: 1960 MHz Output13 −80/−84 −80/−84 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD frequency. ADF4113: 1960 MHz Output13 −80/−84 −80/−84 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD frequency. ADF4113: 3100 MHz Output14 −80/−82 −82/−82 dBc typ @ 1 MHz/2 MHz and 1 MHz PFD frequency. 1The B chip specifications are given as typical values. 2This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that is less than this value. 3AC coupling ensures AVDD/2 bias. See Figure 33 for a typical circuit. 4Guaranteed by design. 5 TA = 25°C; AVDD = DVDD = 3 V; P = 16; SYNC = 0; DLY = 0; RFIN for ADF4110 = 540 MHz; RFIN for ADF4111, ADF4112, ADF4113 = 900 MHz. 6 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO, PNTOT, and subtracting 20logN (where N is the N divider value) and 10logFPFD: PNSYNTH = PNTOT – 10logFPFD – 20logN. 7 The phase noise is measured with the EV-ADF411XSD1Z evaluation board and the HP8562E spectrum analyzer. The spectrum analyzer provides the REFIN for the synthesizer (fREFOUT = 10 MHz @ 0 dBm). SYNC = 0; DLY = 0 (Table 7). 8 fREFIN = 10 MHz; fPFD = 200 kHz; offset frequency = 1 kHz; fRF = 540 MHz; N = 2700; loop B/W = 20 kHz. 9 fREFIN = 10 MHz; fPFD = 200 kHz; offset frequency = 1 kHz; fRF = 900 MHz; N = 4500; loop B/W = 20 kHz. 10 fREFIN = 10 MHz; fPFD = 30 kHz; offset frequency = 300 Hz; fRF = 836 MHz; N = 27867; loop B/W = 3 kHz. 11 fREFIN = 10 MHz; fPFD = 200 kHz; offset frequency = 1 kHz; fRF = 1750 MHz; N = 8750; loop B/W = 20 kHz 12 fREFIN = 10 MHz; fPFD = 10 kHz; offset frequency = 200 Hz; fRF = 1750 MHz; N = 175000; loop B/W = 1 kHz. 13 fREFIN = 10 MHz; fPFD = 200 kHz; offset frequency = 1 kHz; fRF = 1960 MHz; N = 9800; loop B/W = 20 kHz. 14 fREFIN = 10 MHz; fPFD = 1 MHz; offset frequency = 1 kHz; fRF = 3100 MHz; N = 3100; loop B/W = 20 kHz.
AGND = DGND = CPGND = 0 V; RSET = 4.7 kΩ; TA = TMIN to TMAX, unless otherwise noted. Figure 2. Timing Diagram
ADF4110/ADF4111/ADF4112/ADF4113 Data Sheet Rev. F | Page 6 of 28 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted Table 3. Parameter Rating AVDD to GND1 −0.3 V to +7 V AVDD to DVDD −0.3 V to +0.3 V VP to GND −0.3 V to +7 V VP to AVDD −0.3 V to +5.5 V Digital I/O Voltage to GND −0.3 V to VDD + 0.3 V Analog I/O Voltage to GND −0.3 V to VP + 0.3 V REFIN, RFINA, RFINB to GND −0.3 V to VDD + 0.3 V RFINA to RFINB ±320 mV Operating Temperature Range Industrial (B Version) −40°C to +85°C Storage Temperature Range −65°C to +150°C Maximum Junction Temperature 150°C TSSOP θJA Thermal Impedance 150.4°C/W LFCSP θJA Thermal Impedance (Paddle Soldered) 122°C/W LFCSP θJA Thermal Impedance (Paddle Not Soldered) 216°C/W Lead Temperature, Soldering Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C 1 GND = AGND = DGND = 0 V. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. This device is a high performance RF integrated circuit with an ESD rating of <2 kV, and it is ESD sensitive. Proper precautions should be taken for handling and assembly. TRANSISTOR COUNT 6425 (CMOS) and 303 (Bipolar). ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
- THE EXPOSED PADDLE SHOULD BE CONNECTED TO AGND.
15 MUXOUT
Figure 3. TSSOP Pin Configuration Figure 4. LFCSP Pin Configuration Table 4. Pin Function Descriptions 1 19 RSET Connecting a resistor between this pin and CPGND sets the maximum charge pump output current. So, with RSET = 4.7 kΩ, ICPmax = 5 mA. 3 1 CPGND Charge Pump Ground. This is the ground return path for the charge pump. 4 2, 3 AGND Analog Ground. This is the ground return path of the prescaler. a small bypass capacitor, typically 100 pF. See Figure 29. 6 5 RFINA Input to the RF Prescaler. This small-signal input is ac-coupled from the VCO. plane should be placed as close as possible to this pin. AVDD must be the same value as DVDD. 9 9, 10 DGND Digital Ground. input is a high impedance CMOS input. one of the four latches; the latch is selected using the control bits. frequency to be accessed externally. plane should be placed as close as possible to this pin. DVDD must be the same value as AVDD. EPAD Exposed Pad (LFCSP Only). The exposed paddle should be connected to AGND.
Table 6. ADF4110 Family Latch Summary
Table 7. Reference Counter Latch Map 15ns MUST OCCUR BEFORE LOCK DETECT IS SET. 15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
Table 8. AB Counter Latch Map OF (NX FREF), AT THE OUTPUT, NMIN IS (P2–P).
Table 9. Function Latch Map
Table 10. Initialization Latch Map
Data Sheet ADF4110/ADF4111/ADF4112/ADF4113 Rev. F | Page 19 of 28 FUNCTION LATCH The on-chip function latch is programmed with C2, C1 set to 1. Table 9 shows the input data format for programming the function latch. Counter Reset DB2 (F1) is the counter reset bit. When DB2 is 1, the R counter and the AB counters are reset. For normal operation, this bit should be 0. Upon powering up, the F1 bit must be disabled, and the N counter resumes counting in “close” alignment with the R counter. (The maximum error is one prescaler cycle.) Power-Down DB3 (PD1) and DB21 (PD2) on the ADF411x provide program-mable power-down modes. They are enabled by the CE pin. When the CE pin is low, the device is immediately disabled regardless of the states of PD2, PD1. In the programmed asynchronous power-down, the device powers down immediately after latching a 1 into Bit PD1, provided PD2 has been loaded with a 0. In the programmed synchronous power-down, the device power-down is gated by the charge pump to prevent unwanted frequency jumps. Once power-down is enabled by writing a 1 into Bit PD1 (provided a 1 has also been loaded to PD2), the device goes into power-down on the next charge pump event. When a power-down is activated (either synchronous or asynchronous mode including CE pin activated power-down), the following events occur:
- All active dc current paths are removed.
- The R, N, and timeout counters are forced to their load state conditions.
- The charge pump is forced into three-state mode.
- The digital clock detect circuitry is reset.
- The RFIN input is debiased.
- The reference input buffer circuitry is disabled.
- The input register remains active and capable of loading and latching data. MUXOUT Control The on-chip multiplexer is controlled by M3, M2, and M1 on the ADF4110 family. Table 9 shows the truth table. Fastlock Enable Bit DB9 of the function latch is the fastlock enable bit. Fastlock is enables only when this is 1. Fastlock Mode Bit DB10 of the function latch is the fastlock enable bit. When fastlock is enabled, this bit determines which fastlock mode is used. If the fastlock mode bit is 0, fastlock mode 1 is selected; if the fastlock mode bit is 1, fastlock mode 2 is selected. Fastlock Mode 1 The charge pump current is switched to the contents of Current Setting 2. The device enters fastlock by having a 1 written to the CP gain bit in the AB counter latch. The device exits fastlock by having a 0 written to the CP gain bit in the AB counter latch. Fastlock Mode 2 The charge pump current is switched to the contents of Current Setting 2. The device enters fastlock by having a 1 written to the CP gain bit in the AB counter latch. The device exits fastlock under the control of the timer counter. After the timeout period determined by the value in TC4 through TC1, the CP gain bit in the AB counter latch is automatically reset to 0 and the device reverts to normal mode instead of fastlock. See Table 9 for the timeout periods. Timer Counter Control The user has the option of programming two charge pump cur- rents. Current Setting 1 is meant to be used when the RF output is stable and the system is in a static state. Current Setting 2 is meant to be used when the system is dynamic and in a state of change (i.e., when a new output frequency is programmed). The normal sequence of events is as follows: The user initially decides what the preferred charge pump currents are going to be. For example, they may choose 2.5 mA as Current Setting 1 and 5 mA as Current Setting 2. At the same time, they must also decide how long they want the secondary current to stay active before reverting to the primary current. This is controlled by the timer counter control bits, DB14 through DB11 (TC4 through TC1) in the function latch. The truth table is given in Table 10. A user can program a new output frequency simply by pro- gramming the AB counter latch with new values for A and B. At the same time, the CP gain bit can be set to 1, which sets the charge pump with the value in CPI6–CPI4 for a period deter- mined by TC4 through TC1. When this time is up, the charge pump current reverts to the value set by CPI3–CPI1. At the same time, the CP gain bit in the AB counter latch is reset to 0 and is ready for the next time the user wishes to change the frequency.
ADF4110/ADF4111/ADF4112/ADF4113 Data Sheet Rev. F | Page 20 of 28 Note that there is an enable feature on the timer counter. It is enabled when Fastlock Mode 2 is chosen by setting the fastlock mode bit (DB10) in the function latch to 1. Charge Pump Currents CPI3, CPI2, and CPI1 program Current Setting 1 for the charge pump. CPI6, CPI5, and CPI4 program Current Setting 2 for the charge pump. The truth table is given in Table 10. Prescaler Value P2 and P1 in the function latch set the prescaler values. The prescaler value should be chosen so that the prescaler output frequency is always less than or equal to 200 MHz. Thus, with an RF frequency of 2 GHz, a prescaler value of 16/17 is valid but a value of 8/9 is not. PD Polarity This bit sets the phase detector polarity bit. See Table 10. CP Three-State This bit controls the CP output pin. With the bit set high, the CP output is put into three-state. With the bit set low, the CP output is enabled. INITIALIZATION LATCH When C2, C1 = 1, 1, the initialization latch is programmed. This is essentially the same as the function latch (programmed when C2, C1 = 1, 0). However, when the initialization latch is programmed, an addi- tional internal reset pulse is applied to the R and AB counters. This pulse ensures that the AB counter is at load point when the AB counter data is latched, and the device begins counting in close phase alignment. If the latch is programmed for synchronous power-down (CE pin high; PD1 bit high; PD2 bit low), the internal pulse also triggers this power-down. The prescaler reference and the oscillator input buffer are unaffected by the internal reset pulse, so close phase alignment is maintained when counting resumes. When the first AB counter data is latched after initialization, the internal reset pulse is again activated. However, successive AB counter loads after this will not trigger the internal reset pulse. DEVICE PROGRAMMING AFTER INITIAL POWER-UP After initial power-up of the device, there are three ways to program the device. Initialization Latch Method Apply VDD. Program the initialization latch (11 in 2 LSBs of input word). Make sure the F1 bit is programmed to 0. Then, do an R load (00 in 2 LSBs). Then do an AB load (01 in 2 LSBs). When the initialization latch is loaded, the following occurs: 1. The function latch contents are loaded. 2. An internal pulse resets the R, A, B, and timeout counters to load state conditions and three-states the charge pump. Note that the prescaler band gap reference and the oscil- lator input buffer are unaffected by the internal reset pulse, allowing close phase alignment when counting resumes. 3. Latching the first AB counter data after the initialization word activates the same internal reset pulse. Successive AB loads do not trigger the internal reset pulse unless there is another initialization. CE Pin Method 1. Apply VDD. 2. Bring CE low to put the device into power-down. This is an asynchronous power-down in that it happens immediately. 3. Program the function latch (10). Program the R counter latch (00). Program the AB counter latch (01). 4. Bring CE high to take the device out of power-down. The R and AB counters now resume counting in close alignment. After CE goes high, a duration of 1 µs may be required for the prescaler band gap voltage and oscillator input buffer bias to reach steady state. CE can be used to power the device up and down in order to check for channel activity. The input register does not need to be reprogrammed each time the device is disabled and enabled as long as it has been programmed at least once after V DD was initially applied. Counter Reset Method 1. Apply VDD. 2. Do a function latch load (10 in 2 LSBs). As part of this, load 1 to the F1 bit. This enables the counter reset. 3. Do an R counter load (00 in 2 LSBs). Do an AB counter load (01 in 2 LSBs). Do a function latch load (10 in 2 LSBs). As part of this, load 0 to the F1 bit. This disables the counter reset. This sequence provides the same close alignment as the initiali- zation method. It offers direct control over the internal reset. Note that counter reset holds the counters at load point and three states the charge pump but does not trigger synchronous power-down. The counter reset method requires an extra function latch load compared to the initialization latch method.
Data Sheet ADF4110/ADF4111/ADF4112/ADF4113 Rev. F | Page 21 of 28 RESYNCHRONIZING THE PRESCALER OUTPUT Table 7 (the Reference Counter Latch Map) shows two bits, DB22 and DB21, which are labeled DLY and SYNC, respectively. These bits affect the operation of the prescaler. With SYNC = 1, the prescaler output is resynchronized with the RF input. This has the effect of reducing jitter due to the prescaler and can lead to an overall improvement in synthesizer phase noise performance. Typically, a 1 dB to 2 dB improvement is seen in the ADF4113. The lower bandwidth devices can show an even greater improvement. For example, the ADF4110 phase noise is typically improved by 3 dB when SYNC is enabled. With DLY = 1, the prescaler output is resynchronized with a delayed version of the RF input. If the SYNC feature is used on the synthesizer, some care must be taken. At some point, (at certain temperatures and output frequencies), the delay through the prescaler coincides with the active edge on RF input; this causes the SYNC feature to break down. It is important to be aware of this when using the SYNC feature. Adding a delay to the RF signal, by programming DLY = 1, extends the operating frequency and temperature somewhat. Using the SYNC feature also increases the value of the AI DD for the device. With a 900 MHz output, the ADF4113 AIDD increases by about 1.3 mA when SYNC is enabled and by an additional 0.3 mA if DLY is enabled. All the typical performance plots in this data sheet, except for Figure 8, apply for DLY and SYNC = 0, i.e., no resynchroniza- tion or delay enabled.
tion available from ADI to implement this solution. temperature) from this portion of the signal chain. channel spacing and an output center frequency of 1960 MHz. The target application is a WCDMA base station transmitter. The LO port of the AD8346 is driven in single-ended fashion. is driven through the ac coupling capacitor from a 50 Ω source. An LO drive level of between −6 dBm and −12 dBm is required. The circuit of Figure 37 gives a typical level of −8 dBm. ARE OMITTED FROM DIAGRAM TO INCREASE CLARITY. Figure 37. Direct Conversion Transmitter Solution
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-1.
0.02 NOM
0.20 REF
0.20 MIN
Figure 40. 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] Figure 41. 16-Lead Thin Shrink Small Outline Package [TSSOP]
ADF4110/ADF4111/ADF4112/ADF4113 Data Sheet Rev. F | Page 28 of 28 ORDERING GUIDE Model1 Temperature Range Package Description Package Option2 ADF4110BCPZ –40°C to +85°C 20-Lead Frame Chip Scale Package [LFCSP_WQ] CP-20-6 ADF4110BCPZ-RL –40°C to +85°C 20-Lead Frame Chip Scale Package [LFCSP_WQ] CP-20-6 ADF4110BCPZ-RL7 –40°C to +85°C 20-Lead Frame Chip Scale Package [LFCSP_WQ] CP-20-6 ADF4110BRU –40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 ADF4110BRU-REEL –40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 ADF4110BRU-REEL7 -40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 ADF4110BRUZ –40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 ADF4110BRUZ-RL –40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 ADF4110BRUZ-RL7 –40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 ADF4111BCPZ –40°C to +85°C 20-Lead Frame Chip Scale Package [LFCSP_WQ] CP-20-6 ADF4111BCPZ-RL –40°C to +85°C 20-Lead Frame Chip Scale Package [LFCSP_WQ] CP-20-6 ADF4111BCPZ-RL7 –40°C to +85°C 20-Lead Frame Chip Scale Package [LFCSP_WQ] CP-20-6 ADF4111BRU –40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 ADF4111BRUZ –40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 ADF4111BRUZ-RL –40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 ADF4111BRUZ-RL7 –40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 ADF4112BCPZ –40°C to +85°C 20-Lead Frame Chip Scale Package [LFCSP_WQ] CP-20-6 ADF4112BCPZ-RL –40°C to +85°C 20-Lead Frame Chip Scale Package [LFCSP_WQ] CP-20-6 ADF4112BCPZ-RL7 –40°C to +85°C 20-Lead Frame Chip Scale Package [LFCSP_WQ] CP-20-6 ADF4112BRU –40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 ADF4112BRU-REEL7 –40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 ADF4112BRUZ –40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 ADF4112BRUZ-REEL –40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 ADF4112BRUZ-REEL7 –40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 ADF4113BCPZ –40°C to +85°C 20-Lead Frame Chip Scale Package [LFCSP_WQ] CP-20-6 ADF4113BCPZ-RL –40°C to +85°C 20-Lead Frame Chip Scale Package [LFCSP_WQ] CP-20-6 ADF4113BCPZ-RL7 –40°C to +85°C 20-Lead Frame Chip Scale Package [LFCSP_WQ] CP-20-6 ADF4113BRU –40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 ADF4113BRU-REEL7 –40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 ADF4113BRUZ –40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 ADF4113BRUZ-REEL –40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 ADF4113BRUZ-REEL7 –40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 ADF4113BCHIPS –40°C to +85°C DIE EVAL-ADF4113EBZ1 Evaluation Board EVAL-ADF4113EBZ2 Evaluation Board EV-ADF411XSD1Z Evaluation Board 1 Z = RoHS Compliant Part. 2 CP-20-6 package was formerly CP-20-1 package. Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. ©2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03496-0-1/13(F)