ADF4107BCPZ-REEL7

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Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2003–2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

7.0 GHz bandwidth

2.7 V to 3.3 V power supply Separate charge pump supply (VP) allows extended tuning voltage in 3 V systems Programmable dual-modulus prescaler Programmable charge pump currents Programmable antibacklash pulse width 3-wire serial interface Analog and digital lock detect Hardware and software power-down mode

APPLICATIONS

Base stations for wireless radio GENERAL DESCRIPTION The ADF4107 frequency synthesizer can be used to implement local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. It consists of a low noise digital PFD (phase frequency detector), a precision charge pump, a programmable reference divider, programmable A and B counters, and a dual-modulus prescaler (P/P + 1). The A (6-bit) and B (13-bit) counters, in conjunction with the dual-modulus prescaler (P/P + 1), implement an N divider (N = BP + A). In addition, the 14-bit reference counter (R counter), allows selectable REFIN frequencies at the PFD input. A complete PLL (phase-locked loop) can be implemented if the synthesizer is used with an external loop filter and VCO (voltage controlled oscillator). Its very high bandwidth means that frequency doublers can be eliminated in many high frequency systems, simplifying system architecture and reducing cost. FUNCTIONAL BLOCK DIAGRAM 03338-001 CLK DATA LE REFIN RFINA RFINB 24-BIT INPUT REGISTER SDOUT AVDD DVDD CE AGND DGND 14-BIT R COUNTER R COUNTER LATCH FUNCTION LATCH A, B COUNTER LATCHFROM FUNCTION LATCH PRESCALER P/P + 1 N = BP + A LOAD LOAD 13-BIT B COUNTER 6-BIT A COUNTER M3 M2 M1 MUX SDOUT AVDD HIGH Z MUXOUT CPGND RSETVP CP PHASE FREQUENCY DETECTOR LOCK DETECT REFERENCE CHARGE PUMP CURRENT SETTING 1 ADF4107 CPI3 CPI2 CPI1 CPI6 CPI5 CPI4 CURRENT SETTING 2 Figure 1.

Rev. D | Page 2 of 20 TABLE OF CONTENTS

REVISION HISTORY

3/13—Rev. C to Rev. D Changed RFINA to RFINB Parameter from ±320 mV to ±600 mV , 11/12—Rev. B to Rev. C 9/11—Rev. A to Rev. B Changes to Normalized Phase Noise Floor (PNSYNTH) Parameter, Added Normalized 1/f Noise (PN1_f) Parameter and Endnote 11, 4/07—Rev. 0 to Rev. A 5/03—Revision 0: Initial Version

Rev. D | Page 3 of 20 SPECIFICATIONS AVDD = DVDD = 3 V ± 10%, AVDD ≤ VP ≤ 5.5 V , AGND = DGND = CPGND = 0 V , RSET = 5.1 kΩ, dBm referred to 50 Ω, TA = TMAX to TMIN, unless otherwise noted. Table 1. Parameter B Version1 B Chips2 (Typ) Unit Test Conditions/Comments RF CHARACTERISTICS RF Input Frequency (RFIN)3 1.0/7.0 1.0/7.0 GHz min/max See Figure 18 for input circuit RF Input Sensitivity –5/+5 –5/+5 dBm min/max Maximum Allowable Prescaler Output Frequency4 300 300 MHz max REFIN CHARACTERISTICS REFIN Input Frequency 20/250 20/250 MHz min/max For f < 20 MHz, ensure slew rate >50 V/µs REFIN Input Sensitivity5 0.8/VDD 0.8/VDD V p-p min/max Biased at AVDD/26 REFIN Input Capacitance 10 10 pF max REFIN Input Current ±100 ±100 µA max PHASE DETECTOR Phase Detector Frequency7 104 104 MHz max ABP = 0,0 (2.9 ns antibacklash pulse width) CHARGE PUMP Programmable; see Figure 25 ICP Sink/Source High Value 5 5 mA typ With RSET = 5.1 kΩ Low Value 625 625 µA typ Absolute Accuracy 2.5 2.5 % typ With RSET = 5.1 kΩ RSET Range 3.0 to 11 3.0 to 11 kΩ typ See Figure 25 ICP Three-State Leakage 1 1 nA typ Sink and Source Current Matching 2 2 % typ 0.5 V ≤ VCP ≤ VP − 0.5 V ICP vs. Temperature 2 2 % typ VCP = VP/2 LOGIC INPUTS VIH, Input High Voltage 1.4 1.4 V min VIL, Input Low Voltage 0.6 0.6 V max IINH, IINL, Input Current ±1 ±1 µA max CIN, Input Capacitance 10 10 pF max LOGIC OUTPUTS VOH, Output High Voltage 1.4 1.4 V min Open-drain output chosen; 1 kΩ pull-up resistor to 1.8 V VOH, Output High Voltage VDD − 0.4 VDD − 0.4 V min CMOS output chosen IOH 100 100 µA max VOL, Output Low Voltage 0.4 0.4 V max IOL = 500 µA POWER SUPPLIES AVDD 2.7/3.3 2.7/3.3 V min/V max DVDD AVDD AVDD VP AVDD/5.5 AVDD/5.5 V min/V max AVDD ≤ VP ≤ 5.5 V IDD8 (AIDD + DIDD) 17 15 mA max 15 mA typ IP 0.4 0.4 mA max TA = 25°C Power-Down Mode9 (AIDD + DIDD) 10 10 µA typ NOISE CHARACTERISTICS Normalized Phase Noise Floor (PNSYNTH)10 −223 −223 dBc/Hz typ PLL loop BW = 500 kHz, measured at 100 kHz offset Normalized 1/f Noise (PN1_f)11 −122 −122 dBc/Hz typ 10 kHz offset; normalized to 1 GHz

900 MHz Output13 −93 −93 dBc/Hz typ @ 1 kHz offset and 200 kHz PFD frequency

6400 MHz Output14 −76 −76 dBc/Hz typ @ 1 kHz offset and 200 kHz PFD frequency

6400 MHz Output15 −83 −83 dBc/Hz typ @ 1 kHz offset and 1 MHz PFD frequency

900 MHz Output13 −90/−92 −90/−92 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD

6400 MHz Output14 −65/−70 −65/−70 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD

6400 MHz Output15 −70/−75 −70/−75 dBc typ @ 1 MHz/2 MHz and 1 MHz PFD frequency

1 Operating temperature range (B version) is −40°C to +85°C. 2 The B chip specifications are given as typical values. 3 Use a square wave for lower frequencies, below the minimum stated. 6 AC-coupling ensures AVDD/2 bias. 7 Guaranteed by design. Sample tested to ensure compliance. and 10 log(FPFD). PNSYNTH = PNTOT – 20 logN −10 logFPFD. synthesizer (fREFOUT = 10 MHz @ 0 dBm). 13 fREFIN = 10 MHz; fPFD = 200 kHz; offset frequency = 1 kHz; fRF = 900 MHz; N = 4500; loop BW = 20 kHz. 14 fREFIN = 10 MHz; fPFD = 200 kHz; offset frequency = 1 kHz; fRF = 6400 MHz; N = 32,000; loop BW = 20 kHz. 15 fREFIN = 10 MHz; fPFD = 1 MHz; offset frequency = 1 kHz; fRF = 6400 MHz; N = 6400; loop BW = 100 kHz. 1 Guaranteed by design but not production tested. 2 Operating temperature range (B Version) is −40°C to +85°C. Figure 2. Timing Diagram

Rev. D | Page 5 of 20 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter Rating AVDD to GND1 −0.3 V to +3.6 V AVDD to DVDD −0.3 V to +0.3 V VP to GND −0.3 V to +5.8 V VP to AVDD −0.3 V to +5.8 V Digital I/O Voltage to GND −0.3 V to VDD + 0.3 V Analog I/O Voltage to GND −0.3 V to Vp + 0.3 V REFIN, RFINA, RFINB to GND −0.3 V to VDD + 0.3 V RFINA to RFINB ±600 mV Operating Temperature Range Industrial (B Version) −40°C to +85°C Storage Temperature Range −65°C to +125°C Maximum Junction Temperature 150°C TSSOP θJA Thermal Impedance 112°C/W LFCSP θJA Thermal Impedance (Paddle Soldered) 30.4°C/W Reflow Soldering Peak Temperature 260°C Time at Peak Temperature 40 sec Transistor Count CMOS 6425 Bipolar 303 1 GND = AGND = DGND = 0 V. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. This device is a high performance RF integrated circuit with an ESD rating of <2 kV , and it is ESD sensitive. Proper precautions should be taken for handling and assembly. ESD CAUTION

1. TRANSISTOR COUNT 6425 (CMOS),

Figure 3. Pin Configuration, TSSOP

15 MUXOUT

1. TRANSISTOR COUNT 6425 (CMOS),

Figure 4. Pin Configuration, LFCSP Table 4. Pin Function Descriptions so, with RSET = 5.1 kΩ, ICP MAX = 5 mA. 3 1 CPGND Charge Pump Ground. This is the ground return path for the charge pump. 4 2, 3 AGND Analog Ground. This is the ground return path of the prescaler. bypass capacitor, typically 100 pF. See Figure 18. 6 5 RFINA Input to the RF Prescaler. This small signal input is ac-coupled to the external VCO. DD must be the same value as DVDD. 9 9, 10 DGND Digital Ground. state mode. Taking the pin high powers up the device, depending on the status of the power-down bit, F2. into the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input. the four latches, the latch being selected using the control bits. plane should be placed as close as possible to this pin. DVDD must be the same value as AVDD. can be set to 5 V and used to drive a VCO with a tuning range of up to 5 V. EP Exposed Pad. The exposed pad must be connected to AGND.

Figure 22. Latch Summary

15ns MUST OCCUR BEFORE LOCK DETECT IS SET. 15ns MUST OCCUR BEFORE LOCK DETECT IS SET. Figure 23. Reference Counter Latch Map

SETTING 1 IS PERMANENTLY USED. SETTING 2 IS PERMANENTLY USED. Figure 24. AB Counter Latch Map

0 X X

1 X 0

Figure 25. Function Latch Map

Figure 26. Initialization Latch Map

Rev. D | Page 16 of 20 FUNCTION LATCH The on-chip function latch is programmed with C2 and C1 set to 1 and 0, respectively. Figure 25 shows the input data format for programming the function latch. Counter Reset DB2 (F1) is the counter reset bit. When this bit is 1, the R counter and the AB counters are reset. For normal operation, this bit should be 0. Upon powering up, the F1 bit needs to be disabled (set to 0). Then, the N counter resumes counting in close alignment with the R counter. (The maximum error is one prescaler cycle). Power-Down DB3 (PD1) and DB21 (PD2) provide programmable power- down modes. They are enabled by the CE pin. When the CE pin is low, the device is immediately disabled regardless of the states of PD2 and PD1. In the programmed asynchronous power-down, the device powers down immediately after latching a 1 into the PD1 bit, with the condition that PD2 has been loaded with a 0. In the programmed synchronous power-down, the device power-down is gated by the charge pump to prevent unwanted frequency jumps. Once the power-down is enabled by writing a 1 into PD1 (on condition that a 1 has also been loaded to PD2), then the device goes into power-down on the occurrence of the next charge pump event. When a power-down is activated (either in synchronous or asynchronous mode, including CE pin-activated power-down), the following events occur:

• All active dc current paths are removed.
• The R, N, and timeout counters are forced to their load state conditions.
• The charge pump is forced into three-state mode.
• The digital lock detect circuitry is reset.
• The RF IN input is debiased.
• The reference input buffer circuitry is disabled.
• The input register remains active and capable of loading and latching data. MUXOUT Control The on-chip multiplexer is controlled by M3, M2, and M1 on the ADF4107. Figure 25 shows the truth table. Fastlock Enable Bit DB9 of the function latch is the fastlock enable bit. Fastlock is enabled only when this bit is 1. Fastlock Mode Bit DB10 of the function latch is the fastlock mode bit. When fastlock is enabled, this bit determines which fastlock mode is used. If the fastlock mode bit is 0, then Fastlock Mode 1 is selected; and if the fastlock mode bit is 1, then Fastlock Mode 2 is selected. Fastlock Mode 1 The charge pump current is switched to the contents of Current Setting 2. The device enters fastlock by having a 1 written to the CP gain bit in the AB counter latch. The device exits fastlock by having a 0 written to the CP gain bit in the AB counter latch. Fastlock Mode 2 The charge pump current is switched to the contents of Current Setting 2. The device enters fastlock by having a 1 written to the CP gain bit in the AB counter latch. The device exits fastlock under the control of the timer counter. After the timeout period determined by the value in TC4 to TC1, the CP gain bit in the AB counter latch is automatically reset to 0 and the device reverts to normal mode instead of fastlock. See Figure 25 for the timeout periods. Timer Counter Control The user has the option of programming two charge pump currents. The intent is that Current Setting 1 is used when the RF output is stable and the system is in a static state. Current Setting 2 is meant to be used when the system is dynamic and in a state of change (that is, when a new output frequency is programmed). The normal sequence of events is as follows: The user initially decides what the preferred charge pump currents are going to be. For example, the choice may be 2.5 mA as Current Setting 1 and 5 mA as Current Setting 2. At the same time, it must be decided how long the secondary current is to stay active before reverting to the primary current. This is controlled by the timer counter control bits, DB14 to DB11 (TC4 to TC1), in the function latch. The truth table is given in Figure 25. To program a new output frequency, the user simply programs the AB counter latch with new values for A and B. At the same time, the CP gain bit can be set to 1, which sets the charge pump with the value in CPI6 to CPI4 for a period of time determined by TC4 to TC1. When this time is up, the charge pump current reverts to the value set by CPI3 to CPI1. At the same time, the CP gain bit in the AB counter latch is reset to 0 and is ready for the next time that the user wishes to change the frequency. Note that there is an enable feature on the timer counter. It is enabled when Fastlock Mode 2 is chosen by setting the fastlock mode bit (DB10) in the function latch to 1.

Rev. D | Page 17 of 20 Charge Pump Currents CPI3, CPI2, and CPI1 program Current Setting 1 for the charge pump. CPI6, CPI5, and CPI4 program Current Setting 2 for the charge pump. The truth table is given in Figure 25. Prescaler Value P2 and P1 in the function latch set the prescaler values. The prescaler value should be chosen so that the prescaler output frequency is always less than or equal to 300 MHz. Thus, with an RF frequency of 4 GHz, a prescaler value of 16/17 is valid but a value of 8/9 is not valid. PD Polarity This bit sets the phase detector polarity bit. See Figure 25. CP Three-State This bit controls the CP output pin. With the bit set high, the CP output is put into three-state. With the bit set low, the CP output is enabled. INITIALIZATION LATCH The initialization latch is programmed when C2 and C1 are set to 1 and 1. This is essentially the same as the function latch (programmed when C2, C1 = 1, 0). However, when the initialization latch is programmed an additional internal reset pulse is applied to the R and AB counters. This pulse ensures that the AB counter is at load point when the AB counter data is latched and the device will begin counting in close phase alignment. If the latch is programmed for synchronous power-down (CE pin is high; PD1 bit is high; PD2 bit is low), the internal pulse also triggers this power-down. The prescaler reference and the oscillator input buffer are unaffected by the internal reset pulse and so close phase alignment is maintained when counting resumes. When the first AB counter data is latched after initialization, the internal reset pulse is again activated. However, successive AB counter loads after this will not trigger the internal reset pulse. DEVICE PROGRAMMING AFTER INITIAL POWER-UP After initially powering up the device, there are three ways to program the device. Initialization Latch Method 1. Apply VDD. 2. Program the initialization latch (11 in two LSBs of input word). Make sure that the F1 bit is programmed to 0. 3. Next, do a function latch load (10 in two LSBs of the control word), making sure that the F1 bit is programmed to a 0. 4. Then do an R load (00 in two LSBs). 5. Then do an AB load (01 in two LSBs). 6. When the initialization latch is loaded, the following occurs: a. The function latch contents are loaded. b. An internal pulse resets the R, AB, and timeout counters to load-state conditions and also three-states the charge pump. Note that the prescaler band gap reference and the oscillator input buffer are unaffected by the internal reset pulse, allowing close phase alignment when counting resumes. c. Latching the first AB counter data after the initialization word activates the same internal reset pulse. Successive AB loads do not trigger the internal reset pulse unless there is another initialization. CE Pin Method 1. Apply VDD. 2. Bring CE low to put the device into power-down. This is an asychronous power-down in that it happens immediately. 3. Program the function latch (10). 4. Program the R counter latch (00). 5. Program the AB counter latch (01). 6. Bring CE high to take the device out of power-down. The R and AB counters resume counting in close alignment. Note that after CE goes high, a duration of 1 µs may be required for the prescaler band gap voltage and oscillator input buffer bias to reach steady state. CE can be used to power the device up and down in order to check for channel activity. The input register does not need to be reprogrammed each time the device is disabled and enabled as long as it has been programmed at least once after V DD was initially applied. Counter Reset Method 1. Apply VDD. 2. Do a function latch load (10 in two LSBs). As part of this, load 1 to the F1 bit. This enables the counter reset. 3. Do an R counter load (00 in two LSBs). 4. Do an AB counter load (01 in two LSBs). 5. Do a function latch load (10 in two LSBs). As part of this, load 0 to the F1 bit. This disables the counter reset. This sequence provides the same close alignment as the initialization method. It offers direct control over the internal reset. Note that counter reset holds the counters at load point and three-states the charge pump, but does not trigger synchronous power-down.

Figure 30. 16-Lead Thin Shrink Small Outline Package [TSSOP] COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-1.

0.02 NOM

0.20 REF

0.20 MIN

Figure 31. 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] registered trademarks are the property of their respective owners.