ADF4106BCPZ

DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 24

Technical content

Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2001–2012 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

6.0 GHz bandwidth

2.7 V to 3.3 V power supply Separate charge pump supply (VP) allows extended tuning voltage in 3 V systems Programmable dual-modulus prescaler Programmable charge pump currents Programmable antibacklash pulse width 3-wire serial interface Analog and digital lock detect Hardware and software power-down mode

APPLICATIONS

Base stations for wireless radios GENERAL DESCRIPTION The ADF4106 frequency synthesizer can be used to implement local oscillators in the up-conversion and down-conversion sections of wireless receivers and transmitters. It consists of a low noise, digital phase frequency detector (PFD), a precision charge pump, a programmable reference divider, programmable A counter and B counter, and a dual-modulus prescaler (P/P + 1). The A (6-bit) counter and B (13-bit) counter, in conjunction with the dual-modulus prescaler (P/P + 1), implement an N divider (N = BP + A). In addition, the 14-bit reference counter (R Counter) allows selectable REF IN frequencies at the PFD input. A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and voltage controlled oscillator (VCO). Its very high bandwidth means that frequency doublers can be eliminated in many high frequency systems, simplifying system architecture and reducing cost. FUNCTIONAL BLOCK DIAGRAM 02720-001 CLK DATA LE REFIN RFINA RFINB 24-BIT INPUT REGISTER SDOUT AVDD DVDD CE AGND DGND 14-BIT R COUNTER R COUNTER LATCH FUNCTION LATCH A, B COUNTER LATCHFROM FUNCTION LATCH PRESCALER P/P + 1 N = BP + A LOAD LOAD 13-BIT B COUNTER 6-BIT A COUNTER M3 M2 M1 MUX SDOUT AVDD HIGH Z MUXOUT CPGND RSETVP CP PHASE FREQUENCY DETECTOR LOCK DETECT REFERENCE CHARGE PUMP CURRENT SETTING 1 ADF4106 CPI3 CPI2 CPI1 CPI6 CPI5 CPI4 CURRENT SETTING 2 Figure 1.

Rev. E | Page 2 of 24 TABLE OF CONTENTS

REVISION HISTORY

11/12—Rev. D to Rev. E 9/11—Rev. C to Rev. D Changes to Normalized Phase Noise Floor (PNSYNTH) Parameter, Added Normalized 1/f Noise (PN1_f) Parameter and Endnote 12, 2/10—Rev. B to Rev. C 6/05—Rev. A to Rev. B 5/03—Rev. 0 to Rev. A 10/01—Revision 0: Initial Revision

Rev. E | Page 3 of 24 SPECIFICATIONS AVDD = DVDD = 3 V ± 10%, AVDD ≤ VP ≤ 5.5 V , AGND = DGND = CPGND = 0 V , RSET = 5.1 kΩ, dBm referred to 50 Ω, TA = TMAX to TMIN, unless otherwise noted. Table 1. Parameter B Version1 B Chips 2 (typ) Unit Test Conditions/Comments RF CHARACTERISTICS See Figure 18 for input circuit RF Input Frequency (RFIN) 0.5/6.0 0.5/6.0 GHz min/max For lower frequencies, ensure slew rate (SR) > 320 V/μs RF Input Sensitivity –10/0 –10/0 dBm min/max Maximum Allowable Prescaler Output Frequency 300 300 MHz max P = 8 325 325 MHz max P = 16 REFIN CHARACTERISTICS REFIN Input Frequency 20/300 20/300 MHz min/max For f < 20 MHz, ensure SR > 50 V/μs REFIN Input Sensitivity4 0.8/V DD 0.8/V DD V p-p min/max Biased at AV DD/2 (see Note 55) REFIN Input Capacitance 10 10 pF max REFIN Input Current ±100 ±100 μA max PHASE DETECTOR Phase Detector Frequency6 104 104 MHz max ABP = 0, 0 (2.9 ns antibacklash pulse width) CHARGE PUMP Programmable, see Table 9 ICP Sink/Source High Value 5 5 mA typ With R SET = 5.1 kΩ Low Value 625 625 μA typ Absolute Accuracy 2.5 2.5 % typ With RSET = 5.1 kΩ RSET Range 3.0/11 3.0/11 kΩ typ See Table 9 ICP Three-State Leakage 2 2 nA max 1 nA typical; T A = 25°C Sink and Source Current Matching 2 2 % typ 0.5 V ≤ VCP ≤ VP − 0.5 V ICP vs. Temperature 2 2 % typ VCP = VP/2 LOGIC INPUTS VIH, Input High Voltage 1.4 1.4 V min VIL, Input Low Voltage 0.6 0.6 V max IINH, IINL, Input Current ±1 ±1 μA max CIN, Input Capacitance 10 10 pF max LOGIC OUTPUTS VOH, Output High Voltage 1.4 1.4 V min Open-drain output chosen, 1 kΩ pull-up resistor to 1.8 V VOH, Output High Voltage VDD − 0.4 V DD − 0.4 V min CMOS output chosen IOH 100 100 μA max VOL, Output Low Voltage 0.4 0.4 V max I OL = 500 μA POWER SUPPLIES AVDD 2.7/3.3 2.7/3.3 V min/V max DVDD AV DD AV DD VP AV DD/5.5 AV DD/5.5 V min/V max AV DD ≤ VP ≤ 5.5V IDD7 (AIDD + DIDD) 11 9.0 mA max 9.0 mA typ IDD8 (AIDD + DIDD) 11.5 9.5 mA max 9.5 mA typ IDD9 (AIDD + DIDD) 13 10.5 mA max 10.5 mA typ IP 0.4 0.4 mA max TA = 25°C Power-Down Mode10 (AIDD + DIDD) 10 10 μA typ

Rev. E | Page 4 of 24 Parameter B Version1 B Chips 2 (typ) Unit Test Conditions/Comments NOISE CHARACTERISTICS Normalized Phase Noise Floor (PNSYNTH)11 –223 –223 dBc/Hz typ PLL loop B/W = 500 kHz, measured at 100 kHz offset Normalized 1/f Noise (PN1_f)12 −122 −122 dBc/Hz typ 10 kHz offset; normalized to 1 GHz Phase Noise Performance13 @ VCO output 900 MHz14 –92.5 −92.5 dBc/Hz typ @ 1 kHz offset and 200 kHz PFD frequency 5800 MHz15 −76.5 −76.5 dBc/Hz typ @ 1 kHz offset and 200 kHz PFD frequency 5800 MHz16 −83.5 −83.5 dBc/Hz typ @ 1 kHz offset and 1 MHz PFD frequency Spurious Signals

900 MHz14 –90/–92 –90/–92 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD frequency

5800 MHz15 –65/–70 –65/–70 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD frequency

5800 MHz16 –70/–75 –70/–75 dBc typ @ 1 MHz/2 MHz and 1 MHz PFD frequency

1 Operating temperature range (B Version) is –40°C to +85°C. 2 The B chip specifications are given as typical values. 3 This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that is less than this value. 4 AVDD = DVDD = 3 V. 5 AC coupling ensures AVDD/2 bias. 6 Guaranteed by design. Sample tested to ensure compliance. 7 TA = 25°C; AVDD = DVDD = 3 V; P = 16; RFIN = 900 MHz. 8 TA = 25°C; AVDD = DVDD = 3 V; P = 16; RFIN = 2.0 GHz. 9 TA = 25°C; AVDD = DVDD = 3 V; P = 32; RFIN = 6.0 GHz. 10 TA = 25°C; AVDD = DVDD = 3.3 V; R = 16383; A = 63; B = 891; P = 32; RFIN = 6.0 GHz. 11 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider value) and 10 log FPFD. PNSYNTH = PNTOT − 10 log FPFD − 20 log N. 12 The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, fRF, and at a frequency offset, f, is given by PN = PN1_f + 10 log(10 kHz/f) + 20 log(fRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL. 13 The phase noise is measured with the EV-ADF4106SD1Z evaluation board and the Agilent E4440A Spectrum Analyzer. The spectrum analyzer provides the REFIN for the synthesizer (fREFOUT = 10 MHz @ 0 dBm). 14 fREFIN = 10 MHz; fPFD = 200 kHz; Offset Frequency = 1 kHz; fRF = 900 MHz; N = 4500; Loop B/W = 20 kHz. 15 fREFIN = 10 MHz; fPFD = 200 kHz; Offset Frequency = 1 kHz; fRF = 5800 MHz; N = 29000; Loop B/W = 20 kHz. 16 fREFIN = 10 MHz; fPFD = 1 MHz; Offset Frequency = 1 kHz; fRF = 5800 MHz; N = 5800; Loop B/W = 100 kHz. TIMING CHARACTERISITICS AVDD = DVDD = 3 V ± 10%, AVDD ≤ VP ≤ 5.5 V , AGND = DGND = CPGND = 0 V , RSET = 5.1 kΩ, dBm referred to 50 Ω, TA = TMAX to TMIN, unless otherwise noted. Table 2. Parameter Limit 1 (B Version) Unit Test Conditions/Comments t1 10 ns min DATA to CLOCK Setup Time t2 10 ns min DATA to CLOCK Hold Time t3 25 ns min CLOCK High Duration t4 25 ns min CLOCK Low Duration t5 10 ns min CLOCK to LE Setup Time t6 20 ns min LE Pulse Width 1 Operating temperature range (B Version) is –40°C to +85°C.

Figure 2. Timing Diagram

Rev. E | Page 6 of 24 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter Rating AVDD to GND1 –0.3 V to + 3.6 V AVDD to DVDD –0.3 V to + 0.3 V VP to GND –0.3 V to + 5.8 V VP to AVDD –0.3 V to + 5.8 V Digital I/O Voltage to GND –0.3 V to VDD + 0.3 V Analog I/O Voltage to GND –0.3 V to VP + 0.3 V REFIN, RFINA, RFINB to GND –0.3 V to VDD + 0.3 V RFINA to RFINB ±320 mV Operating Temperature Range Industrial (B Version) –40°C to +85°C Storage Temperature Range –65°C to +125°C Maximum Junction Temperature 150°C TSSOP θJA Thermal Impedance 112°C/W LFCSP θJA Thermal Impedance (Paddle Soldered) 30.4°C/W Reflow Soldering Peak Temperature 260°C Time at Peak Temperature 40 sec Transistor Count CMOS 6425 Bipolar 303 1GND = AGND = DGND = 0 V. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. This device is a high performance RF integrated circuit with an ESD rating of <2 kV , and it is ESD sensitive. Proper precautions should be taken for handling and assembly. ESD CAUTION

Figure 3. 16-Lead TSSOP Pin Configuration

15 MUXOUT

13 DATA

12 CLK

1. TRANSISTOR COUNT 6425 (CMOS),

Figure 4. 20-Lead LFCSP_VQ Pin Configuration Table 4. Pin Function Descriptions 1 19 RSET Connecting a resistor between this pin and CPGND sets the maximum charge pump output current. So, with RSET = 5.1 kΩ, ICP MAX = 5 mA. 3 1 CPGND Charge Pump Ground. This is the ground return path for the charge pump. 4 2, 3 AGND Analog Ground. This is the ground return path of the prescaler. a small bypass capacitor, typically 100 pF. See Figure 18. 6 5 RFINA Input to the RF Prescaler. This small signal input is ac-coupled to the external VCO. plane should be placed as close as possible to this pin. AVDD must be the same value as DVDD. 9 9, 10 DGND Digital Ground. into the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input. 12 13 DATA Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a high impedance CMOS input. of the four latches with the latch being selected using the control bits. plane should be placed as close as possible to this pin. DVDD must be the same value as AVDD. it can be set to 5.5 V and used to drive a VCO with a tuning range of up to 5 V. EP Exposed Pad. The exposed pad must be connected to AGND.

Table 6. Latch Summary

Table 7. Reference Counter Latch Map 15ns MUST OCCUR BEFORE LOCK DETECT IS SET. 15ns MUST OCCUR BEFORE LOCK DETECT IS SET.

Table 8. N (A, B) Counter Latch Map SETTING 1 IS PERMANENTLY USED. SETTING 2 IS PERMANENTLY USED.

Table 9. Function Latch Map

0 X X

1 X 0

Table 10. Initialization Latch Map

Rev. E | Page 17 of 24 THE FUNCTION LATCH With C2 and C1 set to 1 and 0, respectively, the on-chip function latch is programmed. Table 9 shows the input data format for programming the function latch. Counter Reset DB2 (F1) is the counter reset bit. When this is 1, the R counter and the N (A, B) counter are reset. For normal operation, this bit should be 0. When powering up, disable the F1 bit (set to 0). The N counter will then resume counting in close alignment with the R counter. (The maximum error is one prescaler cycle). Power-Down DB3 (PD1) and DB21 (PD2) provide programmable power- down modes. They are enabled by the CE pin. When the CE pin is low, the device is immediately disabled regardless of the states of PD2, PD1. In the programmed asynchronous power-down, the device powers down immediately after latching 1 into the PD1 bit, with the condition that PD2 is loaded with 0. In the programmed synchronous power-down, the device power-down is gated by the charge pump to prevent unwanted frequency jumps. Once the power-down is enabled by writing 1 into the PD1 bit (provided that 1 has also been loaded to PD2), then the device goes into power-down during the next charge pump event. When a power-down is activated (either synchronous or asynchronous mode, including CE pin activated power-down), the following events occur:

• All active dc current paths are removed.
• The R, N, and timeout counters are forced to their load state conditions.
• The charge pump is forced into three-state mode.
• The digital clock detect circuitry is reset.
• The RF IN input is debiased.
• The reference input buffer circuitry is disabled.
• The input register remains active and capable of loading and latching data. MUXOUT Control The on-chip multiplexer is controlled by M3, M2, and M1 on the ADF4106 family. Table 9 shows the truth table. Fastlock Enable Bit DB9 of the function latch is the fastlock enable bit. When this bit is 1, fastlock is enabled. Fastlock Mode Bit DB10 of the function latch is the fastlock mode bit. When fastlock is enabled, this bit determines which fastlock mode is used. If the fastlock mode bit is 0, then Fastlock Mode 1 is selected; and if the fastlock mode bit is 1, then Fastlock Mode 2 is selected. Fastlock Mode 1 The charge pump current is switched to the contents of Current Setting 2. The device enters fastlock when 1 is written to the CP gain bit in the N (A, B) counter latch. The device exits fastlock when 0 is written to the CP gain bit in the N (A, B) counter latch. Fastlock Mode 2 The charge pump current is switched to the contents of Current Setting 2. The device enters fastlock when 1 is written to the CP gain bit in the N (A, B) counter latch. The device exits fastlock under the control of the timer counter. After the timeout period, which is determined by the value in TC4 to TC1, the CP gain bit in the N (A, B) counter latch is automatically reset to 0, and the device reverts to normal mode instead of fastlock. See Table 9 for the timeout periods. Timer Counter Control The user has the option of programming two charge pump currents. The intent is that Current Setting 1 is used when the RF output is stable and the system is in a static state. Current Setting 2 is used when the system is dynamic and in a state of change (that is, when a new output frequency is programmed). The normal sequence of events follows. The user initially decides what the preferred charge pump currents are going to be. For example, the choice may be 2.5 mA as Current Setting 1 and 5 mA as the Current Setting 2. Simultaneously, the decision must be made as to how long the secondary current stays active before reverting to the primary current. This is controlled by the timer counter control bits, DB14 to DB11 (TC4 to TC1), in the function latch. The truth table is given in Table 9. To program a new output frequency, simply program the N (A, B) counter latch with new values for A and B. Simultaneously, the CP gain bit can be set to 1, which sets the charge pump with the value in CPI6 to CPI4 for a period of time determined by TC4 to TC1. When this time is up, the charge pump current reverts to the value set by CPI3 to CPI1. At the same time, the CP gain bit in the N (A, B) counter latch is reset to 0 and is now ready for the next time the user wishes to change the frequency. Note that there is an enable feature on the timer counter. It is enabled when Fastlock Mode 2 is chosen by setting the fastlock mode bit (DB10) in the function latch to 1.

Rev. E | Page 18 of 24 Charge Pump Currents CPI3, CPI2, and CPI1 program Current Setting 1 for the charge pump. CPI6, CPI5, and CPI4 program Current Setting 2 for the charge pump. The truth table is given in Table 9. Prescaler Value P2 and P1 in the function latch set the prescaler values. The prescaler value should be chosen so that the prescaler output frequency is always less than or equal to 325 MHz. Therefore, with an RF frequency of 4 GHz, a prescaler value of 16/17 is valid, but a value of 8/9 is not valid. PD Polarity This bit sets the phase detector polarity bit. See Table 9. CP Three-State This bit controls the CP output pin. With the bit set high, the CP output is put into three-state. With the bit set low, the CP output is enabled. THE INITIALIZATION LATCH When C2 and C1 = 1 and 1, respectively, the initialization latch is programmed. This is essentially the same as the function latch (programmed when C2 and C1 = 1 and 0, respectively). However, when the initialization latch is programmed, there is an additional internal reset pulse applied to the R and N (A, B) counters. This pulse ensures that the N (A, B) counter is at the load point when the N (A, B) counter data is latched and the device begins counting in close phase alignment. If the latch is programmed for synchronous power-down (CE pin is high, PD1 bit is high, and PD2 bit is low), the internal pulse also triggers this power-down. The prescaler reference and the oscillator input buffer are unaffected by the internal reset pulse; therefore, close phase alignment is maintained when counting resumes. When the first N (A, B) counter data is latched after initialization, the internal reset pulse is again activated. However, successive N (A, B) counter loads after this will not trigger the internal reset pulse. Device Programming After Initial Power-Up After initial power up of the device, there are three methods for programming the device: initialization latch, CE pin, and counter reset. Initialization Latch Method

• Apply VDD.
• Program the initialization latch (11 in two LSBs of input word). Make sure that the F1 bit is programmed to 0.
• Do a function latch load (10 in two LSBs of the control word), making sure that the F1 bit is programmed to a 0.
• Do an R load (00 in two LSBs).
• Do an N (A, B) load (01 in two LSBs). When the initialization latch is loaded, the following occurs:
• The function latch contents are loaded.
• An internal pulse resets the R, N (A, B), and timeout counters to load-state conditions and also three-states the charge pump. Note that the prescaler band gap reference and the oscillator input buffer are unaffected by the internal reset pulse, allowing close phase alignment when counting resumes.
• Latching the first N (A, B) counter data after the initialization word activates the same internal reset pulse. Successive N (A, B) loads will not trigger the internal reset pulse, unless there is another initialization. CE PIN METHOD
• Apply VDD.
• Bring CE low to put the device into power-down. This is an asychronous power-down in that it happens immediately.
• Program the function latch (10).
• Program the R counter latch (00).
• Program the N (A, B) counter latch (01).
• Bring CE high to take the device out of power-down. The R and N (A, B) counters now resume counting in close alignment. Note that after CE goes high, a 1 µs duration may be required for the prescaler band gap voltage and oscillator input buffer bias to reach steady state. CE can be used to power the device up and down to check for channel activity. The input register does not need to be reprogrammed each time the device is disabled and enabled as long as it is programmed at least once after V DD is initially applied. COUNTER RESET METHOD
• Apply VDD.
• Do a function latch load (10 in two LSBs). As part of this, load 1 to the F1 bit. This enables the counter reset.
• Do an R counter load (00 in two LSBs).
• Do an N (A, B) counter load (01 in two LSBs).
• Do a function latch load (10 in two LSBs). As part of this, load 0 to the F1 bit. This disables the counter reset. This sequence provides the same close alignment as the initialization method. It offers direct control over the internal reset. Note that counter reset holds the counters at load point and three-states the charge pump but does not trigger synchronous power-down.

Rev. E | Page 19 of 24 LOCAL OSCILLATOR FOR LMDS BASE STATION TRANSMITTER Figure 22 shows the ADF4106 being used with a VCO to produce the LO for an LMDS base station. The reference input signal is applied to the circuit at FREFIN and, in this case, is terminated in 50 Ω. A typical base station system would have either a TCXO or an OCXO driving the reference input without any 50 Ω termination. To achieve a channel spacing of 1 MHz at the output, the

10 MHz reference input must be divided by 10, using the

on-chip reference divider of the ADF4106. The charge pump output of the ADF4106 (Pin 2) drives the loop filter. In calculating the loop filter component values, a number of items need to be considered. In this example, the loop filter was designed so that the overall phase margin for the system would be 45°. Other PLL system specifications include: KD = 2.5 mA KV = 80 MHz/V Loop Bandwidth = 50 kHz FPFD = 1 MHz N = 5800 Extra Reference Spur Attenuation = 10 dB These specifications are needed and used to derive the loop filter component values shown in Figure 22. The circuit in Figure 22 shows a typical phase noise performance of −83.5 dBc/Hz at 1 kHz offset from the carrier. Spurs are better than −62 dBc. The loop filter output drives the VCO, which in turn is fed back to the RF input of the PLL synthesizer and also drives the RF output terminal. A T-circuit configuration provides 50 Ω matching between the VCO output, the RF output, and the RFIN terminal of the synthesizer. In a PLL system, it is important to know when the system is in lock. In Figure 22, this is accomplished by using the MUXOUT signal from the synthesizer. The MUXOUT pin can be programmed to monitor various internal signals in the synthesizer. One of these is the LD or lock-detect signal. ADF4106 CE CLK DATA LE 1000pF 1000pF REF IN 100pF CP MUXOUT CPGND AGND DGND 100pF 1.5nF 20pF 100pF 51Ω 6.2kΩ 4.3kΩ 100pF 18Ω NOTE DECOUPLING CAPACITORS (0.1µF/10pF) ON AVDD, DVDD, AND VP OF THE ADF4106 AND ON VCC OF THE V956ME03 HAVE BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY. SPI®-COMPATIBLE SERIAL BUS RSET RFINA RFINB AVDD DVDD VP FREFIN VDD VP LOCK DETECT VCC V956ME03 1, 3, 4, 5, 7, 8, 9, 11, 12, 13 18Ω 18Ω 100pF RF OUT 5.1kΩ 7 15 16 943 2 10 51Ω 02720-027 Figure 22. Local Oscillator for LMDS Base Station

Figure 25. 16-Lead Thin Shrink Small Outline Package [TSSOP]

0.65 TYP

0.05 MAX

0.02 NOM

0.20 REF

0.60 MAX

0.25 MIN

Figure 26. 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

Rev. E | Page 22 of 24 ORDERING GUIDE Model1 Temperature Range Package Description Package Option ADF4106BRU –40°C to + 85°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16 ADF4106BRU-REEL –40°C to + 85°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16 ADF4106BRU-REEL7 –40°C to + 85°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16 ADF4106BRUZ –40°C to + 85°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16 ADF4106BRUZ-RL –40°C to + 85°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16 ADF4106BRUZ-R7 –40°C to + 85°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16 ADF4106BCPZ –40°C to + 85°C 20-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-20-1 ADF4106BCPZ-RL –40°C to + 85°C 20-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-20-1 ADF4106BCPZ-R7 –40°C to + 85°C 20-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-20-1 EV-ADF4106SD1Z Evaluation Board EV-ADF411XSD1Z Evaluation Board 1 Z = RoHS Compliant.

Rev. E | Page 23 of 24 NOTES

Rev. E | Page 24 of 24 NOTES ©2001–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respecti ve owners. D02720-0-11/12(E)