ADF4106BCP

ADF4106 AD | Alldatasheet

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REV.0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a ADF4106 Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001 PLL Frequency Synthesizer

FEATURES

6.0 GHz Bandwidth

2.7 V to 3.3 V Power Supply Separate Charge Pump Supply (V P) Allows Extended Tuning Voltage in 3 V Systems Programmable Dual Modulus Prescaler Programmable Charge Pump Currents Programmable Anti-Backlash Pulsewidth 3-Wire Serial Interface Analog and Digital Lock Detect Hardware and Software Power-Down Mode

APPLICATIONS

Base Stations For Wireless Radio FUNCTIONAL BLOCK DIAGRAM 14-BIT R COUNTER R COUNTER LA TCH FUNCTION LA TCH AB COUNTER LA TCH 24-BIT INPUT REGISTER 22 REFIN CLK DATA LE AVDD DVDD PHASE FREQUENCY DETECTOR CHARGE PUMP REFERENCE VP CPGND RSET CURRENT SETTING 2 CURRENT SETTING 1 CPI3 CPI2 CPI1 CPI6 CPI5 CPI4 LOCK DETECT CP MUXOUT AVDD SDOUT HIGH Z 13-BIT B COUNTER PRESCALER P/P + 1 RFINA RFINB 6-BIT A COUNTER FROM FUNCTION LA TCH LOAD LOAD M3 M2 M1 MUX N = BP + A CE AGND DGND ADF4106 GENERAL DESCRIPTION The ADF4106 frequency synthesizer can be used to implement local oscillators in the up-conversion and down-conversion sections of wireless receivers and transmitters. It consists of a low-noise digital PFD (Phase Frequency Detector), a precision charge pump, a programmable reference divider, programmable A and B counters and a dual-modulus prescaler (P/P + 1). The A (6-bit) and B (13-bit) counters, in conjunction with the dual modulus prescaler (P/P + 1), implement an N divider (N = BP + A). In addition, the 14-bit reference counter (R Counter), allows selectable REFIN frequencies at the PFD input. A complete PLL (Phase-Locked Loop) can be implemented if the synthe- sizer is used with an external loop filter and VCO (Voltage Controlled Oscillator). Its very high bandwidth means that frequency doublers can be eliminated in many high-frequency systems, simplifying system architecture and lowering cost.

REV. 0–2– ADF4106–SPECIFICATIONS1 BChips2 Parameter B Version 1 (typ) Unit Test Conditions/Comments RF CHARACTERISTICS See Figure 3 for Input Circuit RF Input Frequency (RF IN)3 0.5/6.0 0.5/6.0 GHz min/max RF Input Sensitivity –10/0 –10/0 dBm min/max Maximum Allowable Prescaler Output Frequency 4 300 300 MHz max REFIN CHARACTERISTICS REFIN Input Frequency 20/250 20/250 MHz min/max For f < 20 MHz, Use DC-Coupled Square Wave, (0 to V DD) REFIN Input Sensitivity 5 0.8/AVDD 0.8/AVDD V p-p min/max AC-Coupled; When DC-Coupled, 0 to VDD max (CMOS Compatible) REFIN Input Capacitance 10 10 pF max REFIN Input Current ± 100 ± 100 µA max PHASE DETECTOR Phase Detector Frequency 6 56 56 MHz max CHARGE PUMP ICP Sink/Source Programmable, See Table V High Value 5 5 mA typ With R SET = 5.1 kΩ Low Value 625 625 µA typ Absolute Accuracy 2.5 2.5 % typ With R SET = 5.1 kΩ RSET Range 2.7/10 2.7/10 k Ω typ See Table V ICP Three-State Leakage Current 1 1 nA typ Sink and Source Current Matching 2 2 % typ 0.5 V /H11349 VCP /H11349 VP – 0.5 V ICP vs. Temperature 2 2 % typ V CP = VP/2 LOGIC INPUTS VINH, Input High Voltage 1.4 1.4 V min VINL, Input Low Voltage 0.6 0.6 V max IINH/IINL, Input Current ± 1 ± 1 µA max CIN, Input Capacitance 10 10 pF max LOGIC OUTPUTS VOH, Output High Voltage 1.4 1.4 V min Open Drain Output Chosen 1 k Ω Pull-up to 1.8 V VOH, Output High Voltage 1.4 1.4 V min CMOS Output Chosen IOH 100 100 µA max VOL, Output Low Voltage 0.4 0.4 V max I OL = 500 µA POWER SUPPLIES AVDD 2.7/3.3 2.7/3.3 V min/V max DVDD AVDD AVDD VP AVDD/5.5 AV DD/5.5 V min/V max AV DD /H11349 VP /H11349 5.5 V IDD 7 (AIDD + DIDD) 15 13 mA max 13 mA typ IP 0.4 0.4 mA max T A = 25°C Power-Down Mode8 (AIDD + DIDD)1 0 1 0 µA typ (AVDD = DVDD = 3 V /H11550 10%; AVDD ≤ VP ≤ 5.5 V; AGND = DGND = CPGND = 0 V; RSET = 5.1 k/H9024; dBm referred to 50 /H9024; TA = TMIN to TMAX unless otherwise noted.)

900 MHz Output11 –93 –93 dBc/Hz typ @ 1 kHz Offset and 200 kHz PFD Frequency

5800 MHz Output12 –74 –74 dBc/Hz typ @ 1 kHz Offset and 200 kHz PFD Frequency

5800 MHz Output13 –84 –84 dBc/Hz typ @ 1 kHz Offset and 1 MHz PFD Frequency

900 MHz Output11 –90/–92 –90/–92 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD Frequency

5800 MHz Output12 –65/–70 –65/–70 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD Frequency

5800 MHz Output13 –70/–75 –70/–75 dBc typ @ 1 MHz/2 MHz and 1 MHz PFD Frequency

1Operating temperature range (B Version) is –40°C to +85°C. 2The BChip specifications are given as typical values. 3Use a square wave for lower frequencies, below the mimimum stated. that is less than this value. 6Guaranteed by design. Sample tested to ensure compliance. 9The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 logN (where N is the N divider value). the synthesizer (f REFOUT = 10 MHz @ 0 dBm). Specifications subject to change without notice. Figure 1. Timing Diagram Guaranteed by design but not production tested.

REV. 0 ADF4106 –4– ABSOLUTE MAXIMUM RATINGS 1, 2 (TA = 25°C unless otherwise noted.) Operating Temperature Range Lead Temperature, Soldering NOTES 1Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2This device is a high-performance RF integrated circuit with an ESD rating of <2 kV and it is ESD sensitive. Proper precautions should be taken for handling and assembly. 3GND = AGND = DGND = 0 V ORDERING GUIDE Model Temperature Range Package Option * ADF4106BRU –40°C to +85°C RU-16 ADF4106BCP –40°C to +85°C CP-20 *RU = Thin Shrink Small Outline Package (TSSOP) CP = Chip Scale Package Contact the factory for chip availability. Note that aluminum bond wire should not be used with the ADF4106 die. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADF4106 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE

REV. 0 ADF4106 –5– PIN CONFIGURATIONS PIN FUNCTION DESCRIPTIONS Mnemonic Function RSET Connecting a resistor between this pin and CPGND sets the maximum charge pump output current. The nominal voltage potential at the R SET pin is 0.6 V. The relationship between I CP and RSET is I R CP MAX SET = 25 5. So, with RSET = 5.1 kΩ, ICPMAX = 5 mA. CP Charge Pump Output. When enabled this provides ±ICP to the external loop filter, which in turn drives the external VCO. CPGND Charge Pump Ground. This is the ground return path for the charge pump. AGND Analog Ground. This is the ground return path of the prescaler. RF INB Complementary Input to the RF Prescaler. This point must be decoupled to the ground plane with a small bypass capacitor, typically 100 pF. See Figure 3. RFINA Input to the RF Prescaler. This small signal input is ac coupled to the external VCO. AVDD Analog Power Supply. This may range from 2.7 V to 3.3 V. Decoupling capacitors to the analog ground plane should be placed as close as possible to this pin. AV DD must be the same value as DV DD. REFIN Reference Input. This is a CMOS input with a nominal threshold of V DD/2 and a dc equivalent input resistance of 100 kΩ. See Figure 2. This input can be driven from a TTL or CMOS crystal oscillator or it can be ac coupled. DGND Digital Ground CE Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three-state mode. Taking the pin high will power up the device depending on the status of the power-down bit F2. CLK Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input. DATA Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a high impedance CMOS input. LE Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four latches, the latch being selected using the control bits. MUXOUT This multiplexer output allows either the Lock Detect, the scaled RF or the scaled Reference Frequency to be accessed externally. DVDD Digital Power Supply. This may range from 2.7 V to 3.3 V. Decoupling capacitors to the digital ground plane should be placed as close as possible to this pin. DV DD must be the same value as AV DD. VP Charge Pump Power Supply. This should be greater than or equal to V DD. In systems where V DD is 3 V, it can be set to 5 V and used to drive a VCO with a tuning range of up to 5 V. TSSOP TOP VIEW (Not to Scale) RSET CP CPGND AGND RFINB RFINA AVDD REFIN VP DVDD MUXOUT LE DATA CLK CE DGND ADF4106 Chip Scale Package

15 MUXOUT

13 DA T A

12 CLK

19 RSET

17 DVDD

16 DVDD

NOTE: TRANSISTOR COUNT 6425 (CMOS), 303 (BIPOLAR)

REV. 0 ADF4106–Typical Performance Characteristics –6– FREQ UNIT – GHz PARAM TYPE – S DATA FORMAT – MA FREQ MAGS11 ANGS11 3.300 0.42777 – 102.748 3.400 0.42859 – 107.167 3.500 0.43365 – 111.883 3.600 0.43849 – 117.548 3.700 0.44475 – 123.856 3.800 0.44800 – 130.399 3.900 0.45223 – 136.744 4.000 0.45555 – 142.766 4.100 0.45313 – 149.269 4.200 0.45622 – 154.884 4.300 0.45555 – 159.680 4.400 0.46108 – 164.916 4.500 0.45325 – 168.452 4.600 0.45054 – 173.462 4.700 0.45200 – 176.697 4.800 0.45043 178.824 4.900 0.45282 174.947 5.000 0.44287 170.237 5.100 0.44909 166.617 5.200 0.44294 162.786 5.300 0.44558 158.766 5.400 0.45417 153.195 5.500 0.46038 147.721 5.600 0.47128 139.760 5.700 0.47439 132.657 5.800 0.48604 125.782 5.900 0.50637 121.110 6.000 0.52172 115.400 FREQ MAGS11 ANGS11 0.500 0.89148 – 17.2820 0.600 0.88133 – 20.6919 0.700 0.87152 – 24.5386 0.800 0.85855 – 27.3228 0.900 0.84911 – 31.0698 1.000 0.83512 – 34.8623 1.100 0.82374 – 38.5574 1.200 0.80871 – 41.9093 1.300 0.79176 – 45.6990 1.400 0.77205 – 49.4185 1.500 0.75696 – 52.8898 1.600 0.74234 – 56.2923 1.700 0.72239 – 60.2584 1.800 0.69419 – 63.1446 1.900 0.67288 – 65.6464 2.000 0.66227 – 68.0742 2.100 0.64758 – 71.3530 2.200 0.62454 – 75.5658 2.300 0.59466 – 79.6404 2.400 0.55932 – 82.8246 2.500 0.52256 – 85.2795 2.600 0.48754 – 85.6298 2.700 0.46411 – 86.1854 2.800 0.45776 – 86.4997 2.900 0.44859 – 88.8080 3.000 0.44588 – 91.9737 3.100 0.43810 – 95.4087 3.200 0.43269 – 99.1282 KEYWORD – R IMPEDANCE /H9024 – 5 0 TPC 1. S-Parameter Data for the RF Input RF INPUT FREQUENCY – GHz 01–30 OUTPUT POWER – dB 246 –10 –25 –20 –15 VDD = 3V VP = 3V TA = +85/H11543C TA = +25/H11543C TA = –40/H11543C TPC 2. Input Sensitivity FREQUENCY –60 –2kHz OUTPUT POWER – dB –10 –50 –70 –90 –30 –40 –80 –20 2kHz900MHz–1kHz 1kHz REF LEVEL = –14.3dBm VDD = 3V, VP = 5V ICP = 5mA PFD FREQUENCY = 200kHz LOOP BANDWIDTH = 20kHz RES BANDWIDTH = 10Hz VIDEO BANDWIDTH = 10Hz SWEEP = 1.9 SECONDS AVERAGES = 10 –93.0dBc/Hz –100 TPC 3. Phase Noise (900MHz, 200kHz, and 20kHz) FREQUENCY OFFSET FROM 900MHz CARRIER 100Hz 1MHz PHASE NOISE – dBc/Hz –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 10dB/DIV RL = –40dBc/Hz RMS NOISE = 0.36 –140 TPC 4. Integrated Phase Noise (900 MHz, 200kHz, and 20 kHz) FREQUENCY –60 –400kHz OUTPUT POWER – dB –10 –50 –70 –90 –30 –40 –80 –20 400kHz900MHz–200kHz 200kHz REF LEVEL = –14.0dBm VDD = 3V, VP = 5V ICP = 5mA PFD FREQUENCY = 200kHz LOOP BANDWIDTH = 20kHz RES BANDWIDTH = 1kHz VIDEO BANDWIDTH = 1kHz SWEEP = 2.5 SECONDS AVERAGES = 30 –91.0dBc/Hz –100 TPC 5. Reference Spurs (900 MHz, 200kHz, and 20 kHz) FREQUENCY –60 –2kHz OUTPUT POWER – dB –10 –50 –70 –90 –30 –40 –80 –20 2kHz5800MHz–1kHz 1kHz REF LEVEL = –10dBm VDD = 3V, VP = 5V ICP = 5mA PFD FREQUENCY = 1MHz LOOP BANDWIDTH = 100kHz RES BANDWIDTH = 10Hz VIDEO BANDWIDTH = 10Hz SWEEP = 1.9 SECONDS AVERAGES = 10 –84.0dBc/Hz –100 TPC 6. Phase Noise (5.8GHz, 1MHz, and 100kHz)

REV. 0 –7– ADF4106 FREQUENCY OFFSET FROM 5800MHz CARRIER 100Hz 1MHz PHASE NOISE – dBc/Hz –40 –50 –140 –60 –70 –80 –90 –100 –110 –120 –130 10dB/DIV RL = –40dBc/Hz RMS NOISE = 1.8 TPC 7. Integrated Phase Noise (5.8 GHz, 1 MHz, and 100 kHz) –60 –100 –2MHz OUTPUT POWER – dB –1MHz 5800MHz 1MHz 2MHz –10 –50 –70 –90 –30 –40 –80 –20 VDD = 3V , VP = 5V ICP = 5mA PDF FREQUENCY = 1MHz LOOP BANDWIDTH = 100kHz RES BANDWIDTH = 1kHz VIDEO BANDWIDTH = 1kHz SWEEP = 13 SECONDS AVERAGES = 1 REF LEVEL = –10.0dBm –65.0dBc FREQUENCY –66.0dBc TPC 8. Reference Spurs (5.8 GHz, 1 MHz, and 100 kHz) TEMPERA TURE – C –60 –70 –100–40 100 –20 PHASE NOISE – dBc/Hz 02 0 4 0 6 0 8 0 –80 –90 VDD = 3V VP = 5V TPC 9. Phase Noise (5.8 GHz, 1 MHz, and 100kHz) vs. Temperature TUNING VOL T AGE – V –15 –105 05 1234 –45 –75 –85 –95 –25 –35 –65 –55 FIRST REFERENCE SPUR – dBc VDD = 3V VP = 5V TPC 10. Reference Spurs vs. VTUNE (5.8 GHz, 1MHz, and 100 kHz) PHASE DETECTOR FREQUENCY – Hz –120 –130 –180 10 100k 100 OUTPUT POWER – dBc/Hz 1k 10k –140 –150 –160 –170 VDD = 3V VP = 5V TPC 11. Phase Noise (referred to CP output) vs. PFD Frequency PRESCALER VALUE 8/9 64/65 16/17 AIDD – mA TPC 12. AIDD vs. Prescaler Value

REV. 0 ADF4106 –10– Table II. Latch Summary DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 C2 (0) C1 (0)R1R2R3R4R5R6R7R8R9R10R11R12R13R14ABP1ABP2T1T2LDP CONTROL BITS 14-BIT REFERENCE COUNTERTEST MODE BITS DB21DB22DB23 ANTI- BACKLASH WIDTH REFERENCE COUNTER LATCH N COUNTER LATCH X DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 C2 (0) C1 (1)A1A2A3A4A5B1B2B3B4B5B6B7B8B9B10B11B12B13 A6 CONTROL BITS6-BIT A COUNTER13-BIT B COUNTER DB21 RESERVED DB22DB23 CP GAIN DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 C2 (1) C1 (0)F1PD1M1M2M3F3P1P2 CPI1 CPI2CPI5CPI6 TC4PD2 F2 CONTROL BITS COUNTER RESET POWER- DOWN 1 MUXOUT CONTROL PD POLARITY POWER- DOWN 2 CURRENT SETTING PRESCALER VALUE TIMER COUNTER CONTROL CPI3CPI4 DB21 CURRENT SETTING TC3 TC2 TC1 DB22DB23 FASTLOCK ENABLE FASTLOCK MODE F4F5 FUNCTION LATCH DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 C2 (1) C1 (1)F1PD1M1M2M3F3P1P2 CPI1CPI2CPI5CPI6 TC4PD2 F2 CONTROL BITS COUNTER RESET POWER- DOWN 1 MUXOUT CONTROL PD POLARITY POWER- DOWN 2 CURRENT SETTING PRESCALER VALUE TIMER COUNTER CONTROL CPI3CPI4 DB21 CURRENT SETTING TC3 TC2 TC1 DB22DB23 FASTLOCK ENABLE FASTLOCK MODE F4F5 INITIALIZATION LATCH LOCK DETECT PRECISION CP THREE- STATE CP THREE- STATE RESERVED

REV. 0 ADF4106 –11– Table III. Reference Counter Latch Map LDP OPERATION

0 THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN

15ns MUST OCCUR BEFORE LOCK DETECT IS SET.

1 FIVE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN

15ns MUST OCCUR BEFORE LOCK DETECT IS SET. TEST MODE BITS SHOULD BE SET TO 00 FOR NORMAL OPERATION ABP2 ABP1 ANTIBACKLASH PULSEWIDTH 0 0 2.9ns 0 1 1.3ns 1 0 6.0ns 1 1 2.9ns X = DON’T CARE BOTH OF THESE BITS MUST BE SET TO 0 FOR NORMAL OPERATION DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 C2 (0) C1 (0)R1R2R3R4R5R6R7R8R9R10R11R12R13R14ABP1ABP2T1T2LDP CONTROL BITS14-BIT REFERENCE COUNTERTEST MODE BITS DB21DB22DB23 0 0 ANTI- BACKLASH WIDTH X LOCK DETECT PRECISION RESERVED

REV. 0 ADF4106 –12– Table IV. AB Counter Latch Map DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 C2 (0) C1 (1)A1A2A3A4A5B1B2B3B4B5B6B7B8B9B10B11B12B13 A6 CONTROL BITS6-BIT A COUNTER13-BIT B COUNTER DB21 RESERVED DB22DB23 CP GAIN THESE BITS ARE NOT USED BY THE DEVICE AND ARE DON'T CARE BITS. F4 (FUNCTION LATCH) FASTLOCK ENABLE CP GAIN OPERATION 0 0 CHARGE PUMP CURRENT SETTING

1 IS PERMANENTLY USED

0 1 CHARGE PUMP CURRENT SETTING

2 IS PERMANENTLY USED

1 0 CHARGE PUMP CURRENT SETTING

1 IS USED

1 1 CHARGE PUMP CURRENT IS SWITCHED TO SETTING 2. THE TIME SPENT IN SETTING 2 IS DEPENDENT ON WHICH FASTLOCK MODE IS USED. SEE FUNCTION LATCH DESCRIPTION A COUNTER N = BP + A, P IS PRESCALER VALUE SET IN THE FUNCTION LATCH. B MUST BE GREATER THAN OR EQUAL TO A. FOR CONTINUOUSLY ADJACENT VALUES OF (N /H11547 FREF), AT THE OUTPUT, NMIN IS (P2 - P) XX X = DON’T CARE B13 B12 B11 B3 B2 B1 B COUNTER DIVIDE RATIO

REV. 0 ADF4106 –13– Table V. Function Latch Map P2 P1 PRESCALER VALUE 0 0 8/9 0 1 16/17 1 0 32/33 1 1 64/65 CE PIN PD2 PD1 MODE

0 X X ASYNCHRONOUS POWER-DOWN

1 X 0 NORMAL OPERATION

101A S Y NCHRONOUS POWER-DOWN 111S Y NCHRONOUS POWER-DOWN CPI6 CPI5 CP14 I CP (mA) CPI3 CPI2 CPI1 3k /H9024 5.1k /H902411k/H9024 0 0 0 1.06 0.625 0.289 0 0 1 2.12 1.25 0.580 0 1 0 3.18 1.875 0.870 0 1 1 4.24 2.5 1.160 1 0 0 5.30 3.125 1.450 1 0 1 6.36 3.75 1.730 1 1 0 7.42 4.375 2.020 1 1 1 8.50 5.0 2.320 TIMEOUT TC4 TC3 TC2 TC1 (PFD CYCLES) 00003 00017 00101 1 00111 5 01001 9 01012 3 01102 7 01113 1 10003 5 10013 9 10104 3 10114 7 11005 1 11015 5 11105 9 11116 3 M3 M2 M1 000 001 010

011 DVDD

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 C2 (1) C1 (0)F1PD1M1M2M3F3P1P2 CPI1CPI2CPI5CPI6 TC4PD2 F2 CONTROL BITS COUNTER RESET POWER- DOWN 1 MUXOUT CONTROL PD POLARITY CP THREE- STATE POWER- DOWN 2 CURRENT SETTING PRESCALER VALUE TIMER COUNTER CONTROL CPI3CPI4 DB21 CURRENT SETTING TC3 TC2 TC1 DB22DB23 FASTLOCK ENABLE FASTLOCK MODE F4F5 CHARGE PUMP OUTPUT NORMAL THREE-STATE FASTLOCK MODE FASTLOCK DISABLED FASTLOCK MODE 1 FASTLOCK MODE 2 COUNTER OPERATION NORMAL R, A, B COUNTERS HELD IN RESET X OUTPUT THREE-STATE OUTPUT DIGITAL LOCK DETECT (ACTIVE HIGH) N DIVIDER OUTPUT DV DD R DIVIDER OUTPUT N-CHANNEL OPEN-DRAIN LOCK DETECT SERIAL DATA OUTPUT DGND PHASE DETECTOR POLARITY NEGATIVE POSITIVE

REV. 0 ADF4106 –14– Table VI. Initialization Latch Map P2 P1 PRESCALER VALUE 0 0 8/9 0 1 16/17 1 0 32/33 1 1 64/65 CE PIN PD2 PD1 MODE 101A S Y NCHRONOUS POWER-DOWN 111S Y NCHRONOUS POWER-DOWN CPI6 CPI5 CP14 I CP (mA) CPI3 CPI2 CPI1 3k /H9024 5.1k /H902411k/H9024 0 0 0 1.06 0.625 0.289 0 0 1 2.12 1.25 0.580 0 1 0 3.18 1.875 0.870 0 1 1 4.24 2.5 1.160 1 0 0 5.30 3.125 1.450 1 0 1 6.36 3.75 1.730 1 1 0 7.42 4.375 2.020 1 1 1 8.50 5.0 2.320 TIMEOUT TC4 TC3 TC2 TC1 (PFD CYCLES) 00003 00017 00101 1 00111 5 01001 9 01012 3 01102 7 01113 1 10003 5 10013 9 10104 3 10114 7 11005 1 11015 5 11105 9 11116 3 M3 M2 M1 000 001 010 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 C2 (1) C1 (1)F1PD1M1M2M3F3P1P2 CPI1CPI2CPI5CPI6 TC4PD2 F2 CONTROL BITS COUNTER RESET POWER- DOWN 1 MUXOUT CONTROL PD POLARITY CP THREE- STATE POWER- DOWN 2 CURRENT SETTING PRESCALER VALUE TIMER COUNTER CONTROL CPI3CPI4 DB21 CURRENT SETTING TC3 TC2 TC1 DB22DB23 FASTLOCK ENABLE FASTLOCK MODE F4F5 CHARGE PUMP OUTPUT NORMAL THREE-STATE FASTLOCK MODE FASTLOCK DISABLED FASTLOCK MODE 1 FASTLOCK MODE 2 COUNTER OPERATION NORMAL R, A, B COUNTERS HELD IN RESET X OUTPUT THREE-STATE OUTPUT DIGITAL LOCK DETECT (ACTIVE HIGH) N DIVIDER OUTPUT DV DD R DIVIDER OUTPUT N-CHANNEL OPEN-DRAIN LOCK DETECT SERIAL DATA OUTPUT DGND PHASE DETECTOR POLARITY NEGATIVE POSITIVE

REV. 0 ADF4106 –15– Fastlock Mode 2 The charge pump current is switched to the contents of Current Setting 2. The device enters Fastlock by having a “1” written to the CP Gain bit in the AB counter latch. The device exits Fastlock under the control of the Timer Counter. After the timeout period determined by the value in TC4 –TC1, the CP Gain bit in the AB counter latch is automatically reset to “0” and the device reverts to normal mode instead of Fastlock. See Table V for the timeout periods. Timer Counter Control The user has the option of programming two charge pump cur- rents. The intent is that the Current Setting 1 is used when the RF output is stable and the system is in a static state. Current Setting 2 is meant to be used when the system is dynamic and in a state of change (i.e., when a new output frequency is programmed). The normal sequence of events is as follows: Users initially decide what the preferred charge pump currents are will be. For example, they may choose 2.5 mA as Current Setting 1 and 5 mA as the Current Setting 2. At the same time they must also decide how long they want the secondary cur- rent to stay active before reverting to the primary current. This is controlled by the Timer Counter Control Bits DB14 to DB11 (TC4–TC1) in the Function Latch. The truth table is given in Table V. Now, when users wish to program a new output frequency, they can simply program the AB counter latch with new values for A and B. At the same time they can set the CP Gain bit to a “1,” which sets the charge pump with the value in CPI6 –CPI4 for a period of time determined by TC4 –TC1. When this time is up, the charge pump current reverts to the value set by CPI3 –CPI1. At the same time the CP Gain bit in the A, B Counter latch is reset to 0 and is now ready for the next time that the user wishes to change the frequency again. Note that there is an enable feature on the Timer Counter. It is enabled when Fastlock Mode 2 is chosen by setting the Fastlock Mode bit (DB10) in the Function Latch to “1.” Charge Pump Currents CPI3, CPI2, CPI1 program Current Setting 1 for the charge pump. CPI6, CPI5, CPI4 program Current Setting 2 for the charge pump. The truth table is given in Table V. Prescaler Value P2 and P1 in the Function Latch set the prescaler values. The prescaler value should be chosen so that the prescaler output frequency is always less than or equal to 300 MHz. Thus, with an RF frequency of 4 GHz, a prescaler value of 16/17 is valid but a value of 8/9 is not valid. PD Polarity This bit sets the Phase Detector Polarity Bit. See Table V. CP Three-State This bit controls the CP output pin. With the bit set high, the CP output is put into three-state. With the bit set low, the CP output is enabled. THE FUNCTION LATCH With C2, C1 set to 1,0, the on-chip function latch will be programmed. Table V shows the input data format for program- ming the Function Latch. Counter Reset DB2 (F1) is the counter reset bit. When this is “1,” the R counter and the A,B counters are reset. For normal operation this bit should be “0.” Upon powering up, the F1 bit needs to be disabled (set to “0”). The N counter then resumes counting in “close” align- ment with the R counter. (The maximum error is one prescaler cycle) . Power-Down DB3 (PD1) and DB21 (PD2) on the ADF4110 Family, provide programmable power-down modes. They are enabled by the CE pin. When the CE pin is low, the device is immediately disabled regardless of the states of PD2, PD1. In the programmed asyn- chronous power-down, the device powers down immediately after latching a “1” into bit PD1, with the condition that PD2 has been loaded with a “0.” In the programmed synchronous power-down, the device power down is gated by the charge pump to prevent unwanted frequency jumps. Once the power- down is enabled by writing a “1” into bit PD1 (on condition that a “1” has also been loaded to PD2), then the device will go into power-down on the occurrence of the next charge pump event. When a power down is activated (either synchronous or asynchronous mode including CE-pin-activated power down), the following events occur: All active dc current paths are removed. The R, N, and timeout counters are forced to their load state conditions. The charge pump is forced into three-state mode. The digital clock detect circuitry is reset. The RF IN input is debiased. The reference input buffer circuitry is disabled. The input register remains active and capable of loading and latching data. MUXOUT Control The on-chip multiplexer is controlled by M3, M2, M1 on the ADF4110 Family. Table V shows the truth table. Fastlock Enable Bit DB9 of the Function Latch is the Fastlock Enable Bit. Only when this is “1” is Fastlock enabled. Fastlock Mode Bit DB10 of the Function Latch is the Fastlock Mode bit. When Fastlock is enabled, this bit determines which Fastlock Mode is used. If the Fastlock Mode bit is “0,” Fastlock Mode 1 is selected and if the Fastlock Mode bit is “1,” Fastlock Mode 2 is selected. Fastlock Mode 1 The charge pump current is switched to the contents of Current Setting 2. The device enters Fastlock by having a “1” written to the CP Gain bit in the AB counter latch. The device exits Fastlock by having a “0” written to the CP Gain bit in the AB counter latch.

REV. 0 ADF4106 –16– THE INITIALIZATION LATCH When C2, C1 = 1, 1, the Initialization Latch is programmed. This is essentially the same as the Function Latch (programmed when C2, C1 = 1, 0). However, when the Initialization Latch is programmed there is an additional internal reset pulse applied to the R and AB counters. This pulse ensures that the AB counter is at load point when the AB counter data is latched and the device will begin counting in close phase alignment. If the Latch is programmed for synchronous power-down (CE pin is High; PD1 bit is High; PD2 bit is Low), the internal pulse also triggers this powerdown. The prescaler reference and the oscillator input buffer are unaffected by the internal reset pulse and so close phase alignment is maintained when counting resumes. When the first AB counter data is latched after initialization, the internal reset pulse is again activated. However, successive AB counter loads after this will not trigger the internal reset pulse. DEVICE PROGRAMMING AFTER INITIAL POWER-UP After initially powering up the device, there are three ways to program the device. Initialization Latch Method

• Apply VDD.
• Program the Initialization Latch ( “11” in two LSBs of input word). Make sure that F1 bit is programmed to “0.”
• Do a Function Latch load ( “10” in two LSBs of the control word), making sure that the F1 bit is programmed to a “0.”
• Do an R load (“00” in two LSBs).
• Do an AB load (“01” in two LSBs). When the Initialization Latch is loaded, the following occurs: 1. The function latch contents are loaded. 2. An internal pulse resets the R, A, B and timeout counters to load state conditions and also three-states the charge pump. Note that the prescaler bandgap reference and the oscillator input buffer are unaffected by the internal reset pulse, allow- ing close phase alignment when counting resumes. 3. Latching the first AB counter data after the initialization word will activate the same internal reset pulse. Successive AB loads will not trigger the internal reset pulse unless there is another initialization. CE Pin Method
• Apply VDD.
• Bring CE low to put the device into power-down. This is an asynchronous power-down in that it happens immediately.
• Program the Function Latch (10).
• Program the R Counter Latch (00).
• Program the AB Counter Latch (01).
• Bring CE high to take the device out of power-down. The R and AB counters will now resume counting in close alignment. Note that after CE goes high, a duration of 1 µs may be required for the prescaler bandgap voltage and oscillator input buffer bias to reach steady state. CE can be used to power the device up and down in order to check for channel activity. The input register does not need to be reprogrammed each time the device is disabled and enabled as long as it has been programmed at least once after V DD was initially applied. Counter Reset Method
• Apply VDD.
• Do a Function Latch Load ( “10” in two LSBs). As part of this, load “1” to the F1 bit. This enables the counter reset.
• Do an R Counter Load ( “00” in two LSBs).
• Do an AB Counter Load ( “01” in two LSBs).
• Do a Function Latch Load ( “10” in two LSBs). As part of this, load “0” to the F1 bit. This disables the counter reset. This sequence provides the same close alignment as the initial- ization method. It offers direct control over the internal reset. Note that counter reset holds the counters at load point and three-states the charge pump, but does not trigger synchronous power-down. APPLICATION SECTION Local Oscillator for LMDS Base Station Transmitter Figure 7 shows the ADF4106 being used with a VCO to pro- duce the LO for an LMDS base station operation in the 5.4 GHz to 5.8 GHz band. The reference input signal is applied to the circuit at FREF IN and, in this case, is terminated in 50 Ω. A typical base station system would have either a TCXO or an OCXO driving the Reference Input without any 50 Ω termination. In order to have a channel spacing of 1 MHz at the output, the

10 MHz reference input must be divided by 10, using the on-chip

reference divider of the ADF4106. The charge pump output of the ADF4106 (Pin 2) drives the loop filter. In calculating the loop filter component values, a number of items need to be considered. In this example, the loop filter was designed so that the overall phase margin for the system would be 45 degrees. Other PLL system specifications are given below: K D = 2.5 mA KV = 80 MHz/V Loop Bandwidth = 50 kHz FREF = 1 MHz N = 5800 Extra Reference Spur Attenuation = 10 dB All of these specifications are needed and used to come up with the loop filter component values shown in Figure 7. Figure 7 gives a typical phase noise performance of –83 dBc/Hz at 1 kHz offset from the carrier. Spurs are better than –62 dBc. The loop filter output drives the VCO, which, in turn, is fed back to the RF input of the PLL synthesizer and also drives the RF Output terminal. A T-circuit configuration provides 50 Ω matching between the VCO output, the RF output and the RF IN terminal of the synthesizer. Note that the ADF4106 RF input looks like 50 Ω at 5.8 GHz and so no terminating resistor is needed. When operating at lower frequencies however, this is not the case. In a PLL system, it is important to know when the system is in lock. In Figure 7, this is accomplished by using the MUXOUT signal from the synthesizer. The MUXOUT pin can be pro- grammed to monitor various internal signals in the synthesizer. One of these is the LD or lock-detect signal.

REV. 0 ADF4106 –19– OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 16-Lead Thin Shrink SO Package (TSSOP) (RU-16) 16 9 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30)PIN 1 0.201 (5.10) 0.193 (4.90) SEATING PLANE 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) BSC 0.0433 (1.10) MAX 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) 8/H11543 0/H11543 20-Leadless Frame Chip Scale Package (LFCSP) (CP-20) BOTTOM VIEW 0.080 (2.25) 0.083 (2.10) SQ 0.077 (1.95) 0.024 (0.60) 0.017 (0.42) 0.009 (0.24) 0.024 (0.60) 0.017 (0.42) 0.009 (0.24) 0.030 (0.75) 0.022 (0.60) 0.014 (0.50) 0.012 (0.30) 0.009 (0.23) 0.007 (0.18) 0.080 (2.00) REF 0.010 (0.25) MIN 0.020 (0.50) BSC 12/H11543 MAX 0.008 (0.20) REF 0.031 (0.80) MAX 0.026 (0.65) NOM 0.002 (0.05) 0.0004 (0.01) 0.0 (0.0) 0.035 (0.90) MAX 0.033 (0.85) NOM SEATING PLANE CONTROLLING DIMENSIONS ARE IN MILLIMETERS PIN 1 INDICATOR TOP VIEW 0.148 (3.75) BSC SQ 0.157 (4.0) BSC SQ

–20– C02720–.8–10/01(0) PRINTED IN U.S.A.