ADF4030BCCZ

ADF4030 AD | Alldatasheet

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10-Channel Precision Synchronizer Rev. 0 DOCUMENT FEEDBACK TECHNICAL SUPPORT Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

FEATURES

►10 BSYNC channels ►Precise BSYNC time alignment (<5 ps) ►Enables clock synchronization in large distribution networks ►Independent programmable BSYNC channel delay ►Precise path delay compensation of each BSYNC channel using bidirectional loopback capability ►Flexible physical interface supports PCB trace or cable connec- tions with DC or AC coupling ►Each BSYNC channel supports gapped periodic clocking ►Integrated TDC ►Integrated temperature sensor

APPLICATIONS

►5G timing transport high precision synchronization ►Phased array radar ►Automatic test equipment (ATE) pin electronics ►JESD204B/JESD204C support for analog-to-digital converter (ADC) and digital-to-analog converter (DAC) clocking FUNCTIONAL BLOCK DIAGRAM Figure 1. Functional Block Diagram those devices support bidirectional clock exchanges). clocks arriving at the inputs. The RMS jitter of one ADF4030 BSYNC clock is 4.3 ps typical. Throughout the data sheet, the letter x is used to mean any integer.

analog.com Rev. 0 | 2 of 86 Differential Time-to-Digital Converter (dTDC).. 22 Maximum BSYNC Frequency Reduction vs.

REVISION HISTORY

10/2024—Revision 0: Initial Version

VDD18x = 1.8 V, VDD33x = 3.3 V, and TA = 25°C, unless otherwise noted. Table 1. Specifications

100 MHz with driver current at 14 mA and one BSYNCx

100 MHz with driver current at 14 mA, one BSYNCx

Table 1. Specifications (Continued)

1.8 V Supplies 2 500 μA IVDD18_DIG + IVDD18_TDC

1.85 V Provided for information only; AC coupling is

0.35 V to 1 V or ΔVCMI < 75 mV12

1 Digital core clock frequency. 3 Channel not selected as TDC source or target. 5 PD_TX_PATH_x = 1, AC_COUPLEDx = 1. 6 PD_TX_PATH_x = 0, PD_DRV_x = 1. 7 PD_TX_PATH_x = 0, PD_DRV_x = 0, EN_DRVx = 0. 8 PD_TX_PATH_x = 0, PD_DRV_x = 0, EN_DRVx = 1. 9 PD_TX_PATH_x = 0, PD_DRV_x = 0, EN_DRVx = 1, BOOSTx = 1. 10 Channel selected as TDC source or target.

Table 3. Absolute Maximum Ratings

1 Device is guaranteed to meet the specified performance limits over the full

operating junction temperature range. the latest revision of this standard. ing conditions for extended periods may affect product reliability. natural convection JEDEC environment. junction-to-top of case and junction-to-bottom of case, respectively. θJB is the junction-to-board JEDEC thermal resistance. Table 4. Thermal Resistance

1 Test Condition: thermal impedance simulated values are based on use of a

6-layer PCB with the thermal impedance paddle soldered to a ground plane. (CDM) per ANSI/ESDA/JEDEC JS-002. Table 5. ADF4030, 48-Terminal LGA damage may occur on devices subjected to high energy ESD. performance degradation or loss of functionality.

Figure 5. Pin Configuration Table 6. Pin Function Descriptions 1 BSYNC0– I/O Complementary Bidirectional Clock, Channel 0. 2 BSYNC0+ I/O Normal Bidirectional Clock, Channel 0. 3 VDD33_BS0 Power 3.3 V Supply to BSYNC Channel 0. 4 BSYNC1– I/O Complementary Bidirectional Clock, Channel 1. 5 BSYNC1+ I/O Normal Bidirectional Clock, Channel 1. 6 VDD33_BS1 Power 3.3 V Supply to BSYNC Channel 1. 7 BSYNC2– I/O Complementary Bidirectional Clock, Channel 2. 8 BSYNC2+ I/O Normal Bidirectional Clock, Channel 2. 9 VDD33_BS2 Power 3.3 V Supply to BSYNC Channel 2. 10 BSYNC3– I/O Complementary Bidirectional Clock, Channel 3. 11 BSYNC3+ I/O Normal Bidirectional Clock, Channel 3. 12 VDD33_BS3 Power 3.3 V Supply to BSYNC Channel 3. 13 BSYNC4– I/O Complementary Bidirectional Clock, Channel 4. 14 BSYNC4+ I/O Normal Bidirectional Clock, Channel 4. 15 VDD33_BS4 Power 3.3 V Supply to BSYNC Channel 4. pull-down resistors. Tie ADDR0 to GND, 1.8 V, or 3.3 V to define the Bit A[9] in the SPI instruction word (see Figure 48). ADDR1 to GND, 1.8 V, or 3.3 V to define the Bit A[10] in the SPI instruction word (see Figure 48). 18 REFIN+ I Normal Reference Clock Input. 19 REFIN– I Complementary Reference Clock Input. 20 VDD33_PLL Power 3.3 V Supply to PLL. ADDR2 to GND, 1.8 V, or 3.3 V to define the Bit A[11] in the SPI instruction word (see Figure 48). 22 VDD33_BS5 Power 3.3 V Supply to BSYNC Channel 5. 23 BSYNC5– I/O Complementary Bidirectional Clock, Channel 5. 24 BSYNC5+ I/O Normal Bidirectional Clock, Channel 5. 25 VDD33_BS6 Power 3.3 V Supply to BSYNC Channel 6. 26 BSYNC6– I/O Complementary Bidirectional Clock, Channel 6. 27 BSYNC6+ I/O Normal Bidirectional Clock, Channel 6. 28 VDD33_BS7 Power 3.3 V Supply to BSYNC Channel 7. 29 BSYNC7– I/O Complementary Bidirectional Clock, Channel 7.

Table 6. Pin Function Descriptions (Continued) 30 BSYNC7+ I/O Normal bidirectional clock, Channel 7. 31 VDD33_BS8 Power 3.3 V Supply to BSYNC Channel 8. 32 BSYNC8– I/O Complementary Bidirectional Clock, Channel 8. 33 BSYNC8+ I/O Normal Bidirectional clock, Channel 8. 34 VDD33_BS9 Power 3.3 V Supply to BSYNC Channel 9. 35 BSYNC9– I/O Complementary Bidirectional Clock, Channel 9. 36 BSYNC9+ I/O Normal Bidirectional Clock, Channel 9. 37 GND Power Ground Connection. 38 IRQB O Interrupt Request. Programmable output mode and selectable internal interrupt source. 39 VDD33_TDC Power 3.3 V Supply to Differential TDC. 40 CS I Serial Port Chip Select. 1.8 V or 3.3 V compatible CMOS input. Bidirectional for 3-wire SPI mode. Input only for 4-wire SPI mode. 42 SCLK I Serial Port Clock. 1.8 V or 3.3 V compatible CMOS input. 44 VDD18_DIG Power 1.8 V Supply to Digital Core. 45 MUXOUT1 O Access to Various Internal Test Points (programmable). 46 MUXOUT2 O Access to Various Internal Test Points (programmable). ADDR3 to GND, 1.8 V, or 3.3 V to define the Bit A[12] in the SPI instruction word (see Figure 48). 48 VDD18_TDC Power 1.8 V Supply to Differential TDC. EPAD Power Primary Ground Connection. 1 I/O is input/output, I is input, and O is output.

SPI Broadcast Mode section for more details. Figure 18. ADF4030 Programming Sequence After Power Up ADF4030 registers to be written in the shortest amount of time. from Address 0x72 and ending with Address 0x10. Table 7. Registers with Nonzero Values Initialized After Power Up

Figure 19. Detailed Block Diagram from an external frequency source applied at the REFIN input. fVCO must be in the range of 2.5 GHz ±5%. fREFIN/RDIV must be in the range of 10 MHz to 20 MHz. Table 8. ODIV Selection value selection per Table 8. output frequency other than the frequency associated with ODIVA. = NDIV/RDIV (under the constraint that NDIV/RDIV is an integer). clock on BSYNC channels using ODIVB. like fanning out the REFIN clock.

time base for those functions that rely on the digital core clock. the REFIN frequency by 2CORE_CLK_DIV to less than 125 MHz. selected as the clock source for the digital core clock (≈ 44 MHz). REFIN frequency source, hence the approximate value of 44 MHz. possible values per Equation 3.

2 CO RE C L K D I V , for SEL_DIGCLK=0

fRO is the TDC ring oscillator frequency (≈ 700 MHz). fREFIN is the frequency of the clock applied to the REFIN pins. CORE_CLK_DIV is 0, 1, 2, or 3. compatible signals, independent of the state of CMOS_OV bit. signals. See the SPI Operation section for more details. template for all BSYNC channels. Figure 24. BSYNC Channel Diagram the BSYNC channel (see the Device Overview section for details).

Programmable Power Down Options section) to save power. Figure 28. BSYNC Terminations Diagram the Transmit and Receive Interface section). Table 9. Transmit Configurations configuration is voltage driver. channel) reside in the odd register addresses from 0x3F to 0x51. differential voltage driver configuration as shown in Figure 29.

Table 10. Receive Configurations Figure 33. BSYNC Receive Configurations Diagram

Figure 43. TDC Postprocessor Diagram time stamps is around tTDC ≈ 86 ps. Table 11. TDC Measurement Averaging

1 The tabulated values of σMEAS are based on tTDC = 86 ps, which varies with

2 AVGEXP = 14 requires fBSYNC ≥ 1 MHz for gapped periodic clocks.

3 AVGEXP = 15 requires fBSYNC ≥ 1 MHz for nongapped periodic clocks and

fBSYNC ≥ 2 MHz for gapped periodic clocks. 1σ measurement repeatability of 59 fs rms given ideal input signals. ps rms) may be sufficient for making the measurement. relative to the nongapped clock case.

of time stamp samples to guarantee a valid phase error result. degrades the σMEAS, especially for fBSYNC ≤ 80 MHz. clock signal (see the TDC Input Clock Signal Assignment section). to just below +180° with a resolution of 21.46 μ°). clock lags the target clock. Figure 44. TDC Measurement (TDC_RSLT_UI) Sign relationship between the source and target clock signals. target clock selection use the same code scheme. Table 12. Selection Codes (Source and Target)

0 RX0: Output of BSYNC0 receiver

1 RX1: Output of BSYNC1 receiver

2 RX2: Output of BSYNC2 receiver

3 RX3: Output of BSYNC3 receiver

4 RX4: Output of BSYNC4 receiver

5 RX5: Output of BSYNC5 receiver

6 RX6: Output of BSYNC6 receiver

7 RX7: Output of BSYNC7 receiver

8 RX8: Output of BSYNC8 receiver

9 RX9: Output of BSYNC9 receiver

26 Output of REFIN receiver

ment. Excessive drift will cause the TDC to flag an error.

analog.com Rev. 0 | 25 of 86 If the TDC error monitor triggers an error during a TDC conversion, the error is latched into Bits[2:1], TDC_ERR, in Register 0x90. ►TDC_ERR = 00, the TDC measurement does not present any error. ►TDC_ERR = 01, at least one TDC input clock presents excessive jitter. ►TDC_ERR = 10, at least one TDC input clock is not present, is outside the allowed duty cycle range, or the frequency is much higher than 200 MHz. ►TDC_ERR = 11, excessive phase shift happened during the TDC measurement. This situation may appear when the TDC input clocks have different frequencies or when the TDC input clocks have too much jitter. When the TDC_ERR bits become set, they remain as such until the TDC error monitor is reset using the following procedure: ►Set Bit 7, RST_TDC_ERR, in Register 0x61 to 1 ►Clear the RST_TDC_ERR bit to 0 Before a TDC Measurement is started, reset the TDC error monitor. The TDC_ERR bits can be or-ed and reflected at the MUXOUT1 and MUXOUT2 pins. See the MUXOUT1 and MUXOUT2 section. The TDC_ERR output at MUXOUT1 or MUXOUT2 pins is not latched. MEASUREMENT TIME ESTIMATION As described in the TDC Time Stamp Averaging section, a com- plete TDC time difference measurement is the result of averaging many individual TDC time difference sample measurements. Be- cause each sample occurs at the rate of the measured clock signal, the time required for the TDC to perform a complete time offset measurement depends on the frequency (fBSYNC) of the measured clock signal and the specified number (AVG) of individual time offset measurements as shown in the following equation: Measurement Time = A VG f BSY NC = 64 × 2 AVG E XP f BS YN C DUTY CYCLE MEASUREMENT A duty cycle measurement implies measuring a single clock signal. Because the TDC requires two clock input signals, the same clock source as both the source clock and target clock must be assigned (see the TDC Input Clock Signal Assignment section). That is, the same 5-bit selection code is programmed into the register map for both source and target. In addition, the TDC must be set to use the rising edge of the target clock signal and the falling edge of the source clock signal. A TDC measurement configured in this way yields a result (see the TDC Results section) that indicates the DC duty cycle as follows: DC = T DC _ RS LT _ U I 2 24 × 100 % MAXIMUM BSYNC FREQUENCY REDUCTION VS. DUTY CYCLE When the ODIV divider in a BSYNC channel uses an odd divide value, the resulting output clock signal exhibits non-50% duty cycle (int(ODIV/2)/ODIV). The amount of duty cycle deviation from 50% depends on the divide value (smaller divide values result in larger deviation). The duty cycle of the signal can affect the ability of the TDC to perform an accurate measurement. Because of the likely possibility of a BSYNC channel generating a non-50% duty cycle clock signal, the effect on the TDC must be taken into consideration. Notably, the maximum BSYNC frequency (fBSYNC) listed in the specifications table assumes a signal with 48% to 52% duty cycle. When fBSYNC is at the specified maximum (see the Specifications section) and the BSYNC signal is not 48% to 52% duty cycle, the TDC is not guaranteed to complete a measurement. As such, for BSYNC signals that do not satisfy the 48% to 52% duty cycle requirement, the maximum fBSYNC specification must be degraded per Equation 11. f BSY NC _ M A X _ A D J = D CF × f BSY NC _ M A X (11) where: fBSYNC_MAX_ADJ is the adjusted maximum frequency based on the duty cycle. fBSYNC_MAX is the maximum BSYNC frequency (200 MHz) per the specifications table. See the Specifications section. DCF is a duty cycle correction factor between 0 and 1. The value of DCF, given below, relates to DC (the duty cycle of the BSYNC signal per the Duty Cycle Measurement section), where 0 < DC < 1. ►DCF = DC/0.48 when DC < 0.48 ►DCF = (1 − DC)/0.48 when DC > 0.52 ►DCF = 1 otherwise A non-50% duty cycle signal can significantly reduce the specified maximum fBSYNC. For example, a BSYNC signal that exhibits a duty cycle of 25% (DC = 0.25) yields a 52% reduction of the maximum specified fBSYNC. TEMPERATURE MEASUREMENT SYSTEM The temperature measurement system contains a proportional to ambient temperature (PTAT) circuit, an ADC, and a code-to-temper- ature converter (CTC) (Figure 45). Ideally, the PTAT circuit gener- ates a voltage that varies linearly with the silicon die temperature in its vicinity. The CTC output, that is the temperature measurement, is expressed in °C. There is also a temperature monitor that keeps track of the temperature change relative to a reference temperature (see the Interrupt Request (IRQ) section for details). The purpose of the temperature measurement system is to measure changes in die temperature, not the absolute junction temperature.

analog.com Rev. 0 | 26 of 86 A temperature measurement is only possible when the ADC is con- figured for proper operation. First, initialize the ADF4030 (see the Device Initialization section). Then, ensure the following conditions are met: ►Bit 0, EN_ADC, in Register 0x61 is set to 1 (ADC enabled) ►Bit 4, PD_ADC, in Register 0x3C is cleared to 0 (the ADC is not explicitly powered down) ►A valid ADC clock signal (ADCCLK) is present When the EN_ADC bit is cleared to 0, the ADC is disabled, and the PTAT circuit is powered down. When the PD_ADC bit is set to 1, that is when the ADC is powered down, the EN_ADC bit may be left equal to 1. Bit 6, ADC_CLK_SEL, in Register 0x61 selects how the ADC clock is created. When the ADC_CLK_SEL bit is cleared to 0 (default), a clock derived from the digital core clock is used. When the ADC_CLK_SEL bit is set to 1, a clock provided at the SCLK pin is used. The frequency of the ADCCLK signal must be ≤400kHz. If the source of the ADCCLK clock is >400 kHz, divide it down using the divider K in Register 0x62. The divider value, K, must be an integer that satisfies Equation 12. K ≥ f C ORE CL K 1 . 6 × 10 6 − 1 2 (12) where: fCORECLK is the frequency of the digital core clock (see the Digital Core Clock section). Programming Register 0x62 = K (assuming 1 ≤ K ≤ 255) ensures that fADCCLK ≤ 400kHz. The ADC clock frequency relates to the integer K per Equation 13. f ADC C LK = f CO REC L K 4 × K + 2 (13) To enable the ADC clock, set Bit 1, EN_ADC_CLK, in Register 0x61 to 1. This allows the clock selected by the ADC_CLK_SEL bit to pass on to the ADC circuitry. The ADC only performs a temperature measurement when trig- gered, which results from writing any 8-bit value to Register 0x72. Enable the trigger function by setting Bit 2, EN_ADC_CNV, in Register 0x61 to 1. Upon triggering, the ADC requires 17 cycles of ADCCLK to complete a temperature measurement. As such, the minimum time required for the ADC to make a temperature measurement (tADC_MEAS) is given by Equation 14. t ADC _ ME AS = 17 f AD CC L K (14) Therefore, the minimum time to perform a temperature measure- ment is 42.5 μs, which is obtained when fADCCLK = 400 kHz. While the ADC is performing a temperature measurement, a busy status is indicated by Bit 1, ADC_BUSY, in Register 0x8F being set to 1. When the ADC is triggered to take a temperature measurement, the CTC stores the temperature result in the form of sign and magnitude. The 8-bit magnitude of the CTC result resides in Regis- ter 0x92 and has units of °C (that is, the measurement resolution is 1°C). For example, if Register 0x92 = 0x3C (60 decimal), the magnitude of the temperature is 60°C. The sign of the CTC result resides in Bit 0 of Register 0x93, which means the temperature is positive when the bit is 0 and is negative when the bit is 1. Temperature results from the CTC are monitored by the tempera- ture monitor block. The temperature monitor provides a mechanism to notify the user (via the IRQB pin) when the temperature changes by a prescribed amount (see the Interrupt Request (IRQ) section for details). After the ADF4030 has been initialized (see the Device Initialization section), the procedure to execute a temperature measurement is as follows: 1. Write K divider value in Register 0x62 2. Initialize Bit 6, ADC_CLK_SEL, in Register 0x61 to desired value 3. Set Bit 1, EN_ADC_CLK, in Register 0x61 to 1 4. Set Bit 2, EN_ADC_CNV, in Register 0x61 to 1 5. Set Bit 0, EN_ADC, in Register 0x61 to 1 (Bit 6, Bit 2, Bit 1, and Bit 0 in Register 0x61 may be written simultaneously) 6. Clear Bit 4, PD_ADC, in Register 0x3C to 0 7. Write any 8-bit value to Register 0x72 8. Monitor Bit 1, ADC_BUSY, in Register 0x8F until it becomes 0 9. Read Bit 0 of Register 0x93 and Register 0x92 to obtain the temperature result The recommendation is to use the core clock to clock the ADC while the ADF4030 is fully functional (ADC_CLK_SEL bit cleared to 0). If the ambient temperature measurement is desired, power down the ADF4030 circuits, with the exception of the ADC, for the die temperature to become equal to the ambient. Clock the ADC from the SCLK pin (ADC_CLK_SEL bit set to 1). Set the divider K to a value that ensures the ADCCLK clock is <400 kHz. A nonzero K divider value means more SPI SCLK cycles are required to obtain the 17 ADCCLK cycles. Read the Register 0x8F as many times is necessary to create 17 ADCCLK cycles. The additional SCLK cycles do not matter. For example, if the SCLK frequency is 75 MHz, the K divider must be at least 47, which means ADCLK ~ 395 kHz. To create 17 ADCCLK cycles, there must be 17 × (4 × 47 + 2) = 3230 SCLK cycles, so the Register 0x8F must be read 135 times or 10 SCLK cycles more than necessary (10 = 135 × 24 − 3230). The last 10 SCLK cycles do not matter. If instead the SCLK is reduced to 800 kHz and the K divider is set to 0, the ADCCLK is 400 kHz. To create 17 ADCCLK cycles, there must be 17 × 2 = 34 SCLK cycles, meaning the Register 0x8F must be read twice, 14 SCLK cycles more than necessary (14 = 2 × 24 − 34). The last 14 SCLK cycles do not matter.

Figure 45. Temperature Measurement System Block Diagram logic high level associated with 1.8 V, pull up the resistor to 1.8 V. circuit does not generate an interrupt, and the interrupt is masked. generate an interrupt if the mask bit is set to 1. are responsible for asserting the IRQB pin.

Figure 46. IRQ Block Diagram status indication of the PLL lock detect IRQ. temperature IRQ via Bit 5, RST_TEMP, in Register 0x5C. will establish a new TREF value. Temperature Measurement System section). alignment between various BSYNC channels. Set the 8-bit unsigned ALIGN_IRQ_TH threshold in Register 0x5D.

analog.com Rev. 0 | 29 of 86 Activate the monitoring by clearing Bit 6, RST_ALIGN_IRQ, in Register 0x5C to 0. After power up or reset, the recommendation is to set the RST_ALIGN_IRQ to 1, meaning the monitoring is inactive (see the Device Initialization section). If monitoring needs to be stopped, set the RST_ALIGN_IRQ bit to 1. To start a new monitoring cycle, reset the monitor by setting the RST_ALIGN_IRQ to 1 and then clearing it to 0. Every time an alignment procedure is executed (any procedure presented in the BSYNC Channel Alignment section), the mon- itor accumulates the delay that the alignment procedure can- cels. When the accumulated error becomes greater than the ALIGN_IRQ_TH threshold on a certain BSYNC channel, the IRQ_BSYNC[9:0] bit corresponding to that BSYNC channel be- comes 1.The IRQ_BSYNC[9:2] bits are Bits[7:0] in Register 0x91, and the IRQ_BSYNC[1:0] are Bits[7:6] in Register 0x90. Enable the interrupt by setting Bit 2, MASK_ALIGN_IRQ, in Register 0x5C to 1. Disable the interrupt by clearing the MASK_ALIGN_IRQ to 0. TDC Error Monitor IRQ The TDC error monitor interrupt line is shared with the ADEL overflow interrupt. The TDC error monitor is a logical OR of Bits[2:1], TDC_ERR, in Register 0x90 (see the TDC Status section for details on these bits). A zero to one transition by the TDC error monitor latches a TDC error IRQ flag that constitutes the TDC ERR + TEMP ALIGN ERR IRQ signal in Figure 46. Activate the monitoring be clearing Bit 7, RST_TDC_ERR, in Register 0x61 to 0. After power up or reset, the recommendation is to set the RST_TDC_ERR to 1, meaning the monitoring is inactive (see the Device Initialization section). If monitoring needs to be stopped, set the RST_TDC_ERR bit to 1. To start a new monitoring cycle, reset the monitor by setting the RST_TDC_ERR to 1 and then clearing it to 0. Enable (mask) the interrupt by setting Bit 4, MASK_TDC_ERR, in Register 0x5C to 1. Disable (unmask) the interrupt by clearing the MASK_TDC_ERR to 0. When the interrupt is triggered, check the TDC_ERR bits to understand if the interrupt has been triggered by the TDC error monitor. If the TDC_ERR bits are 00, it signifies that an interrupt was generated by the temporary alignment error interrupt. Temporary Alignment Error IRQ The temporary alignment error interrupt line is shared with the TDC error monitor interrupt. Enable the temporary alignment error interrupt using the same Bit 4, MASK_TDC_ERR, in Register 0x5C (see the TDC Error Monitor IRQ section). If the ADF4030 executes one of the alignment procedures that have a closed-loop delay adjustment at the core (see the Applications Information section) and an additional alignment is required due to the temperature drift, most closed-loop delay adjustments change the ADEL_x setting only. In this case, the temperature drift may eventually exhaust the ADEL typical ~88 ps range, requiring a coarse adjustment along the ADEL_x. The adjustment may create a temporary phase offset between the BSYNC channels of up ±15 ps, and the ADF4030 signals this as a temporary alignment error. During the single-channel alignment procedure (see the Single- Channel Alignment section), the temporary alignment error monitor flag is Bit 3, TMP_ALIGN_ERR, in Register 0x90. If a temporary alignment error happened, the TMP_ALIGN_ERR becomes 1. During the fixed iteration alignment procedure (see the Fixed Iter- ation Alignment section), the TMP_ALIGN_ERR flag becoming 1 signifies that a temporary alignment error occurred during the last iteration. During the threshold alignment procedure (see the Threshold Align- ment section), the TMP_ALIGN_ERR flag becomes 1 if the align- ment process reaches the maximum number of alignment cycles (ALIGN_CYCLES + 1) without the alignment becoming less than the AUTO_ALIGN_THOLD threshold. To reset the TMP_ALIGN_ERR flag and reduce the alignment error, execute the alignment procedure again. During the serial alignment process in which multiple BSYNC channels are aligned (see the Serial Alignment section), ev- ery BSYNC channel has an assigned temporary alignment error monitor flag within the TMP_ALIGN_ERR_CH[9:0] field. The TMP_ALIGN_ERR_CH[0] corresponds to the BSYNC0 chan- nel, the TMP_ALIGN_ERR_CH[1] corresponds to the BSYNC1 channel, continuing to the TMP_ALIGN_ERR_CH[9] correspond- ing to the BSYNC9 channel. Register 0xCA bits contain the TMP_ALIGN_ERR_CH[7:0] bits, and Bits[1:0] of Register 0xCB contain the TMP_ALIGN_ERR_CH[9:8] bits. When a temporary alignment error occurs on one or multiple BSYNC channels, the Bit 3, TMP_ALIGN_ERR, in Register 0x90 is set to 1 and latches the corresponding TMP_ALIGN_ERR_CH bits to identify which channels triggered the interrupt. In such case, to resolve the temporary alignment errors, execute a single-channel alignment procedure on the channels that triggered the interrupt to clear the TMP_ALIGN_ERR and the affected TEMP_ALIGN_ERR_CH. The temporary alignment error monitor does not work when the background serial alignment procedure is executed. MUXOUT1 AND MUXOUT2 The MUXOUT1 and MUXOUT2 pins provide access to various sig- nals within the ADF4030. The user selects which internal signal is to be presented at the pin via a 5-bit code. Bits[4:0], MUXCODE1, of Register 0x63, associate with the MUXOUT1 pin, and Bits[4:0], MUXCODE2, of Register 0x64 associate with the MUXOUT2 pin. Table 13 presents the available selections of MUXCODE1 and MUXCODE2 bits. When the TDC is used, do not set MUXCODE1 and MUXCODE2 bits to 28, providing the TDC input clocks at the MUXOUT pins. This setting should only be used as a debug tool to verify signals.

Table 13. MUXCODE1 and MUXCODE2 Bit Selections 1 Digital core clock (see Figure 23) divided by 2. 2 Period clock (see Figure 43) divided by 2. 3 State of Bit 1, ADC_BUSY, of Register 0x8F. 4 State of Bit 4, TDC_BUSY, of Register 0x8F. 5 State of Bit 3, DL_BUSY, of Register 0x8F. 6 State of Bit 0, FSM_BUSY, of Register 0x8F. 7 PLL PFD input clock from the NDIV divider divided by 2. 8 PLL PFD input clock from the RDIV divider divided by 2. 18 State of Bit 0, PLL_LD, of Register 0x90. 19 State of Bit 1, CAL_COMP, of Register 0xBA. 20 State of Bit 0, CAL_BUSY, of Register 0xBA.

23 Logical OR of the live (not latched) TDC error signals associated

with Bits[2:1], TDC_ERR, of Register 0x90.

28 TDC source clock for MUXOUT1 pin and TDC target clock for

To power down the entire IC, set Bit 7, PD_ALL, in Register 0x3C. 5, PD_TDC, in Register 0x3C to 1. ered down by setting Bit 4, PD_ADC, in Register 0x3C to 1. channel without losing the alignment data in the analog delay block. 0x3B. The PD_TX_PATH_9, 8, …, 6 are Bits[3:0] in Register 0x3C. set to 1, the state of the corresponding PD_DRV_x bit is ignored. the PD_DRV_x bit is set to 1.

Table 14. ADF4030 Power Down Modes 1 Don't care. Value can be 0 or 1. Table 15 clarifies what the AUTO_PD_RCV_x and AUTO_PD_COMP_x, bits mean overall. Table 15. Power Down BSYNCx Receiver Modes

0 Not Selected 1 BSYNCx not selected as a TDC input, receiver pow-

1 Not Selected 0 BSYNCx not selected as a TDC input, receiver pow-

2 Selected -1 BSYNCx selected as a TDC input, receiver powered up

1 Don't care. Value can be 0 or 1.

SDO enter a high impedance state. 3.3 V CMOS inputs with no internal pull-up or pull-down resistors.

3.3 V to establish the memory page associated with a specific

the bits relate to the SCLK pulses that follow the instruction word. Figure 47. SPI Communication Cycle Diagram

remainder of the SPI communication cycle. following the falling edge of the CS signal denotes the R/W bit. successive address bits in descending order. Figure 48. Instruction Word Diagram leftmost bit becomes A0 and the rightmost bit becomes R/W. address locations) to a particular ADF4030. write operations are ignored. cleared to 0000, independent of the ADDR pin code. regardless of the ADDR pin code. group comprising less than eight bits is ignored. 4-wire mode, respectively (see the SPI Pin Descriptions section). according to the programmed mode.

1. Select the source of the digital core clock (see the Digital Core

the ADF4030 may function as a stand alone TDC.

1. Initialize Bits[3:0], AVGEXP, in Register 0x16. This procedure

urements to produce a result.

1. Set Bit 7, MANUAL_MODE, in Register 0x11 to 1 to enable a
2. Initialize Bits[4:0], TDC_Target, in Register 0x10 to select which

BSYNC channel is the TDC target clock.

1. Initialize Bits[4:0], TDC_Source, in Register 0x11 to select

which BSYNC channel is the TDC source clock.

1. Initialize Bits[7:6], FALL_EDGE_SRC and FALL_EDGE_TGT, in

target clocks used by the TDC.

1. Reset the TDC_ERR monitor bits by setting Bit 7,
2. Set Bit 7, TDC_ARM_M, in Register 0x16 to 1 to start the TDC
3. Monitor Bit 4, TDC_BUSY, in Register 0x8F. It stays 1 while

urement error (see the TDC Status section). presents the delay adjustment process. Figure 52. Open-Loop Delay Adjustment Process NDEL_COAR = DELTA_NDEL_COAR + existing NDEL_COAR. the DL_BUSY status Bit 3 in Register 0x8F.

done in steps of approximately 400 ps (one fVCO period). delay adjustment operation and goes to 0 when the operation ends. procedures to align BSYNC clocks to the desired delay. ns, the TDC_OFFSETx is all that is needed.

2.5 GHz), good to phase shift the minimum BSYNC frequency of

iterating the TDC measurement and the delay adjustment. Figure 53. Closed-Loop Delay Adjustment Process

analog.com Rev. 0 | 37 of 86 BSYNC CHANNEL ALIGNMENT Alignment is the recommended procedure to introduce a desired time delay between the ADF4030 BSYNC clocks. The ADF4030 can align one target BSYNC clock to a source BSYNC clock, and this procedure is called single-channel alignment. The ADF4030 can serially align multiple target BSYNC clocks to a source BSYNC clock, and this procedure is called serial alignment. Use these procedures to introduce time adjustments that compensate the propagation delays of BSYNC clocks. The alignment procedures use the closed-loop delay adjustment data path to achieve the desired alignment. Single-Channel Alignment To execute a single-channel alignment, the following steps must be executed: 1. Set Bits[7:5], ALIGN_CYCLES, in Register 0x37 to 000. This setting executes one alignment cycle only. 2. Clear Bit 2, EN_SERIAL_ALIGN, in Register 0x37 to 0 to disable a serial alignment. 3. Set Bit 6, EN_ALIGN, in Register 0x11 to 1 to enable the single-channel alignment. 4. Clear Bit 7, MANUAL_MODE, in Register 0x11 to 0 to disable the manual TDC measurement. 5. Initialize Bits[3:0], AVGEXP, in Register 0x16. This procedure represents the TDC averaging number of samples. The bigger the number, the more accurate the TDC measurement. The initialization procedure (see the Device Initialization section) sets this to six, which means the TDC averages 4096 measure- ments to produce a result. 6. Initialize Bits[4:0], TDC_SOURCE, in Register 0x11 to select which BSYNC channel is the TDC source clock. 7. Initialize Bit 5, TDC_CLK_SEL, in Register 0x11 to select TDC source clock or the TDC target clock as the period clock. 8. Initialize Bits[7:6], FALL_EDGE_SRC and FALL_EDGE_TGT, in Register 0x15 to select the clock edge of the TDC source and target clocks used by the TDC. 9. Set the desired time delay in Bits [15:0], TDC_OFFSETx, sign- ed register that corresponds to the target BSYNC channel. Also use Bits[20:0], TDC_OFFSET_COM, signed register if necessary (see Closed-Loop Delay Adjustment section). The bit weight of these registers is ~1/fVCO/29, that is 0.78125 ps when fVCO = 2.5 GHz. 10.Initialize Bits[4:0], TDC_TARGET, in Register 0x10 to select which BSYNC channel is the TDC target clock. This starts the alignment procedure. 11.Monitor Bit 0, FSM_BUSY, in Register 0x8F. The signal stays 1 while the ADF4030 executes the alignment and clears to 0 when the alignment ends. 12.Verify Bits[2:1], TDC_ERR, in Register 0x90 are 00 (see the TDC Status section). If not, repeat the procedure starting with Step 10. 13.Verify Bit 3, TMP_ALIGN_ERR, in Register 0x90 is cleared to 0 (see the Temporary Alignment Error IRQ section). If not, repeat the procedure starting with Step 10. 14.Optionally, execute a TDC measurement between the BSYNC channels object to the alignment to verify the achieved align- ment error is below 1.4 ps, the bit weight of the ADEL_x bits. If the achieved phase delay error is greater than 1.4 ps or an even better result is desired, the alignment process may be repeated. Repeat execution of the procedure starting from Step 10. Instead of executing these last five steps again, the ADF4030 offers the following two ways of repeating the single-channel alignment: repeat the alignment process until the alignment becomes better than a threshold, which is called threshold iteration alignment, or repeat the alignment process for a fixed number of times, which is called fixed number of iterations alignment. A gapped periodic clock can only be aligned to a nongapped periodic clock. The recommended alignment procedure follows: ►Measure the time difference between the gapped clock and the nongapped clock. ►If the time difference is ≥+350 ps, execute the single-channel alignment procedure. The resultant alignment error is within ± 5 ps at room temperature. ►If the time difference is <+350 ps, including negative values, the resultant alignment error may be bigger. In this case, generate a nongapped periodic clock first, instead of a gapped one. Align it to the nongapped periodic clock of the same frequency. Then, generate the gapped clock again. This introduces an additional approximate alignment error of ± 3 ps at room temperature. Threshold Alignment The threshold alignment procedure repeats the alignment until either the alignment becomes lower than a desired threshold or the alignment cycles reach the maximum number of alignment cycles stored in the ALIGN_CYCLES bit field. The following steps must be executed: 1. Set Bits[5:0], ALIGN_THOLD, in Register 0x35 to the desired alignment threshold. The adjustment weight of the LSB is equal to the LSB weight of the ADEL_x bits, that is approxi- mately 1.4 ps. ALIGN_THOLD = 1 is the recommended align- ment threshold. If the system is relatively noisy, increase the ALIGN_THOLD value only. 2. Initialize Bits[7:5], ALIGN_CYCLES, in Register 0x37 with the desired maximum number of alignment cycles to be executed minus one. The maximum allowed number of iterations is eight. 3. Initialize Bit 1, EN_CYCS_RED, in Register 0x37 to decide how many averages of the TDC time stamps are executed each iteration as follows:

analog.com Rev. 0 | 38 of 86 ►If EN_CYCS_RED = 0, every alignment cycles uses A VG = 64 × 2 AV GE XP the TDC time stamps (see also TDC Time Stamp Averaging section for more details on the AVGEXP). ►If EN_CYCS_RED = 1, the first alignment cycle uses A VG = 64 × 2 AV GE XP − AL I G N _ C YC L ES the TDC time stamps. Each successive alignment cycle uses a number of the TDC time stamps equal to the previous cycle AVG multiplied by 2. 4. Set Bit 0, EN_ITER, in Register 0x37 to enable the threshold alignment. 5. Execute the steps of the single-channel alignment procedure. Fixed Iteration Alignment The fixed iteration alignment procedure repeats the alignment for the number of cycles stored in the ALIGN_CYCLES bit field. The following steps must be executed: ►Initialize Bits[7:5], ALIGN_CYCLES, in Register 0x37 with the desired number of alignment cycles to be executed minus one. The maximum number of iterations is eight, which is the num- ber of iterations recommended to use for best performance (ALIGN_CYCLES = 7). Normally, this setting gives better results than the threshold alignment procedure configured with the ALIGN_THOLD = 1. ►Initialize Bit 1, EN_CYCS_RED, in Register 0x37 to decide how many averages of the TDC time stamps are executed each iteration. See the Threshold Alignment section for more details. ►Clear Bit 0, EN_ITER, in Register 0x37 to disable the threshold iteration alignment. ►Execute the steps of the single-channel alignment procedure. Serial Alignment All the alignment procedures presented until now, single-channel, threshold iteration, and fixed iteration, align one single BSYNC channel to a source BSYNC clock. The ADF4030 can align several BSYNC channels serially, one after the other, in numerical order. If the TDC source channel is an incoming clock, select any BSYNC channel as the TDC source. If the TDC source channel is an outgoing clock, choose the lowest numbered BSYNC channel as the TDC source. To execute the serial alignment procedure, the following steps must be executed: ►Identify the desired BSYNC channels to align in Bits[7:6], BSYNC_CAL_ON[1:0], in Register 0x35 and in Bits[7:0], BSYNC_CAL_ON[9:2], in Register 0x36. Each bit corresponds to one BSYNC channel. When set to 1, BSYNC_CAL_ON[0] includes the BSYNC0 channel into the serial procedure, BSYNC_CAL_ON[1] includes the BSYNC1 channel, continuing consecutively to BSYNC_CAL_ON[9] including the BSYNC9 channel. ►When the TDC source channel is an incoming clock, to reduce the power consumption during the serial alignment, set the ADF4030 to power down the drivers of all BSYNC channels that are not being used in real time. This is done by setting Bit 4, AUTO_PD_BG, in Register 0x37 to 1. ►When the TDC source is an outgoing clock, set to 1 the BSYNC_CAL_ON bit of the BSYNC channel identified as the TDC source to include the channel into the procedure. Then clear the AUTO_PD_BG bit to 0. When the AUTO_PD_BG bit is set to 1, it disables the driver of the TDC source, stopping the serial alignment process. ►Introduce the desired time delay in the TDC_OFFSETx[15:0] signed registers that correspond to all targeted BSYNC chan- nels. Use the TDC_OFFSET_COM[20:0] signed register also, if necessary. ►Execute the steps of the threshold iteration or the fixed iteration alignment procedures. To start the alignment procedure, there is no need to identify the TDC_TARGET bits in the Register 0x10. Any writing to the Register 0x10 starts the procedure. Background Serial Alignment The ADF4030 can also automatically and continuously align BSYNC channels in the background until the controller stops the procedure. No SPI commands are required while the ADF4030 executes the procedure. After every passage through all BSYNC channels identified in Bits[9:0], BSYNC_CAL_ON, a temperature measurement is also executed. Then, the procedure starts another alignment cycle and continues the procedure until stopped. If the TDC source channel is an incoming clock, select any BSYNC channel as TDC source. The background serial alignment proce- dure does not work when the TDC source channel is an outgoing clock. To execute the background serial alignment, the following steps must be executed: 1. Set Bit 3, EN_BKGND_ALGN, in Register 0x37 to 1 to enable the background serial alignment procedure. 2. Initialize the temperature measurement: a. Write the K divider value in Register 0x62. b. Clear Bit 6, ADC_CLK_SEL, in Register 0x61 to 0. c. Set Bit 1, EN_ADC_CLK, in Register 0x61 to 1. d. Set Bit 2, EN_ADC_CNV, in Register 0x61 to 1. e. Set Bit 0, EN_ADC, in Register 0x61 to 1. Bit 6, Bit 2, Bit 1, and Bit 0 in Register 0x61 may be written simultaneously. f. Clear Bit 4, PD_ADC, in Register 0x3C to 0. 3. Select the BSYNC channels to align continuously in the back- ground in Bits[9:0], BSYNC_CAL_ON, in Register 0x35 and Register 0x36 by setting the corresponding bits to 1. 4. To reduce the power consumption during the background align- ment, set the ADF4030 to power down the drivers of all BSYNC

analog.com Rev. 0 | 39 of 86 channels that are not being used in real time. This is done by setting Bit 4, AUTO_PD_BG, in Register 0x37 to 1. 5. Execute Step 1 to Step 8 of the single channel automatic align- ment procedure (see the Single-Channel Alignment section). 6. Introduce the desired time delay in the TDC_OFFSETx[15:0] signed registers that correspond to all targeted BSYNC chan- nels. Also use the TDC_OFFSET_COM[20:0] signed register if necessary. 7. Execute a write with any value to the Register 0x10 to start the procedure. Bits[5:0], TDC_TARGET, in Register 0x10 may have any value. The background serial alignment mode does not execute the threshold iteration or the fixed number of iterations alignment proce- dures. It ignores the bits that configure these modes. To immediately stop the background serial alignment, set Bit 6, STOP_FSM, in Register 0x17 to 1. Then, clear it back to 0. To stop the background serial alignment after the ADF4030 completes the current alignment cycle, that is, after all BSYNC channels identified by the BSYNC_CAL_ON bits have been aligned, clear the EN_BKGND_ALGN bit to 0. MEASURING ALIGNMENT RESULTS To measure the time alignment between various BSYNC clocks, execute the following steps: ►Always use both + and − lines of the particular BSYNC channel to probe the clock. ►Use instruments that can subtract the + and − signals in real time to create a differential BSYNC clock. ►The differential BSYNC clock has jitter (see Table 1). Average several clock edges. More averaging means less jitter and better alignment measurement accuracy. Choose the particular number of averages as a function of the clock noise. ►Measure the time delay between the averaged clock edges. Typically, the BSYNC alignment errors are much lower than 1 ps.

Table 16. ADF4030 Register Map

4 RESERVEDREG01_RSV

0 RESERVED

Table 16. ADF4030 Register Map (Continued)

Table 17. Bit Descriptions for REG0000 0: SDO pin tristate (SDIO pin bidirectional), 3-wire SPI mode. 1: SDO pin active output (SDIO pin input only), 4-wire SPI mode. 1: Least significant bit (LSB) first. Table 18. Bit Descriptions for REG0001 0: For double-buffered bit-fields readback subordinate register. 1: For double-buffered bit-fields readback main register. Table 19. Bit Descriptions for REG0002

Table 20. Bit Descriptions for REG0003 Table 21. Bit Descriptions for REG0004 [7:0] PRODUCT_ID[7:0] This read-only 16-bit field represents the Product ID. Product_ID[7:0] bits are equal to 0x0A. Product_ID[15:8] bits are equal to 0x00. Table 22. Bit Descriptions for REG0005 [7:0] PRODUCT_ID[15:8] This read-only 16-bit field represents the Product ID. Product_ID[7:0] bits are equal to 0x0A. Product_ID[15:8] bits are equal to 0x00. Table 23. Bit Descriptions for REG0006 Table 24. Bit Descriptions for REG0007 Table 25. Bit Descriptions for REG0008 Table 26. Bit Descriptions for REG0009 Table 27. Bit Descriptions for REG000A Table 28. Bit Descriptions for REG000B

Table 29. Bit Descriptions for REG000C [7:0] VENDOR_ID[7:0] This read-only 16-bit field represents the Vendor ID. Vendor_ID[7:0] bits are equal to 0x56. Vendor_ID[15:8] bits are equal to 0x04. Table 30. Bit Descriptions for REG000D [7:0] VENDOR_ID[15:8] This read-only 16-bit field represents the Vendor ID. Vendor_ID[7:0] bits are equal to 0x56. Vendor_ID[15:8] bits are equal to 0x04. Table 31. Bit Descriptions for REG000E Table 32. Bit Descriptions for REG000F Table 33. Bit Descriptions for REG0010 and 27, 28, … , 31 are unused. Initialize these bits to 11111 after power up/reset. 00000: Source clock is RX0, the output of BSYNC0 receiver. 00001: Source clock is RX1, the output of BSYN10 receiver. 00010: Source clock is RX2, the output of BSYNC2 receiver. 00011: Source clock is RX3, the output of BSYNC3 receiver. 00100: Source clock is RX4, the output of BSYNC4 receiver. 00101: Source clock is RX5, the output of BSYNC5 receiver. 00110: Source clock is RX6, the output of BSYNC6 receiver. 00111: Source clock is RX7, the output of BSYNC7 receiver. 01000: Source clock is RX8, the output of BSYNC8 receiver. 01001: Source clock is RX9, the output of BSYNC9 receiver. 11010: Source clock is REFIN receiver output. Table 34. Bit Descriptions for REG0011 … , 25 and 27, 28, … , 31 are unused. Initialize these bits to 11111 after power up/reset.

Table 34. Bit Descriptions for REG0011 (Continued) 00000: Source clock is RX0, the output of BSYNC0 receiver. 00001: Source clock is RX1, the output of BSYNC1 receiver. 00010: Source clock is RX2, the output of BSYNC2 receiver. 00011: Source clock is RX3, the output of BSYNC3 receiver. 00100: Source clock is RX4, the output of BSYNC4 receiver. 00101: Source clock is RX5, the output of BSYNC5 receiver. 00110: Source clock is RX6, the output of BSYNC6 receiver. 00111: Source clock is RX7, the output of BSYNC7 receiver. 01000: Source clock is RX8, the output of BSYNC8 receiver. 01001: Source clock is RX9, the output of BSYNC9 receiver. 11010: Source clock is REFIN receiver output. Table 35. Bit Descriptions for REG0012 0: BSYNC 7 channel receives a clock signal (default). 1: BSYNC 7 channel transmits a clock signal. 0: BSYNC 6 channel receives a clock signal (default). 1: BSYNC 6 channel transmits a clock signal. 0: BSYNC 5 channel receives a clock signal (default). 1: BSYNC 5 channel transmits a clock signal. 0: BSYNC 4 channel receives a clock signal (default). 1: BSYNC 4 channel transmits a clock signal. 0: BSYNC 3 channel receives a clock signal (default). 1: BSYNC 3 channel transmits a clock signal. 0: BSYNC 2 channel receives a clock signal (default). 1: BSYNC 2 channel transmits a clock signal. 0: BSYNC 1 channel receives a clock signal (default). 1: BSYNC 1 channel transmits a clock signal. 0: BSYNC 0 channel receives a clock signal (default). 1: BSYNC 0 channel transmits a clock signal. Table 36. Bit Descriptions for REG0013 nongapped periodic clock signal. nongapped periodic clock signal.

Table 36. Bit Descriptions for REG0013 (Continued) 0: BSYNC4 channel ODIV divider outputs a nongapped clock signal (default). 1: BSYNC4 channel ODIV divider outputs a gapped clock signal. nongapped periodic clock signal. 0: BSYNC3 channel ODIV divider outputs a nongapped clock signal (default). 1: BSYNC3 channel ODIV divider outputs a gapped clock signal. nongapped periodic clock signal. 0: BSYNC2 channel ODIV divider outputs a nongapped clock signal (default). 1: BSYNC2 channel ODIV divider outputs a gapped clock signal. nongapped periodic clock signal. 0: BSYNC1 channel ODIV divider outputs a nongapped clock signal (default). 1: BSYNC1 channel ODIV divider outputs a gapped clock signal. nongapped periodic clock signal. 0: BSYNC0 channel ODIV divider outputs a nongapped clock signal (default). 1: BSYNC0 channel ODIV divider outputs a gapped clock signal. 0: BSYNC 9 channel receives a clock signal (default). 1: BSYNC 9 channel transmits a clock signal. 0: BSYNC 8 channel receives a clock signal (default). 1: BSYNC 8 channel transmits a clock signal. Table 37. Bit Descriptions for REG0014 0: Analog delay block does not invert the BSYNC3 channel output (default). 1: Analog delay block inverts the BSYNC3 channel output. 0: Analog delay block does not invert the BSYNC2 channel output (default). 1: Analog delay block inverts the BSYNC2 channel output. 0: Analog delay block does not invert the BSYNC1 channel output (default). 1: Analog delay block inverts the BSYNC1 channel output. 0: Analog delay block does not invert the BSYNC0 channel output (default). 1: Analog delay block inverts the BSYNC0 channel output. nongapped periodic clock signal. 0: BSYNC9 channel ODIV divider outputs a nongapped clock signal (default). 1: BSYNC9 channel ODIV divider outputs a gapped clock signal. nongapped periodic clock signal. 0: BSYNC8 channel ODIV divider outputs a nongapped clock signal (default). 1: BSYNC8 channel ODIV divider outputs a gapped clock signal.

Table 37. Bit Descriptions for REG0014 (Continued) nongapped periodic clock signal. 0: BSYNC7 channel ODIV divider outputs a nongapped clock signal (default). 1: BSYNC7 channel ODIV divider outputs a gapped clock signal. nongapped periodic clock signal. 0: BSYNC6 channel ODIV divider outputs a nongapped clock signal (default). 1: BSYNC6 channel ODIV divider outputs a gapped clock signal. Table 38. Bit Descriptions for REG0015 0: TDC uses rising edges of the source clock signal (default). 1: TDC uses falling edges of the source clock signal. 0: TDC uses rising edges of the target clock signal (default). 1: TDC uses falling edges of the source clock signal. 0: Analog delay block does not invert the BSYNC9 channel output (default). 1: Analog delay block inverts the BSYNC9 channel output. 0: Analog delay block does not invert the BSYNC8 channel output (default). 1: Analog delay block inverts BSYNC8 channel output. 0: Analog delay block does not invert the BSYNC7 channel output (default). 1: Analog delay block inverts the BSYNC7 channel output. 0: Analog delay block does not invert the BSYNC6 channel output (default). 1: Analog delay block inverts the BSYNC6 channel output. 0: Analog delay block does not invert the BSYNC5 channel output (default). 1: Analog delay block inverts the BSYNC5 channel output. 0: Analog delay block does not invert the BSYNC4 channel output (default). 1: Analog delay block inverts the BSYNC4 channel output. Table 39. Bit Descriptions for REG0016 0: TDC operation is reset and stopped. Clear this bit to 0 to end the TDC measurement. 1: Start the TDC measurement.

Table 39. Bit Descriptions for REG0016 (Continued) 2AVGEXP. The AVGEXP values 0, 1, 2 are not supported. Initialize these bits to 0110 after power up/reset. Table 40. Bit Descriptions for REG0017 0: Stop the open-loop delay adjustment on the target BSYNC channel. 1: Start the open-loop delay adjustment on the target BSYNC channel. adjustment weight of the LSB is approximately 1.4 ps. Table 41. Bit Descriptions for REG0018 Table 42. Bit Descriptions for REG0019 Table 43. Bit Descriptions for REG001A LSB is 1/29 of the VCO period. Table 44. Bit Descriptions for REG001B LSB is 1/29 of the VCO period. Table 45. Bit Descriptions for REG001C

Table 45. Bit Descriptions for REG001C (Continued) LSB is 1/29 of the VCO period. Table 46. Bit Descriptions for REG001D an alignment procedure. The adjustment weight of the LSB is 1/29 of the VCO period. Table 47. Bit Descriptions for REG001E an alignment procedure. The adjustment weight of the LSB is 1/29 of the VCO period. Table 48. Bit Descriptions for REG001F an alignment procedure. The adjustment weight of the LSB is 1/29 of the VCO period. Table 49. Bit Descriptions for REG0020 an alignment procedure. The adjustment weight of the LSB is 1/29 of the VCO period. Table 50. Bit Descriptions for REG0021 an alignment procedure. The adjustment weight of the LSB is 1/29 of the VCO period. Table 51. Bit Descriptions for REG0022 an alignment procedure. The adjustment weight of the LSB is 1/29 of the VCO period. Table 52. Bit Descriptions for REG0023 an alignment procedure. The adjustment weight of the LSB is 1/29 of the VCO period. Table 53. Bit Descriptions for REG0024 an alignment procedure. The adjustment weight of the LSB is 1/29 of the VCO period.

Table 54. Bit Descriptions for REG0025 an alignment procedure. The adjustment weight of the LSB is 1/29 of the VCO period. Table 55. Bit Descriptions for REG0026 an alignment procedure. The adjustment weight of the LSB is 1/29 of the VCO period. Table 56. Bit Descriptions for REG0027 an alignment procedure. The adjustment weight of the LSB is 1/29 of the VCO period. Table 57. Bit Descriptions for REG0028 an alignment procedure. The adjustment weight of the LSB is 1/29 of the VCO period. Table 58. Bit Descriptions for REG0029 an alignment procedure. The adjustment weight of the LSB is 1/29 of the VCO period. Table 59. Bit Descriptions for REG002A an alignment procedure. The adjustment weight of the LSB is 1/29 of the VCO period. Table 60. Bit Descriptions for REG002B an alignment procedure. The adjustment weight of the LSB is 1/29 of the VCO period. Table 61. Bit Descriptions for REG002C an alignment procedure. The adjustment weight of the LSB is 1/29 of the VCO period.

Table 62. Bit Descriptions for REG002D an alignment procedure. The adjustment weight of the LSB is 1/29 of the VCO period. Table 63. Bit Descriptions for REG002E an alignment procedure. The adjustment weight of the LSB is 1/29 of the VCO period. Table 64. Bit Descriptions for REG002F an alignment procedure. The adjustment weight of the LSB is 1/29 of the VCO period. Table 65. Bit Descriptions for REG0030 an alignment procedure. The adjustment weight of the LSB is 1/29 of the VCO period. Table 66. Bit Descriptions for REG0031 Table 67. Bit Descriptions for REG0032 Table 68. Bit Descriptions for REG0033 Table 69. Bit Descriptions for REG0034 0: Delay adjustment is done function of the cycles bit value. 1: Delay adjustment is done in one single BSYNC period. 0: Delay adjustment is done in steps of approximately 50 ps (1/8 of the VCO period). 1: Delay adjustment is done in steps of one VCO period. bits to 100100 after power up/reset.

Table 70. Bit Descriptions for REG0035 procedure is executed. Bit 0 selects BSYNC0, Bit 1 selects BSYNC1, … , Bit 9 selects BSYNC9. 000101 after power up/reset. Table 71. Bit Descriptions for REG0036 procedure is executed. Bit 0 selects BSYNC0, Bit 1 selects BSYNC1, … , Bit 9 selects BSYNC9. Table 72. Bit Descriptions for REG0037 001: Run 2 alignment cycles. 010: Run 3 alignment cycles. 011: Run 4 alignment cycles. 100: Run 5 alignment cycles. 101: Run 6 alignment cycles. 110: Run 7 alignment cycles. 111: Run 8 alignment cycles. and background serial alignment procedures. source TDC channel is an outgoing clock. consumption during the procedures. fixed iteration alignment procedures. Initialize this bit to 1 after power up/reset. 0: Every alignment cycle uses AVG = 64 × 2CIC_DEC_RATE TDC time stamps. maximum number of iterations is determined by Bits ALIGN_CYCLES in Register 0x37. Table 73. Bit Descriptions for REG0038

Table 74. Bit Descriptions for REG0039 Table 75. Bit Descriptions for REG003A 0: BSYNC7 transmit driver powered up. 1: BSYNC7 transmit driver powered down. 0: BSYNC6 transmit driver powered up. 1: BSYNC6 transmit driver powered down. 0: BSYNC5 transmit driver powered up. 1: BSYNC5 transmit driver powered down. 0: BSYNC4 transmit driver powered up. 1: BSYNC4 transmit driver powered down. 0: BSYNC3 transmit driver powered up. 1: BSYNC3 transmit driver powered down. 0: BSYNC2 transmit driver powered up. 1: BSYNC2 transmit driver powered down. 0: BSYNC1 transmit driver powered up. 1: BSYNC1 transmit driver powered down. 0: BSYNC0 transmit driver powered up. 1: BSYNC0 transmit driver powered down. Table 76. Bit Descriptions for REG003B 0: BSYNC5 transmit driver and analog delay block powered up. 1: BSYNC5 transmit driver and analog delay block powered down. 0: BSYNC4 transmit driver and analog delay block powered up. 1: BSYNC4 transmit driver and analog delay block powered down. 0: BSYNC3 transmit driver and analog delay block powered up. 1: BSYNC3 transmit driver and analog delay block powered down.

Table 76. Bit Descriptions for REG003B (Continued) 0: BSYNC2 transmit driver and analog delay block powered up. 1: BSYNC2 transmit driver and analog delay block powered down. 0: BSYNC1 transmit driver and analog delay block powered up. 1: BSYNC1 transmit driver and analog delay block powered down. 0: BSYNC0 transmit driver and analog delay block powered up. 1: BSYNC0 transmit driver and analog delay block powered down. 0: BSYNC9 transmit driver powered up. 1: BSYNC9 transmit driver powered down. 0: BSYNC8 transmit driver powered up. 1: BSYNC8 transmit driver powered down. Table 77. Bit Descriptions for REG003C 0: TDC and multiplexer powered up. 1: TDC and multiplexer powered down. system. Initialize this bit to 1 after a power up/reset. 0: Temperature ADC powered up. 1: Temperature ADC powered down. 0: BSYNC9 transmit driver and analog delay block powered up. 1: BSYNC9 transmit driver and analog delay block powered down. 0: BSYNC8 transmit driver and analog delay block powered up. 1: BSYNC8 transmit driver and analog delay block powered down. 0: BSYNC7 transmit driver and analog delay block powered up. 1: BSYNC7 transmit driver and analog delay block powered down.

Table 77. Bit Descriptions for REG003C (Continued) 0: BSYNC6 transmit driver and analog delay block powered up. 1: BSYNC6 transmit driver and analog delay block powered down. Table 78. Bit Descriptions for REG003D Table 79. Bit Descriptions for REG003E Table 80. Bit Descriptions for REG003F (when cleared to 0 (default)) or ODIVB (when set to 1). 0: 14 mA driver current (default). then V_CM0 = I_DRV× (26.5 + R_CM0), where I_DRV is the BSYNC driver current level set by the BOOST0 bit. I_DRV = 20 mA when BOOST0 = 1. I_DRV = 14 mA when BOOST0 = 0. Table 81. Bit Descriptions for REG0040 down or not when it is not used by the TDC. Initialize this bit to 1 after power up/reset. 0: BSYNC0 receiver stays powered up all the time. 1: BSYNC0 receiver powers down when not used in the TDC measurement. terminations of the BSYNC0 receiver are connected to ground or not. 0: Terminations connected to ground (default). 1: Terminations not connected to ground. terminations of the BSYNC0 driver are connected to ground or not. 0: Terminations connected to ground (default). 1: Terminations not connected to ground. of the BSYNC0 receiver are shorted together or not. Initialize this bit to 1 after power up/reset. 0: Terminations not shorted together (default). 1: Terminations shorted together. BSYNC0 driver are shorted together or not. 0: Terminations not shorted together (default).

Table 81. Bit Descriptions for REG0040 (Continued) 1: Terminations shorted together. 0: DC-coupled clocks (default). Table 82. Bit Descriptions for REG0041 ODIVB (when set to 1) divide ratios for the BSYNC1 channel. 0: 14 mA driver current (default). then V_CM1 = I_DRV × (26.5 + R_CM1), where I_DRV is the BSYNC driver current level set by the BOOST1 bit. I_DRV = 20 mA when BOOST1 = 1. I_DRV = 14 mA when BOOST1 = 0. Table 83. Bit Descriptions for REG0042 down or not when it is not used by the TDC. Initialize this bit to 1 after power up/reset. 0: BSYNC1 Receiver stays powered up all the time. 1: BSYNC1 Receiver powers down when not used in the TDC measurement. terminations of the BSYNC1 receiver are connected to ground or not. 0: Terminations connected to ground (default). 1: Terminations not connected to ground. terminations of the BSYNC1 driver are connected to ground or not. 0: Terminations connected to ground (default). 1: Terminations not connected to ground. of the BSYNC1 receiver are shorted together or not. Initialize this bit to 1 after power up/reset. 0: Terminations not shorted together (default). 1: Terminations shorted together. the BSYNC1 driver are shorted together or not. 0: Terminations not shorted together (default). 1: Terminations shorted together. 0: DC-coupled clocks (default).

Table 84. Bit Descriptions for REG0043 ODIVB (when set to 1) divide ratios for BSYNC2 channel. 0: 14 mA driver current (default). then V_CM2 = I_DRV × (26.5 + R_CM2), where I_DRV is the BSYNC driver current level set by BOOST2 bit. I_DRV = 20 mA when BOOST2 = 1. I_DRV = 14 mA when BOOST2 = 0. Table 85. Bit Descriptions for REG0044 or not when it is not used by the TDC. Initialize this bit to 1 after power up/reset. 0: BSYNC2 receiver stays powered up all the time. 1: BSYNC2 receiver powers down when not used in the TDC measurement. terminations of the BSYNC2 receiver are connected to ground or not. 0: Terminations connected to ground (default). 1: Terminations not connected to ground. terminations of the BSYNC2 driver are connected to ground or not. 0: Terminations connected to ground (default). 1: Terminations not connected to ground. of BSYNC2 receiver are shorted together or not. Initialize this bit to 1 after power up/reset. 0: Terminations not shorted together (default). 1: Terminations shorted together. BSYNC2 driver are shorted together or not. 0: Terminations not shorted together (default). 1: Terminations shorted together. 0: DC-coupled clocks (default). Table 86. Bit Descriptions for REG0045 ODIVB (when set to 1) divide ratios for the BSYNC3 channel. 0: 14 mA driver current (default).

Table 86. Bit Descriptions for REG0045 (Continued) then V_CM3 = I_DRV × (26.5 + R_CM3), where I_DRV is the BSYNC driver current level set by BOOST3 bit. I_DRV=20 mA when BOOST3 = 1. I_DRV = 14 mA when BOOST3 = 0. Table 87. Bit Descriptions for REG0046 or not when it is not used by the TDC. Initialize this bit to 1 after power up/reset. 0: BSYNC3 receiver stays powered up all the time. 1: BSYNC3 receiver powers down when not used in the TDC measurement. terminations of the BSYNC3 receiver are connected to ground or not. 0: Terminations connected to ground (default). 1: Terminations not connected to ground. terminations of the BSYNC3 driver are connected to ground or not. 0: Terminations connected to ground (default). 1: Terminations not connected to ground. of the BSYNC3 receiver are shorted together or not. Initialize this bit to 1 after power up/reset. 0: Terminations not shorted together (default). 1: Terminations shorted together. the BSYNC3 driver are shorted together or not. 0: Terminations not shorted together (default). 1: Terminations shorted together. 0: DC-coupled clocks (default). Table 88. Bit Descriptions for REG0047 ODIVB (when set to 1) divide ratios for the BSYNC4 channel. 0: 14 mA driver current (default). then V_CM4 = I_DRV × (26.5 + R_CM4), where I_DRV is the BSYNC driver current level set by BOOST4 bit. I_DRV = 20 mA when BOOST4 = 1. I_DRV = 14 mA when BOOST4 = 0.

Table 89. Bit Descriptions for REG0048 or not when it is not used by the TDC. Initialize this bit to 1 after power up/reset. 0: BSYNC4 Receiver stays powered up all the time. 1: BSYNC4 Receiver powers down when not used in the TDC measurement. terminations of the BSYNC4 receiver are connected to ground or not. 0: Terminations connected to ground (default). 1: Terminations not connected to ground. terminations of the BSYNC4 driver are connected to ground or not. 0: Terminations connected to ground (default). 1: Terminations not connected to ground. of the BSYNC4 receiver are shorted together or not. Initialize this bit to 1 after power up/reset. 0: Terminations not shorted together (default). 1: Terminations shorted together. the BSYNC4 driver are shorted together or not. 0: Terminations not shorted together (default). 1: Terminations shorted together. 0: DC-coupled clocks (default). Table 90. Bit Descriptions for REG0049 ODIVB (when set to 1) divide ratios for the BSYNC5 channel. 0: 14 mA driver current (default). then V_CM5 = I_DRV × (26.5 + R_CM5), where I_DRV is the BSYNC driver current level set by BOOST5 bit. I_DRV = 20 mA when BOOST5 = 1. I_DRV=14 mA when BOOST5 = 0. Table 91. Bit Descriptions for REG004A or not when it is not used by the TDC. Initialize this bit to 1 after power up/reset. 0: BSYNC5 Receiver stays powered up all the time. 1: BSYNC5 Receiver powers down when not used in the TDC measurement.

Table 91. Bit Descriptions for REG004A (Continued) terminations of the BSYNC5 receiver are connected to ground or not. 0: Terminations connected to ground (default). 1: Terminations not connected to ground. terminations of the BSYNC5 driver are connected to ground or not. 0: Terminations connected to ground (default). 1: Terminations not connected to ground. of the BSYNC5 receiver are shorted together or not. Initialize this bit to 1 after power up/reset. 0: Terminations not shorted together (default). 1: Terminations shorted together. the BSYNC5 driver are shorted together or not. 0: Terminations not shorted together (default). 1: Terminations shorted together. 0: DC-coupled clocks (default). Table 92. Bit Descriptions for REG004B ODIVB (when set to 1) divide ratios for the BSYNC6 channel. 0: 14 mA driver current (default). then V_CM6 = I_DRV × (26.5 + R_CM6), where I_DRV is the BSYNC driver current level set by BOOST6 bit. I_DRV = 20 mA when BOOST6 = 1. I_DRV = 14 mA when BOOST6 = 0. Table 93. Bit Descriptions for REG004C or not when it is not used by the TDC. Initialize this bit to 1 after power up/reset. 0: BSYNC6 Receiver stays powered up all the time. 1: BSYNC6 Receiver powers down when not used in the TDC measurement. terminations of the BSYNC6 receiver are connected to ground or not. 0: Terminations connected to ground (default). 1: Terminations not connected to ground. terminations of the BSYNC6 driver are connected to ground or not.

Table 93. Bit Descriptions for REG004C (Continued) 0: Terminations connected to ground (default). 1: Terminations not connected to ground. 0: Terminations not shorted together (default). 1: Terminations shorted together. the BSYNC6 driver are shorted together or not. 0: Terminations not shorted together (default). 1: Terminations shorted together. 0: DC-coupled clocks (default). Table 94. Bit Descriptions for REG004D ODIVB (when set to 1) divide ratios for the BSYNC7 channel. 0: 14 mA driver current (default). then V_CM7 = I_DRV × (26.5 + R_CM7), where I_DRV is the BSYNC driver current level set by BOOST7 bit. I_DRV = 20 mA when BOOST7 = 1. I_DRV = 14 mA when BOOST7 = 0. Table 95. Bit Descriptions for REG004E or not when it is not used by the TDC. Initialize this bit to 1 after power up/reset. 0: BSYNC7 Receiver stays powered up all the time. 1: BSYNC7 Receiver powers down when not used in the TDC measurement. terminations of the BSYNC7 receiver are connected to ground or not. 0: Terminations connected to ground (default). 1: Terminations not connected to ground. terminations of the BSYNC7 driver are connected to ground or not. 0: Terminations connected to ground (default). 1: Terminations not connected to ground. of the BSYNC7 receiver are shorted together or not. Initialize this bit to 1 after power up/reset. 0: Terminations not shorted together (default).

Table 95. Bit Descriptions for REG004E (Continued) 1: Terminations shorted together. the BSYNC7 driver are shorted together or not. 0: Terminations not shorted together (default). 1: Terminations shorted together. 0: DC-coupled clocks (default). Table 96. Bit Descriptions for REG004F ODIVB (when set to 1) divide ratios for the BSYNC8 channel. 0: 14 mA driver current (default). mA when BOOST8=1 and I_DRV=14 mA when BOOST8=0. Table 97. Bit Descriptions for REG0050 or not when it is not used by the TDC. Initialize this bit to 1 after power up/reset.

6 RESERVED RESERVED 0x0 R/W

terminations of the BSYNC8 receiver are connected to ground or not. 0: Terminations connected to ground (default). 1: Terminations not connected to ground. terminations of the BSYNC8 driver are connected to ground or not. 0: Terminations connected to ground (default). 1: Terminations not connected to ground. of the BSYNC8 receiver are shorted together or not. Initialize this bit to 1 after power up/reset. 0: Terminations not shorted together (default). 1: Terminations shorted together. the BSYNC8 driver are shorted together or not. 0: Terminations not shorted together (default). 1: Terminations shorted together.

Table 97. Bit Descriptions for REG0050 (Continued) 0: DC-coupled clocks (default). Table 98. Bit Descriptions for REG0051 default value) or ODIVB (when set to 1) divide ratios for BSYNC9 channel. 0: 14 mA driver current (default). then V_CM9 = I_DRV × (26.5 + R_CM9), where I_DRV is the BSYNC driver current level set by BOOST9 bit. I_DRV = 20 mA when BOOST9 = 1. I_DRV=14 mA when BOOST9 = 0. Table 99. Bit Descriptions for REG0052 or not when it is not used by the TDC. Initialize this bit to 1 after power up/reset. 0: BSYNC9 Receiver stays powered up all the time. 1: BSYNC9 Receiver powers down when not used in the TDC measurement. terminations of the BSYNC9 receiver are connected to ground or not. 0: Terminations connected to ground (default). 1: Terminations not connected to ground. terminations of the BSYNC9 driver are connected to ground or not. 0: Terminations connected to ground (default). 1: Terminations not connected to ground. of the BSYNC9 receiver are shorted together or not. Initialize this bit to 1 after power up/reset. 0: Terminations not shorted together (default). 1: Terminations shorted together. the BSYNC9 driver are shorted together or not. 0: Terminations not shorted together (default). 1: Terminations shorted together. 0: DC-coupled clocks (default).

Table 100. Bit Descriptions for REG0053 than 10. Initialize these bits to 0000 0001 1001 after power up/reset, that is ODIVA = 25. Table 101. Bit Descriptions for REG0054 lower than 10. Initialize these bits to 0000 0001 1001 after power up/reset, that is ODIVB = 25. lower than 10. Initialize these bits to 0000 0001 1001 after power up/reset, that is ODIVA = 25. Table 102. Bit Descriptions for REG0055 lower than 10. Initialize these bits to 0000 0001 1001 after power up/reset, that is ODIVB = 25. Table 103. Bit Descriptions for REG0056 than 8. Initialize this Register to 0x7D after power up/reset. Table 104. Bit Descriptions for REG0057

1. The value of the reference divider is the value stored in this register. If the reference divider is set to 0, the

ADF4030 behaves as if the value was 1. Initialize these bits to 00101 after power up/reset, that is set RDIV = 5. Table 105. Bit Descriptions for REG0058

Table 105. Bit Descriptions for REG0058 (Continued) digital core clock lower than 125 MHz. Initialize these bits to 01 after power up/reset. Table 106. Bit Descriptions for REG0059 Table 107. Bit Descriptions for REG005A Table 108. Bit Descriptions for REG005B Table 109. Bit Descriptions for REG005C high level. Clear CMOS_OV bit to 0 (default) to select a 1.8 V CMOS high level.

Table 109. Bit Descriptions for REG005C (Continued) 0: Normal operation of accumulated delay monitor. 1: Stop the accumulated delay monitor. 1: Stop the temperature monitor. 0: Disable (that is, mask) the TDC error and ADEL overflow monitors interrupt. 1: Enable (that is unmask) TDC error and ADEL overflow monitors interrupt. 0: Disable (mask) PLL lock detect interrupt. 1: Enable (unmask) PLL lock detect interrupt. 0: Disable (mask) BSYNC accumulated delay interrupt. 1: Enable (unmask) BSYNC accumulated delay interrupt. 0: Disable (mask) temperature monitor interrupt. 1: Enable (unmask) temperature monitor interrupt. 0: IRQB pin behaves like a standard CMOS output. 1: IRQB pin is an open drain output. Table 110. Bit Descriptions for REG005D threshold of around ±23 ps. Initialize this register to 0x10 after power up/reset. Table 111. Bit Descriptions for REG005E the temperature monitoring. It is expressed in °C. Initialize this register to 0x32 after power up/reset. Table 112. Bit Descriptions for REG005F Table 113. Bit Descriptions for REG0060

Table 114. Bit Descriptions for REG0061 and then write it again with the value cleared to 0. 1: Stop the TDC error and ADEL overflow monitors. 0: The digital core clock is the ADC clock source (default). 1: A clock generated at the SCLK pin is the ADC clock source. 0: ADC conversion is disabled (default). 1: ADC conversion is enabled. 0: The ADC clock path is not enabled (default). 1: The ADC clock path is enabled. Table 115. Bit Descriptions for REG0062 or equal to fCORECLOCK/1.6E6 − 0.5. Initialize this register to 0x4C after power up/reset. Table 116. Bit Descriptions for REG0063 00001: 1 = Digital core clock divided by 2. 00010: 2 = Period clock divided by 2. 00011: 3 = State of Bit 1, ADC_BUSY, of Register 0x8F. 00100: 4 = State of Bit 4, TDC_BUSY, of Register 0x8F. 00101: 5 = State of Bit 3, DL_BUSY, of Register 0x8F. 00110: 6 = State of Bit 0, FSM_BUSY, of Register 0x8F. 00111: 7 = PLL PFD input clock from the NDIV divider divided by 2. 01000: 8 = PLL PFD input clock from the RDIV divider divided by 2. 10010: 18 = State if Bit 0, PLL_LD, of Register 0x90. 10011: 19 = State of Bit 1, CAL_COMP, of Register 0xBA.

Table 116. Bit Descriptions for REG0063 (Continued) 10100: 20 = State of Bit 0, CAL_BUSY, of Register 0xBA. 11100: 28 = TDC Source Clock. 11110: 30 = The state of Bit 6, GPO1, of Register 0x68. Table 117. Bit Descriptions for REG0064 00001: 1 = Digital core clock divided by 2. 00010: 2 = Period clock divided by 2. 00011: 3 = State of Bit 1, ADC_BUSY, of Register 0x8F. 00100: 4 = State of Bit 4, TDC_BUSY, of Register 0x8F. 00101: 5 = State of Bit 3, DL_BUSY, of Register 0x8F. 00110: 6 = State of Bit 0, FSM_BUSY, of Register 0x8F. 00111: 7 = PLL PFD input clock from the NDIV divider divided by 2. 01000: 8 = PLL PFD input clock from the RDIV divider divided by 2. 10000: 16 = PLL NDIV divider output clock. 10001: 17 = PLL RDIV divider output clock. 10010: 18 = State if Bit 0, PLL_LD, of Register 0x90. 10011: 19 = State of Bit 1, CAL_COMP, of Register 0xBA. 10100: 20 = State of Bit 0, CAL_BUSY, of Register 0xBA. 11100: 28 = TDC Target clock.

Table 117. Bit Descriptions for REG0064 (Continued) 11110: 30 = The state of Bit 7, GPO2, of Register 0x68. Table 118. Bit Descriptions for REG0065 Table 119. Bit Descriptions for REG0066 Table 120. Bit Descriptions for REG0067 Table 121. Bit Descriptions for REG0068 MUXCODE2 Bits[4:0] in Register 0x0064 are set to 30. MUXCODE1 Bits[4:0] in Register 0x0063 are set to 30. Table 122. Bit Descriptions for REG0069 Table 123. Bit Descriptions for REG006A Table 124. Bit Descriptions for REG006B Table 125. Bit Descriptions for REG006C

Table 126. Bit Descriptions for REG006D Table 127. Bit Descriptions for REG006E Table 128. Bit Descriptions for REG006F Table 129. Bit Descriptions for REG0070 Table 130. Bit Descriptions for REG0071 Table 131. Bit Descriptions for REG0072 of the Register 0x0072 can also be written with any value during this write operation. Table 132. Bit Descriptions for REG0073 lags the target clock in time, and a negative result means the source clock leads the target clock in time. Table 133. Bit Descriptions for REG0074 Table 134. Bit Descriptions for REG0075

Table 134. Bit Descriptions for REG0075 (Continued) Table 135. Bit Descriptions for REG0076 Table 136. Bit Descriptions for REG0077 represents the average of the last four TIMEDIFF samples of the TDC post processor. Table 137. Bit Descriptions for REG0078 Table 138. Bit Descriptions for REG0079 Table 139. Bit Descriptions for REG007A Table 140. Bit Descriptions for REG007B Table 141. Bit Descriptions for REG007C Table 142. Bit Descriptions for REG007D

Table 143. Bit Descriptions for REG007E Table 144. Bit Descriptions for REG007F Table 145. Bit Descriptions for REG0080 Table 146. Bit Descriptions for REG0081 Table 147. Bit Descriptions for REG0082 Table 148. Bit Descriptions for REG0083 Table 149. Bit Descriptions for REG0084 Table 150. Bit Descriptions for REG0085 Table 151. Bit Descriptions for REG0086

Table 152. Bit Descriptions for REG0087 Table 153. Bit Descriptions for REG0088 Table 154. Bit Descriptions for REG0089 Table 155. Bit Descriptions for REG008A Table 156. Bit Descriptions for REG008B Table 157. Bit Descriptions for REG008C Table 158. Bit Descriptions for REG008D Table 159. Bit Descriptions for REG008E

Table 160. Bit Descriptions for REG008F when the TDC is not executing a conversion. Table 161. Bit Descriptions for REG0090 IRQ_BSYNC[3:0] and Bits[5:0] of Register 0x91 represent IRQ_BSYNC[9:4]. 1: BSYNC channel output clock has accumulated a delay greater than the ALIGN_IRQ_TH threshold. 0: T_DIFF, the temperature monitor output, is less than or equal to the temperature threshold. 1: T_DIFF, the temperature monitor output, is greater than the temperature threshold. Alignment Error IRQ section for details. 0: No temporary alignment error has occurred. 1: Temporary alignment error has occurred. 00: TDC measurement does not have any error. 01: At least one TDC input clock presents excessive jitter. 10: At least one TDC input clock is not present. 11: Excessive phase shift happened during TDC measurement. 0: PLL lock detector indicates the PLL is not locked. 1: PLL lock detector indicates the PLL is locked. Table 162. Bit Descriptions for REG0091 Bits[5:0] of Register 0x91 represent IRQ_BSYNC[9:4]. 1: BSYNC channel output clock has accumulated a delay greater than the ALIGN_IRQ_TH threshold.

Table 163. Bit Descriptions for REG0092 the sign of the CTC magnitude result. When Bit 8 is cleared to 0, the CTC magnitude result is positive. When Bit 8 is set to 1, the CTC magnitude result is negative. Table 164. Bit Descriptions for REG0093 0 TEMP_MEAS[8] Temperature Measurement Result. This 9-bit field represents the temperature output value of the CTC block. set to 1, the CTC magnitude result is negative. Table 165. Bit Descriptions for REG0094 Table 166. Bit Descriptions for REG0095 setting for BSYNC1. The bit weight is 1/8 of the VCO period. setting for BSYNC0. The bit weight is 1/8 of the VCO period. Table 167. Bit Descriptions for REG0096 setting for BSYNC3. The bit weight is 1/8 of the VCO period. setting for BSYNC2. The bit weight is 1/8 of the VCO period. Table 168. Bit Descriptions for REG0097 setting for BSYNC5. The bit weight is 1/8 of the VCO period. setting for BSYNC4. The bit weight is 1/8 of the VCO period.

Table 169. Bit Descriptions for REG0098 setting for BSYNC7. The bit weight is 1/8 of the VCO period. setting for BSYNC6. The bit weight is 1/8 of the VCO period. Table 170. Bit Descriptions for REG0099 setting for BSYNC9. The bit weight is 1/8 of the VCO period. setting for BSYNC8. The bit weight is 1/8 of the VCO period. Table 171. Bit Descriptions for REG009A monitor interrupt has been activated (RST_ALIGN_IRQ bit cleared to 0). Table 172. Bit Descriptions for REG009B Table 173. Bit Descriptions for REG009C monitor interrupt has been activated (RST_ALIGN_IRQ bit cleared to 0). Table 174. Bit Descriptions for REG009D monitor interrupt has been activated (RST_ALIGN_IRQ bit cleared to 0). Table 175. Bit Descriptions for REG009E monitor interrupt has been activated (RST_ALIGN_IRQ bit cleared to 0).

Table 176. Bit Descriptions for REG009F monitor interrupt has been activated (RST_ALIGN_IRQ bit cleared to 0). Table 177. Bit Descriptions for REG00A0 monitor interrupt has been activated (RST_ALIGN_IRQ bit cleared to 0). Table 178. Bit Descriptions for REG00A1 monitor interrupt has been activated (RST_ALIGN_IRQ bit cleared to 0). Table 179. Bit Descriptions for REG00A2 monitor interrupt has been activated (RST_ALIGN_IRQ bit cleared to 0). Table 180. Bit Descriptions for REG00A3 monitor interrupt has been activated (RST_ALIGN_IRQ bit cleared to 0). Table 181. Bit Descriptions for REG00A4 monitor interrupt has been activated (RST_ALIGN_IRQ bit cleared to 0). Table 182. Bit Descriptions for REG00A5 monitor interrupt has been activated (RST_ALIGN_IRQ bit cleared to 0). Table 183. Bit Descriptions for REG00A6 monitor interrupt has been activated (RST_ALIGN_IRQ bit cleared to 0).

Table 184. Bit Descriptions for REG00A7 monitor interrupt has been activated (RST_ALIGN_IRQ bit cleared to 0). Table 185. Bit Descriptions for REG00A8 monitor interrupt has been activated (RST_ALIGN_IRQ bit cleared to 0). Table 186. Bit Descriptions for REG00A9 monitor interrupt has been activated (RST_ALIGN_IRQ bit cleared to 0). Table 187. Bit Descriptions for REG00AA monitor interrupt has been activated (RST_ALIGN_IRQ bit cleared to 0). Table 188. Bit Descriptions for REG00AB monitor interrupt has been activated (RST_ALIGN_IRQ bit cleared to 0). Table 189. Bit Descriptions for REG00AC monitor interrupt has been activated (RST_ALIGN_IRQ bit cleared to 0). Table 190. Bit Descriptions for REG00AD monitor interrupt has been activated (RST_ALIGN_IRQ bit cleared to 0). Table 191. Bit Descriptions for REG00AE

Table 192. Bit Descriptions for REG00AF Table 193. Bit Descriptions for REG00B0 Table 194. Bit Descriptions for REG00B1 Table 195. Bit Descriptions for REG00B2 Table 196. Bit Descriptions for REG00B3 Table 197. Bit Descriptions for REG00B4 Table 198. Bit Descriptions for REG00B5 Table 199. Bit Descriptions for REG00B6 Table 200. Bit Descriptions for REG00B7 Table 201. Bit Descriptions for REG00B8

Table 202. Bit Descriptions for REG00B9 Table 203. Bit Descriptions for REG00BA Table 204. Bit Descriptions for REG00BB Table 205. Bit Descriptions for REG00CA TMP_ALIGN_ERR_CH[9:8]. See the Temporary Alignment Error IRQ IRQ section for details. 0: No temporary alignment error has occurred. 1: Temporary alignment error has occurred. Table 206. Bit Descriptions for REG00CB TMP_ALIGN_ERR_CH[9:8]. See the Temporary Alignment Error IRQ section for details. 0: No temporary alignment error has occurred. 1: Temporary alignment error has occurred. Table 207. Bit Descriptions for REG00FF 0: SPI broadcast mode is disabled. 1: SPI broadcast mode is enabled. cycling the device in terms of the register map). This bit clears automatically.

Table 207. Bit Descriptions for REG00FF (Continued)

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1 Z=RoHS Compliant Part