ADF4002BRUZ-RL7

ADF4002 AD | Alldatasheet

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Phase Detector/Frequency Synthesizer ADF4002 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.

FEATURES

400 MHz bandwidth

2.7 V to 3.3 V power supply Separate charge pump supply (VP) allows extended tuning voltage in 3 V systems Programmable charge pump currents 3-wire serial interface Analog and digital lock detect Hardware and software power-down mode

200 MHz phase detector

APPLICATIONS

The ADF4002 frequency synthesizer is used to implement local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. It consists of a low-noise digital phase frequency detector (PFD), a precision charge pump, a programmable reference divider, and programmable N divider. The 14-bit reference counter (R counter), allows selectable REFIN frequencies at the PFD input. A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and voltage controlled oscillator (VCO). In addition, by programming R and N to 1, the part can be used as a stand alone PFD and charge pump. FUNCTIONAL BLOCK DIAGRAM CLK DATA LE REFIN RFINA RFINB 24-BIT INPUT REGISTER SDOUT AVDD DVDD CE AGND DGND 14-BIT R COUNTER R COUNTER LATCH FUNCTION LATCH N COUNTER LATCH 13-BIT N COUNTER M3 M2 M1 MUX SDOUT AVDD HIGH Z MUXOUT CPGND RSETVP CP PHASE FREQUENCY DETECTOR LOCK DETECT REFERENCE CHARGE PUMP CURRENT SETTING 1 ADF4002 CPI3 CPI2 CPI1 CPI6 CPI5 CPI4 CURRENT SETTING 2 06052-001 Figure 1.

Rev. 0 | Page 2 of 24 TABLE OF CONTENTS Very Low Jitter Encode Clock for High Speed Converters... 17

REVISION HISTORY

4/06—Revision 0: Initial Version

Rev. 0 | Page 3 of 24 SPECIFICATIONS AVDD = DVDD = 3 V ± 10%, AVDD ≤ VP ≤ 5.5 V , AGND = DGND = CPGND = 0 V , RSET = 5.1 kΩ, dBm referred to 50 Ω, TA = TMAX to TMIN, unless otherwise noted. Table 1. B Version1 Parameter Min Typ Max Unit Test Conditions/Comments RF CHARACTERISTICS See Figure 12 for input circuit RF Input Sensitivity −10 0 dBm RF Input Frequency (RFIN) 5 400 MHz For RFIN < 5 MHz, ensure slew rate (SR) > 4 V/μs REFIN CHARACTERISTICS REFIN Input Frequency 20 300 MHz For REFIN < 20 MHz, ensure SR > 50 V/μs REFIN Input Sensitivity2 0.8 VDD V p-p Biased at AVDD/23 REFIN Input Capacitance 10 pF REFIN Input Current ±100 μA PHASE DETECTOR Phase Detector Frequency4 200 MHz CHARGE PUMP Programmable, see Figure 19 ICP Sink/Source High Value 5 mA With RSET = 5.1 kΩ Low Value 625 μA Absolute Accuracy 2.5 % With RSET = 5.1 kΩ RSET Range 3.0 11 kΩ See Figure 19 ICP Three-State Leakage 1 nA TA = 25°C ICP vs. VCP 1.5 % 0.5 V ≤ VCP ≤ VP – 0.5 V Sink and Source Current Matching 2 % 0.5 V ≤ VCP ≤ VP – 0.5 V ICP vs. Temperature 2 % VCP = VP/2 LOGIC INPUTS VIH, Input High Voltage 1.4 V VIL, Input Low Voltage 0.6 V IINH, IINL, Input Current ±1 μA CIN, Input Capacitance 10 pF LOGIC OUTPUTS VOH, Output High Voltage 1.4 V Open-drain output chosen, 1 kΩ pull-up resistor to 1.8 V VOH, Output High Voltage VDD – 0.4 V CMOS output chosen IOH 100 μA VOL, Output Low Voltage 0.4 V IOL = 500 μA POWER SUPPLIES AVDD 2.7 3.3 V DVDD AVDD VP AVDD 5.5 V AVDD ≤ VP ≤ 5.5 V IDD5 (AIDD DD + DI ) 5.0 6.0 mA IP 0.4 mA TA = 25°C Power-Down Mode 1 μA AIDD + DIDD NOISE CHARACTERISTICS Normalized Phase Noise Floor6 –222 dBc/Hz 1 Operating temperature range (B version) is –40°C to +85°C. 2 AVDD = DVDD = 3 V. 3 AC coupling ensures AVDD/2 bias. 4 Guaranteed by design. Sample tested to ensure compliance. Use of the PFD at frequencies above 104 MHz requires the minimum antibacklash pulse width enabled. frequency in MHz. 6 The normalized phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value) and 10logFPFD. PNSYNTH = PNTOT – 10logFPFD – 20logN. All phase noise measurements were performed with an Agilent E5500 phase noise test system, using the EVAL- ADF4002EB1 and the HP8644B as the PLL reference.

1 Guaranteed by design, but not production tested. 2 Operating temperature range (B version) is –40°C to +85°C. Figure 2. Timing Diagram

TA = 25°C, unless otherwise noted. should be taken for handling and assembly. Table 4. Thermal Impedance degradation or loss of functionality.

Figure 3. TSSOP (Top View)

15 MUXOUT

13 DATA

12 CLK

Figure 4. LFCSP_VQ (Top View) Table 5. Pin Function Descriptions 1 19 RSET Connecting a resistor between this pin and CPGND sets the maximum charge pump output current. Where RSET = 5.1 kΩ and ICP MAX = 5 mA. 3 1 CPGND Charge Pump Ground. This is the ground return path for the charge pump. 4 2, 3 AGND Analog Ground. This is the ground return path of the RF input. bypass capacitor, typically 100 pF. See Figure 12. 6 5 RFINA Input to the RF Input. This small signal input is ac-coupled to the external VCO. plane should be placed as close as possible to the AVDD pin. AVDD must be the same value as DVDD. 9 9, 10 DGND Digital Ground. input is a high impedance CMOS input. of the four latches; the latch is selected using the control bits. plane should be placed as close as possible to this pin. DVDD must be the same value as AVDD. can be set to 5.5 V and used to drive a VCO with a tuning range of up to 5 V.

Figure 16. Latch Summary

15ns MUST OCCUR BEFORE LOCK DETECT IS SET. 15ns MUST OCCUR BEFORE LOCK DETECT IS SET. Figure 17. Reference Counter Latch Map

SETTING 1 IS PERMANENTLY USED. SETTING 2 IS PERMANENTLY USED. Figure 18. N Counter Latch Map

0 X X

Figure 19. Function Latch Map

Figure 20. Initialization Latch Map

Rev. 0 | Page 16 of 24 Charge Pump Currents CPI3, CPI2, and CPI1 program Current Setting 1 for the charge pump. CPI6, CPI5, and CPI4 program Current Setting 2 for the charge pump. See Figure 19 for the truth table. PD Polarity This bit sets the phase detector polarity bit (see Figure 19). CP Three-State This bit controls the CP output pin. Setting the bit high, puts the CP output into three-state. With the bit set low, the CP output is enabled. THE INITIALIZATION LATCH The initialization latch is programmed when C2, C1 = 1, 1. This is essentially the same as the function latch (programmed when C2, C1 = 1, 0). However, when the initialization latch is programmed there is an additional internal reset pulse applied to the R and N counters. This pulse ensures that the N counter is at load point when the N counter data is latched and the device begins counting in close phase alignment. If the latch is programmed for synchronous power-down (CE pin is high; PD1 bit is high; and PD2 bit is low), the internal pulse also triggers this power-down. The prescaler reference and the oscillator input buffer are unaffected by the internal reset pulse, thereby maintaining close phase alignment when counting resumes. When the first N counter data is latched after initialization, the internal reset pulse is reactivated. However, successive AB counter loads after this do not trigger the internal reset pulse. Device Programming After Initial Power-Up After initially powering up the device, there are three ways to program the device. Initialization Latch Method 1. Apply VDD. 2. Program the initialization latch (11 in two LSBs of input word). Make sure that the F1 bit is programmed to 0. 3. Conduct a function latch load (10 in two LSBs of the control word). Make sure that the F1 bit is programmed to 0. 4. Perform an R load (00 in two LSBs). 5. Perform an N load (01 in two LSBs). When the initialization latch is loaded, the following occurs:

• The function latch contents are loaded.
• An internal pulse resets the R, N, and timeout counters to load-state conditions and three-states the charge pump. Note that the prescaler band gap reference and the oscillator input buffer are unaffected by the internal reset pulse, allowing close phase alignment when counting resumes.
• Latching the first N counter data after the initialization word activates the same internal reset pulse. Successive N loads do not trigger the internal reset pulse unless there is another initi alization. CE Pin Method 1. Apply VDD. 2. Bring CE low to put the device into power-down. This is an asynchronous power-down because it happens immediately. 3. Program the function latch (10). 4. Program the R counter latch (00). 5. Program the N counter latch (01). 6. Bring CE high to take the device out of power-down. The R and N counters resume counting in close alignment. Note that after CE goes high, a duration of 1 μs can be required for the prescaler band gap voltage and oscillator input buffer bias to reach steady state. CE can be used to power the device up and down to check for channel activity. The input register does not need to be reprogrammed each time the device is disabled and enabled, as long as it has been programmed at least once after V DD was initially applied. Counter Reset Method 1. Apply VDD. 2. Do a function latch load (10 in two LSBs). As part of this step, load 1 to the F1 bit. This enables the counter reset. 3. Perform an R counter load (00 in two LSBs). 4. Perform an N counter load (01 in two LSBs). 5. Do a function latch load (10 in two LSBs). As part of this step, load 0 to the F1 bit. This disables the counter reset. This sequence provides the same close alignment as the initialization method. It offers direct control over the internal reset. Note that counter reset holds the counters at load point and three-states the charge pump, but does not trigger synchronous power-down.

Rev. 0 | Page 19 of 24 The bottom of the lead frame chip scale package has a central thermal pad. The thermal pad on the printed circuit board should be at least as large as this exposed pad. On the printed circuit board, there should be a clearance of at least 0.25 mm between the thermal pad and the inner edges of the pad pattern. This ensures that shorting is avoided. Thermal vias can be used on the printed circuit board thermal pad to improve thermal performance of the package. If vias are used, they should be incorporated in the thermal pad at a 1.2 mm pitch grid. The via diameter should be between 0.3 mm and 0.33 mm and the via barrel should be plated with 1 oz. copper to plug the via. The user should connect the printed circuit board thermal pad to AGND.

Figure 25. 16-Lead Thin Shrink Small Outline Package [TSSOP]

0.80 MAX

0.65 TYP

0.05 MAX

0.02 NOM

0.25 MIN

Figure 26. 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

Rev. 0 | Page 21 of 24 ORDERING GUIDE Model Temperature Range Package Description Package Option ADF4002BRUZ1 –40°C to +85°C 16-Lead TSSOP RU-16 ADF4002BRUZ–RL1 –40°C to +85°C 16-Lead TSSOP RU-16 ADF4002BRUZ–RL71 –40°C to +85°C 16-Lead TSSOP RU-16 ADF4002BCPZ1 –40°C to +85°C 20-Lead LFCSP_VQ CP-20-1 ADF4002BCPZ–RL1 –40°C to +85°C 20-Lead LFCSP_VQ CP-20-1 ADF4002BCPZ–RL71 –40°C to +85°C 20-Lead LFCSP_VQ CP-20-1 EVAL-ADF4002EB1 Evaluation Board EVAL-ADF411XEB1 Evaluation Board 1 Z = Pb-free part.

Rev. 0 | Page 22 of 24 NOTES

Rev. 0 | Page 23 of 24 NOTES

Rev. 0 | Page 24 of 24 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06052-0-4/06(0)