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a ADF4001 Tel: 781/329-4700 www.analog.com Fax: © Analog Devices, Inc. All rights reserved. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. REV.
200 MHz Clock Generator PLL
CPI3 CPI2 CPI1 CPI6 CPI5 CPI4 M1M3 M2 SDOUT AVDD REFIN CLK DATA LE AVDD DVDD VP CPGND RSET 14-BIT R COUNTER R COUNTER LA TCH FUNCTION LA TCH 24-BIT INPUT REGISTER N COUNTER LA TCH SDOUT ADF4001 MUXOUTMUX HIGH Z CURRENT SETTING 2 CHARGE PUMP CP CE AGND DGND PHASE FREQUENCY DETECTOR REFERENCE
FEATURES
200 MHz Bandwidth
2.7 V to 5.5 V Power Supply Separate Charge Pump Supply (V P) Allows Extended Tuning Voltage in 5 V Systems Programmable Charge Pump Currents 3-Wire Serial Interface Hardware and Software Power-Down Mode Analog and Digital Lock Detect Hardware Compatible to the ADF4110/ADF4111/ ADF4112/ADF4113 Typical Operating Current 4.5 mA Ultralow Phase Noise 16-Lead TSSOP 20-Lead LFCSP
APPLICATIONS
SONET, ATM, ADM, DSLAM, SDM GENERAL DESCRIPTION The ADF4001 clock generator can be used to implement clock sources for PLLs that require very low noise, stable reference signals. It consists of a low noise digital PFD (phase frequency detector), a precision charge pump, a programmable reference divider, and a programmable 13-bit N counter. In addition, the 14-bit reference counter (R counter) allows selectable REF IN frequencies at the PFD input. A complete PLL (phase-locked loop) can be implemented if the synthesizer is used with an exter- nal loop filter and VCO (voltage controlled oscillator) or VCXO (voltage controlled crystal oscillator). The N minimum value of 1 allows flexibility in clock generation. 2013 781/461-3113 B
REV. –2– ADF4001–SPECIFICATIONS1 (AVDD = DVDD = 3 V /H11550 10%, 5 V /H11550 10%; AVDD ≤ VP ≤ 6.0 V ; AGND = DGND = CPGND = 0 V; RSET = 4.7 k/H9024; TA = TMIN to TMAX, unless otherwise noted; dBm referred to 50 /H9024.) Parameter B Version Unit Test Conditions/Comments RF CHARACTERISTICS (3 V) See Figure 3 for Input Circuit RF Input Frequency 5/165 MHz min/max RF Input Sensitivity –10/0 dBm min/max RF CHARACTERISTICS (5 V) RF Input Frequency 10/200 MHz min/max –5/0 dBm min/max 20/200 MHz min/max –10/0 dBm min/max REFIN CHARACTERISTICS See Figure 2 for Input Circuit REFIN Input Frequency 5/104 MHz min/max For f < 5 MHz, Use DC-Coupled Square Wave (0 to VDD) REFIN Input Sensitivity2 –5 dBm min AC-Coupled. When DC-Coupled: 0 to VDD Max (CMOS Compatible) REFIN Input Capacitance 10 pF max REFIN Input Current ±100 µA max PHASE DETECTOR Phase Detector Frequency 3 55 MHz max CHARGE PUMP ICP Sink/Source Programmable: See Table V High Value 5 mA typ With R SET = 4.7 kΩ Low Value 625 µA typ Absolute Accuracy 2.5 % typ With R SET = 4.7 kΩ RSET Range 2.7/10 k Ω typ See Table V ICP Three-State Leakage Current 1 nA typ Sink and Source Current Matching 2 % typ 0.5 V ≤ VCP ≤ VP – 0.5 ICP vs. VCP 1.5 % typ 0.5 V ≤ VCP ≤ VP – 0.5 ICP vs. Temperature 2 % typ V CP = VP/2 LOGIC INPUTS VINH, Input High Voltage 0.8 × DVDD V min VINL, Input Low Voltage 0.2 × DVDD V max IINH/IINL, Input Current ± 1 µA max CIN, Input Capacitance 10 pF max LOGIC OUTPUTS VOH, Output High Voltage DVDD – 0.4 V min I OH = 500 µA VOL, Output Low Voltage 0.4 V max IOL = 500 µA POWER SUPPLIES AVDD 2.7/5.5 V min/V max DVDD AVDD VP AVDD/6.0 V min/V max AV DD ≤ VP ≤ 6.0 V IDD 4 (AIDD + DIDD) ADF4001 5.5 mA max 4.5 mA typical IP 0.4 mA max TA = 25°C Low Power Sleep Mode 1 µA typ NOISE CHARACTERISTICS ADF4001 Phase Noise Floor 5 –161 dBc/Hz typ @ 200 kHz PFD Frequency –153 dBc/Hz typ @ 1 MHz PFD Frequency Phase Noise Performance 6 @ VCXO Output
200 MHz Output7 –99 dBc/Hz typ @ 1 kHz Offset and 200 kHz PFD Frequency
200 MHz Output7 –90/–95 dBc typ/dBc typ @ 200 kHz/400 kHz and 200 kHz PFD Frequency
1Operating temperature range (B Version) is –40 °C to +85°C. 2AVDD = DVDD = 3 V; for AV DD = DVDD = 5 V, use CMOS compatible levels. 3Guaranteed by design. Sample tested to ensure compliance. 4TA = 25°C; AVDD = DVDD = 3 V; RF IN = 100 MHz. 5The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 logN (where N is the N divider value). 6The phase noise is measured with the EVAL-ADF4001EB1 evaluation board and the HP8562E spectrum analyzer. 7fREFIN = 10 MHz; f PFD = 200 kHz; Offset Frequency = 1 kHz; f RF = 200 MHz; N = 1000; Loop B/W = 20 kHz. Specifications subject to change without notice. B
Guaranteed by design but not production tested. Specifications subject to change without notice. Figure 1. Timing Diagram conditions for extended periods may affect device reliability. recommended to avoid performance degradation or loss of functionality.
Table 1. Pin Function Descriptions So, with RSET = 4.7 kΩ, ICP MAX = 5 mA. in turn, drives the external VCO or VCXO. 3 1 CPGND Charge Pump Ground. This is th e ground return path for the charge pump. 4 2, 3 AGND Analog Ground. This is the ground return path of the prescaler. plane with a small bypass capacitor, typically 100 pF. See Figure 3. 6 5 RF INA Input to the N counter. This small signal inp ut is ac-coupled to the external VCO or VCXO. or CMOS crystal oscillator or can be ac-coupled. 9 9, 10 DGND Digital Ground. the status of the power-down bit F2. bits. This input is a high impedance CMOS input. loaded into one of the four latches, the latch being selected by using the control bits. frequency to be accessed externally. N/A EP EPAD Exposed Pad. The exposed pad should be connected to AGND.
- TRANSISTOR COUNT 6425 (CMOS)
- TRANSISTOR COUNT 6425 (CMOS) AND 50 (BIPOLAR).
- CONNECT EXPOSED PAD TO AGND.
REV. –5– Typical Performance Characteristics–ADF4001 FREQUENCY – MHz AMPLITUDE – dBm –10 –15 –20 –25 –30 –35 50 100 150 200 250 TA = +25/H11543C TA = +85/H11543C TA = –40/H11543C TPC 1. Input Sensitivity, V DD = 3.3 V, 100 pF on RF IN FREQUENCY – MHz AMPLITUDE – dBm –10 –15 –20 –25 –30 51 0 1 52 02 5 TPC 2. Input Sensitivity, V DD = 3.3 V, 100 pF on RF IN –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 OUTPUT POWER – dB –2kHz –1kHz 200MHz 1kHz 2kHz 0 REFERENCE LEVEL = –5.7dBm VDD = 3V , VP = 5V ICP = 2.5mA PFD FREQUENCY = 200kHz LOOP BANDWIDTH = 20kHz RES. BANDWIDTH = 10Hz VIDEO BANDWIDTH = 10Hz SWEEP = 1.9 SECONDS AVERAGES = 26 –99.2dBc/Hz TPC 3. Phase Noise (200 MHz, 200 kHz, 20 kHz) FREQUENCY OFFSET FROM 200MHz CARRIER – Hz –40 100 PHASE NOISE – dBc/Hz –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 1k 10k 100k 1M 0.229/H11543 rms 10dB/DIVISION R L = –40dBc/Hz rms NOISE = 0.229 DEGREES TPC 4. Integrated Phase Noise (200 MHz, 200 kHz, 20 kHz) –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 OUTPUT POWER – dB –200kHz –100kHz 0200MHz 100kHz 200kHz VDD = 3V , VP = 5V ICP = 2.5mA PFD FREQUENCY = 200kHz LOOP BANDWIDTH = 20kHz RES. BANDWIDTH = 300Hz VIDEO BANDWIDTH = 300Hz SWEEP = 4.2 SECONDS AVERAGES = 20 REFERENCE LEVEL = –5.7dBm –92.3dBc TPC 5. Reference Spurs (200 MHz, 200 kHz, 20 kHz) B
Figure 6. MUXOUT Circuit this output will be high with narrow low-going pulses. mary of how the latches are programmed.
00 R Counter
01 N Counter
10 Function Latch
11 Initialization Latch
REV. ADF4001 –8– Table III. Reference Counter Latch Map LDP OPERATION 0T HREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN 15ns MUST OCCUR BEFORE LOCK DETECT IS SET. 1F IVE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN 15ns MUST OCCUR BEFORE LOCK DETECT IS SET. ABP2 ABP1 ANTIBACKLASH PULSE WIDTH 002 . 9 n s 011 . 3 n s 106 . 0 n s 112 . 9ns TEST MODE BITS SHOULD BE SET TO 00 FOR NORMAL OPERA TION DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 C2 (0) C1 (0)R1R2 R3 R4 R5R7R14ABP1T2LDP R13 R6 CONTROL BITS ABP2T1 DB21 R12 R11 R10 DB22DB23 R8R9 RESERVED LOCK DETECT PRECISION TEST MODE BITS ANTI- BACKLASH WIDTH 14-BIT REFERENCE COUNTER XXX X = DON’T CARE B
REV. ADF4001 –9– Table IV. N Counter Latch Map THESE BITS ARE NOT USED BY THE DEVICE AND ARE DON’T CARE BITS. F4 (FUNCTION LATCH) FASTLOCK ENABLE CP GAIN OPERATION 0 0C HARGE PUMP CURRENT SETTING
1 IS PERMANENTLY USED
0 1C HARGE PUMP CURRENT SETTING
2 IS PERMANENTLY USED
1 0C HARGE PUMP CURRENT SETTING
1 IS USED
1 1C HARGE PUMP CURRENT IS SWITCHED TO SETTING 2. THE TIME SPENT IN SETTING 2 IS DEPENDENT ON WHICH FASTLOCK MODE IS USED. SEE FUNCTION LATCH DESCRIPTION. N13 N12 N11 N3 N2 N1 N COUNTER DIVIDE RATIO DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 C2 (0) C1 (1)N1N2 N3N4N5N6N7N8 N9N10N11N12N13 CONTROL BITSRESERVED13-BIT N COUNTER DB21 RESERVED DB22DB23 CP GAIN X = DON’T CARE X X X XXX X X B
REV. ADF4001 –10– Table V. Function Latch Map DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 C2 (1) C1 (0)F1PD1M1 M2 M3F3CPI1CPI2CPI5CPI6 TC4PD2 F2 CONTROL BITS COUNTER RESET POWER- DOWN 1 MUXOUT CONTROL PHASE DETECTOR POLARITY CP THREE- STATE POWER- DOWN 2 CURRENT SETTING TIMER COUNTER CONTROL CPI3CPI4 DB21 CURRENT SETTING TC3 TC2 TC1 DB22DB23 FASTLOCK ENABLE FASTLOCK MODE F4F5 RESERVED CE PIN PD2 PD1 MODE
0 XXA SYNCHRONOUS POWER-DOWN
101A S Y NCHRONOUS POWER-DOWN 111S Y NCHRONOUS POWER-DOWN CPI6 CPI5 CP14 ICP (mA) CPI3 CPI2 CPI1 2.7k/H9024 4.7k/H9024 10k/H9024 000 1.088 0.625 0.294 001 2.176 1.25 0.588 010 3.264 1.875 0.882 011 4.352 2.5 1.176 100 5.44 3.125 1.47 101 6.528 3.75 1.764 110 7.616 4.375 2.058 111 8.704 5.0 2.352 TIMEOUT TC4 TC3 TC2 TC1 (PFD CYCLES) 00003 00017 00101 1 00111 5 01001 9 01012 3 01102 7 01113 1 10003 5 10013 9 10104 3 10114 7 11005 1 11015 5 11105 9 11116 3 F4 F5 FASTLOCK MODE 0X FASTLOCK DISABLED
10 FASTLOCK MODE 1
11 FASTLOCK MODE 2
000 THREE-STATE OUTPUT
101 N-CHANNEL OPEN-DRAIN
111 DGND
0 NORMAL
1 R, N COUNTER
X = DON’T CARE X X B
REV. ADF4001 –11– Table VI. Initialization Latch Map DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 C2 (1) C1 (1)F1PD1M1 M2 M3F3CPI1CPI2CPI5CPI6 TC4PD2 F2 CONTROL BITS COUNTER RESET POWER- DOWN 1 MUXOUT CONTROL PHASE DETECTOR POLARITY CP THREE- STATE POWER- DOWN 2 CURRENT SETTING TIMER COUNTER CONTROL CPI3CPI4 DB21 CURRENT SETTING TC3 TC2 TC1 DB22DB23 FASTLOCK ENABLE FASTLOCK MODE F4F5 RESERVED CE PIN PD2 PD1 MODE 101A S Y NCHRONOUS POWER-DOWN 111S Y NCHRONOUS POWER-DOWN CPI6 CPI5 CP14 ICP (mA) CPI3 CPI2 CPI1 2.7k/H9024 4.7k/H902410k/H9024 000 1.088 0.625 0.294 001 2.176 1.25 0.588 010 3.264 1.875 0.882 011 4.352 2.5 1.176 100 5.44 3.125 1.47 101 6.528 3.75 1.764 110 7.616 4.375 2.058 111 8.704 5.0 2.352 TIMEOUT TC4 TC3 TC2 TC1 (PFD CYCLES) 00003 00017 00101 1 00111 5 01001 9 01012 3 01102 7 01113 1 10003 5 10013 9 10104 3 10114 7 11005 1 11015 5 11105 9 11116 3 F4 F5 FASTLOCK MODE 0X FASTLOCK DISABLED X = DON’T CARE XX B
REV. ADF4001 –12– FUNCTION LATCH With C2, C1 set to 1, 0, the on-chip function latch will be pro- grammed. Table V shows the input data format for programming the function latch. Counter Reset DB2 (F1) is the counter reset bit. When this is 1, the R counter and the A, B counters are reset. For normal operation, this bit should be 0. Upon powering up, the F1 bit needs to be disabled, and the N counter resumes counting in close alignment with the R counter. (The maximum error is one prescaler cycle.) Power-Down DB3 (PD1) and DB21 (PD2) on the ADF4001 family provide programmable power-down modes. They are enabled by the CE pin. When the CE pin is low, the device is immediately disabled regardless of the states of PD2, PD1. In the programmed asynchronous power-down, the device pow- ers down immediately after latching a 1 into Bit PD1, with the condition that PD2 has been loaded with a 0. In the programmed synchronous power-down, the device power- down is gated by the charge pump to prevent unwanted frequency jumps. Once the power-down is enabled by writing a 1 into Bit PD1 (on condition that a 1 has also been loaded to PD2), the device will go into power-down on the occurrence of the next charge pump event. When a power-down is activated (either synchronous or asyn- chronous mode, including CE pin activated power-down), the following events occur:
- All active dc current paths are removed.
- The R, N, and timeout counters are forced to their load state conditions.
- The charge pump is forced into three-state mode.
- The digital clock detect circuitry is reset.
- The RF IN input is debiased.
- The reference input buffer circuitry is disabled.
- The input register remains active and capable of loading and latching data. MUXOUT Control The on-chip multiplexer is controlled by M3, M2, M1 on the ADF4001. Table V shows the truth table. Fastlock Enable Bit DB9 of the function latch is the fastlock enable bit. Only when this is 1 is fastlock enabled. Fastlock Mode Bit DB10 of the function latch is the fastlock mode bit. When fastlock is enabled, this bit determines which fastlock mode is used. If the fastlock mode bit is 0, fastlock mode 1 is selected; if the fastlock mode bit is 1, fastlock mode 2 is selected. Fastlock Mode 1 The charge pump current is switched to the contents of Current Setting 2. The device enters fastlock by having a 1 written to the CP gain bit in the N counter latch. The device exits fastlock by having a 0 written to the CP gain bit in the AB counter latch. Fastlock Mode 2 The charge pump current is switched to the contents of Current Setting 2. The device enters fastlock by having a 1 written to the CP gain bit in the N counter latch. The device exits fastlock under the control of the timer counter. After the timeout period determined by the value in TC4–TC1, the CP gain bit in the N counter latch is automatically reset to 0 and the device reverts to normal mode instead of fastlock. See Table V for the timeout periods. Timer Counter Control The user has the option of programming two charge pump currents. The intent is that the Current Setting 1 is used when the RF output is stable and the system is in a static state. Cur- rent Setting 2 is meant to be used when the system is dynamic and in a state of change (i.e., when a new output frequency is programmed). The normal sequence of events is as follows. The user initially decides what the preferred charge pump cur- rents are going to be. For example, they may choose 2.5 mA as Current Setting 1 and 5 mA as Current Setting 2. At the same time, they must also decide how long they want the secondary current to stay active before reverting to the primary current. This is controlled by the Timer Counter Control Bits DB14 to DB11 (TC4–TC1) in the function latch. The truth table is given in Table V. Now, when the user wishes to program a new output frequency, they can simply program the N counter latch with new value for N. At the same time, they can set the CP gain bit to a 1, which sets the charge pump with the value in CPI6–CPI4 for a period of time determined by TC4–TC1. When this time is up, the charge pump current reverts to the value set by CPI3–CPI1. At the same time, the CP gain bit in the N counter latch is reset to 0 and is now ready for the next time that the user wishes to change the frequency. Note that there is an enable feature on the timer counter. It is enabled when Fastlock Mode 2 is chosen by setting the fastlock mode bit (DB10) in the function latch to 1. Charge Pump Currents CPI3, CPI2, CPI1 program Current Setting 1 for the charge pump. CPI6, CPI5, CPI4 program Current Setting 2 for the charge pump. The truth table is given in Table V. PD Polarity This bit sets the PD polarity bit (see Table V). CP Three-State This bit sets the CP output pin. With the bit set high, the CP output is put into three-state. With the bit set low, the CP output is enabled. B
Figure 13. 16-Lead Thin Shrink Small Outline Package [TSSOP] Figure 14. 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] COMPLIANT TOJEDEC STANDARDS MO-220-WGGD-1.
0.02 NOM
0.20 REF
0.20 MIN
Rev. B | Page 17
REVISION HISTORY
4/13—Rev. A to Rev. B 10/03—Rev. 0 to Rev. A Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. ©2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D02569-0-4/13(B)