ADES1754

Analog Devices

14-Channel, High-Voltage Data- Acquisition Systems 19-101802; Rev 0; 11/23

Manufacturer: Analog Devices

Document: 322 Pages / 3Mb

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ADES1754/ADES1755/ADES1756

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Manufacturer or author: Analog Devices, Inc.
PDF pages: 322

Technical content

ADES1754/ADES1755/ADES1756 14-Channel, High-Voltage Data- Acquisition Systems 19-101802; Rev 0; 11/23 © 202 3 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. General Description The ADES1754/ADES1755/ADES1756 are flexible data-acquisition systems for the management of high - voltage and low -voltage battery modules. The systems can measure 14 cell voltages and a combination of six temperatures or system voltage measurements with fully redundant measurement engines in 162µs, or perform all inputs solely with the ADC measurement engine in 99μs. Fourteen internal balancing switches rated for >300mA for cell-balancing current support extensive built-in diagnostics. Up to 32 devices can be daisy - chained to manage 448 cells and monitor 192 temperatures. Cell and bus-bar voltages ranging from -2.5V to +5V are measured differentially over a 65V common -mode range, with a typical accuracy of 100µV. If oversampling is enabled, up to 128 measurements per channel can be averaged internally with 14-bit resolution and combined with digital post -processing IIR filtering for increased noise immunity. The system can shut itself down in the event of a thermal overload by measuring its own die temperature. The system uses Analog Devices' battery -management UART protocol for robust communications and supports an I2C controller interface for external device control. I t is optimized to support a reduced feature set of internal diagnostics and rapid-alert communication through both embedded communication and hardware-alert interfaces. Key Applications

Residential Battery Storage Systems
High-Voltage Battery Stacks
Battery-Backup Systems (UPS)
Super-Cap Systems
Battery-Powered Tools
EV Charging Ordering Information appears at end of data sheet. Benefits and Features
65V Operating Voltage
Ultra-Low Power Operation
Shutdown Mode: 2μA
Redundant ADC and Comparator (COMP) Acquisitions
Simultaneous Cell and Bus-Bar Voltage Acquisitions
14 Cell-Voltage Measurement Channels
2.2mV/5mV/10mV Accuracy (-40°C to +105°C)
1.8mV Accuracy (+5°C to +65°C)
14 Cell-Balancing Switches
>300mA Software-Programmable Balancing Current
Automated Balancing with Individual Cell Timers
Automated Balancing by Cell Voltage
Emergency Discharge Mode
Six Configurable Auxiliary Inputs for Temperature, Voltage, or GPIO
Integrated Die Temperature Measurement
Automatic Thermal Protection
Hot Plug-Tolerant without External Protection
Individually Configurable Safety Alerts
Overvoltage, Undertemperature Faults
Undervoltage, Overtemperature Faults
1-Cell Mismatch Alert
UART, Dual UART Interface
Battery-Management UART Protocol
Daisy-Chain up to 32 Devices
Inductive for Higher Galvanic Isolation
Up to 2Mbps Baud Rate (Auto-Detect)
1.5μs Propagation Delay per Device
Packet-Error Checking (PEC)
I2C Controller
Configurable Hardware-Alert Interfaces
32-Bit Unique Device ID

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 2 Typical Application Diagram SPI TO UART BRIDGE ADES1754 ADES1755 ADES1756 RXL TXU MICROPROCESSOR/MICROCONTROLLER RXU TXL ISOLA TION ALERTOUT ALERTIN ADES1754 ADES1755 ADES1756 ISOLA TION ISOLA TION RXL TXU RXU TXL ALERTOUT ALERTIN SPI TO UART BRIDGE ISOLA TION

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 3 Absolute Maximum Ratings DCIN, SWn, VBLK, Cn to AGND -0.3V to min (V HV + 0.3 or 72)V RXLP, RXLN, RXUP, RXUN, ALERTIN to AGND -30V to +30V Maximum Continuous Current into Any Pin (Note 1) -50mA to +50mA Maximum Continuous Current into SWn Pin (Note 2) .. -650mA to +650mA Maximum Average Power for ESD Diodes (Note 3) 14.4W / √t Note 1: Balancing switches disabled. Note 2: One balancing switch enabled, 60s (max). Note 3: Average power for time period t where t is the time constant (in µs) of the transient diode current during hot-plug event. For, example, if t is 330µs, the maximum average power is 0.793W. Peak current must never exceed 2A. Actual average power during hot-plug must be calculated from the diode current waveform for the application circuit and compared to the maximum rating. Note 4: Multilayer board. For TA > +70°C, derate 25mW/°C. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Package Information

Land Pattern Number 90-0141 Thermal Resistance, Four Layer Board: Junction to Ambient (θJA) 40°C/W Junction to Case (θJC) 8°C/W For the latest package outline information and land patterns (footprints), go to the Package Index on the Analog Devices website. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. For detailed information on package thermal considerations, refer to Thermal Characterization of IC Packages.

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 4

Electrical Characteristics

(VDCIN = +56V, TA = TMIN to TMAX unless otherwise noted, where TMIN = -40°C and TMAX = +105°C. Typical values are at TA = +25°C. Operation is with the recommend application circuit. (Note 5)) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS POWER REQUIREMENTS Supply Voltage, DCIN VDCIN 9 65 V Supply Voltage VDDL2, VDDL3 VDDL2, VDDL3, VDDIO VDDL2 = VDDL3 External overdrive (>VDDL2/3_REG) allowed. Also used as VDDIO in I2C applications. VDDL2/3 _REG 3.3 5.5 V DCIN Current, Shutdown Mode IDCSHDN VSHDNL = 0V 0.1 µA DCIN Current, Standby Mode IDCSTBY VSHDNL > 1.8V, UART in idle mode; not in acquisition mode; balance switches, test current sources, and alert interface disabled; Note 6 2.2 3.1 mA DCIN Current, ADC Acquisition Mode IDC_ADC All cell and auxiliary measurements enabled, OVSAMPL[2:0] = 000b; Note 6 4.2 5 mA DCIN Current, COMP Acquisition Mode IDC_COMP All cell and auxiliary measurements enabled, OVSAMPL[2:0] = 000b; Note 6 4.6 5.5 mA DCIN Current, ADC + COMP Acquisition Mode IDC_ADCCOMP All cell and auxiliary measurements enabled; Note 6 5.4 6.4 mA DCIN Incremental Current, UART Communication IDCCOMM_UA RT Baud rate = 2Mbps (0% idle time preambles mode), 200pF load on TXUP and TXUN, TXL not active, not in acquisition mode, BALSWEN, CTSTEN = 0000h; Note 6 160 230 μA HV Current, ADC Acquisition Mode IHVMEAS ADC-only acquisition, all cells and auxiliary channels enabled, VHV = VDCIN + 5.5V 0.7 0.9 1.1 mA HV Current, Comparator Scan Mode IHVCOMP COMP only acquisition, all cells and auxiliary channels enabled, VHV = VDCIN + 5.5V 0.7 0.9 1.1 mA Incremental HV Current, Cell-Balancing Mode IHVBAL VHV = VDCIN + 5.5V, n balancing switches enabled (n + 1) x (n + 1) x 15.5 (n + 1) x 26 µA CELL VOLTAGE INPUTS (Cn, VBLK) Differential Input Range VCELLn Unipolar mode, Note 7 0 5 V Bipolar mode, Note 7 -2.5 2.5 Common-Mode Input Range VCnCM Not connected to SWn inputs 0 65 V Input Leakage Current ILKG_Cn Not in acquisition mode, VCn = 65V -100 ±10 100 nA VBLK Input Resistance RVBLK VBLK = VDCIN = 57.6V 4.5 10 20 MΩ HVMUX Switch Resistance RHVMUX CTSTDAC[3:0] = Fh 1.7 3.3 5 kΩ CELL-BALANCING INPUTS (SWn) Leakage Current ILKG_SW VSW0 = 0V, VSWn = 5V, VSWn - 1 = 0V -1.0 +1.0 µA Resistance, SWn to SWn-1 RSW BALSWEN[n-1] = 1, ISWn = 100mA 0.5 1.25 2.25 Ω BALSWEN[n-1] = 1, ISWn = 300mA; Note 8 1.3

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 5 (VDCIN = +56V, TA = TMIN to TMAX unless otherwise noted, where TMIN = -40°C and TMAX = +105°C. Typical values are at TA = +25°C. Operation is with the recommend application circuit. (Note 5)) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Maximum Allowed Balancing Current IBAL_MAX TJ = +105°C, CBMEASEN = 0x00, FLXPCKEN1/2 = 0, all even or all odd channels enabled. Note 9 650 mA AUXILIARY INPUTS (AUXINn) Input Voltage Range VAUXIN VADCREF = VTHRM or VREF based on AUXREFSEL 0 VADCRE F V Input Leakage Current ILKG_AUX Not in acquisition mode, VAUXINn = 1.65V -400 +10 +400 nA THRM OUTPUT Switch Resistance, VAA to THRM RTHRM 25 70 Ω Leakage Current ILKG_THRM VTHRM = VAA -1 +1 µA MEASUREMENT ACCURACY ADC Measurement Error, HVMUX Inputs VCELLnERR Unipolar mode; VCELLn = 3.6V; SCANMODE = 0x0, 0x1; Note 10 ±200 μV Unipolar mode; 0.2V ≤ VCELLn ≤ 4.8V; +5°C < temp < +65°C; SCANMODE = 0x0, 0x1; Note 10 -1.8 +1.8 mV Unipolar mode; 0.2V ≤ VCELLn ≤ 4.8V; - 40°C < temp < +105°C; SCANMODE = 0x0, 0x1; Note 10 (ADES1754) -2.2 +2.2 Unipolar mode; 0.2V ≤ VCELLn ≤ 4.8V; - 40°C < temp < +105°C; SCANMODE = 0x0, 0x1; Note 10 (ADES1755) -5 +5 Unipolar mode; 0.2V ≤ VCELLn ≤ 4.8V; - 40°C < temp < +105°C; SCANMODE = 0x0, 0x1; Note 10 (ADES1756) -10 +10 Bipolar mode; VCELLn = 1.1V; SCANMODE = 0x0, 0x1; Note 10 ±200 μV Bipolar mode; -2.3V ≤ VCELLn ≤ +2.3V; +5°C < temp < +65°C; SCANMODE = 0x0, 0x1; Note 10 -1.8 +1.8 mV Bipolar mode; -2.3V ≤ VCELLn ≤ +2.3V; - 40°C < temp < +105°C; SCANMODE = 0x0, 0x1; Note 10 (ADES1754) -2.2 +2.2 Bipolar mode; -2.3V ≤ VCELLn ≤ +2.3V; - 40°C < temp < +105°C; SCANMODE = 0x0, 0x1; Note 10 (ADES1755) -5 +5 Bipolar mode; -2.3V ≤ VCELLn ≤ +2.3V; - 40°C < temp < +105°C; SCANMODE = 0x0, 0x1; Note 10 (ADES1756) -10 +10 ADC Measurement Error, ALTMUX Inputs VSWnERR Unipolar mode; VCELL = 3.6V; SCANMODE = 0x0, 0x1; Note 10 ±200 μV

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 6 (VDCIN = +56V, TA = TMIN to TMAX unless otherwise noted, where TMIN = -40°C and TMAX = +105°C. Typical values are at TA = +25°C. Operation is with the recommend application circuit. (Note 5)) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Unipolar mode; 0.2V ≤ VCELLn ≤ 4.8V; SCANMODE = 0x0, 0x1; Note 10 (ADES1754) -2.2 +2.2 mV Unipolar mode; 0.2V ≤ VCELLn ≤ 4.8V; SCANMODE = 0x0, 0x1; Note 10 (ADES1755) -5 +5 Unipolar mode; 0.2V ≤ VCELLn ≤ 4.8V; SCANMODE = 0x0, 0x1; Note 10 (ADES1756) -10 +10 Bipolar mode; VCELLn = 1.1V; SCANMODE = 0x0, 0x1; Note 10 ±200 μV Bipolar mode; 0 ≤ VCELLn ≤ 2.3V; SCANMODE = 0x0, 0x1 (ADES1754) -2.2 +2.2 mV Bipolar mode; 0 ≤ VCELLn ≤ 2.3V; SCANMODE = 0x0, 0x1 (ADES1755) -5 +5 Bipolar mode; 0 ≤ VCELLn ≤ 2.3V; SCANMODE = 0x0, 0x1 (ADES1756) -10 +10 ADC Measurement Error, VBLK Input VBLKERR 9V ≤ VBLK ≤ 64.4V; VDCIN = 64.4V; SCANMODE = 0x0, 0x1; Note 11 -160 +160 mV ADC Measurement Error, Ratiometric AUXIN Inputs VOS_AUX_RAT IO AUXREF[n] = 0b; SCANMODE = 0x0, 0x1; OVSAMPL != 0x0; Note 11 -3.5 +3.5 mV ADC Measurement Error, Absolute AUXIN Inputs VOS_AUX_ABS AUXREF[n] = 1b; SCANMODE = 0x0, 0x1; Note 11 -4 +4 mV Total Measurement Error, Die Temperature TDIE_ERR TJ = -40°C to +105°C; OVSAMPL[2:0] = 000b; Note 8 -5 0 +5 °C Cell Input Referred Noise VCELLNOISE OVSAMPL[2:0] = 0x3h; Note 8 250 μVRMS Auxiliary Input Referred Noise VAUXNOISE OVSAMPL[2:0] = 0x3h; Note 8 50 μVRMS Differential Nonlinearity (Any Conversion) DNL ±1.0 LSb ADC Resolution 12 bits Level-Shifting Amplifier Offset VOS_LSAMP DIAGSEL[2:0] = 011b; Note 12 -2 +0.1 +2 mV COMPARATOR Input Common-Mode Range VCM_COMP 0 65 V Input Differential Mode Range VDM_COMP 0 5 V Comparator Accuracy CELL VOS_COMP_C ELL 0.2V ≤ VCELLn ≤ 4.8V -20 +20 mV Comparator Accuracy AUX VOS_COMP_A UX 0V ≤ VAUXn ≤ VAA -20 +20 mV SHDNL INPUT AND CHARGE PUMP Input Low Voltage VIL_SHDNL 0.6 V Input High Voltage VIH_SHDNL 1.8 V Regulated Voltage VSHDNLIMIT VDCIN ≥ 12V 7 10.8 14 V VDCIN = 9V 8.5

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 7 (VDCIN = +56V, TA = TMIN to TMAX unless otherwise noted, where TMIN = -40°C and TMAX = +105°C. Typical values are at TA = +25°C. Operation is with the recommend application circuit. (Note 5)) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Pull-down Resistance RFORCEPOR FORCEPOR = 1 200 500 800 Ω Input Leakage Current ILKG_SHDNL VSHDNL = 3.3V 1 µA VSHDNL = 65V 40 75 Charge Pump Current - UARTL/UARTU ISHDNL VSHDNL < VSHDNLIMIT; baud rate = 2Mbps; Note 13 15 117 350 µA UARTSEL UARTSEL Input High Voltage VIH_UARTSEL 0.7 x VAA V GENERAL-PURPOSE I/O (GPIOn) Input Low Voltage VIL_GPIO 0.3 x VDDL2 V Input High Voltage VIH_GPIO 0.7 x VDDL2 V Pull-down Resistance RGPIO AUXINn/GPIOn configured as GPIO input 0.5 2 7.5 MΩ Output Low Voltage VOL_GPIO ISINK = 4mA 0.4 V Output High Voltage VOH_GPIO ISOURCE = 4mA VDDL2 - 0.4 V ALERTIN ALERTIN Comparator Threshold VCL VDDL2/3 /2 - 0.4 VDDL2/3 VDDL2/3 /2 + 0.4 V ALERTIN Comparator Hysteresis VHYS_ALERTI N 75 mV ALERTIN Common- Mode Voltage Bias VCM VDDL2/3 /2 V Leakage Current ILKG_ALERTIN VALERTIN = 1.5V ±1.0 µA Input Capacitance CALERTIN 2 pF Bit Period tBIT Note 14 8 fOSC_16 M ALERTIN Fall Time tALERTIN_FALL Note 8, Note 15 0.5 tBIT ALERTIN Rise Time tALERTIN_RISE Note 8, Note 15 0.5 tBIT ALERTIN Qualification Time tALERTIN_QUA L 25 μs Propagation Delay (ALERTIN Port to ALERTOUT Port) tALERT_PROP 2.5 3 tBIT Start-Up Time from SHNDL High and VAA = 0V to ALERTIN Valid tALERTIN_STA RTUP 1 ms ALERTOUT Output Low Voltage VOL_ALERTOU T ISINK = 20mA 0.4 V Output High Voltage VOH_ALERTOU T ISOURCE = 20mA VDDL2 - 0.4 V Leakage Current ILKG_ALERTO UT VALERTOUT = 1.5V -1 +1 µA 3.3V REGULATOR (VDDL2, VDDL3)

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 8 (VDCIN = +56V, TA = TMIN to TMAX unless otherwise noted, where TMIN = -40°C and TMAX = +105°C. Typical values are at TA = +25°C. Operation is with the recommend application circuit. (Note 5)) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 3.3V Regulator Output Voltage VDDL2/3_REG 0 ≤ IDDL2/3 < 30mA 3.2 3.3 3.4 V Short-Circuit Current IDDL2/3_SC VDDL2/3 shorted to AGND 30 mA 1.8V REGULATOR (VAA) 1.8V Regulator Output Voltage VAA 0 ≤ IAA < 3mA 1.71 1.8 1.89 V Short-Circuit Current IAA_SC VAA shorted to AGND 10 mA POR Threshold V1.8REG_POR RISE VAA rising 1.3 1.5 1.65 V V1.8REG_POR HYS 50 mV THERMAL SHUTDOWN Thermal Shutdown Temperature TSHDN Temperature rising; Note 8 +145 °C Thermal Shutdown Hysteresis THYS Note 8 15 °C HV CHARGE PUMP Output Voltage (VHV - VDCIN) VHV-DCIN 9V ≤ VDCIN ≤ 12V, ILOAD = 1.5mA 6.5 6.9 7.4 V 12V ≤ VDCIN ≤ 65V, ILOAD = 3mA 6.5 6.9 7.4 Output Voltage (VHV - VTOPCELL) VHV- DCIN_FLEX 14V ≤ VDCIN ≤ 65V, ILOAD = 3mA, FLXPCKEN1/2 = 1b 8.0 8.5 9.0 V Charge Pump Efficiency EffHVCP VDCIN = 57.6V; Note 16 38 % OSCILLATORS LFOSC Frequency fLFOSC 32.11 32.768 33.42 kHz HFOSC Frequency fHFOSC 15.68 16 16.32 MHz DIAGNOSTIC TEST SOURCES Cell Test Source Current ITSTCn CTSTDAC[3:0] = 9h, VC0 < VDDL2/3 - 1.4V, VDDL2/3 = 3.3V 50 62.5 75 µA CTSTDAC[3:0] = 6h, VC0 < VDDL2/3 - 1.4V, VDDL2/3 = 3.3V 36 45 54 CTSTDAC[3:0] = 6h, VC1-C14 > VAGND + 1.4V -54 -45 -36 CTSTDAC[3:0] = 9Fh, VC1-C14 > VAGND HVMUX Test Source Current ITSTHVMUX CTSTDAC[3:0] = 9h, VCn < VHV - 1.4V, VHV = 53.5V 25 31.25 37.5 µA CTSTDAC[3:0] = 6h, VCn < VHV - 1.4V, VHV = 53.5V 18 22.5 27 AUXIN Test Source Current ITSTAUXIN CTSTDAC[3:0] = 9h, VAUXINn < VDDL2/3 - 1.4V, VDDL2/3 = 3.3V 50 62.5 75 µA CTSTDAC[3:0] = 6h, VAUXINn < VDDL2/3 – 1.4V, VDDL2/3 = 3.3V 36 45 54 CTSTDAC[3:0] = 6h, VAUXINn > VAGND + 1.4V -54 -45 -36 CTSTDAC[3:0] = 9h, VAUXINn > VAGND DIAGNOSTIC REFERENCES

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 9 (VDCIN = +56V, TA = TMIN to TMAX unless otherwise noted, where TMIN = -40°C and TMAX = +105°C. Typical values are at TA = +25°C. Operation is with the recommend application circuit. (Note 5)) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ALTREF Voltage VALTREF DIAGSEL[2:0] = 001b; Note 12 0.99 1.00 1.01 V DIAGSEL[2:0] = 001b; 5°C < temp < +65°C; Note 12 0.995 1.00 1.005 ALTREF Temperature Coefficient (ΔVALTREF/ΔT) AALTREF Note 8 ±25 ppm/°C PTAT Output Voltage VPTAT TJ = +120°C; Note 8 1.14 V PTAT Temperature Coefficient (ΔVPTATΔT) AV_PTAT Note 8 2.87 mV/°C PTAT Temperature Offset TOS_PTAT Note 8 -4.4 °C ALERTS ALRTVDDL1 Threshold VVDDL1_OC VAA = 1.8V 1.62 1.65 1.68 V ALRTVDDL2/3 Threshold VVDDL2/3_OC VDDL2/3 = 3.3V 2.9 3.0 3.1 V ALRTGNDLn Threshold VGNDL_OC AGND = 0V 0.05 0.15 0.3 V ALRTHVUV Threshold VHVUV VHV - VDCIN falling, FLXPCKEN1/2 = 0 1.8 2 2.2 V ALRTHVOV Threshold VHVOV VHV - VDCIN rising 9.0 9.5 9.9 V ALRTHVHDRM Threshold VHVHDRM ALRTHVHDRM = 0 3.0 V ALRTTEMP Threshold TALRTTEMP Note 8 115 120 125 °C ALRTTEMP Hysteresis TALRTTEMPHY S Note 8 2 °C UART OUTPUTS (TXLP, TXLN, TXUP, TXUN) Output Low Voltage VOL ISINK = 20mA 0.4 V Output High Voltage (TXLP, TXLN) VOH ISOURCE = 20mA VDDL2 - 0.4 V Output High Voltage (TXUP, TXUN) VOH ISOURCE = 20mA VDDL3 - 0.4 V Leakage Current ILKG_TX VTX = 1.5V -1 +1 µA UART INPUTS (RXLP, RXLN, RXUP, RXUN) Input Voltage Range VRX -25 +25 V Receiver High Comparator Threshold VCH Note 17 VAA/2 - 0.4 VAA/2 VAA/2 + 0.4 V Receiver Zero-Crossing Comparator Threshold VZC Note 17 -0.4 0 +0.4 V Receiver Low Comparator Threshold VCL Note 17 -VAA/2 - 0.4 -VAA/2 -VAA/2 + 0.4 V Receiver Comparator Hysteresis VHYS_RX Note 17 75 mV Receiver Common- Mode Voltage Bias VCM Note 17 VAA/2 V Leakage Current ILKG_RX VRX = 0.9V ±1.0 µA Input Capacitance (RXLP, RXLN) CRXL 4 pF Input Capacitance (RXUP, RXUN) CRXU 4 pF

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 10 (VDCIN = +56V, TA = TMIN to TMAX unless otherwise noted, where TMIN = -40°C and TMAX = +105°C. Typical values are at TA = +25°C. Operation is with the recommend application circuit. (Note 5)) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS UART TIMING Bit Period tBIT Baud rate = 2Mbps; Note 14 8 1/fOSC_1 6M Baud rate = 1Mbps; Note 14 16 Baud rate = 0.5Mbps; Note 14 32 Rx Idle to START Setup Time tRXSTSU Note 8 0 1 tBIT STOP Hold Time to Idle tSPHD Note 8 0.5 tBIT Rx Minimum Idle Time (STOP Bit to START Bit) tRXIDLESPST Note 8 1 tBIT Rx Fall Time tFALL Note 8, Note 15 0.5 tBIT Rx Rise Time tRISE Note 8, Note 15 0.5 tBIT Propagation Delay (Rx Port to Tx Port) tPROP 2.5 3 tBIT Start-Up Time from SHNDL High and VAA = 0V to RXUP/RXUN Valid tSTARTUP 1 ms I2C Input Voltage Low VIL VDDL2/3 ≤ VDDIO ≤ 5.5V 0.3VDDI O V Input Voltage High VIH VDDL2/3 ≤ VDDIO ≤ 5.5V 0.7VDDI O V Input Voltage Hysteresis VHYST 0.15 V Input Leakage Current IIN -1.0 +0.1 +1.0 μA Input Capacitance CIN 10 pF Output Voltage Low VOL ISINK = 3mA 0.4 V SCL Clock Frequency fSCL 400kHz mode (I2CFSCL = 1) 0 400 kHz 100kHz mode (I2CFSCL = 0) 0 100 Hold Time for a (Repeated) START Condition tHD;STA 400kHz mode (I2CFSCL = 1) 0.6 μs 100kHz mode (I2CFSCL = 0) 4.0 SCL Pulse Width Low tLOW 400kHz mode (I2CFSCL = 1) 1.3 μs 100kHz mode (I2CFSCL = 0) 4.7 SCL Pulse Width High tHIGH 400kHz mode (I2CFSCL = 1) 0.6 μs 100kHz mode (I2CFSCL = 0) 4.0 Set-up Time for a Repeated START Condition tSU;STA 400kHz mode (I2CFSCL = 1) 0.6 μs 100kHz mode (I2CFSCL = 0) 4.7 Data Hold Time tHD;DAT Note 18 0 ns Controller transmitting data 300 Data Setup Time tSU;DAT Controller receiving data, and 400kHz mode (I2CFSCL = 1) bus monitor check 100 ns Controller receiving data, and 100kHz mode (I2CFSCL = 0) bus monitor check 250 Controller transmitting data 300

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 11 (VDCIN = +56V, TA = TMIN to TMAX unless otherwise noted, where TMIN = -40°C and TMAX = +105°C. Typical values are at TA = +25°C. Operation is with the recommend application circuit. (Note 5)) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Rise Time of SDA and SCL tr 300 ns Fall Time of SDA and SCL tf 300 ns Setup Time for STOP Condition tSU;STO 400kHz mode (I2CFSCL = 1) 0.6 μs 100kHz mode (I2CFSCL = 0) 4.0 Bus Free Time Between a STOP and START Condition tBUF 400kHz mode (I2CFSCL = 1) 1.3 μs 100kHz mode (I2CFSCL = 0) 4.7 Bus Capacitance Allowed Cb 400 pF Suppressed Spike Pulse Width tsp Width of spikes that must be suppressed by the input filter of both SDA and SCL signals 50 ns Noise Margin at LOW Level VnL For each connected device (including hysteresis) 0.1VDDI O V Noise Margin at HIGH Level VnL For each connected device (including hysteresis) 0.2VDDI O V Note 5: Unless otherwise noted, limits are 100% production-tested at TA = +25°C. Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. Note 6: Acquisition mode (ADC conversions) is entered when the SCAN bit is set and ends when SCANDONE is set. With the typical acquisition duty cycle very low, the average current IDCIN is much less than IDCMEAS. Total supply current during communication IDCIN = IDCCOMM + IDCSTBY. Note 7: Measurement accuracy range is guaranteed from VCELLn_min + 0.2V and VCELLn_max - 0.2V. Note 8: Guaranteed by design and not production tested. Note 9: Not production tested. See the Cell Balancing section for details on the maximum allowed balancing current. Duty cycle is calculated for a 10-year device lifetime. Note 10: VCELLn = VCn - VCn-1, VCELLn = VCELLn-1, and VDCIN = 14 x │VCELLn│ (VDCIN = 9V, min). Accuracy measurements represent initial total measurement error with the input noise oversampled below 1 LSB. Note 11: Accuracy measurements represent the initial total measurement error with the input noise oversampled below 1 LSB. Note 12: As measured during specified diagnostic mode. Note 13: ISHDNL measured with VSHDNL = 0.3V, STOP characters, zero idle time, VRX_PEAK = 3.3V. Note 14: In daisy-chain applications, the bit time of the second stop bit may be less than specified to account for clock rate variation and sampling error between devices. Note 15: Fall time measured 90% to 10%; rise time measured 10% to 90%. Note 16: Charge pump efficiency = ΔILOAD / ΔISUPPLY, where ILOAD is applied from HV to AGND, ΔILOAD = 5mA, and ΔISUPPLY = IDCIN (for ILOAD = 5mA) - IDCIN (for ILOAD = 0). Note 17: Differential signal (VUARTP - VUARTN) where VUARTP and VUARTN do not exceed a common-mode voltage range of ±40V. Note 18: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIH_min of the SCL signal) to bridge the undefined region of the falling edge of SCL.

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 12 Typical Operating Characteristics (DCIN = 56V, VDDL2/3 = 3.3V, TA = +25°C, unless otherwise noted)

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 13 (DCIN = 56V, VDDL2/3 = 3.3V, TA = +25°C, unless otherwise noted)

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 14 Pin Configurations 49505152535455565758596061626364 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 SW8 SW7 SW5 SW4 SW3 SW2 SW1 SW6 SW0 THRM AGND AUXIN1/GPIO1/SCL AUXIN0/GPIO0/SDA AUXIN2/GPIO2 AUXIN3/GPIO3 AUXGND AUXIN4/GPIO4 AUXIN5/GPIO5 TOP VIEW C14 C13 C12 SW14 C11 SW13 C10 SW12 SW11 SW10 VBLK DCIN CPN HV CPP SW9 GNDL1 VAA AGND RXUN GNDL3 VDDL1 UARTSEL GNDL2 TXUN TXUP SHDNL VDDL3 TXLP TXLN RXUP ALERTIN VDDL2 RXLN RXLP ALERTOUT ADES1754 ADES1755 ADES1756

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 15 Pin Descriptions PIN NAME FUNCTION REF SUPPLY Type SHDNL Shutdown Active-Low Input, +72V Tolerant. This input is controlled solely through UART communication and software control when bypassed with a 1nF capacitor to AGND. Connect only passive components to this pin. For single-ended UART, SHDNL must be driven externally. AGND Input 2 AGND Analog Ground. Connect to the negative terminal of cell 1 and the ground plane. DCIN Ground 3 VAA VAA (1.8V) Regulator Output Used to Supply VDDL1. Bypass with a 1µF capacitor to AGND. AGND Power

4 UARTSEL Connect to VAA VDDL1 Input

5 VDDL1 1.8V Digital Supply. Connect externally to VAA and bypass with 0.47µF capacitor to GNDL1 GNDL1 Power 6 GNDL1 Digital Ground. Connect to ground plane. VDDL1 Ground 7 ALERTIN Fault Alert Input. Connect to upper daisy-chained device. VAA Input 8 GNDL3 Ground for Upper Port Transmitter. Connect to ground plane. VDDL3 Ground

9 TXUN

Negative Output for Upper UART Transmitter. Driven between VDDL3 and GNDL3. VDDL3 Output/Inp ut

10 TXUP

Positive Output for Upper UART Transmitter. Driven between VDDL3 and GNDL3. VDDL3 Output/Inp ut

11 VDDL3

3.3V Regulator Output. Supply for upper UART transceiver and ALERT pins. Connect externally to VDDL2 and bypass with 0.47µF capacitor to GNDL3. External overdrive allowed: VDDL3 must be ≥ VDDL2/3_REG. GNDL3 Power 12 RXUN Negative Input for Upper UART Port Receiver. If not used, pins can be left unconnected or connected to GNDL3. Tolerates ±30V. VAA Input

13 RXUP

Positive Input for Upper UART Port Receiver. If not used, pins can be left unconnected or connected to GNDL3. Tolerates ±30V. If configured for single-ended UART, connect to GNDL3. VAA Input 14 GNDL2 Ground for Lower Port Transmitter. Connect to ground plane. VDDL2 Ground

15 TXLP

Positive Output for Lower UART Transmitter. Driven between VDDL2 and GNDL2. VDDL2 Output 16 TXLN Negative Output for Lower UART Transmitter. Dependent on UARTSEL selection. Driven between VDDL2 and GNDL2. VDDL2 Output

17 RXLP

Positive Input for Lower UART Port Receiver. If not used, pins can be left unconnected or connected to GNDL3. Tolerates ±30V. If configured for single-ended UART, connect to GNDL3. VAA Input 18 RXLN Negative Input for Lower UART Port Receiver. If not used, pins can be left unconnected or connected to GNDL2. Tolerates ±30V. VAA Input

19 VDDL2

3.3V Regulator Output. Supply for Lower UART transceiver and ALERT pins. Connect externally to VDDL3 and bypass with 0.47µF capacitor to GNDL3. External overdrive allowed: VDDL2 must be ≥ VDDL2/3_REG. GNDL2 Power

20 ALERTOU

T Alert Output Interface. Configured using SPIDRVINT as daisy-chained CMOS output (connected to ALERTIN), or open-drain output (connected to external 10kΩ pull-up to VDDL2, VDDL3). VDDL2 Output AUXIN0/ GPIO0/SD A Configurable between Auxiliary Input, GPIO, or SDA. When configured as a ratiometric auxiliary input for temperature measurement, connect to a voltage-divider consisting of a 10kΩ pull-up to THRM and a 10kΩ NTC thermistor to AGND. If not used, connect to the pull- up only. When configured as a GPIO, it is driven between VDDL2 and GNDL2. A 2MΩ internal pull-down is needed when the pin is configured as an input. When VDDL2 Input/Outp ut

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 16 configured as an I2C SDA I/O, an external pull-up resistor is required. The pin is driven between VDDL2 and GNDL2. AUXIN1/ GPIO1/SC L Configurable between Auxiliary Input, GPIO, or SCL. When configured as a ratiometric auxiliary input for temperature measurement, connect to a voltage-divider consisting of a 10kΩ pull-up to THRM and a 10kΩ NTC thermistor to AGND. If not used, connect to the pull- up only. When configured as a GPIO, it is driven between VDDL2 and GNDL2. A 2MΩ internal pull-down is needed when the pin is configured as an input. When configured as an I2C SCL, it becomes the clock output of I2C. VDDL2 Input/Outp ut

23 AUXIN2/

Configurable between Auxiliary Input or GPIO. When configured as a ratiometric auxiliary input for temperature measurement, connect to a voltage-divider consisting of a 10kΩ pull-up to THRM and a 10kΩ NTC thermistor to AGND. If not used, connect to the pull- up only. When configured as a GPIO, it is driven between VDDL2 and GNDL2. A 2MΩ internal pull-down is needed when the pin is configured as an input. VDDL2 Input/Outp ut

24 AUXIN3/

26 AUXIN4/

27 AUXIN5/

29 THRM

Switched Output Connected Internally to VAA. THRM is used to drive the external NTC voltage-divider for the auxiliary inputs. The output is enabled only during measurements or as configured by THRMMODE[1:0]. This output can source up to 2mA. AUXGND Power 30 C0 Voltage Input for Cell 1 Negative. Connect to AGND. Input 31 SW0 Balance Input for Cell 1 Negative. Input 32 C1 Voltage Input for Cell 1 Positive (Cell 2 Negative). Input 33 SW1 Balance Input for Cell 1 Positive (Cell 2 Negative). Input 34 C2 Voltage Input for Cell 2 Positive (Cell 3 Negative). Input 35 SW2 Balance Input for Cell 2 Positive (Cell 3 Negative). Input 36 C3 Voltage Input for Cell 3 Positive (Cell 4 Negative). Input 37 SW3 Balance Input for Cell 3 Positive (Cell 4 Negative). Input

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 17

38 C4 Voltage Input for Cell 4 Positive (Cell 5 Negative) Input

39 SW4 Balance Input for Cell 4 Positive (Cell 5 Negative). Input 40 C5 Voltage Input for Cell 5 Positive (Cell 6 Negative). Input

41 SW5 Balance Input for Cell 5 Positive (Cell 6 Negative) Input

42 C6 Voltage Input for Cell 6 Positive (Cell 7 Negative). Input 43 SW6 Balance Input for Cell 6 Positive (Cell 7 Negative). Input 44 C7 Voltage Input for Cell 7 Positive (Cell 8 Negative). Input 45 SW7 Balance Input for Cell 7 Positive (Cell 8 Negative). Input 46 C8 Voltage Input for Cell 8 Positive (Cell 9 Negative). Input 47 SW8 Balance Input for Cell 8 Positive (Cell 9 Negative). Input 48 C9 Voltage Input for Cell 9 Positive (Cell 10 Negative). Input 49 SW9 Balance Input for Cell 9 Positive (Cell 10 Negative). Input 50 C10 Voltage Input for Cell 10 Positive (Cell 11 Negative). Input 51 SW10 Balance Input for Cell 10 Positive (Cell 11 Negative). Input 52 C11 Voltage Input for Cell 11 Positive (Cell 12 Negative). Input 53 SW11 Balance Input for Cell 11 Positive (Cell 12 Negative). Input 54 C12 Voltage Input for Cell 12 Positive (Cell 13 Negative). Input 55 SW12 Balance Input for Cell 12 Positive (Cell 13 Negative). Input 56 C13 Voltage Input for Cell 13 Positive (Cell 14 Negative). Input 57 SW13 Balance Input for Cell 13 Positive (Cell 14 Negative). Input 58 C14 Voltage Input for Cell 14 Positive. Input 59 SW14 Balance Input for Cell 14 Positive. Input 60 VBLK Block Voltage Positive Input. Internal pull-down resistor of RVBLK. DCIN Input

61 DCIN

DC Supply for the Low-Voltage Regulator, HV Charge Pump, and SHDNL Charge Pump. Connect to a voltage source between 9V and 65V through a 100Ω series resistor. Bypass with a 100V, 2.2μF capacitor to ground. Power 62 CPN Negative Capacitor Connection for the HV Charge Pump. Power 63 CPP Positive Capacitor Connection for the HV Charge Pump. Connect a 100V, 0.1μF capacitor from CPP to CPN. Power 64 HV Decoupling Capacitor Connection for the HV Charge Pump. Bypass with a 50V, 4.7µF capacitor to DCIN. Power

The data acquisition system consists of the major blocks shown in Figure 1 and described in Table 1. Table 1. System Blocks voltage of 1.25V and supplied by VAA. HVMUX 14-channel, high-voltage (65V) differential multiplexer for the C0–C14 inputs. switch high-voltage signals. Supplied by DCIN. which is the reference voltage for the ADC. ADC for subsequent analog-to-digital conversion. ALTMUX 12-channel, high-voltage differential multiplexer for the SW0-SW14 inputs. BALSW Cell-balancing switches. LINREG 1.8V 1.8V (VAA) linear regulator used to power the ADC and digital logic. Supplied by DCIN. LINREG 3.3V 3.3V (VDDL2/3) linear regulator used to power UART transceiver and ALERT. REF 1.25V precision reference voltage for ADC and LINREG. Temperature compensated. ALTREF 1V precision reference voltage used for diagnostics. HFOSC High-frequency oscillator with 2% accuracy for clocking state machines and UART timing. LFOSC Low-frequency oscillator for driving charge pumps and timers. UPPER PORT Differential UART for communication with up-stack devices. STATUS ALUs, control logic, and data registers. DIE TEMP A proportional-to-absolute-temperature (PTAT) voltage source used to measure the die temperature. COMPARATOR A comparator path to detect OV/UV for cell voltage and AUXIN. programmable OV and UV DAC thresholds. I2C CONTROLLER I2C controller interface for communication with a I2C target.

Figure 1. Functional Block Diagram

Figure 2. ADES1754/ADES1755/ADES1756 ESD Diagram

All diodes are rated for ESD clamping conditions. They are not intended to accurately clamp DC voltage.
All diodes have a parasitic diode from AGND to their cat hode that is omitted for clarity. These parasitic diodes have their anode at AGND.

Figure 3. ADES1754/ADES1755/ADES1756 Analog Front-End

registers described in this section. Configuration changes should be made prior to the acquisition in which the changes are to be effected. Table 2. Data Acquisition Process Conversion The ADC samples a single-input channel, converts it into a binary value, and stores it in an ALU register. Scan The ADC sequentially performs conversions on all enabled cell-input channels. for each input channel) are chopped and referred as measurement or sample. additional device calibration is required. Representation of data follows the conventions shown in Table 3. All registers are 16-bit words. Table 3. Numeric Conventions trim can be further supplemented with a user on-demand calibration when used in a specific customer application.

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 23 measurements, temperature measurements, and auxiliary-voltage measurements. All measurements are synchronously sampled within an acquisition and have minimal delay between acquired samples. Additional programmability is available for balancing currents, and system -interconnect measurements (bus bars) to provide a complete measurement solution independent of hardware configuration. The following sections describe the device operation, feature set, and programming of the ADES1754/ADES1755/ ADES1756. Flexible Battery-Pack Configuration The main supp ly voltage, DCIN, can be routed internally using the SW8 -SW14 inputs of the highest stacked cell. This allows for a single hardware configuration to serve multiple battery modules without requiring external hardware or wiring- harness changes. The flexible battery-pack configuration is enabled by default using FLXPCKEN1/2 bit, to allow for internal powering conditions. If this configuration is not required, the DCIN can still be driven externally, which will effectively disable th e flexible battery-pack configuration. Prior to SDHNL being actively controlled, the DCIN voltage will be driven towards HV and clamped at the highest voltage applied at the SW8 -SW14 inputs. When SHDNL is asserted, DCIN will be driven to within 1V below the highest stacked cell, if no external DCIN is provided. In this case, the host must define the TOPCELL1[3:0] and TOPCELL2[3:0] of the stack by writing to the PACKCFG register and by asserting the FLXPCKEN1 and FLXPCKEN2 bits. TOPCELL_[3:0] selection configures the top -cell position if less than 14 channels are used. TOPCELL_[3:0] selections 0x0 to 0x7 and 0xF are not supported and will be mapped to an OFF position (power -on default). If FLXPCKEN1/2 is unintentionally deasserted while the SHDNL is driven high with no external DCIN c onnection, it is expected that the voltage seen at the DCIN pin will fall at a rate proportional to the current consumption of the part and the external decoupling capacitance until the POR threshold is reached. This resets the digital logic and returns th e FLXPCKEN to the desired power-on reset state. If FLEXPCKEN1 and FLEXPCKEN2 or TOPCELL1 and TOPCELL2 are not the same, the power -on default values will be applied. Note: It is important that TOPCELL1 and TOPCELL2 selects the highest applied cell input, a s an invalid configuration can create an internal path which would connect the highest battery voltage to the selected TOPCELL1/2 input. A second mux internally connects V BLK to a selected cell input after host defines the TOPCELL_[3:0] of the stack and asserts the FLXPCKEN_ bit. TOPBLOCK[3:0] selects the Cn pin to be connected to the V BLOCK resistive divider. 0xF (default) selects the V BLK pin. TOPBLOCK_ selections 0x0 through 0x7 are not supported and will be mapped to 0xF (VBLK, default).

Figure 4. Flexible-Pack Configuration for 12-Cell Pack on 14-Channel CMC filter network to settle before converting the input voltage.

set FLXPCKSCAN = 0 to ensure the quickest sampling rate is achieved. pack is a bus bar. TOPBLOCK_ can refer to cells above TOPCELL_. faults may be issued. The ALRTDCINMUX is gated until clear of ALRTRST after power-up has occurred. Figure 5. Flexible-Pack Power-On Timing

defined as VCn – VCn-1 for n = 1 to 14. measurement redundancy improving safety performance and device robustness. Figure 6. Since the common-mode range of the input signals is 0 to 65V, the signal must be level-shifted to the common- attenuated to the ADC and comparator full scale reference voltage (VREF).

Figure 6. Cell Signal Path

Disabled channels maintain their previous measurement result. Unless stated otherwise, measurement values are

layer of measurement redundancy within the system. Outside of the acquisition, the VBLK input path is opened to avoid power consumption from the internal resistor-divider. Figure 7. Block Measurement Path is stored in the VBLOCK[13:0] bits of the BLOCKREG register where each bit has a resolution of 3.967mV. external voltages, or that can be repurposed for digital functions (GPIO or I2C controller).

the AUXREFSEL bits in the AUXREFCTRL register. corresponding AUXEN bit is high, then the auxiliary setting will be ignored and the port will be configured as a GPIO. NTC connected to the AUXGND pin, as shown in Figure 8. Figure 8. Auxiliary Application Circuit VAA and the need to settle the external NTC network to achieve the highest accuracy measurements.

Figure 9. Auxiliary Temperature Measurements Table 4. THRM Output further details on FOSR and deterministic acquisitions.

Table 5. AUXTIME ADC Acquisition, Comparator Acquisition, and ADC+COMP Acquisition Time sections for further details. Table 6. Auxiliary Temperature Input Range: ADC Table 7. Auxiliary Temperature Input Range: Comparator

the AUXREFSEL bits in the AUXREFCTRL register. failure on the external network, the maximum auxiliary input does not exceed the absolute maximum rating on the port. 0b10 (the THRM switch always OFF). Table 8. Auxiliary Voltage Input Range: ADC

Table 9. Auxiliary Voltage Input Range: Comparator Ratiometric measurements and absolute voltage measurements can both be performed during the same acquisition. as determined by the AUXREFSEL configuration must be applied to obtain correct voltage reading. where VAA is nominally 1.8V. the desired configuration to the AUXGPIOCFG register. All 6 ALRTAUXPRTCT bits will be logically OR'd together to form the ALRTAUXPRTCTSUM bit in the FMEA2 register. of the AUXEN configuration. When a GPIOEN bit is low, the corresponding GPIO portion is three-stated. I2CEN is low and the I2C controller is disabled. Table 10. GPIO/I2C/Auxiliary Enable Priority

GPIODRV[1:0] bits will be ignored for functionality, but will still read back the user setting. functionality is enabled, GPIORD[1:0] reads back 0b00. Table 11. GPIO Configuration Figure 10. AUX/GPIO/I2C Pin Connections

Balancing section for further information). Figure 11. Operational Mode State Diagram The following sections further detail the operational modes and device interactions. the UART idle 98% of the time. The internal charge pump operation requires a differential signal UART signal. received in shutdown mode. Figure 12 details the power-on state transition.

Figure 12. Power-On Sequence

Figure 14. Power-on and Shutdown Timing

Figure 15. Shutdown Timing exceeded, or VAA transitions below the POR threshold, the device will exit acquisition and enter shutdown mode. (ALTREF) may be used to verify the primary reference voltage, as described in the Diagnostics section. and ensures added system reliability. detail in the Measurement Alerts section.

+2.3V should be supplemented with the unipolar measurements. time and interface throughput. mode regardless of the POLARITY_n bit value in the POLARITYCTRL register. optimize acquisition time and interface throughput. Characteristics table for device accuracy specifications. Table 13. ADC Input Range cell measurement will be omitted from the scan. and absolute acquisitions supports an input range of 0V to VREF. Table 14. Comparator Input Range

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 41 Scan Configuration The SCANCFG bits in the SCANCTRL register selects the acquisition that is to be performed. All available configurations are listed below.

ADC
ADC and comparator (ADC+COMP)
Comparator
Calibration 5 – Balancing switch short
Balancing switch open
Cell sense open odds
Cell sense open evens ADC, comparator, and ADC+COMP acquisitions have programmable sample intervals through the configuration of the FOSR bit. This setting, when coupled with the OVSAMPL, allows for specific frequency rejection at either 50Hz/100Hz or 60Hz/120Hz. If not configured, the user may specifically control the sample interval through the timing of the interface to support any desired post processing on the host controller. Note: The balance switch and cell sense acquisitions will i mmediately configure the internal balance switches once the SCANCFG bitfield is written. See the BALSW Diagnostics section for details on the operation of this acquisition mode. ADC Configurations and Properties ADC Polarity Configuration Unipolar and bipolar measurements are supported within a single acquisition to capture all cell and bus -bar data without the need to reconfigure multiple scan configuration registers or perform multiple acquisitions. Cell polarity is configured using the POLARITYCTRL register where all cells are defaulted to unipolar measurements (POLARITY [13:0] = 0000h). Bipolar cells are fault-masked during BALSWDIAG ADC measurement scans. MINMAXPOL determines whether bipolar cells are included in MIN/MAXCELL and ALRTMSMTCH calculations. Bipolar cell measurements are checked against BIPOVTH and BIPUVTH thresholds rather than OVTH and UVTH thresholds. Bipolar cells are not included in comparator measurement scans, and ALRTCOMPOV/ALRTCOMPUV alerts are not evaluated. ADC Scan Properties ADC acquisitions can be applied to the cell, auxiliary, block, and diagnostics measurements. The cell measurements can be programmed through the SCANMODE bit in the SCANCTRL register to use two conversion phases (Pyramid mode) or a single-conversion phase (Ramp mode). For the cell inputs, Pyramid mode (SCANMODE = 0) performs the first conversion phase in ascending cell order (bottom enabled cell to top -enabled cell) and the second conversion phase is in descending order (top -enabled cell to bottom enabled cell). The two -conversion scan allows for chopping of the inputs to effectively remove any offsets or reference induced errors, as well as create a virtual sampling time that is the same for all cell measurements. The Ramp mode (SCANM ODE = 0b1) performs a single -conversion phase (bottom -enabled cell to top -enabled cell), which will improve conversion speed. The auxiliary measurements do not require a pyramid (dual -phase) sampling approach, and are sampled in a single conversion regardless of SCANMODE configuration. ADC Acquisition ADC acquisitions can be configured for the cell, auxiliary, block, and diagnostics. The acquisition is initiated by writing a logic one to the SCAN bit in the SCANCTRL register. This write acts as a strobe, and the SCAN bit content is automatically cleared, reading back a logic 0 if polled. In daisy -chained devices, acquisitions in either UART path (depending on the controller configuration) are delayed by the propagation delay, tPROP, of the command packet through each device. The acquisition for the device is signaled complete when the SCANDONE bit is a logic 1. Note: If any additional write to the SCANCFG is issued prior to the SCANDONE bit being cleared, this command will be ignored.

Disable the HV charge pump.
The following conversions initiate, if enabled:
VBLK conversion (first phase)
All enabled cell conversions (first phase) in ascending order (1 through 14)
All enabled cell conversions (second phase) in descending order (14 through 1)
VBLK conversion (second phase)
<End of Pyramid>
DIAG1 conversion (first phase)
DIAG1 conversion (second phase)
DIAG2 conversion (first phase)
DIAG2 conversion (second phase)
Auxiliary conversions
Enable the HV charge pump for the recovery period unless:
OVSAMPL = 000b (no oversampling), or
All oversample measurements are complete
Repeat steps 1 and 2 until all oversamples are done.
Set the SCANDONE bit. ADC Pyramid Mode Figures C1+ C2+ C3+ C4+ C5+ C6+ C7+ C8+ C9+ C10+ C11+ C12+ C1 - C2 - C3 - C4 - C5 - C6 - C7 - C8 - C9 - C10 - C11 - C12 - SIMULTANEOUS CELL SAMPLING POINT BLK+ TIME INPUT CHANNEL DIAG1+ DIAG1 - AUX0 AUX1 SCANDONE = 1 BLK - C13+ C14+ C14 - C13 - AUX2 AUX3 AUX4 AUX5 DIAG2+ DIAG2 -

Figure 16. Acquisition - SCANCFG = 0h, SCANMODE = 0, OVSAMPL = 0h, ALTMUXSEL = 0, BLOCKEN = 1, DIAGSEL1 > 0h,

Figure 19. Acquisition - SCANCFG = 0h, SCANMODE = 0, OVSAMPL > 0h, ALTMUXSEL = 0, BLOCKEN = 1, DIAGSEL1 > 0h, shown in following tables. There is one measurement cycle per oversample acquisition. Table 15. ADC Pyramid Mode (SCANMODE = 0) Acquisition Time

33.5 Die Temperature diagnostic

24.75 VAA diagnostic

29.25 Comp Signal Path diagnostic

24.75 Cell Gain Calibration diagnostic

87.75 VALTREF diagnostic

20.25 DAC 3/4, DAC 1/4

5.44 All other diagnostics

Disable the HV charge pump.
The following conversions initiate, if enabled:
VBLK conversion (first phase)
All enabled cell conversions (1 through 14)
VBLK conversion (second phase)
< End of Ramp >
DIAG1 conversion
DIAG2 conversion
Auxiliary conversions
Enable the HV charge pump for recovery period unless:
OVSAMPL = 000b (no oversampling), or
All oversample measurements are complete
Repeat steps 1 and 2 until all oversamples are done.
Set the SCANDONE bit. ADC Ramp Mode Figures C1+ C2+ C3+ C4+ C5+ C6+ C7+ C8+ C9+ C10+ C11+ C12+ BLK+ TIME INPUT CHANNEL DIAG1+ DIAG1 - AUX0 AUX1 SCANDONE = 1 BLK - C13+ C14+ AUX2 AUX3 AUX4 AUX5 DIAG2+ DIAG2 -

Figure 20. Acquisition - SCANCFG = 0h, SCANMODE = 1, OVSAMPL = 0h, ALTMUXSEL = 0, BLOCKEN = 1, DIAGSEL1 > 0h,

Figure 21. Acquisition - SCANCFG = 0h, SCANMODE = 1, OVSAMPL = 0h, TOPCELL1/2 = 14, ALTMUXSEL = 1, BLOCKEN = 1, in Table 16. There is one measurement cycle per oversample acquisition. Table 16. ADC Ramp Mode (SCANMODE = 1) Acquisition Time

tInitialization
tVBLK
tCell_Scan_Setup
tCell_Scan
tDiag_Total THRMMODE = Automatic mode and FOSR = Free Run mode VBLK Measurement (if enabled) 31.5 BLOCKEN = 1 Every measurement cycle Cell Measurement 4.5 * y For y = # of enabled cell inputs DIAG1 Measurement and/or DIAG2 Measurement (if enabled)

Table 17 provides an example of common configuration and the associated acquisition time that can be achieved. Table 17. ADC Acquisition Time Examples (with AUXTIME[9:0] = 000h) the MEASUREEN1 register to prior to issuing a SCAN as this will omit these measurements from the acquisition. comparator acquisition process.

Disable the HV charge pump.
Perform overvoltage conversion on all enabled cell inputs (MEASUREEN1) against the COMPOVTH threshold

in ascending order (1 through 14).

Update the ALRTCOMPOV register (MEASUREEN1 and ALRTOVEN).
Perform undervoltage conversion on all enabled cell inputs (MEASUREEN1) against the COMPUVTH threshold

in descending order (14 through 1).

Update the ALRTCOMPUV register (MEASUREEN1 and ALRTUVEN).
Perform overvoltage conversion on a ll enabled auxiliary inputs (MEASUREEN2) against COMPAUXOVTH in

ascending order (0 through 5).

Update the ALRTCOMPAUXOV register (MEASUREEN2 and ALRTAUXOVEN).

Perform undervoltage conversion on all enabled auxiliary inputs (MEASUREEN2) against COMPAUXUVT H in

ascending order (0 through 5).

Update the ALRTCOMPAUXUV register (MEASUREEN2 and ALRTAUXUVEN).
Enable the HV charge pump refresh.
Repeat steps 2 through 6 until all oversamples are complete.
Compare the results against the comparator thresholds and update alert status.
Enable the HV charge pump.

Note: Comparator results are only available when the corresponding OV/UV alerts are enabled. measurements share the same threshold settings as defined by the COMPAUXAOVTH and COMPAUXAUVTH registers. comparator over loading and temperature conditions. Table 18. There is one measurement cycle per oversample acquisition. Table 18. Comparator Acquisition Time Table 19 provides an example of common configuration and the associated acquisition time that can be achieved.

engine (ADC or comparator) retains the functionality discussed previously with additional clarification detailed below. this portion of the acquisition. In ADC+COMP scan mode, the ADC acquisition only operates in Pyramid mode and the SCANMODE bit is ignored. following tables. There is one measurement cycle per oversample acquisition. Table 20. ADC+COMP Acquisition Time

Table 21 provides examples of common configuration and the associated acquisition time that can be achieved. Table 21. ADC+COMP Acquisition Time Examples (with AUXTIME[9:0] = 000h) Figure 24. Simultaneous ADC+COMP Scan Mode

Figure 25. Simultaneous ADC+COMP Scan with Oversampling The calibration time is 3.75ms.

(POLARITYCTRL, SCANCTRL, ACQCFG). calibration coefficients applied. programmed using a 50V DCIN voltage. Table 22 indicates which calibration alerts are associated to the various measurement path. Table 22. Measurement Path Calibration Alerts the DIAGSEL1 and DIAGSEL2 bits. See the Diagnostics section for further details. Figure 26. On-Demand Calibration Block Diagram

of flagging an issue within the Data Check byte or within the hardware alert interface. correct the fault, or to deassert ADCCALEN and use the factory default calibration. reduction required for ADC measurements. Table 23. Comparator Faults for Alerts vs. Oversampling higher lowpass cutoff frequency. Table 24. Watchdog-Timeout Duration

Note 2:When AUXTIME is > 0, the timeout duration is extended by AUXTIME. 100Hz, the FOSR must be set to 0b01. For 60Hz or 120Hz filtering, the FOSR must be set to either 0b10 or 0b11. Table 25. FOSR Notch-Filter Setting interval depends on the oversampling configuration as shown in Table 24. cleared. See the Double-Buffer Mode section for detailed information on the data control in the mode.

Figure 27. Acquisition-Mode Flowchart

Calibration
IIR filter
Single buffer data transfer
Double buffer data transfer
Cell balancing with embedded measurements ALU REGISTERS USER REGISTER MAP ADC IN - ADC IN + ADCTSTEN ADC_CHOP OVSAMP_EVEN_ODD FILTER REGISTERS RDFILT ADCTEST1A[11:0] ADCTEST1B[11:0] ADCTEST2A[11:0] ADCTEST2B[11:0] ADC ALU1 ALU14 ALU2 ALU1_IIR ALU14_IIR ALU2_IIR IIR CALIBRATION ADCCALEN CELL1REG CELL2REG CELL14REG USER INTERFACE COMMUNICATION

Figure 28. Data-Flow Diagram ADCCALEN bit. See the On-Demand Calibration section for details on the configuration and application of calibration.

To augment the accuracy performance over multiple measurement cycles, the user can enable the embedded IIR filter. The filter acts upon all enabled Cn and VBLK inputs according to the user-defined settings in the MEASUREEN1 register. registers as selected through RDFILT. filter and oversampling noise reduction. reduction with the external hardware filter combined with the digital filtering. diagnostic current sources (CTSTCFG, MUXDIAGEN). (off) in automatic cell-balancing modes, the IIR filter is internally forced to 000b (1/8). All other selection of IIRFC are valid. FC is a 3-bit user-programmable filter coefficient. The default value of 0b010 has a weight of 3/8. the noise attenuation. The filter can be turned off by setting the filter coefficient to 1 (IIRFC = 0b111). filtered and raw result data can be read back using the RDFILT option. Figure 29. IIR Filter Algorithm taken by the IIR filter to settle a full-scale step (e.g., 0V to 100mV unipolar cell transition) to 12-bit and 14-bit accuracy. Characteristics section for a typical operating behavior of that filter.

Table 26. IIR 100mV Step Response Settling ALRTFILT) in the SCANCTRL register. The following sections detail this operation. Table 27. IIR Data-Control Settings IIR is not updated, but the IIR results are read. Note: This operation is not recommended. IIR is updated, but the current acquisition is read. See the Out-of-Scan Data Transfer section for information on reading both filtered and unfiltered results. one of these outputs to generate the relevant alerts. MINMAXCELL and TOTAL registers, and perform cell mismatch MSMTCH checks.

to the first measurement taken, and further cell-balancing measurements are amended normally. indicated by SCANDONE = 1 and DATARDY = 1. Figure 30. Single-Buffer Data Transfer

of-scan data transfer method. Figure 31. Double-Buffer Data Transfer accumulator is transferred to the data registers. and SCAN = 0. If updated data processing is required, a new acquisition (SCAN = 1) must be requested.

MINMAXCELL output registers. See the Cell Balancing section for further detail. from the correct accuracy results. Table 28. Measurement Alerts

condition where the alert for the ADC may be set while the alert for the comparator my be cleared and vice versa. Note: ADC alerts provide the most accurate indications of the acquisition. scale, effectively disables voltage alerts independent of the ALRTOVEN and ALRTUVEN. Table 29. Set- and Clear-Threshold Selection the ALRTSUM register and occur when any alert bit is set in the ALRTOVCELL or ALRTUVCELL registers, respectively. STATUS1 register when the acquired BLOCK voltage is over VBLKOVTHSET or under VBLKUVTHSET, respectively. If an alert does not need to be propagated using the alert interface or data check byte, these can be individually masked. See the Alert Interface section for further details on the masking. The cell and block voltage hysteresis diagram is as shown in Figure 32.

Figure 32. Cell Voltage-Alert Thresholds Enable the mismatch alert to signal when the minimum and maximum cell voltages differ by more than a specified voltage. the threshold condition. To disable the alert, write 3FFFh to the MSMTCHREG register bitfield (default value). MINMAXPOL = 0 only unipolar measurements are used. When MINMAXPOL = 0b1, only bipolar measurements are used. configured for bipolar statistics. The MINCELL bitfield reads CELL1 and the MAXCELL bitfield reads CELL4.

of measurement noise, as shown in Table 30. Table 30. Temperature Alert Threshold respectively. The appropriate threshold used is determined by the AUXREFSEL bits, which can be different per channel. the alert for the ADC may be set while the alert for the comparator may be cleared and vice versa. and an UV alert signals an overtemperature (OT) event for the NTC measurement. ALRTAUXOVEN and ALRTAUXUVEN. ALRTAUXUV bitfields, respectively. this can be determined from polling the alert channel within ALRTAUXOV or ALRTAUXUV. ALRTCOMPAUXUVREG registers, respectively. information to get propagated using the hardware alert interface or the data check byte. balancing, discharge control using a timer and/or undervoltage threshold, and duty cycle configuration. achieved from all enabled conditions (UV threshold, timer, and thermal).

integrity prior to balancing. ALRTCBTIMEOUT notifies the user of a health check failure (if one is found). Once a CBMODE mode is selected and started, the device remains in this mode until a new value is written to CBMODE. status of the operation can be checked by reading the BALSTAT and BALUVSTAT registers. register behavior. Note that blockage operations are implemented at the register level. Table 31. Cell-Balancing Register Write Behavior when Cell Balancing Is Selected

14 Yes No 1 No Yes — No Yes —

balancing operation. Although this can be written in other balancing modes, no internal action is taken. Note 2: Writes to the BALSWEN bitfields during manual cell-balancing mode are expected and supported. data from the last completed scan is used to populate CBUVTHR). CBTIMER is incremented on a real-time basis, regardless of BALSWEN settings or suspensions for ADC or CAL events. This means the watchdog will time out as set in CBEXP1 once manual cell balancing is initiated. equivalent to the cell-balancing behavior supported in legacy-Maxim battery-management devices.

requested through normal scan control registers allowing for simultaneous measurements and balancing. cell-balancing event, the user must issue a separate write to the BALCTRL register. balancing current significantly, so care must be taken to not exceed the device’s maximum operating conditions. settling time of 960μs to achieve the calibrated accuracy specified in the Electrical Characteristics table. Note 2: AUTOBALSWDIS effects cell-balancing switch behavior in manual cell-balancing modes only. Note 3: Cell-balancing timer incrementing/expiration behavior is not affected by the AUTOBALSWDIS setting. Figure 33. Logic Diagram when Balancing Switches Will Be Disabled

Figure 34. AUTOBALSWDIS Measurement Settling configuration, ALRTHVUV is expected to trip and the TOPCELL1/2 cell input measurements will not be valid. target can also be set using CBUVTHR. periodically to confirm the auto individual mode is active.

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 69 SHDNL operation can be controlled by HOLDSHDNL, preventing device shutdown during auto individual mode in case of an extended lapse in host communication. Once initiated, Auto Individual mode normally continues to run until CBTIMER reaches max(CBEXPn) or all cells reach the voltage CBUVTHR (whichever comes first, depending on configuration settings). At this point, balancing switch operations cease and CBACTIVE is set to 0b10, indicating a normal exit condition. Cell -balancing checks for thermal, calibration, and watchdog faults apply, if enabled; if any of these conditions occur, switching activity will be halted immediately and CBACTIVE will be set to 0b11, notifying the μC of the result. The cell -balancing timer (CBTIMER) continues to run until expiratio n (CBEXPn), and HOLDSHDNL extensions are supported, if enabled. This allows the μC to confirm the exit condition. Auto Group Mode The Auto Group mode performs cell balancing in a controlled manner so that the cells can be discharged as a group for a duration and/or to a specific voltage level, as required in the end application. The host initiates an Auto Group mode by setting CBMODE to 0b110 (duration is seconds) or 0b111 (duration in minutes), configuring CBEXP1 to the desired value (where the LSB = 1 second or minute, respectively), and setting individual BALSWENn bits; a group voltage target can also be set using CBUVTHR. In Auto Group mode, the balancing switches defined by BALSWEN[n] are automatic controlled through nonoverlapping even/odd cycling in accordance with the programmable timer duration (CBEXP1) and/or the undervoltage threshold (CBUVTHR). The balancing switch duty cycle can further be controlled using CBDUTY to programmatically set the average balancing current. This is indicated as follows: Even Cells (2, 4, ... 14): BALSWn = BALSWEN[n] & (CBTIMER ≤ CBEXP1) & CBEVEN & ( ((CBMEASEN ==0b11) & (CELLn ≥ CBUVTHR)) | (CBMEASEN != 0b11)) Odd Cells (1, 3, ... 13): BALSWn = BALSWEN[n] & (CBTIMER ≤ CBEXP1) & CBODD & ( ((CBMEASEN ==0b11) & (CELLn ≥ CBUVTHR)) | (CBMEASEN != 0b11)) Auto Group modes are identical to Auto Individual modes, except that all timer durations are checked against CBEXP1 (a single expiration event). Emergency Discharge Mode The Emergency-Discharge mode performs cell bala ncing in a controlled manner so that the cells can be discharged in the event of an emergency or battery end-of-life. The host initiates the Emergency-Discharge mode by setting CBMODE to 0b001 and configures CBEXP1 to the desired value (where the LSB = 1 hour). After Emergency -Discharge mode is activated, battery cells are discharged until CBTIMER expires or CBMODE is set to 0b000 (disabled). In Emergency-Discharge mode, all balance switches (BALSWn) are enabled regardless of BALSWEN[n] settings, with a CBTIMER duration set by CBEXP1, and they are governed by nonoverlapping even/odd cycling, as follows: Even Cells (2, 4, ... 14): BALSWn = (CBTIMER ≤ CBEXP1) & CBEVEN Odd Cells (1, 3, ... 13): BALSWn = (CBTIMER ≤ CBEXP1) & CBODD CBUVTHR exit settings do not apply, but ADC measurement and calibration operations can still performed, if enabled, to support host controller readback. CBTIMER is incremented on a duty-cycle basis indicating the time each channel is subject to discharge (i.e., one TCBEO cycle out of each E/O/M discharge cycle). This means, in real time, the discharge operation always runs at least 2x the maximum value set in CBEXP1. As an example, if both an even and odd cell must be balanced for 1 hour and the CBDUTY = 100%, the associated timers would be set to 0x3C and the operation would last for ~2 hours (accounting for nonoverlap timing). If the CBDUTY is now set to 50% with the same timer setting, the total operation time would extend to ~4 hours.

periodically to confirm the Emergency-Discharge mode is active. due to the extended lapse in host communication. to confirm the abnormal exit condition. Table 32 summarizes the cell-balancing modes supported by the ADES1754/ADES1755/ADES1756. Table 32. Cell-Balancing Modes low-power operational modes where the host controller is asleep. highest accuracy measurements). Note 2: CELLDLY is used in manual cell-balancing mode when using AUTOBALSWDIS = 0b1 and ALTMUXSEL = 0b0. Also used in automatic cell-balancing and discharge modes after each pair of even and odd discharge cycles.

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 72 Cell-Balancing Timer – CBTIMER Manual, Emergency Discharge, and Auto Group Mode Timing: In Manual, Emergency Discharge, and Auto Group modes, the CBEXP1 bitfield within the BALEXP1 register is used as the cell-balancing timer duration setting. The duration can be configured from 1 to 1023 seconds, from 1 to 1023 minutes, or from 1 to 1023 hours depending on the CBMODE setting (LSB = hour, minute, or second). A value of 0x3FF allows the switches to be enabled indefinitely for CELLn if BALSWENn is also enabled (CBTIMER is active, and rolls over at 3FFh, but is not check ed against CBEXP1). In Manual, Emergency Discharge, and Auto Group modes, the 10 -bit timer (CBTIMER) counts up until it reaches the duration set by BALEXP1. When the cell -balancing timer expires, all cell balancing switches are disabled. When CBEXP1 is non-zero, the cell balancing timer (CBTIMER) will run and any requested measurement and calibration operations will be performed until expiration, even if BALSWEN[14:1] = 000h (i.e., no balancing switches are actually activated). This ensures that the μC can still access the device to confirm balancing operation progress and exit status. A value of CBEXP1 = 000h ensures that no cell balancing will occur. For safety concerns, having all BALEXPn defaulted to 0x000 ensures that no cell balancing will occur wit hout prior configuration. Auto Individual Mode Timing: In Auto Individual mode, the CBEXPn bits within the BALEXPn registers are used as individual cell -balancing duration times for each corresponding CELLn. Individual durations can be configured from 1–1023 seconds, or from 1 –1023 minutes depending on the CBMODE setting (LSB = minute, or second). A value of 0x3FF allows the switches to be enabled indefinitely for CELLn if BALSWENn is also enabled. (CBTIMER will be active and will rollover at 3FFh, but it is not checked against CBEXPn.) The 10-bit expiration timer (CBTIMER) counts up until it reaches the maximum CBEXPn timeout value in the register block (regardless of BALSWENn settings), governing the balancing operations of all balancing switches. When an individual cell expiration time is reached (determined by CBEXPn), the CELLn switch is disabled going forward. When any CBEXPn is non-zero, the cell-balancing timer runs and any requested measurement and calibration operations are performed until expiration, even if BALSWEN[14:1] = 000h (i.e., no balancing switches are actually activated). This ensures that the μC can still access the device to confirm balancing operation progress and exit status. If all 14 CBEXPn settings are 000h, no cell balancing will occur for the switches. General Timing and Safety Features (All Modes): For safety concerns, all BALEXPn a re defaulted to 0x000, which ensures that no cell balancing will occur without prior configuration. The CBTIMER runs to expiration, even if active cell balancing is halted due to UV or thermal exit conditions. This ensures that the μC can still access the part to confirm balancing operation progress and exit status. If an extended SHDNL hold time is requested (HOLDSHDNL = 1x), CBTIMER will read back the governing CBEXP time for the duration of the extended hold interval, allowing the μC to confirm that the requested balancing operation has run to completion. CBRESTART Usage in Manual Mode The CBRESTART bit within the BALSWCTRL register must periodically be written to a 1 to restart the watchdog timer and prevent the cell-balancing switches from being au tomatically disabled due to exiting manual mode when CBTIMER reaches CBEXP1. In the event that a host fails to write the CBRESTART bit or forgets to disable the cell -balancing switches, the cell-balancing watchdog can automatically disable all cell-balancing switches, regardless of the BALSWEN configuration. The cell-balancing watchdog does not modify the contents of the BALSWEN bits within the BALSWCTRL register. The CBRESTART bit is used in manual cell-balancing mode only. It provides a means to select new BALSW settings and refresh the watchdog timer with a single command. This bit is ignored and has no effect outside of an active manual cell -balancing operation. If a manual operation was selected and the timer is allowed to expire, the operation must be relaunched with a write to BALCTRL (i.e., CBRESTART will not reinitiate a manual operation that has allowed the CBTIMER to expire).

register, the CBTIMER is incremented at specified fractions of 30s (see Table 33). For example, when CBDUTY is set to 1h, CBTIMER is incremented in steps of 3.750s at the end of the E/O/M cycle. Table 33. Emergency-Discharge Mode CBDUTY-adjusted). Notification alerts will continue to be issued during HOLDSHDNL extension periods. In summary, the implementation of the CBTIMER is shown in Figure 37.

1 SE COND

1 MINUTE

1 HOUR

Figure 37. Cell-Balancing Expiration Timer Note: The CELLn time-expired output feeds into the cell-balancing stop control logic. balance switch will be disabled and remain in an idle state until reinitialized by the host. is written to 0b000 (disabled) or when a new CBMODE operation is initiated through BALCTRL. the case that a timer is programmed, it will serve as a redundant mechanism to ensure that a cell is not overdischarged.

register. This register allows for 14 bit values relating to a 305μV LSB. be provided, with CBUVMINCELL indicating the means by which it was selected. determined by the channels enabled in the BALSWEN bitfield as well as the parameters set in the SCANCTRL register. Characteristics table. For the highest accuracy, calibration should be asserted prior to initiating balancing. Figure 38. Cell-Balancing UV Threshold Crossing CELLN UV-threshold crossings are inputs to the cell-balancing stop control logic.

Table 34. Cell-Balancing Measurement Enable used to terminate cell balancing normally. 0b1x Enables embedded measurements for manual UV monitoring or supervision by the host processor. robust balancing performance. = 0b000 = 1/8 for use in debouncing measurements.

In Continuation mode (CBIIRINIT = 0) , the current value in the IIR accumulators is kept (presumably from previous cell measurements) and cell-balancing measurements are amended normally.
In Initialization mode (CBIIRINIT = 1), the IIR accumulators will be reinitialized to the first measurement taken, and further cell -balancing measurements are amended normally. CBUVTHR checking is not enabled after the 16th measurement is taken (checking begins on the 17th measurement), giving the IIR time to settle. Cell-Balancing Calibration In automated and discharge modes, after each pair of even/odd cell-balancing periods, a supervisory ADC measurement can be taken (and checked against CBUVTHR, if enabled/applicable; see CBMEASEN). Due to the expected temperature rise during cell balancing, it is recommend to allow automated calibration sequences to be interleaved with the measurement acquisitions. This is done by programming the CBCALDLY to a non -zero value, which signifies how many measurement cycles are taken prior to a calibration being taken. See Table 35.

Table 35. Cell-Balancing Calibration Selection periodically during the cell-balancing operation. to the cell-balancing operation. based on factory defaults (not recommended). 0 (OFF) 000 (OFF) ADC results are based on factory defaults.

measurement operations are performed). Table 36. Calibration Frequency can be requested using factory calibration defaults by setting ADCCALEN = 0. Figure 39. Cell Balancing with No Calibration

Figure 40. Cell Balancing with Calibration CBSCAN acts as a strobe bit and therefore does not need to be cleared (self-clearing); it always reads logic 0.

Watchdog timer expiration (CBTIMER = CBEXPn)
Reaching the UV threshold (per cell in Automated modes only, if CBMEASEN = 0b11)
Thermal fault condition (Automated and Discharge modes only, if CBTEMPEN = 0b1)
Calibration fault condition (Automated and Discharge modes only, if ADCCALEN = 0b1)
Aborting the operation by changing CBMODE to 0b000 (disabled)
Reinitiating an operation by changing CBMODE to a value other than 0b000 Manual cell -balancing mode switch activity can be temporarily suspended for calibration or ADC measurem ents if AUTOBALSWDIS = 0b1. In Discharge, Manual, and Auto Group modes, the CBTIMER will be stopped when it reaches CBEXP1, regardless of BALSWEN settings. In Auto Individual modes, the CBTIMER will be stopped when it reaches MAX(CBEXPn), regardless of B ALSWENn settings. Automated and Discharge modes are halted if temperature exit is enabled (CBTEMPEN = 0b1) and an overtemperature fault occurs. Automated and Discharge modes are halted if CBMEASEN = 0b1x and a calibration fault occurs. All timed modes run CBTIMER for the full duration specified, even if actual cell -balancing operations are stopped due to UV or thermal exit conditions, allowing the μC to confirm the exit status. Additional time for the μC to check the exit status can be afforded using HOLDSHDNL options. CBACTIVE allows confirmation of cell -balancing operation status. A cell -balancing operation is considered completed normally if the CBTIMER expires (all CB modes), or when all enabled cells reach the programmed CBUVTHR limit (Automatic modes only, if CBMEASEN = 1b1). A cell-balancing operation is considered completed abnormally in the event of an ALRTCBCAL or ALRTCBTEMP condition.

Figure 41. Cell-Balancing Stop Control damaged by exceeding the absolute maximum rated junction temperature. measurements). The exit result reflects the first exit criteria encountered. Table 37. Cell-Balancing and Auto-Polling Stop Criteria Cell-balancing switch activity stops.

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 79 CBUV Threshold Disabled, Measurement Enabled Exit Criteria: Auto-polling will only exit based on timer or timeout criteria. Exit Criteria: N/A - Cell measurements will not induce an exit. Exit Result: N/A - Cell balancing will only exit on other criteria CBMODE = 0b1XX (Auto) CBMEAS = 0b10 (Embedded Measurement, CBUVTHR Checking Enabled) Timeout Fault Exit Criteria: Timer integrity fault found. Exit Result (Fault): CBACTIVE = 0b11 ALRTCBTIMEOUT = 0b1 All timers and measurements stop (state machine compromised). Exit Criteria: Timer integrity or oscillator fault found. Exit Result (Fault): CBACTIVE = 0b11 ALRTCBTIMEOUT = 0b1 All timers, measurements, and cell balancing switch activity stops (timer compromised). CBMODE = 0b1XX (Auto) for auto-polling CBMODE != 0b000 or 0b001 for cell balancing Thermal Fault Exit Criteria: Auto-polling will only exit based on Timer or Timeout criteria Die Temperature faults will be reported through the Alert Packet (FMEA2.ALRTTEMP = 0b1) Exit Criteria: A die temperature fault is detected (FMEA2.ALRTTEMP = 0b1). Exit Result (Fault): CBACTIVE = 0b11 ALRTCBTEMP = 0b1 All timers continue. Measurement, calibration, and cell- balancing switch activity stops. CBMODE = 0b1XX (Auto), 0b001 (Emergency Discharge) CBTEMPEN = 0b1 Calibration Fault Exit Criteria: Auto-polling will only exit based on timer or timeout criteria. Calibration faults will be reported through the Alert Packet (STATUS1.ALRTCAL = 0b1). Exit Criteria: A calibration fault is detected (STATUS1.ALRTCAL = 0b1). Exit Result (fault): CBACTIVE = 0b11 ALRTCBCAL = 0b1 Timers continue. Measurement and cell-balancing switch activity stops (measurements compromised). CBCALDLY != 0b000 ADCCALEN = 0b1 (Enabled) Note: Auto-polling will not assert the ALRTCBTEMP, ALRTCBCAL, and ALRTCBAUX status bits since it does not exit the mode based on the insertion. Any u nderlying alert conditions will be reflected in ALRTTEMP, ALRTCAL, ALRTAUXOV, ALRTAUXOV, and ALRTAUXPRTCTSUM. Note: Auto-polling and auto cell-balancing operation only updates the CELLn, AUXn, and DIAGn registers upon issuance of a CBSCAN during operation with CBMODE != 0b000, 0b001. Note: All timed modes run CBTIMER for the full duration specified, even if actual cell -balancing operations are stopped due to a UV condition or thermal fault. In addition to the above criteria, both auto-polling and cell balancing may be stopped by aborting the operation (CBMODE = 0b000) or reinitializing the operation by changing CBMODE to a value other than 0b000. CBACTIVE allows confirmation of cell-balancing operation status. A cell -balancing operation is considered compl eted normally if the CBTIMER expires (all CB modes), or when all enabled cells reach the programmed CBUVTHR limit (Automatic modes only, if CBMEASEN = 1b11). A cell -balancing operation is considered completed abnormally in the event of an ALRTCBTIMEOUT, ALRTCBCAL, ALRTCBTEMP, or ALRTCBAUX condition.

Figure 42. Cell-Balancing Stop Control by exceeding the absolute maximum rated junction temperature. BALCTRL register. When enabled and engaged, this mode activates an internal diode pullup from the VAA pin to SHDNL. This keeps the device operational, even if UART operation is suspended for long periods of time. The HOLDSHDNL options have no effect in Disabled or Manual modes. issues (ALRTCBCAL), or reaching the specified voltage target (CBUVTHR). infinite (3FFh), SHDNL will be held until removed by a write to BALCTRL. In mode 0b11, the pullup is engaged until removed by a write to BALCTRL. CBMODE to disabled, allowing the device to power down.

Figure 43. SHDNL Pullup Control

Figure 44. Internal Cell-Balancing Switches balancing is also detailed in the Typical Operating Characteristics section.

Figure 45. Thermal Image During Balancing of 7 Cells, 300mA, +60°C Ambient

Host calculates SOC for each of the individual cells.
Host determines which cells to balance and associated balancing time.
Host programs balancing channels using BALSWEN[13:0].
Host programs effective balancing current.
Effective balancing current = VCELLn/(2 x RBALANCE) x CBDUTY[7:4]
Host programs CBEXP1-CBEXP14 based on effective balancing current and SOC.
Host programs HOLDSHDNL to determine shutdown behavior at completion of cell balancing.
Host initiates balancing using CBMODE "auto -individual cell balancing by second" or "auto -individual cell balancing by minute."

and a secondary stop mechanism being a programmable timer.

Host calculates SOC for each of the individual cells.
Host determines which cells to balance and associated balancing time. Timer is a secondary stop mechanism and should have additional margin applied as not to interact with primary UV measurement stop threshold.
Host programs balancing channels using BALSWEN[13:0].
Host programs effective balancing current. Effective balancing current = VCELLn/(2 x RBALANCE) x CBDUTY[7:4]
Host programs CBEXP1-CBEXP14 based on effective balancing current and balancing time calculation.
Host programs CBUVTHR or CBUVMINCELL to program UV measurement stop threshold.
Host programs CBMEASEN as "Embedded ADC/CAL Measurements enabled, CBUVTHR checking enabled."
Host programs CBCALDLY to force measurement calibration to a ccount for temperature rise from balancing. Calibration choice should be chosen based on the thermal time constant of the board.
Host programs HOLDSHDNL shutdown behavior at completion of cell balancing.
Host initiates balancing using CBMODE as "auto-individual cell balancing by second" or "auto-individual cell balancing by minute." Interface UART Interface Overview The battery-management UART protocol allows up to 32 devices to be independently addressed in a daisy-chain fashion as shown in Figure 46. The host initiates all communication with the daisy-chain devices through a UART interface such as the SPI to UART bridge. The UART can be configured to support a variety of flexible implementations depending on the application requirement. The configurations as defined using UARTCFG are shown in Table 38.

Table 38. UART Configurations the data. It does not act on any commands in this configuration.

It is quicker to determine device count for applications where the host does not assume what the device count is.
It helps to match the supply current of the last device to that of the other daisy-chained devices (because the hardware configuration is identical).

Figure 46. Single UART with External Loopback components and wire connections. Additionally, this mode is useful to diagnose the location of daisy-chain signal breaks. loopback mode to the next device, and continuing up the stack until communication is lost.

loopback configuration because the communication was interrupted. Figure 47. Single UART with Differential Alert Interface

with no loss of functionality. Note: For this configuration to be utilized, both the hardware and software configurations should match. By default, the Down Path UART operates as a target, meaning it will have no response to a Write or WriteAll command. controller is performed by reading the UARTHOST bit. See the Battery-Management UART Protocol Commands section. Figure 48. Dual-UART Interface

unless it reinitializes itself as the controller using the UPHOST command. configured to the same controller interface. ALRTDUALUART bit will be set. Figure 49. Dual-UART Controller-Target Interaction (Timing Considerations)

differential mode or single-ended mode per Table 38. By default, the UART receivers are configured for differential mode. voltage (VRXP, VRXN = 0V) is considered to be a logic 1 and a negative differential voltage (VRXN high) is a logic 0. Figure 52. UART Receiver pin voltage will fall with a 10ms time constant (assuming a 1nF capacitor). Note: Do not connect active components to SHDNL. Path or Down Path to initialize the device.

Figure 53. SHDNL Charge Pump stop when a preamble has been received back at the host Rx port. back at the host Rx port, (2 x n) + 1 preambles must be sent. Down Path. Both paths operate at the same communication rate.

All transmitted data bytes are Manchester -encoded where each data bit is transmitted twice with the second bit inverted (G.E. Thomas convention).
Every transmitted character contains 12 bits which include a start bit, a parity bit, and two stop bits.
Read/write packets contain a CRC-8 packet error checking (PEC) byte.
Each packet is framed by a preamble character and stop character.
Read packets contains a Data-Check byte for verifying the integrity of the transmission. The protocol is designed to minimize power consumption by allowing target devices to shut down if the UART is idle for a specified period of time. (See the SHDNL Charge Pump section for additional detail.) Command Packet A command packet is defined as a sequence of UART characters originating at the host. Each packet starts with a preamble character, followed by data characters, and ending with a stop character as shown in Table 54. After sending a packet, the host either goes into idle mode or sends another packet.

Figure 54. Command Packet preamble sequence, then the character is not interpreted as a valid preamble, but rather as a data character. Figure 55. Preamble Character encoding error in any received data character, it will set the ALRTMANUP, or ALRTMANDN bit in the STATUS2 register. sets ALRTMANUP, and a Manchester error in the DOWN path sets ALRTMANDN. The parity is even meaning that the parity bit’s value should always result in an even number of logic 1 bits in the character. configuration, a parity error in the UP path sets ALRTPARUP, and a parity error in the DOWN path sets the ALRTPARDN. Table 39. Data Character Description

1 Start S First bit in character, always logic 0

2 Data0 Least significant bit of data nibble (true)

3 Data0/ Least significant bit of data nibble (inverted)

4 Data1 Data bit 1 (true)

5 Data1/ Data bit 1 (inverted)

6 Data2 Data bit 2 (true)

7 Data2/ Data bit 2 (inverted)

8 Data3 Most significant bit of data nibble (true)

9 Data3/ Most significant bit of data nibble (inverted)

10 Parity E Always logic 0 (even parity)

11 Stop P Always logic 1

12 Stop P Last bit in character, always logic 1

Figure 58. Communication Mode The battery-management UART protocol employs several different data types as described in Table 40. Table 40. Data Types The battery-management UART protocol supports eight command types summarized in Table 41. Table 41. Command Packet Types *Block size[4:0] = 1-32 which is the number of registers read.

Table 42. Battery-Management Protocol Command Byte Encoding *Assumes DA[4:0] = 0x00 where DA[4:0] is the device address in the ADDRESS register. pass through the packet to the next device. All registers are 16-bit words (two data bytes) and are defined in the Register Map. commands. For READDEVICE, the DCByte is updated only by the addressed device. The DCByte sent by the host is a seed value normally set to 00h, although non-zero values may be used as a diagnostic. path's command packet, as described in Table 43. Table 43. Data-Check Byte

7 PEC ERROR PEC error detected during the current transaction on the Up/Down Path issuing this bit

6 ALRTFMEA (ALRTFMEA1 & FMEA1ALRTEN) or (ALRTFMEA2 & FMEA2ALRTEN)

5 ALRTSTATUS

4 AUXOV (UT) (ALRTAUXOVST & AUXOVSTALRTEN)

3 AUXUV (OT) (ALRTAUXUVST & AUXUVSTALRTEN)

2 CELLOV (ALRTCELLOVST & CELLOVSTALRTEN)

1 CELLUV (ALRTCELLUVST & CELLUVSTALRTEN)

0 RESERVED 0

a POR condition, and thus cannot be masked. STATUS1[5]:ALRTPEC is intentionally not included in the DCByte.

calculated value. For read commands, the device must return its own calculated PEC byte based on the returned d ata. should be discarded. See the Applications Information section for details on the PEC calculation. the next device increments it to 00h. next device increments it to 00h. bytes in the packet are to be overwritten. For a READBLOCK command, the number of fill bytes sent is equal to the read data block size. For a READDEVICE command, only two fill bytes are required, since only one device responds (returning two data bytes). subsequent READALL, READ DEVICE, READ BLOCK commands. Table 44. HELLOALL Command Packet

DA[4:0] value returned is one greater than address assigned to the top device. never set the bottom address at a value which would result in the device address exceeding 0x1F. address that has already been determined. Table 45. HELLOALL Up Path Sequencing command through the Down Path prior to sending the HELLOALL. DA[4:0] decremented below 0x0. addressing of the READ DEVICE and READ ALL commands. the device address unaffected (i.e., HELLOALL sent in the Up Path with UARTHOST set to 1'b0). Table 46. HELLOALL Down Path Sequencing In single-UART configuration, the HELLOALL will be processed the same as in the dual-UART Up Path.

on the top device and all ADDRESS registers verified. the device addresses, they should be verified using the READALL command. forwarded to the next device. The PEC is calculated from the first four bytes of the command starting after the preamble. configuration, a PEC error in the UP path sets ALRTPECUP, and a PEC error in the DOWN path sets ALRTPECDN. Table 47. WRITEALL Sequencing (Unchanged by Daisy Chain)

If Alive-Counter mode is enabled.

address is not valid for the device, the command is ignored. The command sequence is shown in Figure 48. PEC error can only occur in the addressed device.

Table 48. WRITEDEVICE Sequencing (Unchanged by Daisy Chain)

If Alive-Counter mode is enabled.

propagated through the daisy chain and back to the host. Table 49. READALL Command Sequencing in Single-UART or Dual-UART Up Path

If Alive-Counter mode is enabled.

Table 50. READALL Command Sequencing in Dual-UART Down Path (z = Number of *If Alive-Counter mode is enabled. addresses, and its own device address and therefore it knows where in the data stream it belongs. daisy chain and back to the host.

Table 51. READDEVICE Sequencing in Single-UART or Dual-UART Up Path *If Alive-Counter mode is enabled. Table 52. READDEVICE Sequencing in Dual-UART Down Path *If Alive-Counter mode is enabled.

The command sequences for a block size of 2 are shown in Table 55 and Table 56. The command packet is forwarded

Table 53. READBLOCK Sequencing in Single-UART or Dual-UART Up Path Block

If Alive-Counter mode is enabled.

Table 54. READBLOCK Sequencing in Dual-UART Down Path Block Size = 1

If Alive-Counter mode is enabled.

Table 55. READBLOCK Sequencing in Single-UART or Dual-UART Up Path Block

If Alive-Counter mode is enabled.

Table 56. READBLOCK Sequencing in Single-UART or Dual-UART Down Path Block

If Alive-Counter mode is enabled.

using the UARTHOST register bit. By default, only the Up Path has the WRITE access (UARTHOST = 1b1). be passed from the Down Path to the Up Path. The UPHOST command is detailed in a different section. UARTHOST unchanged with the Down Path indication. is passed through, unchanging the DEVCOUNT. Table 57. DOWNHOST Sequencing (z = Total Number of Devices) using the UARTHOST register bit. By default, only the Up Path has the WRITE access (UARTHOST = 1b1). control and also increments the DEVCOUNT variable as it sends the command to the next device, upstream, in the chain. The final value of DEVCOUNT received by the host equals the initial DEVCOUNT + total number of devices in the chain. with the Up Path indication. is passed through, unchanging the DEVCOUNT.

Table 58. UPHOST Sequencing (z = Total Number of Devices) Address location (DA[4:0]), Alert Status byte, and the PEC byte of the protected data. See Table 59. the alert type. This creates a method to quickly assess the module status and health with little host interaction. Table 59. ALERTPACKET Sequencing number of associated I2C-compatible target devices connected to the 2-wire bus at clock rates of 100kHz or 400kHz. is optional and, in fact, most target devices do not include an SCL driver, so they are unable to stretch the clock. The I2C timing diagram is shown in Figure 59. See the Electrical Characteristics table for complete timing specifications.

Figure 59. Standard I2C Bus Timing Diagram time after the STOP condition. The bus stays busy if a repeated START (Sr) is generated instead of a STOP condi tion. In this respect, the START (S) and repeated START (Sr) conditions are functionally identical. pulses, including the acknowledge ninth clock pulse. times must also be taken into account. for all read mode transactions, the controller will issue a NACK after the last byte of the transaction.

bus is terminated to the highest interface supply if multiple supplies are required in the application. Figure 60. I2C Device Connection Map for detailed descriptions. devices of a single type, it is generally only necessary to write to the configuration register once. I2CFSCL selects the I2C SCL frequency (0b0 = 100kHz, 0b1 = 400kHz). I2C10BIT selects the target address format used for all transactions (0b0 = 7 bit, 0b1 = 10 bit). available for use in I2C controller transactions using I2CPNTRSEL (minimizing configuration time).

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 107 I2CCONTEN enables digital bus contention monitoring and its associated alert component (0b0 = disabled, 0b1 = enabled). I2CGLITCHEN enables bus glitch monitoring and its associated alert component (0b0 = disabled, 0b1 = enabled). I2CNOISEEN enables bus noise monitoring and its associated alert component (0b0 = disabled, 0b1 = enabled). I2CRDTREN enables redundant Read mode checking and its associated alert component (0b0 = disabled, 0b1 = enabled). I2CTOEN enables watchdog checking of I2C transactions using the 32kHz oscillator (0b0 = disabled, 0b1 = enabled). I2CPNTR Register This register contains I2CPBYTE1 and I2CPBYTE0 of pointer (command) data sent as the command portion of Write and combined format Read mode transactions. If I2CPNTRLNGTH = 0b0, either byte can be sent (selected by I2CPNTRSEL), so two I2C command transactions can be supported by writing to this register only once. If I2CPNTRLNGTH = 0b1, both bytes are sent. This register can also be read back to verify contents. I2CWDATA Registers The I2CWDATA1 and I2CWDATA2 registers contain 4 bytes of data that can be sent to target devices during the data portion of Write mode transactions. Selection of which bytes and how many bytes are sent is determined by I2CDATALNGTH and I2CDATASEL. Thus for transactions of 1 or 2 bytes of data, it is possible for several Writ e mode transactions to be supported by writing to this register only once. This register can also be read back to verify contents. I2C Transaction Requests and Results Once the I2C controller is properly configured and supplied with any required input data, transactions can be sent. See the Register Map for detailed descriptions. I2CSEND Register The I2C controller generates initiates clock and data transactions on the bus in response to an accepted/qualified write to the I2CSEND command register. Each accepted/qualified write to this register initiates a transaction, unless a transaction is already in progress (in which case the new transaction request is ignored and the I2CRJCT alert component is set). Transaction progress and status can be monitored using the I2CSTATUS register. This register can also be read back to verify the specifics of the last accepted transaction. I2CPNTRSEL selects the byte sent as the command portion of Write and combined format Read mode transactions (applicable only if I2CPNTRLNGTH = 0b0). If I2CPNTRLNGTH = 0b1 (2 -byte pointer mode), this bit is ignored and both bytes are sent. I2CDATALNGTH selects the number of data bytes to be sent in a Write mode transaction or received in a Read mode transaction. I2CDATASEL selects the data register locations to be sent in Write mode transactions or filled during Read mode transactions. It also selects the location of the data bytes(s) to be transferred during write transactions and the target location for data byte(s) used for storage during read transactions. The selection indicates the location of the MSB of the data space used during the transaction; the number of bytes used is set by I2CDATALNGTH. Some limitations do apply: If I2CDATALNGTH = 0b11 (4 bytes), this selection is ignored and Bytes[3:0] are used. If I2CDATALNGTH = 0b10 (3 bytes), this selection is ignored and Bytes[2:0] are used. If I2CDATALNGTH = 0b01 (2 bytes), the LSB is ignored; for 0x, Bytes[1:0] are used, and for 1x, Bytes[3:2] are used. If I2CDATALNGTH = 0b00 (1 byte), any of the four available bytes can be used. If I2CDATALNGTH = 0b10 and I2CWALT = 0b1 (0-byte write), this selection is ignored and no bytes are used. I2CDEVIDEXT and I2CDEVID are used to set the target address sent durin g I2C transactions (I2CDEVIDEXT is only used if I2C10BIT = 0b1, otherwise it is ignored). I2CRWB determines if the I2C transaction sent write (0) or read (1).

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 108 I2CRDATA Registers The I2CRDATA1 and I2CRDATA2 registers contain 4 bytes (I2CRBYTE3, I2CRBYT E2, I2CRBYTE1, I2CRBYTE0) of memory that can be filled with data received from target devices during the data portion of read mode transactions. Selection of which bytes are used in support of a Read mode transaction is determined by I2CDATALNGTH and I2CDATASEL. Thus, for transactions of 1 or 2 bytes of data, it is possible for several Read mode transactions to be supported by filling this register using multiple transactions while reading this register only once when filled. This register is read only. Note: During Read commands, data is updated as each byte is received/acknowledged; reading back target registers during read transactions may yield corrupted results. I2CSTAT Register The I2CSTAT register provides information on active and completed I2C transactions. I2CSTATUS reports the status of the last requested transaction and its resolution if completed. No Transaction (0b00) indicates no transaction has been requested since I2CSTAT was last read. Transaction in Progress (0b01) indicates the last requested transaction is in progress; this status will not be changed until the transaction terminates. Once a transaction is completed, the Transaction Complete (0b11, if successful) or Transaction Error (0b10, if unsuccessful) status is reported. A trans action error occurs if the following alert conditions are detected and enabled (I2CRJCT, I2CDEVNACK, and I2CDATANACK are always enabled). These status bits are cleared/updated when I2CSTAT is read back or when a new transaction is begun. The remaining bits relate alert conditions if a problem was encountered. I2CRJCT indicates one or more I 2C transactions were rejected because a write to I2CSEND was attempted during an ongoing transaction. (Note that the ongoing transaction is not impacted). I2CDEVNACK indicates the I2C transaction Device ID byte(s) were not acknowledged by a target. This may indicate the target is malfunctioning or not present on the bus. For Combined Format Read transactions, both target address acknowledge pulses are required to avoid an error. The current I2C transaction will continue until completion. That is, the controller will not issue a STOP bit immediately. I2CDATANACK indicates one or more I2C transaction data byte(s) written were not acknowledged by a target. This may indicate the target is malfunctioning, not present on the bus, is busy, or has rejected an unsupported transaction. The current I2C transaction will continue until completion. That is, the controller will not issue a STOP bit immediately. I2CANACONT and I2CCONT indicate a bus contention condition was observed. Contention is reported when the port result does not match the value driven by the I2C controller. This monitor observes the SCL port and the SDA port when driven by the I2C controller. See the I2C Bus Contention Monitor section for more details. I2CGLITCH indicates a bus glitch condition was observed. A glitch is reported when a port monitor reports two or more consecutive samples (125ns) that disagree with the evaluated value. This condition may also be reported if slow transition times, setup time, or hold time violations occur (outside I 2C specifications). This monitor observes the SCL port and the SDA port outside specified transition intervals. See the I2C Glitch Monitor section for more details. I2CNOISE indicates a noisy bus condition was observed. A noise condition is reported when a port monitor reports a large amount of samples that disagree with the evaluated value. This condition may also be reported if slow transition times, setup time, or hold time violations occur (outside I 2C specifications). This monitor observes the SCL po rt and the SDA port outside of specified transition intervals. See the I2C Glitch Monitor section for more details. I2CRDTRERR indicates the results of an I2C Redundant Read Transaction Check failed (enabled if I2CRDTREN = 0b1). I2CTIMEOUT indicates the I2C transaction did not complete in the expected period of time (enabled if I2CTOEN = 0b1). This register is read only. I2C Controller Register Access During Active I2C Transactions Since the I2C controller register contents are in use during active I2C transactions, user interface access to the registers during ongoing I2C transactions is strictly controlled. Attempts to write or read content to/from these registers that may result in data corruption or synchronization issues are rejected and result in I2CSTAT:I2CRJCT and STATUS2:ALRTI2C being issued, notifying the user that the request has been ignored. Table 60 provides a summary of register accessibility by active I 2C transaction and user transaction type. See the Register Map for complete details on all I 2C controller registers.

the transaction itself. Combined format read transactions are enabled when I2CRFMT = 0b0. I2CDATALENGTH = 0b10 in order to write the pointer location within a target device. this case, it is assumed that the pointer within the target remains in the position used for the Write Mode Transaction. operation before using these transactions in an application. I2CSEND command register with I2CRWB = 0b1. The controller controls SCL for the entirety of the transaction. associated with address portion of the transaction, except the clock cycle reserved for the target acknowledge bit. be achieved with alternate configuration settings. Figure 65. I2C Normal Format Read Mode Transaction Example—7-Bit Address, I2C10BIT = 0, I2CRFMT = 0 command register with I2CRWB = 0b1. The controller controls SCL for the entirety of the transaction.

devices may acknowledge Byte 1, but only the addressed target device acknowledges Bytes 2 and 3. Figure 66. I2C Normal Format Read Mode Transaction Example—10-Bit Address, I2C10BIT = 1, I2CRFMT = 0 and the operation of the bus. observes the SCL port and the SDA port when driven by the I 2C controller. The contention monitor is always enabled. register bit ALRTI2C does not depend on the I2CCONT value. I2CANACONTEN = 0b0, STATUS2 register bit ALRTI2C does not depend on the I2CANACONT value. SDA/SCL ports. The difference between I2CANACONT and I2CCONT is illustrated in the Figure 67 timing diagram. analog filtered value is still high but the raw value is low. Thus, only I2CCONT is set. The third diagram shows the fault when GPIO[0] is stuck low. Both I2CANACONT and I2CCONT are set.

Figure 67. GPIO, I2CANACONT, and I2CCONT Timing Diagram

(outside I2C specifications). This monitor observes the SCL port and the SDA port outside specified transiti on intervals. is set. When I2CGLITCHEN = 0b0, STATUS2 register bit ALRTI2C does not depend on the I2CGLITCH value. I2CNOISEEN = 0b0, STATUS2 register bit ALRTI2C does not depend on the I2CNOISE value. Figure 68. I2C Glitch and I2C Noise Monitor I2CDATASEL is overwritten with the redundant data.

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 115 If any mismatch is found, the I2CSTATUS will read back a Transaction Error (0b10) and the I2CRDTRERR alert component bit will be set high for the transaction. While the redundant data from the repeated transaction is made available for readback in the register space specified, this data should be treated as compromised if I2CRDTRERR is set. Note that Redundant Read Checking may not be advisable in some applications—in particular, if the target device updates register content autonomously (and could change the data during/between the redundant transactions), or if the data requested is subject to noise (as might b e the case if the read transaction triggers a measurement/observation which is read back). If used to read a FIFO with a pointer subject to increment upon readback, this method will not work. Special consideration should be given when using Normal Format R ead Transactions —in particular, if target pointers are autoincremented in response to read transactions, results may be incompatible with transactions of this type (without a preceding Write Transaction to reset the pointer to the original location). Revie w the operation of all target devices carefully before using this feature. There is no Write mode equivalent of a redundant check. Write mode transactions are best checked for success through a readback of written target register content, assuming the target register supports R/W access. I2C Watchdog Timer The I2C watchdog timer monitors all transactions for completion in the expected time required for the command. If the IectionC watchdog timer is enabled (I2CTOEN = 0b1), the I2C controller transaction is monitored for completion against a time out limit based on the transaction requested and mode settings. If the transaction fails to complete, the transaction will be aborted (stopped), any missing read data bytes will not be updated, I2CSTAT US will show a Transaction Error (0b10), and the I2CTIMEOUT fault indicator bit will be set high. The I 2C watchdog timer counts in 32kHz clock increments—488μs for 400kHz operation and 1953μs for 100kHz operation—while I2CSEND is enabled. If terminal time is reached before completion of the current transaction, I2CSEND is cleared, the I2CTIMEOUT fault indicator bit is set, and the controller returns to idle state (SDA = SCL = pulled high). Freeing a Stuck I2C Bus In the unlikely event of an aborted I 2C transaction (due to either an I 2C timeout fault, or an unexpected reset of the ADES1754/ADES1755/ADES1756), it is possible for a target device to occupy the SDA bus and hold it in a low position. This would prevent the ADES1754/ADES1755/ADES1756 from issui ng new transactions until the target device vacates the SDA bus, allowing the I 2C controller to send START and STOP information. If this were to occur, contention errors would be reported. I2C Method (I2CEN = 1) In order to recover, I2C write transactions should be sent to a nonexistent target Device ID. The recommended transaction is a 7 -bit address, single -byte data I 2C Write transaction with all DEVID, PBYTE, and WBYTE content set to ones. Eventually the target device occupying the bus will recognize th e SCL activity, vacate the SDA bus, and observe the STOP condition. Contention errors will continue to be reported until the bus is freed. Normal I 2C communication should then be restored, and new transactions to valid target Device IDs can proceed. GPIO Method (I2CENB = 0) Alternatively, the bus can be freed by sending a stream of SCL pulses until the stuck target device finishes its transaction and frees the bus. This can be accomplished by setting I2CEN = 0, configuring AUX0/SDA as a GPIO input (GPIOEN[ 0] = 1, GPIODIR[0] = 0, GPIODRV = x), and configuring AUX1/SCL as a GPIO output (GPIOEN[1] = 1, GPIODIR[1] = 1, GPIODRV = toggle). Send SCL pulses using GPIODRV[1], until the target frees SDA (GPIORD[0] = 1 for a sustained number of SCL cycles). Once the t arget vacates the bus, it will be able to observe the START/STOP conditions present in normal I2C transactions, and communication will be restored. Alert Interface The alert interface communicates the presence of a fault condition generated from the lo gical OR of the STATUS1 register, which flags any error within safety critical functionality: voltage measurements, temperature measurements, interface communication robustness, calibration, and other internal hardware diagnostics. As safety considerations may differ per platform, each of the associated alerts can be masked to provide individualized control. Additionally, the alert interface may be actively driven without an actual alert condition to validate functionality. This is done using the ALRTUSER bit in the FMEA2 register.

(see the UART Receiver section for details). The ALERTOUT pin uses a single-UART transmitter as its output driver. Table 61. Alert Interface Configuration ALERTOUT output drivers for both single-ended and differential operation. registers as well as verifying the UART Data-Check byte. Table 62. Alert Output Driver Configuration

1 Don't Care 0 1

signal will not be propagated to the host. See Figure 69. Z, and TXLIDLEHIZ = 1'b0, ALERTOUT is driven low.

Figure 69. Alert Detection Timing Diagram readback in the STATUS1 register. Note: ALRTRST indicates a POR condition, and thus cannot be masked.

indicates a POR condition, and thus cannot be masked. registers will mask all ALRTBALSW diagnostics from being reported. All selections are supported for this function and, if TOPCELL2 is not equal to TOPCELL1, no alerts are masked. enabled until TSHDN < +130°C, due to hysteresis. Table 63. High-Voltage Regulator Operation Characteristics Table 64. High-/Low-Voltage Regulator Diagnostic

Figure 70. HV/LV Regulator and Thermal Shutdown Circuit VHV-DCIN. When the charge pump achieves regulation, VHV-DCIN, charge pumping stops until the voltage drops by 20mV. The charge pump is automatically disabled during shutdown. is considered a worst settling delay for the SW input. Outside of an acquisition, the charge pump is clocked at 32kHz. that affects measurement accuracy. HV charge pump diagnostics are summarized in Table 65. of the channel. Headroom alerts are indicated with the ALRTHVDRM bit in the FMEA1 register. and allowing VHV to decay while in acquisition mode. Table 65. HV Charge Pump Diagnostics

Figure 71. HV Charge Pump integrity level. If the HFOSC varies by more than 5%, communication errors may be indicated for the UART. Table 66. Oscillator Diagnostics are provided in this section.

Table 67. Summary of Built-In Diagnostics Procedural diagnostics: Contact Analog Devices for the complete listing of procedural diagnostics found in the safety manual.

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 122 ALERTOUT Pin-to-Pin Short Diagnostic The UART Alert DC Diagnostic Test is used to test the ALERTOUT pin for shorts to AUXIN0/GPIO0 pins. When UARTSEL = 0b1 (UART mode), this test is enabled by setting ALERTDCTSTEN bit to 0b1. When the DC Diagnostic Test is enabled, the ALERTOUT pin will be driven low if an Alert condition is present, and driven high otherwise. The ALRTUSER bit field can be written to exercise ALRTOUT in either direction. Neighboring pins, such as AUXIN0/GPIO0, can be monitored directly or in diagnostic modes to detect a fault. This function works in all UARTCFG modes, including the differential alert, which does not normally use the ALERTOUT pin. CELL Pin Open Diagnostics If an input of the ADES1754/ADES1755/ADES1756 is disconnected from the cell input through any combination of mechanical failure, the position of the failure can be detected by performing cell open diagnostics. It is recommended that comparator measurements are used for quick identification against the default threshold setting COMPOPNTH. If measurement is below the set threshold, the corresponding cell alerts are flagged in ALRTCOMPOV. This diagnostic is enabled by settin g CELLOPNDIAGSEL = 1 and performing comparator scan (SCANCFG = 0b010). Only unipolar measurements are allowed for this diagnostic and, if a cell position is set as bipolar, the corresponding cell is skipped and the alert flag is not set for that bipolar cell. Normally, in Open Diagnostic modes, pulldown current sources are enabled on all measured channels using CTSTEN for required cells. Various current configurations setting are available for the user and can be configured using DIAGCFG:CTSTDAC bit field. Die Temperature Measurement The die temperature measurement allows the host to compute the device temperature (TDIE) as it relates to the acquisition accuracy and allows the device to automatically shut itself down when T DIE > +145°C. The measurement e mploys a source whose voltage, V PTAT, is proportional to absolute temperature (PTAT) as shown in Figure 72 . The V PTAT measurement is enabled by setting DIAGSEL1[3:0] or DIAGSEL2[3:0] to 0b0001, and the 14 -bit measurement is stored in DIAG1 = DIAG1REG[15:2] or DIAG2 = DIAG2REG[15:2], respectively. The die temperature measurement requires a settling time of 39μs from the start of the measurement cycle until the diagnostic conversion. As long as two or more cell measurements are enabled, there will be sufficient settling time for this measurement. See the acquisition timing sections for more details. The PTAT voltage is computed as follows: VPTAT = DIAG1 16384d × VPTAT or VPTAT = DIAG2 16384d × VREF where VREF = 1.25V. The measured voltage may be converted into °C as follows: TDIE(in °C) = VPTAT AV_PTAT + TOS_PTAT − 273°C See the Electrical Characteristics table for AV_PTAT and TOS_PTAT values. Die Temperature Alert The die temperature is continuously monitored in an interval of 1ms to detect if the TDIE > TALRTTEMP. In the event when die temperature is greater, ALRTTEMP bit in FMEA2 register is asserted. The only exception is that ALRTTEMP monitoring is temporarily disabled when the die temperature measurement is requested by configuring DIAGSEL1[3:0] or DIAGSEL2[3:0] = 1h. The signal path for die temperature alert and measurement is shown in Figure 72. If ALRTTEMP is set, the host should consider the possibility that the acqui sition does not meet the expected accuracy specification, or that the die temperature measurement itself may be inaccurate due to insufficient settling time (< 2 cell measurements enabled).

Figure 72. Die Temperature Measurement The result for VAA should fall within the range provided in the Electrical Characteristics table for VAA. measurement cycles to mitigate the variation seen by noise.

nominal voltage of 3.3V, the 14-bit expected range for DIAG[15:2] which passes the diagnostic is from 0x2147 to 0x24B6. Figure 75. VDDL Diagnostic

Comparator functionality verification against specification
Comparator thresholds calibration
Increased comparator performance for improved specification beyond that described in the Electrical Characteristics table. The functionality of the comparator signal conditioning path (shown in Figure 76) can be measured us ing DIAGSEL1 = 0b0100 or DIAGSEL2 = 0b0100 in the DIAGCFG register. This configuration applies an input of V REF = 1.25V to the LSAMP2 while the DAC is programmed to 03FFh (DAC reference of 1.25V). The output of the comparator preamp is routed to the ADC input where it is effectively measured. The result of the ADC measurement is presented in corresponding DIAG1REG[15:2] or DIAG2REG[15:2] registers.

Figure 76. Comparator Signal Path to ADC Comparator functionality is verified by comparing the DIAG register outputs against the ranges shown in Table 68. Table 68. Comp Signal Path Diagnostic Verification Ranges described in the Electrical Characteristics table.

uses values from the COMPACCOVTH and COMPACCUVTH registers. The Comparator Accuracy Diagnostic signal path is shown in Figure 77. Figure 77. Comparator Accuracy Diagnostic Path In order to eliminate false alerts, the user should adjust COMPACCOVTH and COMPACCUVTH by ±18 DAC codes. end of the last oversample of the SCAN measurement request, as indicated in Figure 78.

Figure 78. Comparator Accuracy End of Scan Measurement the DIAGSEL1 = 0b0101 or DIAGSEL2 = 0b0101 in the DIAGCFG register in accordance with the SCANMODE setting. each of the SCANMODE configurations utilized by the application to validate calibration. The expected result is 1/4 of full-scale voltage and can be read from the DIAG1REG [15:2] or DIAG2REG[15:2] registers. To allow for a 14-bit ADC, measurements should extend from 0xFD2 to 0x102F. Note: This diagnostic should not be run without enabling calibration.

Figure 79. Cell Gain Calibration Diagnostic Measurement Characteristics table specifications. diagnostic acquisition must be minimally configured to an oversample of 16, which ensures proper accuracy performance. The expected result is 0V (0x2000) and can be read from DIAG1REG [15:2] or DIAG2REG[15:2] registers. For Pyramid mode, the 14-bit ADC measurement bound that passes this diagnostic ranges from 0x1FF6 to 0x200A.

could be degraded accordingly. The signal path for this diagnostic is shown in Figure 82. The 14-bit ADC measurement bound that passes this diagnostic ranges from 1FD4 to 0x202D. comparison of the VBLK measurement to the sum of the cell measurements. Figure 82. LSAMP Offset Diagnostic measurement, the ADC is automatically set to bipolar mode. The signal path for this diagnostic is shown in Figure 83. acquisition timing sections for details on insertion into the scan and timing.

comparator threshold settings.

12 BIT DAC0x3FF

Figure 85. DAC 1/4- and 3/4-Scale Diagnostic to the ADC and then compared against the following bounds. The 14-bit ADC measurement bounds for passing this diagnostic ranges from 0x2F06 to 0x30A4. with the comparator threshold settings.

Balancing switch shorted (SCANCFG[2:0] = 0b100)
Balancing switch open (SCANCFG[2:0] = 0b101)
Odd sense wire open (SCANCFG[2:0] = 0b110)
Even sense wire open (SCANCFG[2:0] = 0b111) Enabling any of these modes automatically configures several of acquisition settings (e.g., enables the ALTMUX measurement path). The host must initiate the acquisition, but the diagnostic mode automatically compares the measurements to the specific thresholds as configured through BALSHRTTHR, BALLOWTHR, or BALHIGHTHR threshold registers and sets any corresponding alerts in ALRTBALSW register field. The host presets the thresholds as determined by the minimum and maximum resistance of the switch (RSW) specified in the Electrical Characteristics table and the intended cell-balancing current. The Balance Switch Fault Alert register (ALRTBALSW[13:0]) is cleared at the start of a new scan request if balancing switch diagnostic mode is requested (SCANCFG = 0b100, 0b101, 0b110, or 0b111). The result from the current balancing switch diagnostic is written to ALRTBALSW[13:0] at the end of the scan (SCANDONE = 1). The previous result will persist in ALRTBALSW until a new scan is requested with the balancing switch diagnostic mode enabled.

Table 69. BALSW Diagnostic is enabled. ALRTBALSWSUM is a bitwise logical OR of ALRTBALSW[13:0]. for all the four BALSW diagnostic SCAN requests. are resolved by a subsequent scan or by writing to logic 0. these are only applicable during normal cell measurements. voltage) is less than the voltage between Cn and Cn-1 (cell voltage).

Disables the balancing switches automatically
Configures the acquisition using ALTMUX path automatically
Host initiates the acquisition on selected unipolar cells only (~POLARITYn and CELLENn)
Compares the measurement to the threshold value BALSHRTTHR automatically (for unipolar cells only; i.e., POLARITYn = 0, see Table 70)
If outside the threshold, sets the corresponding flag in ALRTBALSW automatically For the best sensitivity to leakage current, set the threshold value based on the minimum cell voltage minus a small noise margin (100mV), then update the threshold value periodically or every time a measurement is taken depending on how fast the cell voltages are expected to change. The BALSW short decision is as shown in Table 70.

Table 70. BALSW Short Diagnostics Operation An example of a BALSW short is shown below in Figure 86.

Figure 86. Balancing Switch Short The BALSW short diagnostic procedural flow chart is shown in Figure 87.

Figure 87. BALSW Short Diagnostic Chart Table 71. BALSW Short Diagnostic Auto-Configuration

Configures acquisition for bipolar mode (for measuring voltages near zero) automatically
Configures acquisition for ALTMUX path automatically
Configures acquisition to measure switch voltages for those switches enabled by BALSWENn automatically on all unipolar cell positions (~POLARITYn and BALSWENn). Note: It is NOT necessary for the device to be in an active manual cell-balancing operation, only that BALSWEN be configured as desired.
Host initiates acquisition
Compares each measurement to the threshold value BALLOWTHR and BALHIGHTHR automatically; see Table 72
If outside the threshold, sets the corresponding flag in ALRTBALSW automatically Set the thresholds by taking into account the minimum and maximum RSW of the switch itself as specified in the Electrical Characteristics table and the balancing current for the application. The BALSW open diagnostics operation decision is as shown in Table 72.

Table 72. BALSW Open Diagnostic Operation The BALSW open diagnostic procedural flow chart is shown in Figure 88.

Figure 88. BALSW Open Diagnostic Table 73. BALSW Open Diagnostic Auto-Configuration

Configures acquisition for bipolar mode (for measuring voltages near zero) automatically
Closes nonadjacent switches (even or odd automatically)
Configures acquisition to use ALTMUX path automatically
Host waits 100μs for settling and then initiates the acquisition
Compares the result to the BALHIGHTHR and BALLOWTHR registers automatically
If outside thresholds, sets flags in ALRTBALSW automatically Examples of normal and faulty operation are shown in Figure 90 through Figure 94 for examples with and without bus bars (identified by POLARITYn = 1). By examining the combined reported results from even and odd runs, the location and type of fault can be determined. Figure 89 shows the procedure performed by the ADES1754/ADES1755/ADES1756 during an Open Sense-Wire Diagnostic. SET SCANCFG ADES1754/55/56 FULLY FUNCTIONAL AND INITIALIZED ENSURE BALLOWTHR AND BALHIGHTHR SET TO DESIRED VALUE 0B110 FOR ODD SWITCHES 0B111 FOR EVEN SWITCHES START ADC MEASUREMENT SCANDONE = 1? NO YES BALSW CONDUCTING CHECK INVALID CLEAR SCANCFG AND SCANDONE BALSW CELL SENSE CHECK DONE CHECK ALRTBALSW OR CELLn REGISTERS FOR DETAILED RESULT ALRTFMEA1 DATACHECK BIT SHOWS RESULT WAIT 100µs

Figure 89. Sense-Wire Open Diagnostic Flow

sense-wire fault can be determined. Table 75. Odd Sense-Wire Open Measurement Results for Broken Sense-Wires

0 NM NM NM NM NM NM NM NM NM NM NM NM NM NM NM

1 OK OK OK OK OK OK OK OK OK OK LO LO OK OK OK

2 NM NM NM NM NM NM NM NM NM NM NM NM NM NM NM

3 OK OK OK OK OK OK OK OK OK OK OK OK LO LO OK

4 NM NM NM NM NM NM NM NM NM NM NM NM NM NM NM

sense-wire fault can be determined. Table 76. Even Sense-Wire Open Measurement Results for Broken Sense-Wires

0 OK OK OK OK OK OK OK OK OK LO LO OK OK OK OK

1 NM NM NM NM NM NM NM NM NM NM NM NM NM NM NM

2 OK OK OK OK OK OK OK OK OK OK OK LO LO OK OK

3 NM NM NM NM NM NM NM NM NM NM NM NM NM NM NM

4 OK OK OK OK OK OK OK OK OK OK OK OK OK LO LO

diagnostic results are shown in Table 77. Table 77. Odd and Even Sense-Wire Open Measurement Results Overlay for Broken Odd and Even Sense-Wire Open Diagnostics. is a fault in an internal switch or connection. The alerts that will be issued as a result of the fault are also shown.

Figure 94. Cell Sense-Wire Open Diagnostic Operations - Example with Broken BALSW or Internal Trace When combined together, the two diagnostics can cover and identify the exact location of a faulty switch or internal trace. ALRTBALSW alert is issued for faults of this type. Table 78. Odd and Even Sense-Wire Open Measurement Results Overlay for Broken

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 146 ADC End of Scan Diagnostics This diagnostic is performed at the end of a measurement sequence that is configured to use the ADC (SCANCFG = 0b000 or 0b001) when ADCZSFSEN = 1. The ADC measurements are taken in bipolar mode. For full-scale diagnostic: ADCREF = VREF and ADCIN = VAA If the result from the ADC is less than FFFh (12-bit result), an alert is issued by setting the ALRTADCFS bit in the FMEA2 register. For zero-scale diagnostic: ADCREF = VREF and ADCIN = -VAA If the result from the ADC is greater than 000h, an alert is is sued by setting the ALRTADCZS bit in the FMEA2 register. The DIAGSEL1 and DIAGSEL2 registers can be configured to obtain further diagnostic information regarding the ADC. Applications Information Battery-Management Systems Daisy-Chain System A daisy-chain system employs a communication link between the host microcontroller and all of the battery modules. The daisy-chain method reduces overall system cost as it requires only a single microcontroller, CAN PHY, and transformers between the lowest module and the host whereas all components would require redundant implementation in a non-daisy chain (distributed CAN system). See the Distributed CAN Systems section for further information regarding its implementation.

Figure 95. Daisy-Chain System

architecture, although realizable, yields increased system cost. Figure 96. Distributed System

a high noise rejection ratio (PSRR) for the internal low-voltage regulator. the filter capacitor maintains power the device through the transient. application can tolerate the induced error, the supply wires can serve as the sense-wires to reduce the wire count. Figure 97. Power Supply Connection with less than 14 cells to mask out any false alerts corresponding to the unused channels. well as distributed daisy-chain systems which employ unequal module sizes within a standard battery pack. module. See the Flexible Battery-Pack Configuration section for further details on implementation. BOM cost reduction as well as eliminating system cost and constraints for calibration.

switches can be used to switch the external transistors and the power is limited by external current-limiting resistors. Figure 98. External Balancing FET

Table 79. FET-Balancing Components current is limited by RBALANCE. The various external cell-balancing summary components are as shown in Table 80. Figure 99. External Cell-Balancing BJT

Table 80. BJT Balancing Components A short-circuit fault in the external balancing path results in continuous current flow through R BALANCE and QBALANCE. resistor may added for this purpose. shown in Figure 100. ESD protection is shown in Figure 102 and Figure 103.

Figure 100. UART Connection mode may be preferred for ports driving inductive loads to minimize ringing.

The AC-coupled differential communication architecture has a ±30V common -mode range and +6V differenti al swing. This range is in addition to the static common -mode voltage across the AC -coupling capacitors between modules. mode noise is present, such as between the vehicle chassis and high-voltage battery pack terminals. daisy-chains that employ capacitor isolation. the primary and secondary are shunted to ground to make a very effective common-mode noise filter. Figure 105. UART Transformer Isolation

The daisy-chain may use optical isolation instead of transformer or capacitor isolation, as shown in Figure 106. Figure 106. UART Optical Isolation UART daisy chain, optical isolation is used as shown in Figure 107.

Figure 107. Single-Ended Alert Interface with UART

Figure 108. Device Initialization Sequence

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 160 without errors. Using the Data -Check and PEC bytes, complete transaction integrity for READALL and READDE VICE command packets can be verified. PEC Errors If the ADES1754/ADES1755/ADES1756 receives an invalid PEC byte, the corresponding ALRTPECUP, or ALRTPECDN bit in the STATUS2 register, and the summary ALRTPEC bit in the STATUS1 register are set. All sin gle-UART configurations will set ALRTPECUP bit, since the Up Path is used for received transactions. In a dual-UART configuration, a PEC error in the Up Path will set ALRTPECUP, and a PEC error in the DOWN path will set the ALRTPECDN. The ADES1754/ADES1755/ADES1756 does not execute/accept any written command unless the received PEC byte matches the calculated CRC remainder, confirming the validity of the received command and data stream. To confirm the command was accepted, the host should perform an appropriate read transaction to verify the contents of the written register(s). PEC Calculations When directly communicating with the ADES1754/ADES1755/ADES1756 through the UART interface, the host must compute and send the PEC byte protecting the data sent to the device. Likewise, for returned read packets, the host should store the received data, perform the CRC calculation, and compare the results to the received PEC byte provided by the ADES1754/ADES1755/ADES1756 before accepting the data received as valid. To support PEC byte computation and checking, the host must implement a CRC-8 (8-bit cyclic redundancy check) encoding and decoding algorithm based on the following polynomial (0xA6): P(x) = x8 + x6 + x3 + x2 + 1 This polynomial is capable of protecti ng a data stream of up to 247 bits with an HD of 3, meaning that any data stream 247 bits or less in length with any combination of 3 bits of error or less is guaranteed to be identified. If more than 3 bit s of error are encountered, the PEC operation will very likely identify the problem, though this cannot be mathematically guaranteed. A hardware implementation of the CRC calculation is shown in Figure 109 . The CRC engine shown is implemented internally within the ADES1754/ADES1755/ADES1756; a similar implementation would be required in the host to support direct UART communication, for purposes of generating the PEC bytes sent to the ADES1754/ADES1755/ADES1756 or for checking PEC bytes received from the ADES1754/ADES1755/ADES1756. The incoming UART data stream is fed into the CRC engine, LSB first. Once the data stream has been completely shifted into the engine, the CRC remainder is known; this becomes the PEC byte for both incoming and outgoing data, PEC[7:0] = BIT[7:0] as shown—be sure to note the ordering of the bits within the remainder. Note that all UART transactions supply the command and data stream LSB first. For incoming UART data streams, the AD ES1754/ADES1755/ADES1756 will first clear the CRC engine and then input the incoming data stream into the the CRC engine, LSB first. After the final bit of data is processed (in this case, the MSB of the incoming data stream is applied to the engine), the engine is stopped and the CRC remainder is known. The incoming PEC byte, as calculated by the host using its copy of the CRC engine, then follows within the UART transaction (also LSB first) and is internally compared against the CRC remainder as calculate d by the ADES1754/ADES1755/ADES1756. If the PEC byte received matches the CRC remainder calculated for the incoming data stream, the PEC operation is successful, and the transaction is accepted and executed by the ADES1754/ADES1755/ADES1756. If there is a mismatch, the ADES1754/ADES1755/ADES1756 will reject the transaction and issue the ALRTPEC status bit, notifying the host of the issue, so the transaction can be resent. For outgoing UART data streams, the ADES1754/ADES1755/ADES1756 will first clear the CRC engine and then provide the outgoing data stream to the the CRC engine, LSB first. After the final bit of data is processed (in this case, the MSB of the outgoing data stream is applied to the engine), th e engine is stopped and the CRC remainder is known —this becomes the outgoing PEC byte. The outgoing PEC byte, as calculated by the ADES1754/ADES1755/ADES1756 using its copy of the CRC engine, then follows within the UART transaction (also LSB first). As the host receives the data stream from the ADES1754/ADES1755/ADES1756, it should apply the data to its copy of the CRC engine (LSB first, in the order it arrives in the UART transaction, until the MSB of the data stream is applied to the engine). At this poi nt, there are two equivalent ways the host can complete the PEC operation to establish the validity of the received data:

Direct Comparison Method: The host stops the CRC engine once the data stream MSB is applied and compares the resulting CRC remainder to the PEC byte supplied by the ADES1754/ADES1755/ADES1756 (again, LSB first). If the 2 bytes match, the data is accepted as valid, otherwise it should be rejected. This is the method employed by the ADES1754/ADES1755/ADES1756 internally, as described above.

Zero Remainder Method: The host continues CRC engine computations after the data MSB is applied by appending the received PEC byte to the end of the data stream, LSB first (i.e., in the order received during the UART transaction). Once the MSB of the PEC byte arrives at the input of the CRC engine, if the resulting CRC remainder = 00h, the data is accepted as valid, otherwise it should be rejected. BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 INPUT DATA BITSTREAM (LSB FIRST) BIT 1BIT 0

Figure 109. PEC CRC Calculation packets, the CRC value of a partial calculation may be used as the initial value for a subsequent runtime calculation. // function in case a partial ByteList calculation is needed.

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 162 // coefficient. This is a right shift for data stored LSb to the right // and POLY having high order coefficients stored to the right. // Determine if LSb = 1 prior to right shift If CRCByte[1] = 1 Then // When LSb = 1, right shift and XOR CRCByte value with 8 LSbs // of the polynomial coefficient constant. “/ 2” must be a true right // shift in the target CPU to avoid rounding problems. CRCByte = ((CRCByte / 2) XOR POLY) Else //When LSb = 0, right shift by 1 bit. “/ 2” must be a true right // shift in the target CPU to avoid rounding problems. CRCByte = (CRCByte / 2) End If //Truncate the CRC value to 8 bits if necessary CRCByte = CRCByte AND 8'hFF //Proceed to the next bit Next BitCounter ) //Operate on the next data byte in the ByteList Next ByteCounter // All calculations done; CRCByte value is the CRC byte for ByteList() and // the initial CRCByte value Return CRCByte ROMCRC Calculation For safety purposes, the factory-trimmed ROM (OTP) content can be read back by the user and checked for errors using an 8-bit CRC. ROMCRC is an 8 -bit CRC remainder computed using the ID/OTP content and stored in OTP12[15:8] at the factory. Both the ID and OTP output data c ontent (excluding OTP12[15:8], which is ROMCRC[7:0]) protected by the ROMCRC operation. To support ROMCRC computation and checking, the host must implement a CRC -8 encoding and decoding algorithm based on the following polynomial (0xA6): P(x) = x8 + x6 + x3 + x2 + 1 This polynomial is capable of protecting the 200-bit ID/OTP content with a HD of 3, meaning any combination of 3 bits of error or less is guaranteed to be identified. If more than 3 bits of error are encountered, the ROMCRC operation will very likely identify the problem, though this cannot be mathematically guaranteed. A hardware implementation of the CRC calculation is shown in Figure 110. The CRC engine shown would be implemented within the host. The same engine is used in the production trim software to compute and store the ROMCRC byte at the factory, using the computation method outlined below. Be sure to note the ordering of the bits within the remainder, as shown in the figure (i.e., BIT[7:0] = ROMCRC [7:0]). Note this is also the same CRC engine used for PEC byte CRC operations in UART mode. To complete the ROMCRC operation, the host would first clear the CRC engine and then apply the entire 200-bit content of the ID/OTP data received from the ADES1754/ADES1755/ADES1756 concatenated in the following order: ID1[0:15], OTP10[0:15], OTP11[0:15], OTP12[0:7]. Note this is essentially the entire ID/OTP content provided LSB first - ID1[0] is the first bit applied to the CRC Engine and OTP12[7] is the last, and all 200 bits must be applied. At this point, there are two equivalent ways the host can complete the ROMCRC operation to establish the validity of the received ID/OTP data:

Direct Comparison Method: The host stops the CRC engine once the ID/OTP MSB is applied and compares the resulting CRC remainder to the ROMCRC byte supplied by the ADES1754/ADES1755/ADES1756 as ROMCRC[7:0]

ADES1754/ADES1755/ADES1756 ROM.

Zero Remainder Method: The host continues CRC engine computations after the data stream is applied by appending the received ROMCRC byte to the end of the data stream, LSB first (i.e., continuing the concatenation pattern shown above with OTP12[8:15], with OTP12[15] now being the last bit applied). Once the MSB of the ROMCRC byte arrives at the input of the CRC engine, if the resulting CRC remainder = 00h, the data is accepted as valid, otherwise it should be rejected and retried in case of a communication fault. If the failure persists, this may indicate a problem within the ADES1754/ADES1755/ADES1756 ROM. BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 INPUT DATA BITSTREAM (LSB FIRST) BIT 1BIT 0

Figure 110. ROMCRC Calculation measurement accuracy is unaffected. should be chosen such that the forward voltage is <0.7V at the SW pin current rating at +25°C. the external network is required.

Figure 111. Bus-Bar Application Circuit Less Than Continuous Current Injection

Figure 112. Bus-Bar Application Circuit Greater Than Continuous Current Injection

BASED ON FINAL A PPLICATION REQUIREME NTS. Figure 113. Simplified Application Diagram with Single-Ended Alert Interface

BASED ON FINAL A PPLICATION REQUIREME NTS. Figure 114. Simplified Application Diagram with Differential Alert Interface

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 168 PCB Layout Recommendations Careful PCB layout is critical to achieving the best accuracy performance and robust performance against environmental conditions. An example circuit and layout can be found in the EV kit data sheet. Layout Procedure

Place the charge pump capacitor close to the CPP and CPN pins and on the same layer as the ADES1754/ADES1755/ ADES1756. Care should be taken to avoid using vias to prevent unwanted coupling into adjacent signals and planes.
Place the decoupling capacitors on the V DCIN, VAA, and VDDL1 close to the respective pins and on the same layer as the ADES1754/ADES1755/ADES1756. VDDL2 and VDDL3 should be placed close to the pins and are preferred on the same layer, if possible. All capacitors should not share a ground return and each should via directly to the AGND internal layer.
AGND, GNDL1, GNDL2, GNDL3, and AUXGND should via directly to a solid AGND plane placed under the ADES1754/ADES1755/ADES1756. Traces and vias should not be shared within before they enter the AGND plane.
The DCIN input resistor must be sized depending on b oth device current consumption (I DCIN) and board current consumption (IVAA_LOAD) to prevent false ALRTHVHDRM alerts. Adjustment of the DCIN resistor due to external loading should follow this equation: RDCIN_LOAD = RDCIN_NOM x (1 - IDCIN/IVAA_LOAD). Note: In flexible-pack operation, the DCIN filter resistor is omitted.
The SHDNL capacitor and associated trace routing should be kept away and shielded from potential noise sources and digital signals such as those present with the communication or alert inter faces, as these may effect the voltage seen by the SHDNL pin.
Cn traces are recommended to be routed on the same layer as the ADES1754/ADES1755/ADES1756 to avoid the potential sources for noise injection into the primary measurement path. These traces car ry a negligible current and can be kept at a minimum trace widths.
SWn traces should be optimized for width in the permissible layout (20mil recommended) to eliminate excessive voltage drop due to the balancing operation.
UART Rx and Tx ports should be routed for an 100Ω differential impedance. If the ADES1754/ADES1755/ADES1756 is used in a distributed BMS system, ESD protection is recommended to be placed as close as possible to the UART communication connector with the ground return via'd directly to th e AGND plane to clamp transient events before they can couple to other nodes that may affect device performance. For centralized BMS systems, ESD components on the UART may be omitted. Register Map ADES1754/ADES1755/ADES1756 User Register Map Register Map Usage Guidelines The Register Map (RMap) for the ADES1754/ADES1755/ADES1756 is detailed in the following section. General usage guidelines pertaining to the entire RMap are outlined here, detailing the expected usage of the RMap, including how various protocol and access issues are handled. Interface Protocol Errors In order for read and write transactions to be accepted, all interface protocol expectations must be met. If protocol errors occur, these will be reported through alerts in the STATUS1 and STATUS2 registers, notifying the user of the issue observed. If a protocol error occurs, none of the following behaviors will apply, because the transaction will be rejected, even if the transaction addresses a reserved register address. See the UART interface descriptions for complete details on expected interface protocols. Reserved Registers All user-accessible registers are contained in the address space 0x00 to 0x98. Any address/register in this space not

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 169 specifically listed in the RMap should be treated as Reserved; for the ADES1754/ADES1755/ADES1756, the following addresses within the user address space are reserved: 0x2C, 0x2D, 0x2E, 0x2F, and 0x46. The address space 0x99 to 0xFF is also Reserved for Analog Devices Use Only. If an otherwise valid attempt to read or write to a reserved register address occurs (with no protocol or CRC/PEC errors), no errors will be issued for the UART transaction. No data written to a reserved register address will be internally stored, and reserved register will always read back all zeros. If a UART Block Readback request includes any reserved register addresses, these addresses will be included in the readback data, with all zeros returned; no addresses will be skipped during UART Block Readback transactions. Users should normally avoid writing to reserved register, as the ADES1754/ADES1755/ADES1756 will not respond to such transactions. Unused Bitfields Within the user-accessible registers, there are many unused bitfields, denoted by a dash (-) in the RMap. During read and write transactions, PEC and CRC checks apply to all 16 bits of data, including any unused bitfields. No data written to an unused bitfield is internally stored, and unused bitfields always read back all zeros. Reserved Bitfields Within the RMap, there are several reserved bitfields: DEVCFG1RSRV (4 bits), DEVCFG2RSRV (5 bits); these are reserved for future use. During read and write transactions, PEC and CRC checks apply to all 16 bits of data, including any reserved bitfields. Data written to a reserved bitfield are internally stored (though the settings of these bitfields will have no effect on internal operations), and the reserved bitfields always read back their current settings. Register Blocks and Transaction Reject Behavior The RMap is organized into several register blocks. Each register block is subject to specific transaction rejection behaviors as detailed in the register block descriptions which follow. These behaviors ensure that register content currently in use by any requested internal process is not subject to alteration while in use. In general, the register blocks are organized and defined to provide maximum transaction efficiency while also ensuring the ultimate level of safety. If a valid write transaction to a blocked (busy) register occurs, the transaction will be rejected, and the ALRTRJCT bit will be set, indicating the write was ignored since that register was currently being used by an ongoing internal operation. In general, user software should be written to avoid modifying register content that is currently in use, instead confirming that the internal process has completed before any modifications are written to the ADES1754/ADES1755/ADES1756. ADD RESS NAME MSB LSB STATUS REGISTERS 0x00 VERSION[15:8] MOD[11:4] VERSION[7:0] MOD[3:0] VER[3:0] 0x01 ADDRESS[15:8] ADDRUNL OCK BA[4:0] TA[4:3] ADDRESS[7:0] TA[2:0] DA[4:0] 0x02 STATUS1[15:8] ALRTSCAN ALRTRST ALRTMSMT CH ALRTCELL OVST ALRTCELL UVST ALRTBLKOV ST ALRTBLKU VST ALRTAUXO VST STATUS1[7:0] ALRTAUXU VST – ALRTPEC ALRTINTRF C ALRTCAL ALRTCBAL ALRTFMEA ALRTFMEA

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 170 ADD RESS NAME MSB LSB 0x03 STATUS2[15:8] ALRTPECU P ALRTPECD N ALRTMANU P ALRTMAND N ALRTPARU P ALRTPARDN ALRTDUAL UART – STATUS2[7:0] ALRTSPI ALRTSCLK ERR ALRTOSC3 ALRTINTBU S – ALRTI2C – ALRTRJCT 0x04 STATUS3[15:8] ALRTCBTI MEOUT ALRTCBTE MP ALRTCBCA L ALRTCBNT FY ALRTCBDO NE – – – 0x05 FMEA1[15:8] ALRTOSC1 ALRTOSC2 ALRTCOMM SEU1 ALRTCOMM SEL1 ALRTCOM MSEU2 ALRTCOMM SEL2 ALRTVDDL

3 ALRTVDDL2

FMEA1[7:0] ALRTVDDL ALRTGNDL ALRTGNDL ALRTGNDL

1 ALRTHVUV ALRTHVHDR

FMEA2[15:8] ALRTUSER ALRTDCIN MUX ALRTAUXP RTCTSUM ALRTTEMP ALRTSCAN TIMEOUT – – – FMEA2[7:0] – – – – ALRTADCZ S ALRTADCFS ALRTCOM PACCOV ALRTCOMP ACCUV 0x07 ALRTSUM[15:8] ALRTADC OVST ALRTCOM POVST ALRTADCU VST ALRTCOMP UVST ALRTADCA UXOVST ALRTCOMPA UXOVST ALRTADCA UXUVST ALRTCOMP AUXUVST ALRTSUM[7:0] – – – ALRTCALO SADC ALRTCALO SR ALRTCALOS THRM ALRTCALG AINP ALRTCALG AINR 0x08 ALRTOVCELL[15 :8] – – ALRTOV[14:9] ALRTOVCELL[7: ALRTOV[8:1] 0x09 ALRTUVCELL[15 :8] – – ALRTUV[14:9] ALRTUVCELL[7: ALRTUV[8:1] 0x0A MINMAXCELL[15 :8] – – – – MAXCELL[3:0] MINMAXCELL[7: – – – – MINCELL[3:0] 0x0B ALRTAUXPRTCT REG[15:8]

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 171 ADD RESS NAME MSB LSB ALRTAUXPRTCT REG[7:0] – – ALRTAUXPRTCT[5:4] ALRTAUXPRTCT[3:0] 0x0C ALRTAUXOVRE G[15:8] ALRTAUXOVRE G[7:0] – – ALRTAUXOV[5:4] ALRTAUXOV[3:0] 0x0D ALRTAUXUVRE G[15:8] ALRTAUXUVRE G[7:0] – – ALRTAUXUV[5:4] ALRTAUXUV[3:0] 0x0E ALRTCOMPOVR EG[15:8] – – ALRTCOMPOV[14:9] ALRTCOMPOVR EG[7:0] ALRTCOMPOV[8:1] 0x0F ALRTCOMPUVR EG[15:8] – – ALRTCOMPUV[14:9] ALRTCOMPUVR EG[7:0] ALRTCOMPUV[8:1] 0x10 ALRTCOMPAUX OVREG[15:8] ALRTCOMPAUX OVREG[7:0] – – ALRTCOMPAUXOV[5:4] ALRTCOMPAUXOV[3:0] 0x11 ALRTCOMPAUX UVREG[15:8] ALRTCOMPAUX UVREG[7:0] – – ALRTCOMPAUXUV[5:4] ALRTCOMPAUXUV[3:0] 0x12 ALRTBALSWRE G[15:8] – – ALRTBALSW[13:8] ALRTBALSWRE G[7:0] ALRTBALSW[7:0] 0x13 GENERAL CONFIGURATION REGISTERS

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 172 ADD RESS NAME MSB LSB 0x14 DEVCFG1[15:8] UARTCFG[1:0] TXUIDLEHI Z TXLIDLEHIZ DEVCFG1RSRV[1:0] ALIVECNT EN UARTHOST DEVCFG1[7:0] DEVCFG 1RSRV DEVCFG 1RSRV DEVCFG 1RSRV DEVCFG 1RSRV UARTDCEN NOPEC ALERTEN DBLBUFEN 0x15 DEVCFG2[15:8] IIRFC[2:0] – – – – – DEVCFG2[7:0] – HVCPDIS FORCEPOR ALERTDCT STEN – DEVCFG2 RSRV SCANTODI S CBTODIS 0x16 AUXGPIOCFG[1 5:8] I2CEN – GPIOEN[5:4] GPIOEN[3:0] AUXGPIOCFG[7: – – GPIODIR[5:4] GPIODIR[3:0] 0x17 GPIOCFG[15:8] – – GPIODRV[5:4] GPIODRV[3:0] GPIOCFG[7:0] – – GPIORD[5:4] GPIORD[3:0] 0x18 PACKCFG[15:8] FLXPCKEN FLXPCKEN FLXPCKSC AN – TOPBLOCK[3:0] PACKCFG[7:0] TOPCELL2[3:0] TOPCELL1[3:0] ALERT CONFIGURATION REGISTERS 0x19 ALRTIRQEN[15:8 SCANALRT EN – MSMTCHAL RTEN CELLOVST ALRTEN CELLUVST ALRTEN BLKOVSTAL RTEN BLKUVSTA LRTEN AUXOVSTA LRTEN ALRTIRQEN[7:0] AUXUVSTA LRTEN – PECALRTE N INTRFCALR TEN CALALRTE N CBALALRTE N FMEA2ALR TEN FMEA1ALR TEN 0x1A ALRTOVEN[15:8] – BLKOVALR TEN OVALRTEN[14:9] ALRTOVEN[7:0] OVALRTEN[8:1] 0x1B ALRTUVEN[15:8] – BLKUVALR TEN UVALRTEN[14:9] ALRTUVEN[7:0] UVALRTEN[8:1] 0x1C ALRTAUXOVEN[ 15:8] ALRTAUXOVEN[ 7:0] – – AUXOVALRTEN[5:4] AUXOVALRTEN[3:0]

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 173 ADD RESS NAME MSB LSB 0x1D ALRTAUXUVEN[ 15:8] ALRTAUXUVEN[ 7:0] – – AUXUVALRTEN[5:4] AUXUVALRTEN[3:0] 0x1E ALRTCALTST[15 :8] ALRTCALTST[7: – – – CALOSADC ALRTFRC CALOSRAL RTFRC CALOSTHR MALRTFRC CALGAINP ALRTFRC CALGAINRA LRTFRC THRESHOLD REGISTERS 0x1F OVTHCLRREG[1 5:8] OVTHCLR[13:6] OVTHCLRREG[7 :0] OVTHCLR[5:0] – – 0x20 OVTHSETREG[1 5:8] OVTHSET[13:6] OVTHSETREG[7 :0] OVTHSET[5:0] – – 0x21 UVTHCLRREG[1 5:8] UVTHCLR[13:6] UVTHCLRREG[7 :0] UVTHCLR[5:0] – – 0x22 UVTHSETREG[1 5:8] UVTHSET[13:6] UVTHSETREG[7: UVTHSET[5:0] – – 0x23 MSMTCHREG[15 :8] MSMTCH[13:6] MSMTCHREG[7: MSMTCH[5:0] – – 0x24 BIPOVTHCLRRE G[15:8] BIPOVTHCLR[13:6] BIPOVTHCLRRE G[7:0] BIPOVTHCLR[5:0] – –

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 174 ADD RESS NAME MSB LSB 0x25 BIPOVTHSETRE G[15:8] BIPOVTHSET[13:6] BIPOVTHSETRE G[7:0] BIPOVTHSET[5:0] – – 0x26 BIPUVTHCLRRE G[15:8] BIPUVTHCLR[13:6] BIPUVTHCLRRE G[7:0] BIPUVTHCLR[5:0] – – 0x27 BIPUVTHSETRE G[15:8] BIPUVTHSET[13:6] BIPUVTHSETRE G[7:0] BIPUVTHSET[5:0] – – 0x28 BLKOVTHCLRR EG[15:8] BLKOVTHCLR[13:6] BLKOVTHCLRR EG[7:0] BLKOVTHCLR[5:0] – – 0x29 BLKOVTHSETR EG[15:8] BLKOVTHSET[13:6] BLKOVTHSETR EG[7:0] BLKOVTHSET[5:0] – – 0x2A BLKUVTHCLRR EG[15:8] BLKUVTHCLR[13:6] BLKUVTHCLRR EG[7:0] BLKUVTHCLR[5:0] – – 0x2B BLKUVTHSETRE G[15:8] BLKUVTHSET[13:6] BLKUVTHSETRE G[7:0] BLKUVTHSET[5:0] – – 0x30 AUXROVTHCLR REG[15:8] AUXROVTHCLR[13:6] AUXROVTHCLR REG[7:0] AUXROVTHCLR[5:0] – – 0x31 AUXROVTHSET REG[15:8] AUXROVTHSET[13:6]

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 175 ADD RESS NAME MSB LSB AUXROVTHSET REG[7:0] AUXROVTHSET[5:0] – – 0x32 AUXRUVTHCLR REG[15:8] AUXRUVTHCLR[13:6] AUXRUVTHCLR REG[7:0] AUXRUVTHCLR[5:0] – – 0x33 AUXRUVTHSET REG[15:8] AUXRUVTHSET[13:6] AUXRUVTHSET REG[7:0] AUXRUVTHSET[5:0] – – 0x34 AUXAOVTHCLR REG[15:8] AUXAOVTHCLR[13:6] AUXAOVTHCLR REG[7:0] AUXAOVTHCLR[5:0] – – 0x35 AUXAOVTHSET REG[15:8] AUXAOVTHSET[13:6] AUXAOVTHSET REG[7:0] AUXAOVTHSET[5:0] – – 0x36 AUXAUVTHCLR REG[15:8] AUXAUVTHCLR[13:6] AUXAUVTHCLR REG[7:0] AUXAUVTHCLR[5:0] – – 0x37 AUXAUVTHSET REG[15:8] AUXAUVTHSET[13:6] AUXAUVTHSET REG[7:0] AUXAUVTHSET[5:0] – – 0x38 COMPOVTHREG [15:8] COMPOVTH[11:4] COMPOVTHREG [7:0] COMPOVTH[3:0] – – – – 0x39 COMPUVTHREG [15:8] COMPUVTH[11:4] COMPUVTHREG [7:0] COMPUVTH[3:0] – – – –

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 176 ADD RESS NAME MSB LSB 0x3A COMPAUXROVT HREG[15:8] COMPAUXROVTH[11:4] COMPAUXROVT HREG[7:0] COMPAUXROVTH[3:0] – – – – 0x3B COMPAUXRUVT HREG[15:8] COMPAUXRUVTH[11:4] COMPAUXRUVT HREG[7:0] COMPAUXRUVTH[3:0] – – – – 0x3C COMPAUXAOVT HREG[15:8] COMPAUXAOVTH[11:4] COMPAUXAOVT HREG[7:0] COMPAUXAOVTH[3:0] – – – – 0x3D COMPAUXAUVT HREG[15:8] COMPAUXAUVTH[11:4] COMPAUXAUVT HREG[7:0] COMPAUXAUVTH[3:0] – – – – DIAGNOSTIC THRESHOLD REGISTERS 0x3E COMPOPNTHRE G[15:8] COMPOPNTH[11:4] COMPOPNTHRE G[7:0] COMPOPNTH[3:0] – – – – 0x3F COMPAUXROPN THREG[15:8] COMPAUXROPNTH[11:4] COMPAUXROPN THREG[7:0] COMPAUXROPNTH[3:0] – – – – 0x40 COMPAUXAOPN THREG[15:8] COMPAUXAOPNTH[11:4] COMPAUXAOPN THREG[7:0] COMPAUXAOPNTH[3:0] – – – – 0x41 COMPACCOVTH REG[15:8] COMPACCOVTH[11:4] COMPACCOVTH REG[7:0] COMPACCOVTH[3:0] – – – –

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 177 ADD RESS NAME MSB LSB 0x42 COMPACCUVTH REG[15:8] COMPACCUVTH[11:4] COMPACCUVTH REG[7:0] COMPACCUVTH[3:0] – – – – 0x43 BALSHRTTHRR EG[15:8] BALSHRTTHR[13:6] BALSHRTTHRR EG[7:0] BALSHRTTHR[5:0] – – 0x44 BALLOWTHRRE G[15:8] BALLOWTHR[13:6] BALLOWTHRRE G[7:0] BALLOWTHR[5:0] – – 0x45 BALHIGHTHRRE G[15:8] BALHIGHTHR[13:6] BALHIGHTHRRE G[7:0] BALHIGHTHR[5:0] – – CELL DATA REGISTERS 0x47 CELL1REG[15:8] CELL1[13:6] CELL1REG[7:0] CELL1[5:0] – – 0x48 CELL2REG[15:8] CELL2[13:6] CELL2REG[7:0] CELL2[5:0] – – 0x49 CELL3REG[15:8] CELL3[13:6] CELL3REG[7:0] CELL3[5:0] – – 0x4A CELL4REG[15:8] CELL4[13:6] CELL4REG[7:0] CELL4[5:0] – – 0x4B CELL5REG[15:8] CELL5[13:6] CELL5REG[7:0] CELL5[5:0] – – 0x4C CELL6REG[15:8] CELL6[13:6] CELL6REG[7:0] CELL6[5:0] – – 0x4D CELL7REG[15:8] CELL7[13:6]

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 178 ADD RESS NAME MSB LSB CELL7REG[7:0] CELL7[5:0] – – 0x4E CELL8REG[15:8] CELL8[13:6] CELL8REG[7:0] CELL8[5:0] – – 0x4F CELL9REG[15:8] CELL9[13:6] CELL9REG[7:0] CELL9[5:0] – – 0x50 CELL10REG[15: CELL10[13:6] CELL10REG[7:0] CELL10[5:0] – – 0x51 CELL11REG[15: CELL11[13:6] CELL11REG[7:0] CELL11[5:0] – – 0x52 CELL12REG[15: CELL12[13:6] CELL12REG[7:0] CELL12[5:0] – – 0x53 CELL13REG[15: CELL13[13:6] CELL13REG[7:0] CELL13[5:0] – – 0x54 CELL14REG[15: CELL14[13:6] CELL14REG[7:0] CELL14[5:0] – – 0x55 BLOCKREG[15:8 VBLOCK[13:6] BLOCKREG[7:0] VBLOCK[5:0] – – TOTAL DIAG AUX DATA REGISTERS 0x56 TOTALREG[15:8] TOTAL[15:8] TOTALREG[7:0] TOTAL[7:0] 0x57 DIAG1REG[15:8] DIAG1[13:6] DIAG1REG[7:0] DIAG1[5:0] – – 0x58 DIAG2REG[15:8] DIAG2[13:6]

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 179 ADD RESS NAME MSB LSB DIAG2REG[7:0] DIAG2[5:0] – – 0x59 AUX0REG[15:8] AUX0[13:6] AUX0REG[7:0] AUX0[5:0] – – 0x5A AUX1REG[15:8] AUX1[13:6] AUX1REG[7:0] AUX1[5:0] – – 0x5B AUX2REG[15:8] AUX2[13:6] AUX2REG[7:0] AUX2[5:0] – – 0x5C AUX3REG[15:8] AUX3[13:6] AUX3REG[7:0] AUX3[5:0] – – 0x5D AUX4REG[15:8] AUX4[13:6] AUX4REG[7:0] AUX4[5:0] – – 0x5E AUX5REG[15:8] AUX5[13:6] AUX5REG[7:0] AUX5[5:0] – – SCAN SETTINGS REGISTERS 0x5F POLARITYCTRL[ 15:8] MINMAXP OL – POLARITY[14:9] POLARITYCTRL[ 7:0] POLARITY[8:1] 0x60 AUXREFCTRL[1 5:8] AUXREFCTRL[7: – – AUXREFSEL[5:4] AUXREFSEL[3:0] 0x61 AUXTIMEREG[1 5:8] AUXTIMEREG[7: AUXTIME[7:0] 0x62 ACQCFG[15:8] ADCZSFSE N ADCCALE N COMPACCE N FOSR[1:0] THRMMODE[1:0] –

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 180 ADD RESS NAME MSB LSB 0x63 BALSWDLY[15:8] CELLDLY[7:0] BALSWDLY[7:0] SWDLY[7:0] SCAN CONTROL REGISTERS 0x64 MEASUREEN1[1 5:8] – BLOCKEN CELLEN[14:9] MEASUREEN1[7 :0] CELLEN[8:1] 0x65 MEASUREEN2[1 5:8] SCANIIRINI MEASUREEN2[7 :0] – – AUXEN[5:4] AUXEN[3:0] 0x66 SCANCTRL[15:8] SCANDON E SCANTIME OUT DATARDY AUTOBALS WDIS ALRTFILTS EL AMENDFILT RDFILT SCANCFG[2 SCANCTRL[7:0] SCANCFG[1:0] OVSAMPL[2:0] ALTMUXSEL SCANMOD E SCAN DIAGNOSTIC SETTINGS REGISTERS 0x67 ADCTEST1ARE G[15:8] ADCTSTEN – – – ADCTEST1A[11:8] ADCTEST1ARE G[7:0] ADCTEST1A[7:0] 0x68 ADCTEST1BRE G[15:8] – – – – ADCTEST1B[11:8] ADCTEST1BRE G[7:0] ADCTEST1B[7:0] 0x69 ADCTEST2ARE G[15:8] – – – – ADCTEST2A[11:8] ADCTEST2ARE G[7:0] ADCTEST2A[7:0] 0x6A ADCTEST2BRE G[15:8] – – – – ADCTEST2B[11:8] ADCTEST2BRE G[7:0] ADCTEST2B[7:0] DIAGNOSTIC CONTROL REGISTERS

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 181 ADD RESS NAME MSB LSB 0x6B DIAGCFG[15:8] CTSTDAC[3:0] CTSTSRC MUXDIAGBU S MUXDIAGP AIR MUXDIAGE N DIAGCFG[7:0] DIAGSEL2[3:0] DIAGSEL1[3:0] 0x6C CTSTCFG[15:8] CELLOPND IAGSEL CTSTEN[14:8] CTSTCFG[7:0] CTSTEN[7:0] 0x6D AUXTSTCFG[15: AUXTSTCFG[7:0 – – AUXTSTEN[5:4] AUXTSTEN[3:0] 0x6E DIAGGENCFG[1 5:8] AUXDIAGSEL[2:0] – – – – – DIAGGENCFG[7: CELL-BALANCING REGISTERS 0x6F BALSWCTRL[15: CBRESTA RT – BALSWEN[14:9] BALSWCTRL[7:0 BALSWEN[8:1] 0x70 BALEXP1[15:8] – – – – – – CBEXP1[9:8] BALEXP1[7:0] CBEXP1[7:0] 0x71 BALEXP2[15:8] – – – – – – CBEXP2[9:8] BALEXP2[7:0] CBEXP2[7:0] 0x72 BALEXP3[15:8] – – – – – – CBEXP3[9:8] BALEXP3[7:0] CBEXP3[7:0] 0x73 BALEXP4[15:8] – – – – – – CBEXP4[9:8] BALEXP4[7:0] CBEXP4[7:0] 0x74 BALEXP5[15:8] – – – – – – CBEXP5[9:8] BALEXP5[7:0] CBEXP5[7:0] 0x75 BALEXP6[15:8] – – – – – – CBEXP6[9:8]

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 182 ADD RESS NAME MSB LSB BALEXP6[7:0] CBEXP6[7:0] 0x76 BALEXP7[15:8] – – – – – – CBEXP7[9:8] BALEXP7[7:0] CBEXP7[7:0] 0x77 BALEXP8[15:8] – – – – – – CBEXP8[9:8] BALEXP8[7:0] CBEXP8[7:0] 0x78 BALEXP9[15:8] – – – – – – CBEXP9[9:8] BALEXP9[7:0] CBEXP9[7:0] 0x79 BALEXP10[15:8] – – – – – – CBEXP10[9:8] BALEXP10[7:0] CBEXP10[7:0] 0x7A BALEXP11[15:8] – – – – – – CBEXP11[9:8] BALEXP11[7:0] CBEXP11[7:0] 0x7B BALEXP12[15:8] – – – – – – CBEXP12[9:8] BALEXP12[7:0] CBEXP12[7:0] 0x7C BALEXP13[15:8] – – – – – – CBEXP13[9:8] BALEXP13[7:0] CBEXP13[7:0] 0x7D BALEXP14[15:8] – – – – – – CBEXP14[9:8] BALEXP14[7:0] CBEXP14[7:0] 0x7E BALAUTOUVTH R[15:8] CBUVTHR[13:6] BALAUTOUVTH R[7:0] CBUVTHR[5:0] – CBUVMINC ELL 0x7F BALDLYCTRL[15 :8] BALDLYCTRL[7: 0x80 BALCTRL[15:8] CBACTIVE[1:0] CBMODE[2:0] CBIIRINIT HOLDSHDNL[1:0] BALCTRL[7:0] CBDUTY[3:0] CBDONEAL RTEN CBTEMPEN CBMEASEN[1:0]

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 183 ADD RESS NAME MSB LSB 0x81 BALSTAT[15:8] CBACTIVE_M1[1:0] CBUNIT[1:0] CBCNTR[1:0] CBTIMER[9:8] BALSTAT[7:0] CBTIMER[7:0] 0x82 BALUVSTAT[15: CBACTIVE_M2[1:0] CBUVSTAT[14:9] BALUVSTAT[7:0] CBUVSTAT[8:1] 0x83 BALDATA[15:8] CBACTIVE_M3[1:0] DATARDY_ I2C CONTROLLER REGISTERS 0x84 I2CPNTR[15:8] I2CPBYTE1[7:0] I2CPNTR[7:0] I2CPBYTE0[7:0] 0x85 I2CWDATA1[15:8 I2CWBYTE3[7:0] I2CWDATA1[7:0] I2CWBYTE2[7:0] 0x86 I2CWDATA2[15:8 I2CWBYTE1[7:0] I2CWDATA2[7:0] I2CWBYTE0[7:0] 0x87 I2CRDATA1[15:8 I2CRBYTE3[7:0] I2CRDATA1[7:0] I2CRBYTE2[7:0] 0x88 I2CRDATA2[15:8 I2CRBYTE1[7:0] I2CRDATA2[7:0] I2CRBYTE0[7:0] 0x89 I2CCFG[15:8] I2CFSCL I2CWALT I2CRFMT I2C10BIT I2CPNTRLN GTH I2CALRTEN – – I2CCFG[7:0] – – I2CANACO NTEN I2CCONTEN I2CGLITCH EN I2CNOISEEN I2CRDTRE N I2CTOEN 0x8A I2CSTAT[15:8] I2CSTATUS[1:0] – – – – – I2CRJCT I2CSTAT[7:0] I2CDEVNA CK I2CDATAN ACK I2CANACO NT I2CCONT I2CGLITCH I2CNOISE I2CRDTRE RR I2CTIMEOU T

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 184 ADD RESS NAME MSB LSB 0x8B I2CSEND[15:8] I2CPNTRS EL I2CDATALNGTH[1:0] I2CDATASEL[1:0] I2CDEVIDEXT[2:0] I2CSEND[7:0] I2CDEVID[6:0] I2CRWB ROM SUPPORT REGISTERS 0x8C ID1[15:8] DEVID[15:8] ID1[7:0] DEVID[7:0] 0x8D ID2[15:8] DEVID[31:24] ID2[7:0] DEVID[23:16] 0x8E ID3[15:8] OTP2[7:0] ID3[7:0] DEVID[39:32] 0x8F OTP3REG[15:8] OTP3[15:8] OTP3REG[7:0] OTP3[7:0] 0x90 OTP4REG[15:8] OTP4[1:0] ALTREF_OTP[13:8] OTP4REG[7:0] ALTREF_OTP[7:0] 0x91 OTP5REG[15:8] OTP5[15:8] OTP5REG[7:0] OTP5[7:0] 0x92 OTP6REG[15:8] OTP6[15:8] OTP6REG[7:0] OTP6[7:0] 0x93 OTP7REG[15:8] OTP7[15:8] OTP7REG[7:0] OTP7[7:0] 0x94 OTP8REG[15:8] OTP8[15:8] OTP8REG[7:0] OTP8[7:0] 0x95 OTP9REG[15:8] OTP9[15:8] OTP9REG[7:0] OTP9[7:0] 0x96 OTP10REG[15:8] OTP10[15:8] OTP10REG[7:0] OTP10[7:0]

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 185 ADD RESS NAME MSB LSB 0x97 OTP11REG[15:8] OTP11[15:8] OTP11REG[7:0] OTP11[7:0] 0x98 OTP12REG[15:8] ROMCRC[7:0] OTP12REG[7:0] OTP12[7:0] Register Details VERSION (0x0) VERSION is a read-only accessible register that returns information on the device. BIT 15 14 13 12 11 10 9 8 Field MOD[11:4] Reset 0x000 Access Type Read Only BIT 7 6 5 4 3 2 1 0 Field MOD[3:0] VER[3:0] Reset 0x000 0x4 Access Type Read Only Read Only BITFIELD BITS DESCRIPTION MOD 15:4 Device Model Number 0x854 = ADES1754/ADES1755/ADES1756 Read only. VER 3:0 Si Version Current Version = 0x4 Read only. ADDRESS (0x1) ADDRESS is a read- and write-accessible register that sets the first, last, and device address used by a device in a UART chain.

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 186 BIT 15 14 13 12 11 10 9 8 Field ADDRUNLOCK BA[4:0] TA[4:3] Reset 0b1 0b00000 0b00000 Access Type Write, Read, Ext Write, Read, Ext Write, Read, Ext BIT 7 6 5 4 3 2 1 0 Field TA[2:0] DA[4:0] Reset 0b00000 0b00000 Access Type Write, Read, Ext Write, Read, Ext BITFIELD BITS DESCRIPTION ADDRUNLOCK 15 UART Device Address Unlock 0 = Normal Operation (following HELLOALL) 1 = Disable write-protection of device address DA[4:0], allowing re-sends of HELLOALL to reassign device addresses without POR (also POR default). Cleared only by HELLOALL command (writes to 0 are ignored). This bitfield is unaffected in the event of a SWPOR (software POR) request by the host. Note: This bit should normally be written to 0 when populating BA and TA content; it should only be necessary to set this bit if the user believes the original DA content populated by the HELLOALL command is corrupted. BA 14:10 Bottom Device Address in a UART Chain Address of the device at the bottom of the daisy chain. If the host sends an initial address other than 0x00 in the HELLOALL command through the UART Up Path (assign/increment), then the host must write that bottom address (as well as the expected top address) to all devices in the daisy chain with a WRITEALL command to this bitfield. READALL commands and Alert Packets require that BA[4:0], TA[4:0], and DA[4:0] be correct in order for the data-check and PEC features to function as intended. This bitfield is unaffected in the event of a SWPOR (software POR) request by the host. TA 9:5 Top Device Address in a UART Chain Address of the device connected to the top of the daisy chain. If the host sends an initial address in the HELLOALL command through the UART Down Path (assign/decrement), then the host must write that top address (as well as the expected bottom address) to all devices in the daisy chain with a WRITEALL command to this bitfield.

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 187 BITFIELD BITS DESCRIPTION READALL commands and Alert Packets require that BA[4:0], TA[4:0], and DA[4:0] be correct in order for the data-check and PEC features to function as intended. This bitfield is unaffected in the event of a SWPOR (software POR) request by the host. DA 4:0 Device Address Device address written only by the HELLOALL command as it propagates through the daisy chain. If HELLOALL is issued through the UART Up Path, this bitfield is accepted and then automatically incremented by each device. If HELLOALL is issued through the UART Down Path, this bitfield is accepted and then automatically decremented by each device. The host must choose an initial (bottom) address 0x00 or greater and ensure the resulting top address will not exceed the maximum address of 0x1F during the propagation of the HELLOALL command through the Up Path. Likewise, the host must choose an initial (top) address 0x1F or lower and ensure that the resulting bottom address will be 0x00 or greater after propagation of the HELLOALL command through the Down Path. Writing has no effect; only a HELLOALL command executed while ADDRUNLOCK = 1 will update this content. This bitfield is unaffected in the event of a SWPOR (software POR) request by the host. STATUS1 (0x2) STATUS1 is a read- and write-accessible register that relates the current status of the device. STATUS1 also contains summary information on STATUS2, STATUS3, and FMEA registers, and other selected registers indicating if additional readback checks are required. BIT 15 14 13 12 11 10 9 8 Field ALRTSCAN ALRTRS T ALRTMSMTC H ALRTCELLOVS T ALRTCELLUVS T ALRTBLKOVS T ALRTBLKUVS T ALRTAUXOVS T Reset 0b0 0b1 0b0 0b0 0b0 0b0 0b0 0b0 Acces s Type Read Only Write 0 to Clear, Read Read Only Read Only Read Only Read Only Read Only Read Only BIT 7 6 5 4 3 2 1 0 Field ALRTAUXUVS T – ALRTPEC ALRTINTRFC ALRTCAL ALRTCBAL ALRTFMEA2 ALRTFMEA1 Reset 0b0 – 0b0 0b0 0b0 0b0 0b0 0b0

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 188 Acces s Type Read Only – Read Only Read Only Read Only Read Only Read Only Read Only BITFIELD BITS DESCRIPTION ALRTSCAN 15 Scan Done Alert 0 = No Measurement Requested or Measurement in Progress (default) 1 = Measurement Complete Cleared if SCANCRTL:SCANDONE is removed. Read only. ALRTRST 14 Reset Alert Indicates a power-on-reset event occurred. UART users should clear this alert after power-on and after a successful HELLOALL transaction in order to detect future resets. Cleared only by writing to logic 0. Writing to a logic 1 has no effect. ALRTMSMTCH 13 Cell Voltage Mismatch Alert Indicates VMAX - VMIN > VMSMTCH threshold. Read MINMAXCELL for detailed information on which channels are involved to aide diagnosis. Cleared at next acquisition if the condition is false. Read only. ALRTCELLOVST 12 Cell Overvoltage Status Summary Alert Bitwise logical OR of ALRTOV[14:1] and ALRTCOMPOV[14:1]. Read ALRTSUM for information on whether the ADC, comparator, or both circuits detected the fault to aide diagnosis. Cleared on next acquisition, if all enabled overvoltage conditions are resolved. Read only. ALRTCELLUVST 11 Cell Undervoltage Status Summary Alert Bitwise logical OR of ALRTUV[14:1] and ALRTCOMPUV[14:1]. Read ALRTSUM for information on whether the ADC, comparator, or both circuits detected the fault to aide diagnosis. Cleared on next acquisition, if all enabled undervoltage conditions are resolved. Read only.

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 189 BITFIELD BITS DESCRIPTION ALRTBLKOVST 10 Block Overvoltage Status Alert Indicates the latest block voltage measurement exceeded the threshold set by BLKOVTHSET. Cleared on next block voltage acquisition, if condition is resolved. Read only. ALRTBLKUVST 9 Block Undervoltage Status Alert Indicates the latest block voltage measurement was below the threshold set by BLKUVTHSET. Cleared on next block voltage acquisition, if condition is resolved. Read only. ALRTAUXOVST 8 Auxiliary Overvoltage (Cold) Status Summary Alert Logical OR of ALRTAUXOV[5:0] and ALRTCOMPAUXOV[5:0] auxiliary alerts. Read ALRTSUM for information on whether the ADC, comparator, or both circuits detected the fault to aide diagnosis. Cleared on next acquisition, if all enabled overvoltage conditions are resolved. Read only. ALRTAUXUVST 7 Auxiliary Undervoltage (Hot) Status Summary Alert Logical OR of ALRTAUXUV[5:0] and ALRTCOMPAUXUV[5:0] auxiliary alerts. Read ALRTSUM for information on whether the ADC, comparator, or both circuits detected the fault to aide diagnosis. Cleared on next acquisition, if all enabled undervoltage conditions are resolved. Read only. ALRTPEC 5 PEC (CRC) Alert Indicates a received UART character/transaction contained a PEC/CRC error and was ignored as a result. Logical OR of (ALRTPECUP, ALRTPECDN). Cleared if component alerts are resolved in STATUS2:ALRTPECUP/DN, see component bitfield descriptions for details. Read only. ALRTINTRFC 4 Interface Specific Error Alert Indicates that an error specific to the selected interface: UART user interface and/or I2C controller interface (if enabled) has occurred. Bitwise OR of (ALRTMANUP/DN, ALRTPARUP/DN, ALRTDUALART, ALRTRJCT,

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 190 BITFIELD BITS DESCRIPTION ALRTI2C). ALRTPEC holds a dedicated position in the STATUS register (assertion of ALRTPEC will not assert ALRTINTRFC). If this alert bit is set, the specific error(s) can be read and cleared using the STATUS2 register. ALRTCAL 3 Calibration Fault Alert Logical OR of all calibration alerts (ALRTCALOSADC, ALRTCALOSR, ALERTCALOSTHRM, ALRTCALGAINP, ALRTCALGAINR). Cleared if component alerts are resolved in ALRTSUM; see ALRTSUM and ALRTIRQEN for details. Read only. If a calibration error occurs during an Automated Cell-Balancing or Discharge operation, the operation will end and issue CBACTIVE = 11 and ALRTCBCAL, notifying the user of the termination. ALRTCBAL 2 Cell-Balancing Status Alert 0 = Cell-Balancing Inactive/Normal 1 = Cell-Balancing Complete/Fault Logical OR of all enabled/unmasked cell-balancing alerts (ALRTCBTIMEOUT, ALRTCBTEMP, ALRTCBCAL, ALRTCBNTFY, ALRTCBDONE). Cleared if component alerts are resolved in STATUS3; see STATUS3 and ALRTIRQEN for details. Read only. ALRTFMEA2 1 FMEA2 Condition Summary Alert Bitwise logical OR of FMEA2[15:0]. Read only. ALRTFMEA1 0 FMEA1 Condition Summary Alert Bitwise logical OR of FMEA1[15:0]. Read only. STATUS2 (0x3) STATUS2 is a read- and write-accessible register that contains summary information on alerts related to interface and communication faults. BIT 15 14 13 12 11 10 9 8 Field ALRTPECUP ALRTPECDN ALRTMANUP ALRTMANDN ALRTPARUP ALRTPARDN ALRTDUALUART – Reset 0b0 0b0 0b0 0b0 0b0 0b0 0b0 –

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 191 Access Type Write 0 to Clear, Read Write 0 to Clear, Read Write 0 to Clear, Read Write 0 to Clear, Read Write 0 to Clear, Read Write 0 to Clear, Read Write 0 to Clear, Read – BIT 7 6 5 4 3 2 1 0 Field ALRTSPI ALRTSCLKERR ALRTOSC3 ALRTINTBUS – ALRTI2C – ALRTRJCT Reset 0b0 0b0 0b0 0b0 – 0b0 – 0b0 Access Type Write, Read, Ext Write, Read, Ext Write, Read, Ext Write, Read, Ext – Read Only – Write 0 to Clear, Read BITFIELD BITS DESCRIPTION ALRTPECUP 15 UART Up Interface Packet Error Check Alert Indicates a character/transaction recieved by the UART Up Interface contained a PEC error and was ignored as a result. Cleared only by writing to logic 0. Writing to a logic 1 has no effect. ALRTPECDN 14 UART Down Interface Packet Error Check Alert Indicates a character/transaction recieved by the UART Down Interface contained a PEC error and was ignored as a result. Cleared only by writing to logic 0. Writing to a logic 1 has no effect. Applies only to parts operating using the dual-UART interface (UARTCFG = 11). ALRTMANUP 13 UART Up Interface Manchester-Encoding Error Indicates that a character received by the UART Up Interface (through RXL) contained a Manchester error. Cleared only by writing to logic 0. Writing to a logic 1 has no effect. ALRTMANDN 12 UART Down Interface Manchester-Encoding Error Indicates that a character received by the UART Down Interface (through RXU) contained a Manchester error. Cleared only by writing to logic 0. Writing to a logic 1 has no effect. Applies only to parts operating using the dual-UART interface (UARTCFG = 11).

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 192 BITFIELD BITS DESCRIPTION ALRTPARUP 11 UART Up Interface Parity Error Indicates that a character received by the UART Up Interface (through RXL) contained a parity error. Cleared only by writing to logic 0. Writing to a logic 1 has no effect. ALRTPARDN 10 UART Down Interface Parity Error Indicates that a character received by the UART Down Interface (through RXU) contained a parity error. Cleared only by writing to logic 0. Writing to a logic 1 has no effect. Applies only to parts operating using the dual-UART interface (UARTCFG = 11). ALRTDUALUART 9 Dual-UART Fault Alert 0 = No Dual-UART Fault Detected 1 = Invalid Dual-UART Command Received ALRTDUALUART indicates one or more of the following conditions occurred: A WRITEDEVICE or WRITEALL command sent through a path not configured as host was ignored (only the host path accepts writes). An UPHOST command was issued and ignored on the downstream UART path. An DOWNHOST command was issued and ignored on the upstream UART path. These conditions are checked only when UARTCFG = DUAL (11). Cleared only by writing to logic 0. Writing to a logic 1 has no effect. ALRTSPI 7 SPI Error Summary Alert Indicates one or more of the following SPI transaction errors have occured:

R/WB != R/WB’ (i.e., DI[31] != DI[3], RW_ERR)
DIN[15:0] != 0x0000 in Read Mode (RW_ERR)
Transaction Timeout (TO_ERR) Specific error condition breakouts are reported as STAT[4:0] (DO[31:27]) as part of all SPI transactions. All existing SPI CRC_ERR, RW_ERR, and TO_ERR alerts will be cleared by writing this bit to logic 0. Writing to a logic 1 has no effect. Applies only to parts operating using the SPI interface (UARTSEL = 0).

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 193 BITFIELD BITS DESCRIPTION Note: The SPI CRC_ERR condition is reported using the dedicated STATUS1:ALRTPEC bit (read only), but is cleared using this bitfield (i.e., the CRC_ERR condition is not reported in ALRTSPI). To clear ALRTPEC, it will be necessary to write ALRTSPI to 0 even if it is already 0 (if no other SPI errors are reported). SPI clock issues covered by SPI CLK_ERR are broken out, reported, and cleared individually (see ALRTSCLKERR, ALRTOSC3, and ALRTINTBUS for details). ALRTSCLKERR 6 SPI SCLK Error Alert Indicates a SPI transaction was received that was not exactly 32 SCLK cycles in length. This error condition is one of three reported as STAT[1] (DO[28]) as part of all SPI transactions. Cleared by writing this bit to logic 0. Writing to a logic 1 has no effect. Applies only to parts operating using the SPI interface (UARTSEL = 0). ALRTOSC3 5 HFOSC Fault Alert Indicates that the HVOSC frequency is not within ±5% of its expected value when measured against the LFOSC. The status is updated every two cycles (LFOSC). Required/supported only in SPI mode (UARTSEL = 0). While it is possible for the SPI interface to continue to function under drift alert conditions, it will not function if the HVOSC is dead or extremely fast/slow. This error condition is one of three reported as STAT[1] (DO[28]) as part of all SPI transactions. Cleared only by writing to logic 0 if the condition has been resolved. Writing to a logic 1 has no effect. ALRTINTBUS 4 SPI Internal Bus Transaction Failure Indicates a SPI read or write transaction was not correctly passed across the internal memory bus. This can happen if the 16MHz oscillator (or branch) clocking the internal bus is dead, intermittent, or severely out of its specified frequency range. May be accompanied by ALRTOSC1, 2, or 3 alerts. This error condition is one of three reported as STAT[1] (DO[28]) as part of all SPI transactions. Cleared by writing this bit to logic 0. Writing to a logic 1 has no effect. Applies only to parts operating using the SPI interface (UARTSEL = 0). ALRTI2C 2 I2C Controller Fault Alert Logical OR of I2CSTAT[8:0] error indicator bits, subject to masking by I2CCFG:I2CALRTEN.

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 194 BITFIELD BITS DESCRIPTION Cleared only when unmasked component alerts are resolved in the I2CSTAT register. Read only. ALRTRJCT 0 Protected Command Rejection Alert 0 = Normal Operation 1 = Invalid Command Rejected during an active scan or cell-balancing operation ALRTRJCT is issued when an invalid write to a protected register is received during an active/gating scan or cell-balancing operation. The invalid command will be ignored. Cleared only by writing to logic 0. Writing to a logic 1 has no effect. STATUS3 (0x4) STATUS3 is a read- and write-accessible register that contains summary information on alerts related to automated cell-balancing operations. BIT 15 14 13 12 11 10 9 8 Field ALRTCBTIMEOUT ALRTCBTEMP ALRTCBCAL ALRTCBNTFY ALRTCBDONE – – – Reset 0b0 0b0 0b0 0b0 0b0 – – – Access Type Write 0 to Clear, Read Write 0 to Clear, Read Write 0 to Clear, Read Write 0 to Clear, Read Write 0 to Clear, Read – – – BIT 7 6 5 4 3 2 1 0 BITFIELD BITS DESCRIPTION ALRTCBTIMEOUT 15 Cell-Balancing Timeout Alert 0 = Cell-Balancing Disabled or in Progress 1 = Cell-Balancing Operation Halted due to Timeout Fault ALRTCBTIMEOUT is issued when a discharge or automated cell-balancing operation is halted due to an internal logic fault condition triggering the watchdog timer. This alert is automatically enabled if CBTODIS = 0. Cleared only by writing to logic 0. Writing to a logic 1 has no effect.

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 195 BITFIELD BITS DESCRIPTION ALRTCBTEMP 14 Cell-Balancing Thermal Alert 0 = Cell-Balancing Disabled or in Progress 1 = Cell-Balancing Operation Halted due to Thermal Fault ALRTCBTEMP is issued when a manual, discharge, or automated cell-balancing operation is halted due to a thermal fault condition. This alert is automatically enabled if CBTEMPEN = 1. Cleared only by writing to logic 0 after the automated cell-balancing operation which generated the alert has been completed or otherwise ended. Writing to a logic 1 has no effect. ALRTCBCAL 13 Cell-Balancing Calibration Alert 0 = Cell-Balancing Disabled or in Progress 1 = Cell-Balancing Operation Halted due to Calibration Fault ALRTCBCAL is issued when a discharge, or automated cell-balancing operation is halted due to an embedded calibration fault condition. Cleared only by writing to logic 0 after the automated cell-balancing operation which generated the alert has been completed or otherwise ended. Writing to a logic 1 has no effect. ALRTCBNTFY 12 Cell-Balancing Notification Alert 0 = No Cell-Balancing Progression Notification Present 1 = Cell-Balancing Progression Notification ALRTCBNTFY is periodically issued during discharge and automated cell-balancing operations to confirm normal progression of the operation. This alert is enabled and configured by CBNTFYCFG. Cleared only by writing to logic 0. Writing to a logic 1 has no effect. ALRTCBDONE 11 Cell-Balancing Complete Alert 0 = Cell-Balancing Disabled or in Progress 1 = Cell-Balancing Operation Complete ALRTCBDONE is issued when a manual, discharge, or automated cell-balancing operation completes due to a normal timed or undervoltage exit condition. Cleared only by writing to logic 0. Writing to a logic 1 has no effect. FMEA1 (0x5) FMEA1 is a read- and write-accessible register that relates current information on possible fault conditions. BIT 15 14 13 12 11 10 9 8

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 196 Field ALRTOSC1 ALRTOSC2 ALRTCOMMSE ALRTCOMMSE ALRTCOMMSE ALRTCOMMSE ALRTVDDL Reset 0b0 0b0 0b0 0b0 0b0 0b0 0b0 0b0 Acces s Type Write 0 to Clear, Read Write 0 to Clear, Read Read Only Read Only Read Only Read Only Write 0 to Clear, Read Write 0 to Clear, Read BIT 7 6 5 4 3 2 1 0 Field ALRTVDDL ALRTGNDL

3 ALRTGNDL2 ALRTGNDL1 ALRTHVUV ALRTHVHDRM ALRTHVO

V ALRTBALSWSU M Reset 0b0 0b0 0b0 0b0 0b0 0b0 0b0 0b0 Acces s Type Write 0 to Clear, Read Write 0 to Clear, Read Write 0 to Clear, Read Write 0 to Clear, Read Write 0 to Clear, Read Write 0 to Clear, Read Write 0 to Clear, Read Write, Read, Ext BITFIELD BITS DESCRIPTION ALRTOSC1 15 LFOSC Fault Alert Indicates that the LFOSC frequency is not within ±5% of its expected value when measured against the HFOSC oscillator. The status is updated every two cycles (LFOSC). Cleared only by writing to logic 0 if the condition has been resolved. Writing to a logic 1 has no effect. ALRTOSC2 14 32kHz Oscillator Fault Alert (Redundant) Identical to ALRTOSC1 - redundant alert with independent latch. Cleared only by writing to logic 0 if the condition has been resolved. Writing to a logic 1 has no effect. ALRTCOMMSEU1 13 UART Upper Port Single-Ended Alert Indicates that the UART has placed the upper port receiver in single-ended mode based on the first preamble received after POR. This bit is not set until the ALRTRST bit is cleared. Read only. ALRTCOMMSEL1 12 UART Lower Port Single-Ended Alert Indicates that the UART has placed the lower port receiver in single-ended mode based on the first preamble received after POR. This bit is not set until the ALRTRST bit is cleared. Read only. ALRTCOMMSEU2 11 UART Upper Port Single-Ended Redundant Alert Same as ALRTCOMMSEU1 (redundant alert) except that it sets before ALRTRST is cleared. Read only.

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 197 BITFIELD BITS DESCRIPTION ALRTCOMMSEL2 10 UART Lower Port Single-Ended Redundant Alert Same as ALRTCOMMSEL1 (redundant alert) except that it sets before ALRTRST is cleared. Read only. ALRTVDDL3 9 VDDL3 Fault Alert Indicates VDDL3 < VVDDL2/3_OC. This bit is not set until the ALRTRST bit is cleared. Cleared only by writing to logic 0 if condition is resolved. Writing to a logic 1 has no effect. ALRTVDDL2 8 VDDL2 Fault Alert Indicates VDDL2 < VVDDL2/3_OC. This bit is not set until the ALRTRST bit is cleared. Cleared only by writing to logic 0 if condition is resolved. Writing to a logic 1 has no effect. ALRTVDDL1 7 VDDL1 Fault Alert Indicates VDDL1 < VVDDL1_OC. This bit is not set until the ALRTRST bit is cleared. Cleared only by writing to logic 0 if condition is resolved. Writing to a logic 1 has no effect. ALRTGNDL3 6 GNDL3 Fault Alert Indicates an open circuit on the GNDL3 pin. This bit is not set until the ALRTRST bit is cleared. Cleared only by writing to logic 0. Writing to a logic 1 has no effect. ALRTGNDL2 5 GNDL2 Fault Alert Indicates an open circuit on the GNDL2 pin. This bit is not set until the ALRTRST bit is cleared. Cleared only by writing to logic 0. Writing to a logic 1 has no effect. ALRTGNDL1 4 GNDL1 Fault Alert Indicates an open circuit on the GNDL1 pin. This bit is not set until the ALRTRST bit is cleared. Cleared only by writing to logic 0. Writing to a logic 1 has no effect. ALRTHVUV 3 HV Undervoltage Fault Alert Indicates VHV < VHVUV. This bit is not set until the ALRTRST bit is cleared. Cleared only by writing to logic 0. Writing to a logic 1 has no effect. ALRTHVHDRM 2 HV Headroom Fault Alert Indicates that VHV – VTOPCELL1/2 was too low during the acquisition for an accurate measurement. Checked only during measurement activity. Cleared only by writing to logic 0. Writing to a logic 1 has no effect. ALRTHVOV 1 HV Overvoltage Fault Alert Indicates that VHV – VDCIN > VHVOV. This bit is not set until the ALRTRST bit is cleared.

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 198 BITFIELD BITS DESCRIPTION Cleared only by writing to logic 0. Writing to a logic 1 has no effect. ALRTBALSWSUM 0 Balance Switch Fault Alert Summary Bitwise logical OR of ALRTBALSW[13:0]. Updated at the end of a BALSWDIAG scan. Cleared if all enabled ALRTBALSW alerts are resolved or by writing to logic 0. Writing to a logic 1 has no effect. FMEA2 (0x6) FMEA2 is a read- and write-accessible register that relates current information on possible fault conditions. BIT 15 14 13 12 11 10 9 8 Field ALRTUSE R ALRTDCINM UX ALRTAUXPRTCTS UM ALRTTEM P ALRTSCANTIMEO UT – – – Reset 0b0 0b0 0b0 0b0 0b0 – – – Acces s Type Write, Read Write 0 to Clear, Read Read Only Write 0 to Clear, Read Read Only – – – BIT 7 6 5 4 3 2 1 0 Field – – – – ALRTADCZS ALRTADC FS ALRTCOMPACC OV ALRTCOMPACC UV Reset – – – – 0b0 0b0 0b0 0b0 Acces s Type – – – – Write 0 to Clear, Read Write 0 to Clear, Read Write 0 to Clear, Read Write 0 to Clear, Read BITFIELD BITS DESCRIPTION ALRTUSER 15 User-Defined Alert (Diagnostic) Used to test the Alert Interface. Asserted by writing to logic 1. The resulting alert will be relayed through the Alert Interface/UART DCByte and can be read back using the FMEA2 command. Cleared by writing to logic 0 (default). ALRTDCINMUX 14 DCIN MUX Fault Alert 0 = No DCINMUX Fault Detected (default) 1 = DCINMUX Fault Detected

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 199 BITFIELD BITS DESCRIPTION A high condition indicates the enabled DCINMUX is not functioning properly in a flexible- pack application. Connections will be made by diodes, and performance may be impacted, and/or other related faults may be issued. This alert is enabled if the DCINMUX is enabled (FLXPACKEN = 1) after STATUS1:ALRTRST has been cleared. The PACKCFG register makes selections on which SW[n] input is used for DCIN supply and which C[n] is used for VBLK measurements in flexible-pack applications. Cleared only by writing to logic 0 if condition has been resolved. Writing to a logic 1 has no effect. ALRTAUXPRTCTSUM 13 Auxiliary Protection Fault Alert Summary Logical OR of all enabled ALRTAUXPRTCT bits, indicating one or more AUXINn inputs is in a fault mode with input protection engaged. These alerts are enabled for all AUX/GPIO pins currently configured as AUXINn inputs. This bit will only be cleared when the ALRTAUXPRTCT register is cleared; see the ALRTAUXPRTCT register for specific details. Read only. ALRTTEMP 12 Die Overtemperature Fault Alert Indicates that TDIE > +115°C (+120°C, typ). Cleared only by writing to logic 0. Writing to a logic 1 has no effect. If a thermal alert occurs during an automated cell-balancing or discharge operation, the operation will end and issue CBACTIVE = 11 and ALRTCBTEMP, notifying the user of the termination. ALRTSCANTIMEOUT 11 Scan Timeout Alert 0 = Scan Not Requested or Progressing Normally (default) 1 = Scan Operation Halted due to Timeout Fault ALRTSCANTIMEOUT is a copy of SCANTIMEOUT. This alert is automatically enabled if SCANTODIS = 0. Cleared only by writing SCANCTRL:SCANTIMEOUT to 0. Read only. ALRTADCZS 3 ADC Zero-Scale BIST Alert 0 = ADC Zero-Scale BIST Passed 1 = ADC Zero-Scale BIST Failed Reports the result of the ADC zero-scale BIST measurement performed during the last acquisition. Tests the SAR ADC DAC, comparator, and logic components. Enabled using ADCZSFSEN. Cleared only by writing to logic 0. Writing to a logic 1 has no effect.

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 200 BITFIELD BITS DESCRIPTION Note: If detailed results are desired, use the Zero-Scale ADC Detailed Diagnostic. ALRTADCFS 2 ADC Full-Scale BIST Alert 0 = ADC Full-Scale BIST Passed 1 = ADC Full-Scale BIST Failed Reports the result of the ADC full-scale BIST measurement performed during the last acquisition. Tests the SAR ADC DAC, comparator, and logic components. Enabled using ADCZSFSEN. Cleared only by writing to logic 0. Writing to a logic 1 has no effect. Note: If detailed results are desired, use the Full-Scale ADC Diagnostic. ALRTCOMPACCOV 1 End-of-Sequence Comparator Accuracy Diagnostic Overvoltage Alert 0 = COMP Accuracy OV Test Passed 1 = COMP Accuracy OV Test Failed Result of the end-of-sequence comparator accuracy overvoltage diagnostic, if enabled (SCANCFG = 001 or 010, and COMPACCEN = 1). Cleared only by writing to logic 0. Writing to a logic 1 has no effect. ALRTCOMPACCUV 0 End-of-Sequence Comparator Accuracy Diagnostic Undervoltage Alert 0 = COMP Accuracy UV Test Passed 1 = COMP Accuracy UV Test Failed Result of the end-of-sequence comparator accuracy undervoltage diagnostic if enabled (SCANCFG = 001 or 010, and COMPACCEN = 1). Cleared only by writing to logic 0. Writing to a logic 1 has no effect. ALRTSUM (0x7) ALRTSUM is a read-accessible register that relates added, detailed information on the current status of the device, breaking out several summary bits in STATUS1. BIT 15 14 13 12 11 10 9 8 Field ALRTADCO VST ALRTCOMPO VST ALRTADCU VST ALRTCOMPU VST ALRTADCAUX OVST ALRTCOMPAUX OVST ALRTADCAUX UVST ALRTCOMPAUX UVST Rese t 0b0 0b0 0b0 0b0 0b0 0b0 0b0 0b0 Acce ss Type Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 201 BIT 7 6 5 4 3 2 1 0 Field – – – ALRTCALOS ADC ALRTCALOSR ALRTCALOSTHR M ALRTCALGAIN P ALRTCALGAINR Rese t – – – 0b0 0b0 0b0 0b0 0b0 Acce ss Type – – – Read Only Read Only Read Only Read Only Read Only BITFIELD BITS DESCRIPTION ALRTADCOVST 15 Cell ADC Overvoltage Alert Status Summary Bitwise logical OR of ALRTOV[14:1], based on ADC measurements. Cleared on next acquisition, if all enabled overvoltage conditions are resolved. Read only. ALRTCOMPOVST 14 Comparator Cell Overvoltage Alert Status Summary Bitwise logical OR of ALRTCOMPOV[14:1], based on redundant comparator monitoring. Cleared on next acquisition, if all enabled overvoltage conditions are resolved. Read only. ALRTADCUVST 13 Cell ADC Undervoltage Alert Status Summary Bitwise logical OR of ALRTUV[14:1], based on ADC measurements. Cleared on next acquisition, if all enabled undervoltage conditions are resolved. Read only. ALRTCOMPUVST 12 Comparator Cell Undervoltage Alert Status Summary Bitwise logical OR of ALRTCOMPUV[14:1], based on redundant comparator monitoring. Cleared on next acquisition, if all enabled undervoltage conditions are resolved. Read only. ALRTADCAUXOVST 11 Auxiliary ADC Overvoltage (Cold) Alert Status Summary Logical OR of ALRTAUXOV[5:0], based on ADC measurements. Cleared on next acquisition, if all enabled overvoltage conditions are resolved. Read only. ALRTCOMPAUXOVST 10 Comparator Auxiliary Overvoltage (Cold) Alert Status Summary Logical OR of ALRTCOMPAUXOV[5:0], based on redundant comparator monitoring. Cleared on next acquisition, if all enabled overvoltage conditions are resolved. Read only. ALRTADCAUXUVST 9 Auxiliary ADC Undervoltage (Hot) Alert Logical OR of ALRTAUXUV[5:0], based on ADC measurements. Cleared on next acquisition, if all enabled undervoltage conditions are resolved. Read only.

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 202 BITFIELD BITS DESCRIPTION ALRTCOMPAUXUVST 8 Comparator Auxiliary Undervoltage (Hot) Alert Status Summary Logical OR of ALRTCOMPAUXUV[5:0], based on redundant comparator monitoring. Cleared on next acquisition, if all enabled undervoltage conditions are resolved. Read only. ALRTCALOSADC 4 ADC Offset Calibration Alert 0 = ADC Offset Calibration Valid 1 = ADC Offset Calibration Fault ALRTCALOSADC indicates the ADC offset calibration operation returned a result outside expected boundaries. Cleared when a later calibration operation or write to CALOSADC returns an expected result. Read only. ALRTCALOSR 3 Ramp LSA + ADC Offset Calibration Alert 0 = LSA + ADC Offset Calibration Valid 1 = LSA + ADC Offset Calibration Fault ALRTCALOSR indicates the LSA + ADC offset calibration operation returned a result outside expected boundaries. Cleared when a later calibration operation or write to CALOSR returns an expected result. Read only. ALRTCALOSTHRM 2 ADC Ratiometric Offset Calibration Alert 0 = Ratiometric ADC Offset Calibration Valid 1 = Ratiometric ADC Offset Calibration Fault ALRTCALOSTHRM indicates the ratiometric ADC offset calibration operation returned a result outside expected boundaries. Cleared when a later calibration operation or write to CALOSTHRM returns an expected result. Read only. ALRTCALGAINP 1 Pyramid Gain Calibration Alert 0 = Pyramid Gain Calibration Valid 1 = Pyramid Calibration Fault ALRTCALGAINP indicates the gain calibration operation returned a result outside expected boundaries. Cleared when a later calibration operation or write to CALGAINP returns an expected result. Read only. ALRTCALGAINR 0 Ramp Gain Calibration Alert 0 = Ramp Gain Calibration Valid 1 = Ramp Calibration Fault ALRTCALGAINR indicates the gain calibration operation returned a result outside expected boundaries. Cleared when a later calibration operation or write to CALGAINR returns an expected

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 203 BITFIELD BITS DESCRIPTION result. Read only. ALRTOVCELL (0x8) ALRTOVCELL is a read-accessible register that relates current information on cell overvoltage fault alerts based on ADC measurements. BIT 15 14 13 12 11 10 9 8 Field – – ALRTOV[14:9] Reset – – 0x00 Access Type – – Read Only BIT 7 6 5 4 3 2 1 0 Field ALRTOV[8:1] Reset 0x00 Access Type Read Only BITFIELD BITS DESCRIPTION ALRTOV 13:0 Cell Overvoltage Fault Alert ALRTOV[n] indicates VCELLN > VOV (OVTHSET threshold for POLARITY = 0, BIPOVTHSET for POLARITY = 1); evaluated/enabled if OVALRTEN[n] = 1. Cleared on next acquisition, if the overvoltage condition is resolved. Read only. ALRTUVCELL (0x9) ALRTUVCELL is a read-accessible register that relates current information on cell undervoltage fault alerts based on ADC measurements. BIT 15 14 13 12 11 10 9 8 Field – – ALRTUV[14:9] Reset – – 0x00 Access Type – – Read Only

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 204 BIT 7 6 5 4 3 2 1 0 Field ALRTUV[8:1] Reset 0x00 Access Type Read Only BITFIELD BITS DESCRIPTION ALRTUV 13:0 Cell Undervoltage Fault Alert ALRTOV[n] indicates VCELLN < VUV (UVTHSET threshold for POLARITY = 0, BIPUVTHSET for POLARITY = 1); evaluated/enabled if UVALRTEN[n] = 1. Cleared on next acquisition, if the undervoltage condition is resolved. Read only. MINMAXCELL (0xA) MINMAXCELL is a read-accessible register that relates the cell locations with the highest and lowest values measured. BIT 15 14 13 12 11 10 9 8 Field – – – – MAXCELL[3:0] Reset – – – – 0x0 Access Type – – – – Read Only BIT 7 6 5 4 3 2 1 0 Field – – – – MINCELL[3:0] Reset – – – – 0x0 Access Type – – – – Read Only BITFIELD BITS DESCRIPTION MAXCELL 11:8 Maximum Voltage Cell Cell number [14:1] of the maximum cell voltage enabled/observed (for all CELLENn = 1) in the last scan (SCAN = 1) based on ALU/IIR data as selected by RDFILT. This bitfield is not updated for data requests made with SCAN = 0. If multiple cells have the same maximum value, this field contains the lowest cell number reporting that result. Note: This operation works on unipolar or bipolar measurement sets, as selected by MINMAXPOL. If MINMAXPOL is set such that no measurements in the scan meet the criteria (e.g., MINMAXPOL = 1 (bipolar), but POLARITY[14:1] = 0000h), a result of Fh will be returned (indicating no valid result was found).

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 205 BITFIELD BITS DESCRIPTION Read only. MINCELL 3:0 Minimum Voltage Cell Cell number [14:1] of the minimum cell voltage enabled/observed (for all CELLENn = 1) in the last scan (SCAN = 1) based on ALU/IIR data as selected by RDFILT. This bitfield is not updated for data requests made with SCAN = 0. If multiple cells have the same minimum value, this field contains the lowest cell number reporting that result. Note: This operation works on unipolar or bipolar measurement sets, as selected by MINMAXPOL. If MINMAXPOL is set such that no measurements in the scan meet the criteria (e.g., MINMAXPOL = 1 (bipolar), but POLARITY[14:1] = 0000h), a result of Fh will be returned (indicating no valid result was found). Read only. ALRTAUXPRTCTREG (0xB) ALRTAUXPRTCT is a read-accessible register that relates current information on auxiliary input protection fault alerts. BIT 15 14 13 12 11 10 9 8 BIT 7 6 5 4 3 2 1 0 Field – – ALRTAUXPRTCT[5:4] ALRTAUXPRTCT[3:0] Reset – – 0b00 0x0 Access Type – – Read Only Read Only BITFIELD BITS DESCRIPTION ALRTAUXPRTCT 5:4 Auxiliary Protection Fault Alert ALRTAUXPRTCT[n] indicates VAUX[n] > VAA; the alert is evaluated/enabled on each AUX/GPIO pin configured as an AUXINn input (see AUXGPIOCFG). Once the fault condition is detected on a pin, the AUXINn input switch is disabled to protect internal circuitry. AUXINn measurements and alerts for that pin will be invalid until proper operating conditions are restored. Cleared only if the condition is resolved upon a retry, or if the affected pin is no longer configured as an AUXINn input (disabling the protection circuit). In order to retry AUX operation and clear the fault condition, rewrite the desired configuration to the

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 206 BITFIELD BITS DESCRIPTION AUXGPIOCFG register (it is not necessary to toggle the configuration). Read only. ALRTAUXPRTCT 3:0 Auxiliary Protection Fault Alert ALRTAUXPRTCT[n] indicates VAUX[n] > VAA; the alert is evaluated/enabled on each AUX/GPIO pin configured as an AUXINn input (see AUXGPIOCFG). Once the fault condition is detected on a pin, the AUX[n] input switch is disabled to protect internal circuitry. AUX[n] measurements and alerts for that pin will be invalid until proper operating conditions are restored. Cleared only if the condition is resolved upon a retry, or if the affected pin is no longer configured as an AUXINn input (disabling the protection circuit). In order to retry AUX operation and clear the fault condition, rewrite the desired configuration to the AUXGPIOCFG register (it is not necessary to toggle the configuration). Read only. ALRTAUXOVREG (0xC) ALRTAUXOV is a read-accessible register that relates current information on auxiliary overvoltage (cold) fault alerts. BIT 15 14 13 12 11 10 9 8 BIT 7 6 5 4 3 2 1 0 Field – – ALRTAUXOV[5:4] ALRTAUXOV[3:0] Reset – – 0b00 0x0 Access Type – – Read Only Read Only BITFIELD BITS DESCRIPTION ALRTAUXOV 5:4 Auxiliary Overvoltage (Cold) Fault Alert ALRTAUXOV[n] indicates VAUXINn > VAUXOVTHSET; evaluated/enabled if AUXOVALRTEN[n] = 1. Cleared on next acquisition, if the overvoltage condition is resolved. Read only. ALRTAUXOV 3:0 Auxiliary Overvoltage (Cold) Fault Alert ALRTAUXOV[n] indicates VAUXINn > VAUXOVTHSET; evaluated/enabled if AUXOVALRTEN[n] = 1.

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 207 BITFIELD BITS DESCRIPTION Cleared on next acquisition, if the overvoltage condition is resolved. Read only. ALRTAUXUVREG (0xD) ALRTAUXUV is a read-accessible register that relates current information on auxiliary undervoltage fault (hot) alerts. BIT 15 14 13 12 11 10 9 8 BIT 7 6 5 4 3 2 1 0 Field – – ALRTAUXUV[5:4] ALRTAUXUV[3:0] Reset – – 0b00 0x0 Access Type – – Read Only Read Only BITFIELD BITS DESCRIPTION ALRTAUXUV 5:4 Auxiliary Undervoltage (Hot) Fault Alert ALRTAUXUV[n] indicates VAUXINn < VAUXUVTHSET; evaluated/enabled if AUXUVALRTEN[n] = 1. Cleared on next acquisition, if the undervoltage condition is resolved. Read only. ALRTAUXUV 3:0 Auxiliary Undervoltage (Hot) Fault Alert ALRTAUXUV[n] indicates VAUXINn < VAUXUVTHSET; evaluated/enabled if AUXUVALRTEN[n] = 1. Cleared on next acquisition, if the undervoltage condition is resolved. Read only. ALRTCOMPOVREG (0xE) ALRTCOMPOV is a read-accessible register that relates current information on cell overvoltage fault alerts based on the redundant comparator. BIT 15 14 13 12 11 10 9 8

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 208 Field – – ALRTCOMPOV[14:9] Reset – – 0b00000000000000 Access Type – – Read Only BIT 7 6 5 4 3 2 1 0 Field ALRTCOMPOV[8:1] Reset 0b00000000000000 Access Type Read Only BITFIELD BITS DESCRIPTION ALRTCOMPOV 13:0 Cell Overvoltage Fault Comparator Alert ALRTCOMPOV[n] indicates VCELL[n] > VCOMPOVTH (Comparator Overvoltage Threshold); evaluated/enabled if OVALRTEN[n] = 1. Cleared on next comparator acquisition, if the overvoltage condition is resolved. Read only. ALRTCOMPUVREG (0xF) ALRTCOMPUV is a read-accessible register that relates current information on cell undervoltage fault alerts based on the redundant comparator. BIT 15 14 13 12 11 10 9 8 Field – – ALRTCOMPUV[14:9] Reset – – 0b00000000000000 Access Type – – Read Only BIT 7 6 5 4 3 2 1 0 Field ALRTCOMPUV[8:1] Reset 0b00000000000000 Access Type Read Only

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 209 BITFIELD BITS DESCRIPTION ALRTCOMPUV 13:0 Cell Undervoltage Fault Comparator Alert ALRTCOMPUV[n] indicates VCELL[n] < VCOMPUVTH (Comparator Undervoltage Threshold); evaluated/enabled if UVALRTEN[n] = 1. Cleared on next comparator acquisition, if the undervoltage condition is resolved. Read only. ALRTCOMPAUXOVREG (0x10) ALRTCOMPAUXOV is a read-accessible register that relates current information on auxiliary overvoltage fault (cold) alerts based on the redundant comparator. BIT 15 14 13 12 11 10 9 8 BIT 7 6 5 4 3 2 1 0 Field – – ALRTCOMPAUXOV[5:4] ALRTCOMPAUXOV[3:0] Reset – – 0b00 0x0 Access Type – – Read Only Read Only BITFIELD BITS DESCRIPTION ALRTCOMPAUXOV 5:4 Auxiliary Overvoltage (Cold) Fault Comparator Alert ALRTCOMPAUXOV[n] indicates VAUXINn > VCOMPOVTH (Comparator Overvoltage Threshold, Cold); evaluated/enabled if AUXOVALRTEN[n] = 1. Cleared on next comparator acquisition, if the overvoltage condition is resolved. Read only. ALRTCOMPAUXOV 3:0 Auxiliary Overvoltage (Cold) Fault Comparator Alert ALRTCOMPAUXOV[n] indicates VAUXINn > VCOMPOVTH (Comparator Overvoltage Threshold, Cold); evaluated/enabled if AUXOVALRTEN[n] = 1. Cleared on next comparator acquisition, if the overvoltage condition is resolved. Read only.

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 210 ALRTCOMPAUXUVREG (0x11) ALRTCOMPAUXUV is a read-accessible register that relates current information on auxiliary undervoltage fault (hot) alerts based on the redundant comparator. BIT 15 14 13 12 11 10 9 8 BIT 7 6 5 4 3 2 1 0 Field – – ALRTCOMPAUXUV[5:4] ALRTCOMPAUXUV[3:0] Reset – – 0b00 0x0 Access Type – – Read Only Read Only BITFIELD BITS DESCRIPTION ALRTCOMPAUXUV 5:4 Auxiliary Undervoltage (Hot) Fault Comparator Alert ALRTCOMPAUXUV[n] indicates VAUXINn < VCOMPUVTH (Comparator Undervoltage Threshold, Hot); evaluated/enabled if AUXUVALRTEN[n] = 1. Cleared on next acquisition, if the undervoltage condition is resolved. Read only. ALRTCOMPAUXUV 3:0 Auxiliary Undervoltage (Hot) Fault Comparator Alert ALRTCOMPAUXUV[n] indicates VAUXINn < VCOMPUVTH (Comparator Undervoltage Threshold, Hot); evaluated/enabled if AUXUVALRTEN[n] = 1. Cleared on next acquisition, if the undervoltage condition is resolved. Read only. ALRTBALSWREG (0x12) ALRTBALSW is a read-accessible register that relates current summary information on balancing switch fault alerts. BIT 15 14 13 12 11 10 9 8 Field – – ALRTBALSW[13:8] Reset – – 0b00000000000000 Access Type – – Read Only

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 211 BIT 7 6 5 4 3 2 1 0 Field ALRTBALSW[7:0] Reset 0b00000000000000 Access Type Read Only BITFIELD BITS DESCRIPTION ALRTBALSW 13:0 Balance Switch Fault Alert ALRTBALSW[n] indicates the corresponding measurement result fails the threshold specified by the Balance Switch Diagnostic modes (SCANCFG = 100 through 111). Testing and faults above the TOPCELL1/2 position are automatically masked out of this register (see PACKCFG:TOPCELL1&2 for complete details). Cleared on next acquisition, if the condition is resolved. Read only. SWACTION (0x13) SWACTION is a read- and write-accessible register that contains bits allowing software exit and reset requests. These requests are not recommended for general use, but may be of use in case of error. BIT 15 14 13 12 11 10 9 8 BIT 7 6 5 4 3 2 1 0 Access Type – – – – – – – Write, Read, Pulse BITFIELD BITS DESCRIPTION SWPOR 0 Software POR Request 0 = Normal Operation (default, no effect) 1 = Initiates Software POR event Always reads logic 0.

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 212 DEVCFG1 (0x14) DEVCFG1 is a read- and write-accessible register that governs the configuration of the device interface operation. BIT 15 14 13 12 11 10 9 8 Field UARTCFG[1:0] TXUIDLEHIZ TXLIDLEHIZ DEVCFG1RSRV[1: ALIVECNTE N UARTHOS T Reset 0b11 0b0 0b0 0b00 0b0 0b1 Acces s Type Write, Read, Ext Write, Read, Ext Write, Read, Ext Write, Read, Ext Write, Read, Ext Read Only BIT 7 6 5 4 3 2 1 0 Field DEVCFG1RS RV DEVCFG1RS RV DEVCFG1RS RV DEVCFG1RS RV UARTDCE N NOPEC ALERTEN DBLBUFE N Reset 0b0 0b0 0b0 0b0 0b1 0b0 0b0 0b0 Acces s Type Write, Read, Ext Write, Read, Ext Write, Read, Ext Write, Read, Ext Write, Read Write, Read, Ext Write, Read, Ext Write, Read BITFIELD BITS DESCRIPTION UARTCFG 15:14 UART Interface Configuration 00 - Single-UART Interface with External Loopback 01 - Single-UART Interface with Internal Loopback 10 - Single-UART Interface with Differential Alert Interface 11 - Dual-UART Interface (default) Single-UART options with Loopback (modes 0x): The UART Up Path is used for read and write commands and the Down Path is used as a return (pass-through) path. If an internal loopback path is desired, the internal shunt should only be engaged on the last device in the chain using mode 01. Alert Interface is single-ended (using the ALERTIN and ALERTOUT pins) since the Down Path is engaged for UART communications. Single UART with Differential Alert Interface (mode 10): The UART Up Path is used for read and write commands with a direct wire return path from the last device in the chain to the μC. The Down Path is used as a differential Alert path. The single-ended Alert path is disabled - the ALERTOUT port will idle and the ALERTIN port will be disabled. Dual-UART Interface: Both the Up and Down Interfaces are used for UART communication. Only the host path (selected using UPHOST or DOWNHOST commands, and indicated by HOSTUART) accepts write commands, while both paths can accept read commands. The Alert Interface is single-ended (using the ALERTIN and ALERTOUT pins) since the Down Path is engaged for UART communications. For all the above options, the UART Up Path uses the RXL->TXU ports, and the

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 213 BITFIELD BITS DESCRIPTION UART Down Path uses the TXL->RXU ports. This bitfield is unaffected in the event of a SWPOR (software POR) request by the host. Note: The device hardware must be preconfigured to support the correct operational mode. The device powers up in the Dual-UART mode to ensure any hardware configuration can configure the device. If the incorrect operating mode is configured, the UART controller should cease communications (and possibly issue a FORCEPOR) to reset the device to default status through SHDNL assertion. TXUIDLEHIZ 13 UART Upper Tx Idle Mode Selection 0 = TXU Drivers Idle in Logic 0 (default) 1 = TXU Drivers Idle in High-Z Leave in default state for normal operation. This bitfield is unaffected in the event of a SWPOR (software POR) request by the host. TXLIDLEHIZ 12 UART Lower Tx Idle Mode Selection 0 = TXL Drivers Idle in Logic 0 (default) 1 = TXL Drivers Idle in High-Z Leave in default state for normal operation. This bitfield is unaffected in the event of a SWPOR (software POR) request by the host. DEVCFG1RSRV 11:10 Reserved. Reads back the value written. ALIVECNTEN 9 Enable UART Interface Alive Counter 0 = Do not send Alive-Counter byte (default). 1 = Enables inclusion of Alive-Counter byte at end of all write and read packets. UARTHOST 8 UART Host Mode Indicator Bit 0 = UART Down Path is Host 1 = UART Up Path is Host (default) Signfies which UART path is currently configured as the host. Down Host mode is only accessible if UARTCFG = DUAL (11). The host mode is selected using UPHOST and DOWNHOST commands. Read only. This bitfield is unaffected in the event of a SWPOR (software POR) request by the host. DEVCFG1RSRV 7 Reserved. Reads back the value written. DEVCFG1RSRV 6 Reserved. Reads back the value written.

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 214 BITFIELD BITS DESCRIPTION DEVCFG1RSRV 5 Reserved. Reads back the value written. DEVCFG1RSRV 4 Reserved. Reads back the value written. UARTDCEN 3 UART Data Check Byte Enable (Interface Option) 0 - Data Check Byte Not Supported 1 - Data Check Byte Required (default) NOPEC 2 UART PEC/CRC Disable 0 = PEC/CRC Enabled (default) 1 = PEC/CRC Disabled Determines if Packet Error Checking is enforced using the UART interface. If this bit is set, the PEC characters should be omitted from the UART packet/command. ALERTEN 1 Alert Interface Enable 0 = Alert Interface is Disabled (Default) 1 = Alert Interface is Enabled If disabled: - If UARTCFG = 0x or 11 (Single-Ended Alert), the ALERTOUT port will idle high-Z and the ALERTIN port will be disabled/ignored. - If UARTCFG = 10 (Differential Alert), the UART Down Path will idle as set by TXLIDLEHIZ. If enabled, the device will initiate alerts based on STATUS1 content, as well as pass through any alerts received from/to the daisy chain. This bit is unaffected in the event of SWPOR (software POR) request by host. DBLBUFEN 0 Double-Buffer Mode Enable 0 = Normal Operation (default) 1 = Double-Buffered Operation Enables the Double-Buffer mode. This mode automatically transfers data from the ALU/IIR to the data registers at the start of the next acquisition instead of at the end of an acquisition. This mode may be used so the host can start a second acquisition and then begin reading the data from the first acquisition (during the second acquisition). This works even if the first data read transactions take longer than the second acquisition to complete; simply hold off on a third acquisition until the first acquisition data is retrieved. Launching a third acquisition will move the data from the second acquisition to the data registers for readback during the third acquisition, and so forth. DEVCFG2 (0x15) DEVCFG2 is a read- and write-accessible register that governs the configuration of the device filtering, several top-level diagnostic modes, and timeout monitors.

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 215 BIT 15 14 13 12 11 10 9 8 Field IIRFC[2:0] – – – – – Access Type Write, Read – – – – – BIT 7 6 5 4 3 2 1 0 Field – HVCPDIS FORCEPOR ALERTDCTSTEN – DEVCFG2RSRV SCANTODIS CBTODIS Reset – 0b0 0b0 0b0 – 0b0 0b0 0b0 Access Type – Write, Read Write, Read Write, Read – Write, Read Write, Read Write, Read BITFIELD BITS DESCRIPTION IIRFC 15:13 IIR Filter Coefficient Selection 000 = 0.125 001 = 0.250 010 = 0.375 (default) 011 = 0.500 100 = 0.625 101 = 0.750 110 = 0.875 111 = 1.000 (filter off) This setting determines the weight of the current measurement result vs. the previously accumulated results in the IIR filter. A setting of 1.0 effectively disables the filter. HVCPDIS 6 HV Charge Pump Disable 0 = Normal Operation (default) 1 = Disable HV Charge Pump Used for ALRTHVUV diagnostic. If the HV charge pump is disabled in normal operation, measurement errors will result due to an VHV undervoltage condition. FORCEPOR 5 Force POR Event 0 = Normal Operation (default) 1 = Enables hard POR by pulling down SHDNL internally. If cleared before the POR occurs, the active pull-down on SHDNL will be removed. Note: This bit is used to accelerate a complete POR event issued by SHDNL falling. In UART applications, it is possible that UART activity will fight or overcome the SHDNL pull-down. For best results, cease UART communications when using this mode. ALERTDCTSTEN 4 UART Alert DC Diagnostic Test Enable 0 = UART Alert DC Testing Disabled (Default) 1 = UART Alert DC Testing Enabled Used to place the ALRTOUT pin in a DC diagnostic mode for use in testing for shorts to GPIO/AUX0.

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 216 BITFIELD BITS DESCRIPTION If enabled, the ALRTOUT pin will be driven low if an alert condition is present, and driven high otherwise. ALRTUSER can be written to exercise ALRTOUT in either direction. Neighboring pins such as AUX/GPIO[0] can be monitored directly or in diagnostic modes to detect a fault. This function works in all UARTCFG modes, including 10 (Differential Alert), which does not normally use the ALRTOUT pin. DEVCFG2RSRV 2 Reserved. Reads back the value written. SCANTODIS 1 Scan Timeout Disable 0 = Normal Operation (default) 1 = Disables the acquisition watchdog, but does not clear the SCANTIMEOUT flag in the SCANCTRL register if it is set. CBTODIS 0 Cell-Balancing Timeout Disable 0 = Normal Operation (default) 1 = Disables the cell-balancing watchdog, but does not clear the ALRTCBTIMEOUT flag in the STATUS3 register if it was previously set. AUXGPIOCFG (0x16) AUXGPIOCFG is a read- and write-accessible register that governs the configuration of the AUX/GPIO multifunction pins. BIT 15 14 13 12 11 10 9 8 Field I2CEN – GPIOEN[5:4] GPIOEN[3:0] Reset 0b0 – 0b11 0xF Access Type Write, Read, Ext – Write, Read, Ext Write, Read, Ext BIT 7 6 5 4 3 2 1 0 Field – – GPIODIR[5:4] GPIODIR[3:0] Reset – – 0b00 0x0 Access Type – – Write, Read, Ext Write, Read, Ext BITFIELD BITS DESCRIPTION I2CEN 15 Digital I2C Mode Enable 0 = Normal Configured Operation (default) 1 = I2C Controller Operation

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 217 BITFIELD BITS DESCRIPTION If I2CEN is set high, AUX/GPIO[0] is configured as the SDA open-drain I/O and AUX/GPIO[1] is configured as the SCL open-drain output driver for use as an I2C controller. If this bit is set, all remaining selections in AUXGPIOCFG, GPIO, and MEASUREEN2 will be ignored for AUX/GPIO[1:0]. GPIOEN 13:12 Digital GPIO Mode Enable 0 = Analog Input (AUX) Mode (High-Z) 1 = Digital GPIO Mode (default) GPIOEN[n] configures the corresponding AUX/GPIO[n] pin for operation in the selected mode. GPIOEN 11:8 Digital GPIO Mode Enable 0 = Analog Input (AUX) Mode (High-Z) 1 = Digital GPIO Mode (default) GPIOEN[n] configures the corresponding AUX/GPIO[n] pin for operation in the selected mode. Note: If I2CEN = 1, GPIOEN[1:0] are ignored, but will still read back the user setting. GPIODIR 5:4 Digital GPIO Direction Selection 0 = Digital Input Mode (High-Z, default) 1 = Digital Output Mode GPIODIR[n] configures the direction of the corresponding AUX/GPIO[n] pin. This setting is only applicable if GPIOEN[n] = 1 (Digital GPIO mode enabled). In digital input mode (GPIOEN = 1 and GPIODIR = 0), a 2MΩ pull-down (RGPIO) will be enabled to prevent the GPIO input from floating. In digital output mode (GPIOEN = 1 and GPIODIR = 1, the GPIO input circuitry will continue to operate, allowing direct observation of the port status. GPIODIR 3:0 Digital GPIO Direction Selection 0 = Digital Input Mode (High-Z, default) 1 = Digital Output Mode GPIODIR[n] configures the direction of the corresponding AUX/GPIO[n] pin. This setting is only applicable if GPIOEN[n] = 1 (Digital GPIO mode enabled). In digital input mode (GPIOEN = 1 and GPIODIR = 0), a 2MΩ pull-down (RGPIO) will be enabled to prevent the GPIO input from floating. In digital output mode (GPIOEN = 1 and GPIODIR = 1), the GPIO input circuitry will continue to operate, allowing direct observation of the port status. Note: If I2CEN = 1, GPIODIR[1:0] is ignored, but will still read back the user setting. GPIOCFG (0x17) GPIOCFG is a read- and write-accessible register that governs the output state of GPIO outputs and reads back the input state of GPIO inputs.

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 218 BIT 15 14 13 12 11 10 9 8 Field – – GPIODRV[5:4] GPIODRV[3:0] Reset – – 0b00 0x0 Access Type – – Write, Read, Ext Write, Read, Ext BIT 7 6 5 4 3 2 1 0 Field – – GPIORD[5:4] GPIORD[3:0] Reset – – 0b00 0x0 Access Type – – Read Only Read Only BITFIELD BITS DESCRIPTION GPIODRV 13:12 Digital GPIO Output State 0 = Output Logic 0 (default) 1 = Output Logic 1 GPIODRV[n] sets the output logic state direction of the corresponding AUX/GPIO[n] pin. This setting is only applicable if GPIOEN[n] = 1 and GPIODIR[n] = 1 (Digital GPIO Output mode enabled). GPIODRV 11:8 Digital GPIO Output State 0 = Output Logic 0 (default) 1 = Output Logic 1 GPIODRV[n] sets the output logic state direction of the corresponding AUX/GPIO[n] pin. This setting is only applicable if GPIOEN[n] = 1 and GPIODIR[n] = 1 (Digital GPIO Output mode enabled). Note: If I2CEN = 1, GPIODRV[1:0] is ignored, but will still read back the user setting. GPIORD 5:4 Digital GPIO Input State Indicator 0 = Logic 0 (default) 1 = Logic 1 GPIORD[n] indicates the current logic state of each active GPIO[n] input buffer. Data is only relevant if GPIOEN[n] = 1 (all digital GPIO pins are monitored in Input or Output mode), otherwise zero will be read back. The logic state is sampled at the end of the parity bit of the register address byte during a read transaction. Read only. GPIORD 3:0 Digital GPIO Input State Indicator 0 = Logic 0 (default)

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 219 BITFIELD BITS DESCRIPTION 1 = Logic 1 GPIORD[n] indicates the current logic state of each active GPIO[n] input buffer. Data is only relevant if GPIOEN[n] = 1 (all digital GPIO pins are monitored in Input or Output mode), otherwise 0 will be read back. The logic state is sampled at the end of the parity bit of the register address byte during a read transaction. Read only. Note: If I2CEN = 1, GPIORD[1:0] is no longer valid and will read back 00. PACKCFG (0x18) PACKCFG is a read- and write-accessible register that configures the part such that the top most cell and block used in the application is known. Details of flexible-pack applications are also configured within this register. BIT 15 14 13 12 11 10 9 8 Field FLXPCKEN2 FLXPCKEN1 FLXPCKSCAN – TOPBLOCK[3:0] Reset 0b1 0b1 0b1 – 0xF Access Type Write, Read Write, Read Write, Read – Write, Read BIT 7 6 5 4 3 2 1 0 Field TOPCELL2[3:0] TOPCELL1[3:0] Reset 0xF 0xF Access Type Write, Read Write, Read BITFIELD BITS DESCRIPTION FLXPCKEN2 15 Flexible-Pack Enable 2 0 = Flexible-Pack Functions Disabled 1 = Flexible-Pack Selection of Top Cell and Top Block Enabled (default) Indicates the flexible-pack support is engaged (DCINMUX and VBLKMUX), selecting the internal power and block routing path when the DCIN pin is not supplied externally. This selection is protected by a redundant bitfield. FLXPCKEN1 and FLXPCKEN2 must agree, resulting in a valid internal FLXPCKEN1/2 selection. If the two bitfields do not agree, the internal FLXPCKEN1/2 selection will be mapped to 1 (enabled, default) and DCINMUX selection will be mapped to the OFF position. SWn selection is determined by TOPCELL1/2 (based on TOPCELL1&2). Valid

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 220 BITFIELD BITS DESCRIPTION selections range from Cell 8 (0x8) to Cell 14 (0xE). If an unsupported selection (0x0 to 0x7, 0xF) is made in TOPCELL1/2, the DCINMUX selection switches are disabled, but the DCINMUX common switch is enabled (this is the default condition). In this condition, DCIN is initially pulled to a diode below the highest SWn input and there is no interference if DCIN is externally supplied. Block selection is determined by TOPBLOCK. Valid cell selections range from Cell 8 (0x8) to Cell 14 (0xE). If an unsupported selection (0x0~0x7, 0xF) is made in TOPBLOCK, the VBLKP port is selected. FLXPCKEN1 14 Flexible-Pack Enable 1 (Redundant Bitfield) 0 = Flexible-Pack Functions Disabled 1 = Flexible-Pack Selection of Top Cell and Top Block Enabled (default) See FLXPCKEN2 for complete details on operation and redundant bitfield checking. FLXPCKSCAN 13 Flexible-Pack Scan Configuration 0 = Flexible-Pack ALTMUX Scan Unmodified 1 = Flexible-Pack ALTMUX Scan Modified with Additional 30μs Delay before Acquisition of TOPCELL1/2 (default) FLEXPCKSCAN will configure the measurement sequence such that for any scan with ALTMUXSEL = 1, there will be 30μs delay prior to sampling the TOPCELL1/2 voltage regardless of SCANMODE. This delay affords the SW[TOPCELL1/2] input time to settle for an accurate diagnostic measurement when DCIN loading is temporarily suspended in flexible-pack configurations. Impacts scan sequences where FLXPCKEN1/2 = 1 and TOPCELL1/2 is set to a supported value (0x8 to 0xE), and ALTMUXSEL = 1 (effective value). Ignored otherwise. TOPBLOCK 11:8 Top Block Selection Configures the top block position if a selection other than the VBLK pin is chosen. Used to properly determine the connection point for the VBLOCK resistive divider. TOPBLOCK[3:0] selects the Cn pin to be connected to the VBLOCK resistive divider. 0xF (default) selects the VBLK pin. Selections 0x0 through 0x7 are not supported and will be mapped to 0xF (VBLK, default). TOPBLOCK may differ from TOPCELL1/2 if there are bus bars installed in channels above the top cell. TOPBLOCK is ignored if FLXPCKEN1/2 = 0. TOPCELL2 7:4 Top Cell Selection 2 Configures the top cell position if less than 14 channels are used. Used to properly mask the ALRTBALSW diagnostic alerts (always) and to make DCINMUX selections when FLXPCKEN1/2 = 1. This selection is protected by a redundant bitfield. TOPCELL1 and TOPCELL2 must agree, resulting in a valid internal TOPCELL1/2 selection. If the two bitfields do not agree, no ALRTBALSW alerts are masked, and the internal DCINMUX selection will be mapped to the OFF position.

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 221 BITFIELD BITS DESCRIPTION 0xF (default) removes all ALRTBALSW masking, and places DCINMUX in the OFF position. Flexible-Pack Behavior TOPCELL1/2 selects the SW pin to be connected to the DCIN pin. Selections 0x8 to 0xE map to SW[8] to SW[14]. Selections 0x0 to 0x7 and 0xF are not supported and will be mapped to an OFF position. In the OFF position, DCIN is initially pulled to a diode below the highest SWn input. Masking Behavior TOPCELL1/2 also sets masking behavior in ALRTBALSW diagnostics. All selections are supported for this function. TOPCELL1 3:0 Top Cell Selection 1 (Redundant Bitfield) Configures the top cell position if less than 14 channels are used. Used to properly mask the ALRTBALSW diagnostic alerts (always) and to make DCINMUX selections when FLXPCKEN1/2 = 1. See TOPCELL2 for complete details on operation and redundant bitfield checking. ALRTIRQEN (0x19) ALRTIRQEN is a read- and write-accessible register that selects which STATUS1 alerts trigger interrupts through the ALERT interface port(s), and are included in notifications through the DCByte and Alert Packet. Note the information in the STATUS1 register itself (or any component terms rolled up into STATUS1) is not masked/disabled by these settings, allowing the underlying data to always be available through STATUS1 readback. BIT 15 1 4 13 12 11 10 9 8 Field SCANALRTEN – MSMTCHALRT EN CELLOVSTALRT EN CELLUVSTALRT EN BLKOVSTALRT EN BLKUVSTALRT EN AUXOVSTALRT EN Reset 0b0 – 0b1 0b1 0b1 0b1 0b1 0b1 Acces s Type Write, Read – Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read BIT 7 6 5 4 3 2 1 0 Field AUXUVSTALRT EN – PECALRTEN INTRFCALRTEN CALALRTEN CBALALRTEN FMEA2ALRTEN FMEA1ALRTEN Reset 0b1 – 0b1 0b1 0b1 0b1 0b1 0b1 Acces s Type Write, Read – Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 222 BITFIELD BITS DESCRIPTION SCANALRTEN 15 Scan Complete Alert Enable 0 = ALRTSCAN Masked (default) 1 = ALRTSCAN Enabled Disabled by default since this is not a safety feature, but a notification option. Applies to the Alert Interface only in order to support interrupt-driven applications; ALRTSCAN is never included in the UART DCByte and Alert Packet. MSMTCHALRTEN 13 Cell Voltage Mismatch Alert Enable 0 = ALRTMSMTCH Masked 1 = ALRTMSMTCH Enabled (default) Applies to the Alert Interface, UART DCByte, and Alert Packet. CELLOVSTALRTEN 12 Cell Overvoltage Status Summary Alert Enable 0 = ALRTCELLOVST Masked 1 = ALRTCELLOVST Enabled (default) Applies to the Alert Interface, UART DCByte, and Alert Packet. CELLUVSTALRTEN 11 Cell Undervoltage Status Summary Alert Enable 0 = ALRTCELLUVST Masked 1 = ALRTCELLUVST Enabled (default) Applies to the Alert Interface, UART DCByte, and Alert Packet. BLKOVSTALRTEN 10 Block Overvoltage Status Alert Enable 0 = ALRTBLKOVST Masked 1 = ALRTBLKOVST Enabled (default) Applies to the Alert Interface, UART DCByte, and Alert Packet. BLKUVSTALRTEN 9 Block Undervoltage Status Alert Enable 0 = ALRTBLKUVST Masked 1 = ALRTBLKUVST Enabled (default) Applies to the Alert Interface, UART DCByte, and Alert Packet. AUXOVSTALRTEN 8 Auxiliary Overvoltage Status Summary Alert Enable 0 = ALRTAUXOVST Masked 1 = ALRTAUXOVST Enabled (default) Applies to the Alert Interface, UART DCByte, and Alert Packet. AUXUVSTALRTEN 7 Auxiliary Undervoltage Status Summary Alert Enable 0 = ALRTAUXUVST Masked 1 = ALRTAUXUVST Enabled (default) Applies to the Alert Interface, UART DCByte, and Alert Packet.

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 223 BITFIELD BITS DESCRIPTION PECALRTEN 5 Packet Error Check (CRC) Alert Enable 0 = ALRTPEC masked 1 = ALRTPEC enabled (default) Applies to the Alert Interface, UART Alert Packet ; ALRTPEC is not included in the UART DCByte. INTRFCALRTEN 4 Interface Specific Error Alert Enable 0 = ALRTINTRFC Masked 1 = ALRTINTRFC Enabled (default) Applies to the Alert Interface, UART DCByte, and Alert Packet. CALALRTEN 3 Calibration Fault Alert Enable 0 = ALRTCAL Masked 1 = ALRTCAL Enabled (default) Applies to the Alert Interface, UART DCByte, and Alert Packet. CBALALRTEN 2 Cell-Balancing Status Alert Enable 0 = ALRTCBAL Masked 1 = ALRTCBAL Enabled (default) Applies to the Alert Interface, UART DCByte, and Alert Packet. FMEA2ALRTEN 1 FMEA2 Condition Summary Alert Enable 0 = ALRTFMEA2 Masked 1 = ALRTFMEA2 Enabled (default) Applies to the Alert Interface, UART DCByte, and Alert Packet. FMEA1ALRTEN 0 FMEA1 Condition Summary Alert Enable 0 = ALRTFMEA1 Masked 1 = ALRTFMEA1 Enabled (default) Applies to the Alert Interface, UART DCByte, and Alert Packet. ALRTOVEN (0x1A) ALRTOVEN is a read- and write-accessible register that enables overvoltage fault checks on selected input channels during scans using either the ADC or comparator. BIT 15 14 13 12 11 10 9 8 Field – BLKOVALRTEN OVALRTEN[14:9] Reset – 0b0 0b00000000000000 Access Type – Write, Read Write, Read

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 224 BIT 7 6 5 4 3 2 1 0 Field OVALRTEN[8:1] Reset 0b00000000000000 Access Type Write, Read BITFIELD BITS DESCRIPTION BLKOVALRTEN 14 Block Overvoltage Fault Check Enable BLKOVALRTEN enables overvoltage fault checking on ADC block measurements against threshold BLKOVTHSET. Clearing also clears the associated block alert. OVALRTEN 13:0 Overvoltage Fault Check Enable OVALRTEN[n] enables overvoltage fault checking on CELL[n] against threshold OVTHSET (ADC) and COMPOVTH (comparator). Clearing also clears the associated cell alert in ALRTOVCELL and ALRTCOMPOVREG. ALRTUVEN (0x1B) ALRTUVEN is a read- and write-accessible register that enables undervoltage fault checks on selected input channels during scans using either the ADC or comparator. BIT 15 14 13 12 11 10 9 8 Field – BLKUVALRTEN UVALRTEN[14:9] Reset – 0b0 0b00000000000000 Access Type – Write, Read Write, Read BIT 7 6 5 4 3 2 1 0 Field UVALRTEN[8:1] Reset 0b00000000000000 Access Type Write, Read BITFIELD BITS DESCRIPTION BLKUVALRTEN 14 Block Undervoltage Fault Check Enable BLKUVALRTEN enables undervoltage fault checking on ADC block measurements against threshold BLKUVTHSET. Clearing also clears the associated block alert.

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 225 BITFIELD BITS DESCRIPTION UVALRTEN 13:0 Undervoltage Fault Check Enable UVALRTEN[n] enables undervoltage fault checking on CELL[n] against threshold UVTHSET (ADC) and COMPUVTH (comparator). Clearing also clears the associated cell alert in ALRTOVCELL and ALRTCOMPOVREG. ALRTAUXOVEN (0x1C) ALRTAUXOVEN is a read- and write-accessible register that enables auxiliary overvoltage (cold) fault checks on selected auxiliary channels during scans using either the ADC or comparator. BIT 15 14 13 12 11 10 9 8 BIT 7 6 5 4 3 2 1 0 Field – – AUXOVALRTEN[5:4] AUXOVALRTEN[3:0] Reset – – 0b00 0x0 Access Type – – Write, Read, Ext Write, Read, Ext BITFIELD BITS DESCRIPTION AUXOVALRTEN 5:4 Auxiliary Overvoltage (Cold) Fault Check Enable AUXOVALRTEN[n] enables overvoltage (cold) fault checking on AUX[n] against the ratiometric/absolute threshold AUXROVTHSET/AUXAOVTHSET (ADC) and COMPAUXROVTH/COMPAUXAOVTH (comparator), as selected by AUXREFSEL[n]. Clearing also clears the associated alert. Note: If the respective GPIOEN bit is set (GPIO mode), this bit is ignored, but will still read back the user setting. AUXOVALRTEN 3:0 Auxiliary Overvoltage (Cold) Fault Check Enable AUXOVALRTEN[n] enables overvoltage (cold) fault checking on AUX[n] against the ratiometric/absolute threshold AUXROVTHSET/AUXAOVTHSET (ADC) and COMPAUXROVTH/COMPAUXAOVTH (comparator), as selected by AUXREFSEL[n]. Clearing also clears the associated alert. Note: If the I2CEN bit (digital I2C mode, applies to [1:0] only) or the respective GPIOEN bit is set (GPIO mode), this bit is ignored, but will still read back the user setting.

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 226 ALRTAUXUVEN (0x1D) ALRTAUXUVEN is a read- and write-accessible register that enables auxiliary undervoltage (hot) fault checks on selected auxiliary channels using either the ADC or comparator. BIT 15 14 13 12 11 10 9 8 BIT 7 6 5 4 3 2 1 0 Field – – AUXUVALRTEN[5:4] AUXUVALRTEN[3:0] Reset – – 0b00 0x0 Access Type – – Write, Read, Ext Write, Read, Ext BITFIELD BITS DESCRIPTION AUXUVALRTEN 5:4 Auxiliary Undervoltage (Hot) Fault Check Enable AUXUVALRTEN[n] enables undervoltage (hot) fault checking on AUX[n] against the ratiometric/absolute threshold AUXRUVTHSET/AUXAUVTHSET (ADC) and COMPAUXRUVTH/COMPAUXAUVTH (comparator), as selected by AUXREFSEL[n]. Clearing also clears the associated alert. Note: If the respective GPIOEN bit is set (GPIO mode), this bit is ignored, but will still read back the user setting. AUXUVALRTEN 3:0 Auxiliary Undervoltage (Hot) Fault Check Enable AUXUVALRTEN[n] enables undervoltage (hot) fault checking on AUX[n] against the ratiometric/absolute threshold AUXRUVTHSET/AUXAUVTHSET (ADC) and COMPAUXRUVTH/COMPAUXAUVTH (comparator), as selected by AUXREFSEL[n]. Clearing also clears the associated alert. Note: If the I2CEN bit (digital I2C mode, applies to [1:0] only), or the respective GPIOEN bit is set (GPIO mode), this bit is ignored, but will still read back the user setting. ALRTCALTST (0x1E) ALRTCALTST is a read- and write-accessible register that allows the user to force calibration alerts to test readback and interrupt logic. The forced alert(s) will remain forced until this register is written back to zeros (assuming the existing calibration data is with range). BIT 15 14 13 12 11 10 9 8

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 227 Access BIT 7 6 5 4 3 2 1 0 Field – – – CALOSADCALRTFRC CALOSRALRTFRC CALOSTHRMALRTFRC CALGAINPALRTFRC CALGAINRALRTFRC Reset – – – 0b0 0b0 0b0 0b0 0b0 Access Type – – – Write, Read Write, Read Write, Read Write, Read Write, Read BITFIELD BITS DESCRIPTION CALOSADCALRTFRC 4 ADC Offset Calibration Alert Force 0 = ALRTCALOSADC Normal Operation (default) 1 = ALRTCALOSADC Forced if Unmasked Used to test alert functionality. CALOSRALRTFRC 3 Ramp LSA + ADC Offset Calibration Alert Force 0 = ALRTCALOSR Normal Operation (default) 1 = ALRTCALOSR Forced if Unmasked Used to test alert functionality. CALOSTHRMALRTFRC 2 Ratiometric ADC Offset Calibration Alert Force 0 = ALRTCALOSTHRM Normal Operation (default) 1 = ALRTCALOSTHRM Forced if Unmasked Used to test alert functionality. CALGAINPALRTFRC 1 Pyramid Gain Calibration Alert Force 0 = ALRTCALGAINP Normal Operation (default) 1 = ALRTCALGAINP Forced if Unmasked Used to test alert functionality. CALGAINRALRTFRC 0 Ramp Gain Calibration Alert Force 0 = ALRTCALGAINR Normal Operation (default) 1 = ALRTCALGAINR Forced if Unmasked Used to test alert functionality.

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 228 OVTHCLRREG (0x1F) OVTHCLR is a read- and write-accessible register that selects the cell overvoltage alert clear threshold used with unipolar ADC measurements. BIT 15 14 13 12 11 10 9 8 Field OVTHCLR[13:6] Reset 0b11111111111111 Access Type Write, Read BIT 7 6 5 4 3 2 1 0 Field OVTHCLR[5:0] – – Reset 0b11111111111111 – – Access Type Write, Read – – BITFIELD BITS DESCRIPTION OVTHCLR 15:2 Unipolar Cell Overvoltage Alert Clear Threshold 14-bit threshold value at/below which ALRTOV alerts will be cleared/deasserted for unipolar cell measurements. Note: For proper operation, this value should always be less than or equal to OVTHSET. OVTHSETREG (0x20) OVTHSET is a read- and write-accessible register that selects the cell overvoltage alert set threshold used with unipolar ADC measurements. BIT 15 14 13 12 11 10 9 8 Field OVTHSET[13:6] Reset 0b11111111111111 Access Type Write, Read BIT 7 6 5 4 3 2 1 0 Field OVTHSET[5:0] – – Reset 0b11111111111111 – –

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 229 Access Type Write, Read – – BITFIELD BITS DESCRIPTION OVTHSET 15:2 Unipolar Cell Overvoltage Alert Set Threshold 14-bit threshold value above which ALRTOV alerts will be set/asserted for unipolar cell measurements. A value of 0x3FFF effectively disables overvoltage checking. UVTHCLRREG (0x21) UVTHCLR is a read- and write-accessible register that selects the cell undervoltage alert clear threshold used with unipolar ADC measurements. BIT 15 14 13 12 11 10 9 8 Field UVTHCLR[13:6] Reset 0b00000000000000 Access Type Write, Read BIT 7 6 5 4 3 2 1 0 Field UVTHCLR[5:0] – – Reset 0b00000000000000 – – Access Type Write, Read – – BITFIELD BITS DESCRIPTION UVTHCLR 15:2 Unipolar Cell Undervoltage Alert Clear Threshold 14-bit threshold value at/above which ALRTUV alerts will be cleared/deasserted for unipolar cell measurements. Note: For proper operation, this value should always be greater than or equal to UVTHSET. UVTHSETREG (0x22) UVTHSET is a read- and write-accessible register that selects the cell undervoltage alert set threshold used with unipolar ADC measurements. BIT 15 14 13 12 11 10 9 8 Field UVTHSET[13:6]

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 230 Reset 0b00000000000000 Access Type Write, Read BIT 7 6 5 4 3 2 1 0 Field UVTHSET[5:0] – – Reset 0b00000000000000 – – Access Type Write, Read – – BITFIELD BITS DESCRIPTION UVTHSET 15:2 Unipolar Cell Undervoltage Alert Set Threshold 14-bit threshold value below which ALRTUV alerts will be set/asserted for unipolar cell measurements. A value of 0x0000 effectively disables undervoltage checking. MSMTCHREG (0x23) MSMTCH is a read- and write-accessible register that selects the cell voltage mismatch alert threshold used with ADC cell scan measurements. BIT 15 14 13 12 11 10 9 8 Field MSMTCH[13:6] Reset 0b11111111111111 Access Type Write, Read BIT 7 6 5 4 3 2 1 0 Field MSMTCH[5:0] – – Reset 0b11111111111111 – – Access Type Write, Read – – BITFIELD BITS DESCRIPTION MSMTCH 15:2 Cell Voltage Mismatch Alert Threshold 14-bit threshold value; if the difference between maximum and minimum cell voltages exceeds this value, ALRTMSMTCH will be set/asserted.

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 231 BITFIELD BITS DESCRIPTION Whether only unipolar ADC measurements (POLARITYn = 0) are included in mismatch calculations or all measurements are included is determined by POLARITYCTRL:MINMAXPOL. BIPOVTHCLRREG (0x24) BIPOVTHCLR is a read- and write-accessible register that selects the cell overvoltage alert clear threshold used with bipolar ADC measurements. BIT 15 14 13 12 11 10 9 8 Field BIPOVTHCLR[13:6] Reset 0b11111111111111 Access Type Write, Read BIT 7 6 5 4 3 2 1 0 Field BIPOVTHCLR[5:0] – – Reset 0b11111111111111 – – Access Type Write, Read – – BITFIELD BITS DESCRIPTION BIPOVTHCLR 15:2 Bipolar Cell Overvoltage Alert Clear Threshold 14-bit threshold value at/below which ALRTOV alerts will be cleared/deasserted for bipolar cell measurements. Bipolar format. Note: For proper operation, this value should always be less than or equal to BIPOVTHSET. BIPOVTHSETREG (0x25) BIPOVTHSET is a read- and write-accessible register that selects the cell overvoltage alert set threshold used with bipolar ADC measurements. BIT 15 14 13 12 11 10 9 8 Field BIPOVTHSET[13:6] Reset 0b11111111111111 Access Type Write, Read

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 232 BIT 7 6 5 4 3 2 1 0 Field BIPOVTHSET[5:0] – – Reset 0b11111111111111 – – Access Type Write, Read – – BITFIELD BITS DESCRIPTION BIPOVTHSET 15:2 Bipolar Cell Overvoltage Alert Set Threshold 14-bit threshold value above which ALRTOV alerts will be set/asserted for bipolar cell measurements. Bipolar format. A value of 0x3FFF effectively disables overvoltage checking. BIPUVTHCLRREG (0x26) BIPUVTHCLR is a read- and write-accessible register that selects the cell undervoltage alert clear threshold used with bipolar ADC measurements. BIT 15 14 13 12 11 10 9 8 Field BIPUVTHCLR[13:6] Reset 0b00000000000000 Access Type Write, Read BIT 7 6 5 4 3 2 1 0 Field BIPUVTHCLR[5:0] – – Reset 0b00000000000000 – – Access Type Write, Read – – BITFIELD BITS DESCRIPTION BIPUVTHCLR 15:2 Bipolar Cell Undervoltage Alert Clear Threshold 14-bit threshold value at/above which ALRTUV alerts will be cleared/deasserted for bipolar cell measurements. Bipolar format. Note: For proper operation, this value should always be greater than or equal to BIPUVTHSET.

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 233 BIPUVTHSETREG (0x27) BIPUVTHSET is a read- and write-accessible register that selects the cell undervoltage alert set threshold used with bipolar ADC measurements. BIT 15 14 13 12 11 10 9 8 Field BIPUVTHSET[13:6] Reset 0b00000000000000 Access Type Write, Read BIT 7 6 5 4 3 2 1 0 Field BIPUVTHSET[5:0] – – Reset 0b00000000000000 – – Access Type Write, Read – – BITFIELD BITS DESCRIPTION BIPUVTHSET 15:2 Bipolar Cell Undervoltage Alert Set Threshold 14-bit threshold value below which ALRTUV alerts will be set/asserted for bipolar cell measurements. Bipolar format. A value of 0x0000 effectively disables undervoltage checking. BLKOVTHCLRREG (0x28) BLKOVTHCLR is a read- and write-accessible register that selects the block overvoltage alert clear threshold used with ADC measurements. BIT 15 14 13 12 11 10 9 8 Field BLKOVTHCLR[13:6] Reset 0b11111111111111 Access Type Write, Read BIT 7 6 5 4 3 2 1 0 Field BLKOVTHCLR[5:0] – – Reset 0b11111111111111 – – Access Type Write, Read – –

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 234 BITFIELD BITS DESCRIPTION BLKOVTHCLR 15:2 Block Overvoltage Alert Clear Threshold 14-bit threshold value at/below which the ALRTBLKOV alert will be cleared/deasserted. Note: For proper operation, this value should always be less than or equal to BLKOVTHSET. BLKOVTHSETREG (0x29) BLKOVTHSET is a read- and write-accessible register that selects the block overvoltage alert set threshold used with ADC measurements. BIT 15 14 13 12 11 10 9 8 Field BLKOVTHSET[13:6] Reset 0b11111111111111 Access Type Write, Read BIT 7 6 5 4 3 2 1 0 Field BLKOVTHSET[5:0] – – Reset 0b11111111111111 – – Access Type Write, Read – – BITFIELD BITS DESCRIPTION BLKOVTHSET 15:2 Block Overvoltage Alert Set Threshold 14-bit threshold value above which the ALRTBLKOV alert will be set/asserted. A value of 0x3FFF effectively disables overvoltage checking. BLKUVTHCLRREG (0x2A) BLKUVTHCLR is a read- and write-accessible register that selects the block undervoltage alert clear threshold used with ADC measurements. BIT 15 14 13 12 11 10 9 8 Field BLKUVTHCLR[13:6] Reset 0b00000000000000 Access Type Write, Read

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 235 BIT 7 6 5 4 3 2 1 0 Field BLKUVTHCLR[5:0] – – Reset 0b00000000000000 – – Access Type Write, Read – – BITFIELD BITS DESCRIPTION BLKUVTHCLR 15:2 Block Undervoltage Alert Clear Threshold 14-bit threshold value at/above which the ALRTBLKUV alert will be cleared/deasserted. Note: For proper operation, this value should always be greater than or equal to BLKUVTHSET. BLKUVTHSETREG (0x2B) BLKUVTHSET is a read- and write-accessible register that selects the block undervoltage alert set threshold used with ADC measurements. BIT 15 14 13 12 11 10 9 8 Field BLKUVTHSET[13:6] Reset 0b00000000000000 Access Type Write, Read BIT 7 6 5 4 3 2 1 0 Field BLKUVTHSET[5:0] – – Reset 0b00000000000000 – – Access Type Write, Read – – BITFIELD BITS DESCRIPTION BLKUVTHSET 15:2 Block Undervoltage Alert Set Threshold 14-bit threshold value below which the ALRTBLKUV alert will be set/asserted. A value of 0x0000 effectively disables undervoltage checking.

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 236 AUXROVTHCLRREG (0x30) AUXROVTHCLR is a read- and write-accessible register that selects the overvoltage (cold) alert clear threshold used with ratiometric auxiliary ADC measurements. BIT 15 14 13 12 11 10 9 8 Field AUXROVTHCLR[13:6] Reset 0b11111111111111 Access Type Write, Read BIT 7 6 5 4 3 2 1 0 Field AUXROVTHCLR[5:0] – – Reset 0b11111111111111 – – Access Type Write, Read – – BITFIELD BITS DESCRIPTION AUXROVTHCLR 15:2 Ratiometric Auxiliary Overvoltage (Cold) Alert Clear Threshold 14-bit overvoltage (cold) clear threshold value, at/below which ALRTAUXOV alerts will be cleared/deasserted. This threshold is applied for auxiliary measurements where AUXREFSELn = 0 (ratiometric). Note: For proper operation, this value should always be less than or equal to AUXROVTHSET. AUXROVTHSETREG (0x31) AUXROVTHSET is a read- and write-accessible register that selects the overvoltage (cold) alert set threshold used with ratiometric auxiliary ADC measurements. BIT 15 14 13 12 11 10 9 8 Field AUXROVTHSET[13:6] Reset 0b11111111111111 Access Type Write, Read BIT 7 6 5 4 3 2 1 0 Field AUXROVTHSET[5:0] – –

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 237 Reset 0b11111111111111 – – Access Type Write, Read – – BITFIELD BITS DESCRIPTION AUXROVTHSET 15:2 Ratiometric Auxiliary Overvoltage (Cold) Alert Set Threshold 14-bit overvoltage (cold) set threshold value, above which ALRTAUXOV alerts will be asserted. This threshold is applied for auxiliary measurements where AUXREFSELn = 0 (ratiometric). A value of 0x3FFF effectively disables overvoltage checking. AUXRUVTHCLRREG (0x32) AUXRUVTHCLR is a read- and write-accessible register that selects the undervoltage (hot) alert clear threshold used with ratiometric auxiliary ADC measurements. BIT 15 14 13 12 11 10 9 8 Field AUXRUVTHCLR[13:6] Reset 0b00000000000000 Access Type Write, Read BIT 7 6 5 4 3 2 1 0 Field AUXRUVTHCLR[5:0] – – Reset 0b00000000000000 – – Access Type Write, Read – – BITFIELD BITS DESCRIPTION AUXRUVTHCLR 15:2 Ratiometric Auxiliary Undervoltage (Hot) Alert Clear Threshold 14-bit undervoltage (hot) clear threshold value, at/above which ALRTAUXUV alerts will be cleared/deasserted. This threshold is applied for auxiliary measurements where AUXREFSELn = 0 (ratiometric). Note: For proper operation, this value should always be greater than or equal to AUXRUVTHSET.

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 238 AUXRUVTHSETREG (0x33) AUXRUVTHSET is a read- and write-accessible register that selects the undervoltage (hot) alert set threshold used with ratiometric auxiliary ADC measurements. BIT 15 14 13 12 11 10 9 8 Field AUXRUVTHSET[13:6] Reset 0b00000000000000 Access Type Write, Read BIT 7 6 5 4 3 2 1 0 Field AUXRUVTHSET[5:0] – – Reset 0b00000000000000 – – Access Type Write, Read – – BITFIELD BITS DESCRIPTION AUXRUVTHSET 15:2 Ratiometric Auxiliary Undervoltage (Hot) Alert Set Threshold 14-bit undervoltage (hot) set threshold value, below which ALRTAUXUV alerts will be asserted. This threshold is applied for auxiliary measurements where AUXREFSELn = 0 (ratiometric). A value of 0x0000 effectively disables undervoltage checking. AUXAOVTHCLRREG (0x34) AUXAOVTHCLR is a read- and write-accessible register that selects the overvoltage alert clear threshold used with absolute auxiliary ADC measurements. BIT 15 14 13 12 11 10 9 8 Field AUXAOVTHCLR[13:6] Reset 0b11111111111111 Access Type Write, Read BIT 7 6 5 4 3 2 1 0 Field AUXAOVTHCLR[5:0] – –

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 239 Reset 0b11111111111111 – – Access Type Write, Read – – BITFIELD BITS DESCRIPTION AUXAOVTHCLR 15:2 Absolute Auxiliary Overvoltage Alert Clear Threshold 14-bit overvoltage clear threshold value, at/below which ALRTAUXOV alerts will be cleared/deasserted. This threshold is applied for auxiliary measurements where AUXREFSELn = 1 (absolute). Note: For proper operation, this value should always be less than or equal to AUXAOVTHSET. AUXAOVTHSETREG (0x35) AUXAOVTHSET is a read- and write-accessible register that selects the overvoltage alert set threshold used with absolute auxiliary ADC measurements. BIT 15 14 13 12 11 10 9 8 Field AUXAOVTHSET[13:6] Reset 0b11111111111111 Access Type Write, Read BIT 7 6 5 4 3 2 1 0 Field AUXAOVTHSET[5:0] – – Reset 0b11111111111111 – – Access Type Write, Read – – BITFIELD BITS DESCRIPTION AUXAOVTHSET 15:2 Auxiliary Overvoltage Alert Set Threshold 14-bit overvoltage set threshold value, above which ALRTAUXOV alerts will be asserted. This threshold is applied for auxiliary measurements where AUXREFSELn = 1 (absolute). A value of 0x3FFF effectively disables overvoltage checking.

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 240 AUXAUVTHCLRREG (0x36) AUXAUVTHCLR is a read- and write-accessible register that selects the undervoltage alert clear threshold used with absolute auxiliary ADC measurements. BIT 15 14 13 12 11 10 9 8 Field AUXAUVTHCLR[13:6] Reset 0b00000000000000 Access Type Write, Read BIT 7 6 5 4 3 2 1 0 Field AUXAUVTHCLR[5:0] – – Reset 0b00000000000000 – – Access Type Write, Read – – BITFIELD BITS DESCRIPTION AUXAUVTHCLR 15:2 Absolute Auxiliary Undervoltage Alert Clear Threshold 14-bit undervoltage clear threshold value, at/above which ALRTAUXUV alerts will be cleared/deasserted. This threshold is applied for auxiliary measurements where AUXREFSELn = 1 (absolute). Note: For proper operation, this value should always be greater than or equal to AUXAUVTHSET. AUXAUVTHSETREG (0x37) AUXAUVTHSET is a read- and write-accessible register that selects the undervoltage alert set threshold used with absolute auxiliary ADC measurements. BIT 15 14 13 12 11 10 9 8 Field AUXAUVTHSET[13:6] Reset 0b00000000000000 Access Type Write, Read BIT 7 6 5 4 3 2 1 0 Field AUXAUVTHSET[5:0] – –

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 241 Reset 0b00000000000000 – – Access Type Write, Read – – BITFIELD BITS DESCRIPTION AUXAUVTHSET 15:2 Absolute Auxiliary Undervoltage Alert Set Threshold 14-bit undervoltage set threshold value, below which ALRTAUXUV alerts will be asserted. This threshold is applied for auxiliary measurements where AUXREFSELn = 1 (absolute). A value of 0x0000 effectively disables undervoltage checking. COMPOVTHREG (0x38) COMPOVTH is a read- and write-accessible register that selects the cell overvoltage alert threshold for the redundant comparator. BIT 15 14 13 12 11 10 9 8 Field COMPOVTH[11:4] Reset 0xFFF Access Type Write, Read BIT 7 6 5 4 3 2 1 0 Field COMPOVTH[3:0] – – – – Reset 0xFFF – – – – Access Type Write, Read – – – – BITFIELD BITS DESCRIPTION COMPOVTH 15:4 Comparator Cell Overvoltage Alert Threshold 12-bit threshold value of a 5V input range above which ALRTCOMPOV alerts will be set/asserted by comparator scans. A value of 0xFFF effectively disables overvoltage checking. Note: For proper operation, this value should always be greater than or equal to COMPUVTH.

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 242 COMPUVTHREG (0x39) COMPUVTH is a read- and write-accessible register that selects the cell undervoltage alert threshold for the redundant comparator. BIT 15 14 13 12 11 10 9 8 Field COMPUVTH[11:4] Reset 0x000 Access Type Write, Read BIT 7 6 5 4 3 2 1 0 Field COMPUVTH[3:0] – – – – Reset 0x000 – – – – Access Type Write, Read – – – – BITFIELD BITS DESCRIPTION COMPUVTH 15:4 Comparator Cell Undervoltage Alert Threshold 12-bit threshold value of a 5V input range below which ALRTCOMPUV alerts will be set/asserted by comparator scans. A value of 0x000 effectively disables undervoltage checking. Note: For proper operation, this value should always be less than or equal to COMPOVTH. COMPAUXROVTHREG (0x3A) COMPAUXROVTH is a read- and write-accessible register that selects the overvoltage (cold) alert threshold applied during ratiometric auxiliary comparator measurements. BIT 15 14 13 12 11 10 9 8 Field COMPAUXROVTH[11:4] Reset 0xFFF Access Type Write, Read BIT 7 6 5 4 3 2 1 0 Field COMPAUXROVTH[3:0] – – – –

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 243 Reset 0xFFF – – – – Access Type Write, Read – – – – BITFIELD BITS DESCRIPTION COMPAUXROVTH 15:4 Comparator Ratiometric Auxiliary Overvoltage (Cold) Alert Threshold 12-bit overvoltage (cold) threshold value of a input range of VAA above which ALRTCOMPAUXOV alerts will be set/asserted by comparator scans. This threshold is applied for auxiliary measurements where AUXREFSELn = 0 (ratiometric). A value of 0xFFF effectively disables overvoltage checking. Note: For proper operation, this value should always be greater than or equal to COMPAUXRUVTH. COMPAUXRUVTHREG (0x3B) COMPAUXRUVTH is a read- and write-accessible register that selects the undervoltage (hot) alert threshold applied during ratiometric auxiliary comparator measurements. BIT 15 14 13 12 11 10 9 8 Field COMPAUXRUVTH[11:4] Reset 0x000 Access Type Write, Read BIT 7 6 5 4 3 2 1 0 Field COMPAUXRUVTH[3:0] – – – – Reset 0x000 – – – – Access Type Write, Read – – – – BITFIELD BITS DESCRIPTION COMPAUXRUVTH 15:4 Comparator Ratiometric Auxiliary Undervoltage (Hot) Alert Threshold 12-bit undervoltage (hot) threshold value of a input range of VAA below which ALRTCOMPAUXUV alerts will be set/asserted by comparator scans. This threshold is applied for auxiliary measurements where AUXREFSELn = 0 (ratiometric). A value of 0x000 effectively disables undervoltage checking.

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 244 BITFIELD BITS DESCRIPTION Note: For proper operation, this value should always be less than or equal to COMPAUXROVTH. COMPAUXAOVTHREG (0x3C) COMPAUXAOVTH is a read- and write-accessible register that selects the overvoltage alert threshold applied during absolute auxiliary comparator measurements. BIT 15 14 13 12 11 10 9 8 Field COMPAUXAOVTH[11:4] Reset 0xFFF Access Type Write, Read BIT 7 6 5 4 3 2 1 0 Field COMPAUXAOVTH[3:0] – – – – Reset 0xFFF – – – – Access Type Write, Read – – – – BITFIELD BITS DESCRIPTION COMPAUXAOVTH 15:4 Comparator Absolute Auxiliary Overvoltage Alert Threshold 12-bit overvoltage threshold value of an input range of VREF above which ALRTCOMPAUXOV alerts will be set/asserted by comparator scans. This threshold is applied for auxiliary measurements where AUXREFSELn = 1 (absolute). A value of 0xFFF effectively disables overvoltage checking. Note: For normal operation, this value should always be greater than or equal to COMPAUXAUVTH. COMPAUXAUVTHREG (0x3D) COMPAUXAUVTH is a read- and write-accessible register that selects the undervoltage alert threshold applied during absolute auxiliary comparator measurements. BIT 15 14 13 12 11 10 9 8 Field COMPAUXAUVTH[11:4]

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 245 Reset 0x000 Access Type Write, Read BIT 7 6 5 4 3 2 1 0 Field COMPAUXAUVTH[3:0] – – – – Reset 0x000 – – – – Access Type Write, Read – – – – BITFIELD BITS DESCRIPTION COMPAUXAUVTH 15:4 Comparator Absolute Auxiliary Undervoltage Alert Threshold 12-bit undervoltage threshold value of an input range of VREF below which ALRTCOMPAUXUV alerts will be set/asserted by comparator scans. This threshold is applied for auxiliary measurements where AUXREFSELn = 1 (absolute). A value of 0x000 effectively disables undervoltage checking. Note: For proper operation, this value should always be less than or equal to COMPAUXAOVTH. COMPOPNTHREG (0x3E) COMPOPNTH is a read- and write-accessible register that selects the undervoltage alert threshold applied to unipolar cell inputs in Open Diagnostic mode. BIT 15 14 13 12 11 10 9 8 Field COMPOPNTH[11:4] Reset 0x000 Access Type Write, Read BIT 7 6 5 4 3 2 1 0 Field COMPOPNTH[3:0] – – – – Reset 0x000 – – – – Access Type Write, Read – – – –

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 246 BITFIELD BITS DESCRIPTION COMPOPNTH 15:4 Comparator Cell Open Undervoltage Alert Threshold 12-bit threshold of a 5V input range below which ALRTCOMPUV alerts will be set/asserted by comparator scans performed on unipolar cell inputs in Open Diagnostic mode (see CTSTCFG:CELLOPNDIAGSEL). A value of 0x000 effectively disables open undervoltage checking. COMPAUXROPNTHREG (0x3F) COMPAUXROPNTH is a read- and write-accessible register that selects the undervoltage alert threshold applied to ratiometric auxiliary inputs in Open Diagnostic mode. BIT 15 14 13 12 11 10 9 8 Field COMPAUXROPNTH[11:4] Reset 0x000 Access Type Write, Read BIT 7 6 5 4 3 2 1 0 Field COMPAUXROPNTH[3:0] – – – – Reset 0x000 – – – – Access Type Write, Read – – – – BITFIELD BITS DESCRIPTION COMPAUXROPNTH 15:4 Comparator Ratiometric Auxiliary Open Undervoltage Alert Threshold 12-bit undervoltage threshold value of an input range of VAA below which ALRTCOMPAUXUV alerts will be set/asserted by comparator scans performed on ratiometric auxiliary inputs in Open Diagnostic mode (see DIAGGENCFG:AUXDIAGSEL). This threshold is applied for auxiliary measurements where AUXREFSELn = 0 (ratiometric). A value of 0x000 effectively disables undervoltage checking. COMPAUXAOPNTHREG (0x40) COMPAUXAOPNTH is a read- and write-accessible register that selects the undervoltage alert threshold applied to absolute auxiliary inputs in Open Diagnostic mode. BIT 15 14 13 12 11 10 9 8

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 247 Field COMPAUXAOPNTH[11:4] Reset 0x000 Access Type Write, Read BIT 7 6 5 4 3 2 1 0 Field COMPAUXAOPNTH[3:0] – – – – Reset 0x000 – – – – Access Type Write, Read – – – – BITFIELD BITS DESCRIPTION COMPAUXAOPNTH 15:4 Comparator Absolute Auxiliary Open Undervoltage Alert Threshold 12-bit undervoltage threshold value of an input range of VREF below which ALRTCOMPAUXUV alerts will be set/asserted by comparator scans performed on absolute auxiliary inputs in Open Diagnostic mode (see DIAGGENCFG:AUXDIAGSEL). This threshold is applied for auxiliary measurements where AUXREFSELn = 1 (absolute). A value of 0x000 effectively disables undervoltage checking. COMPACCOVTHREG (0x41) COMPACCOVTH is a read- and write-accessible register that selects the overvoltage alert threshold applied during comparator accuracy diagnostics. BIT 15 14 13 12 11 10 9 8 Field COMPACCOVTH[11:4] Reset 0xFFF Access Type Write, Read BIT 7 6 5 4 3 2 1 0 Field COMPACCOVTH[3:0] – – – – Reset 0xFFF – – – – Access Type Write, Read – – – –

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 248 BITFIELD BITS DESCRIPTION COMPACCOVTH 15:4 End-of-Sequence Comparator Accuracy Diagnostic Overvoltage Alert Threshold 12-bit overvoltage threshold value of a 5V input range used to validate the accuracy of the comparator at the end of any measurement sequence using the comparator, if enabled (SCANCFG = 001 or 010 and COMPACCEN = 1). Tested for the Cell Signal Path with COMPIN = VREF through LSA2 (gain = 1/4) and DACREF = VREF. A value above COMPACCOVTH will result in the ALRTCOMPACCOV bit being set/asserted. 0x3FF is the ideal value. A precise value can be selected based on information from the Comparator Cell Signal Path Fault diagnostic. A value of 0xFFF effectively disables overvoltage checking (default). COMPACCUVTHREG (0x42) COMPACCUVTH is a read- and write-accessible register that selects the undervoltage alert threshold applied during comparator accuracy diagnostics. BIT 15 14 13 12 11 10 9 8 Field COMPACCUVTH[11:4] Reset 0x000 Access Type Write, Read BIT 7 6 5 4 3 2 1 0 Field COMPACCUVTH[3:0] – – – – Reset 0x000 – – – – Access Type Write, Read – – – – BITFIELD BITS DESCRIPTION COMPACCUVTH 15:4 End-of-Sequence Comparator Accuracy Diagnostic Undervoltage Alert Threshold 12-bit undervoltage threshold value of a 5V input range used to validate the accuracy of the comparator at the end of any measurement sequence using the comparator, if enabled (SCANCFG = 001 or 010, and COMPACCEN = 1). Tested for the cell signal path with COMPIN = VREF through LSA2 (gain = 1/4) and DACREF = VREF. A value below COMPACCUVTH will result in the ALRTCOMPACCUV bit being set/asserted. 0x3FF is the ideal value. A precise value can be selected based on information from the

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 249 BITFIELD BITS DESCRIPTION Comparator Cell Signal Path Fault diagnostic. A value of 0x000 effectively disables undervoltage checking (default). BALSHRTTHRREG (0x43) BALSHRTTHR is a read- and write-accessible register that selects alert threshold used during the Balance Switch Short Diagnostic mode. BIT 15 14 13 12 11 10 9 8 Field BALSHRTTHR[13:6] Reset 0b00000000000000 Access Type Write, Read BIT 7 6 5 4 3 2 1 0 Field BALSHRTTHR[5:0] – – Reset 0b00000000000000 – – Access Type Write, Read – – BITFIELD BITS DESCRIPTION BALSHRTTHR 15:2 Balance Switch Short Diagnostic Alert Threshold 14-bit undervoltage threshold used for the balancing switch short-circuit diagnostic test (SCANCFG = 100). Unipolar format. For BALSW Short Diagnostics, only cells with (POLARITYn = 0 and CELLENn = 1) are measured and checked. The unipolar ADC cell voltage results taken in this mode are compared against the threshold; if any result is below the threshold, it is flagged as a balancing switch alert (ALRTBALSW). Results above the threshold are considered normal. The threshold should be set by the system controller prior to making a diagnostic measurement. BALLOWTHRREG (0x44) BALLOWTHR is a read- and write-accessible register that selects alert low threshold used during the Balance Switch Open Diagnostic mode. BIT 15 14 13 12 11 10 9 8 Field BALLOWTHR[13:6]

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 250 Reset 0b00000000000000 Access Type Write, Read BIT 7 6 5 4 3 2 1 0 Field BALLOWTHR[5:0] – – Reset 0b00000000000000 – – Access Type Write, Read – – BITFIELD BITS DESCRIPTION BALLOWTHR 15:2 Balance Switch Open Diagnostic Alert Low Threshold 14-bit undervoltage threshold used for the balancing switch conducting and cell sense wire diagnostic tests (SCANCFG = 101, 110, and 111). Bipolar format, typically a small positive value is selected. For BALSW Open Diagnostics, only cells with (POLARITYn = 0 and BALSWENn = 1) are measured and checked. For Cell Sense Open Odd/Even Diagnostics, only odd/even cells at/below TOPCELL1/2 with POLARITYn = 0 and are measured and checked. The bipolar ADC cell results in this mode are compared against the threshold; if any result is below the threshold, it is flagged as a balancing switch alert (ALRTBALSW). Results above the threshold are considered normal. The threshold should be set by the system controller prior to making a diagnostic measurement. BALHIGHTHRREG (0x45) BALHIGHTHR is a read- and write-accessible register that selects alert high threshold used during the Balance Switch Open Diagnostic mode. BIT 15 14 13 12 11 10 9 8 Field BALHIGHTHR[13:6] Reset 0b00000000000000 Access Type Write, Read BIT 7 6 5 4 3 2 1 0 Field BALHIGHTHR[5:0] – – Reset 0b00000000000000 – – Access Type Write, Read – –

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 251 BITFIELD BITS DESCRIPTION BALHIGHTHR 15:2 Balance Switch Open Diagnostic Alert High Threshold 14-bit overvoltage threshold used for the balancing switch conducting and cell sense wire diagnostic tests (SCANCFG = 101, 110, 111). Bipolar format, typically a moderate positive value, is selected based on external resistor characteristics. For BALSW Open Diagnostics, only cells with (POLARITYn = 0 and BALSWENn = 1) are measured and checked. For Cell Sense Open Odd/Even Diagnostics, only odd/even cells at/below TOPCELL1/2 with POLARITYn = 0 and are measured and checked. The bipolar ADC cell results in this mode are compared against the threshold; if any result is above the threshold, it is flagged as a balancing switch alert (ALRTBALSW). Results below the threshold are considered normal. The threshold should be set by the system controller prior to making a diagnostic measurement. CELL1REG (0x47) CELLn is a read-accessible register that holds the current value for each individual cell measurement result. BIT 15 14 13 12 11 10 9 8 Field CELL1[13:6] Reset 0b00000000000000 Access Type Read Only BIT 7 6 5 4 3 2 1 0 Field CELL1[5:0] – – Reset 0b00000000000000 – – Access Type Read Only – – BITFIELD BITS DESCRIPTION CELL1 15:2 Cell Voltage Measurement Result CELLn[13:0] contains the 14-bit measurement result for CELLn. Full-scale input range of 5V. If CELLEN = 0 and the measurement was skipped during the latest ADC scan, no internal data is updated and ALU/IIR readback will be determined by RDFILT. Read only.

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 252 CELL2REG (0x48) CELLn is a read-accessible register that holds the current value for each individual cell measurement result. BIT 15 14 13 12 11 10 9 8 Field CELL2[13:6] Reset 0b00000000000000 Access Type Read Only BIT 7 6 5 4 3 2 1 0 Field CELL2[5:0] – – Reset 0b00000000000000 – – Access Type Read Only – – BITFIELD BITS DESCRIPTION CELL2 15:2 Cell Voltage Measurement Result CELLn[13:0] contains the 14-bit measurement result for CELLn. Full-scale input range of 5V. If CELLEN = 0 and the measurement was skipped during the latest ADC scan, no internal data is updated and ALU/IIR readback will be determined by RDFILT. Read only. CELL3REG (0x49) CELLn is a read-accessible register that holds the current value for each individual cell measurement result. BIT 15 14 13 12 11 10 9 8 Field CELL3[13:6] Reset 0b00000000000000 Access Type Read Only BIT 7 6 5 4 3 2 1 0 Field CELL3[5:0] – – Reset 0b00000000000000 – –

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 253 Access Type Read Only – – BITFIELD BITS DESCRIPTION CELL3 15:2 Cell Voltage Measurement Result CELLn[13:0] contains the 14-bit measurement result for CELLn. Full-scale input range of 5V. If CELLEN = 0 and the measurement was skipped during the latest ADC scan, no internal data is updated and ALU/IIR readback will be determined by RDFILT. Read only. CELL4REG (0x4A) CELLn is a read-accessible register that holds the current value for each individual cell measurement result. BIT 15 14 13 12 11 10 9 8 Field CELL4[13:6] Reset 0b00000000000000 Access Type Read Only BIT 7 6 5 4 3 2 1 0 Field CELL4[5:0] – – Reset 0b00000000000000 – – Access Type Read Only – – BITFIELD BITS DESCRIPTION CELL4 15:2 Cell Voltage Measurement Result CELLn[13:0] contains the 14-bit measurement result for CELLn. Full-scale input range of 5V. If CELLEN = 0 and the measurement was skipped during the latest ADC scan, no internal data is updated and ALU/IIR readback will be determined by RDFILT. Read only.

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 254 CELL5REG (0x4B) CELLn is a read-accessible register that holds the current value for each individual cell measurement result. BIT 15 14 13 12 11 10 9 8 Field CELL5[13:6] Reset 0b00000000000000 Access Type Read Only BIT 7 6 5 4 3 2 1 0 Field CELL5[5:0] – – Reset 0b00000000000000 – – Access Type Read Only – – BITFIELD BITS DESCRIPTION CELL5 15:2 Cell Voltage Measurement Result CELLn[13:0] contains the 14-bit measurement result for CELLn. Full-scale input range of 5V. If CELLEN = 0 and the measurement was skipped during the latest ADC scan, no internal data is updated and ALU/IIR readback will be determined by RDFILT. Read only. CELL6REG (0x4C) CELLn is a read-accessible register that holds the current value for each individual cell measurement result. BIT 15 14 13 12 11 10 9 8 Field CELL6[13:6] Reset 0b00000000000000 Access Type Read Only BIT 7 6 5 4 3 2 1 0 Field CELL6[5:0] – – Reset 0b00000000000000 – –

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 255 Access Type Read Only – – BITFIELD BITS DESCRIPTION CELL6 15:2 Cell Voltage Measurement Result CELLn[13:0] contains the 14-bit measurement result for CELLn. Full-scale input range of 5V. If CELLEN = 0 and the measurement was skipped during the latest ADC scan, no internal data is updated and ALU/IIR readback will be determined by RDFILT. Read only. CELL7REG (0x4D) CELLn is a read-accessible register that holds the current value for each individual cell measurement result. BIT 15 14 13 12 11 10 9 8 Field CELL7[13:6] Reset 0b00000000000000 Access Type Read Only BIT 7 6 5 4 3 2 1 0 Field CELL7[5:0] – – Reset 0b00000000000000 – – Access Type Read Only – – BITFIELD BITS DESCRIPTION CELL7 15:2 Cell Voltage Measurement Result CELLn[13:0] contains the 14-bit measurement result for CELLn. Full-scale input range of 5V. If CELLEN = 0 and the measurement was skipped during the latest ADC scan, no internal data is updated and ALU/IIR readback will be determined by RDFILT. Read only.

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 256 CELL8REG (0x4E) CELLn is a read-accessible register that holds the current value for each individual cell measurement result. BIT 15 14 13 12 11 10 9 8 Field CELL8[13:6] Reset 0b00000000000000 Access Type Read Only BIT 7 6 5 4 3 2 1 0 Field CELL8[5:0] – – Reset 0b00000000000000 – – Access Type Read Only – – BITFIELD BITS DESCRIPTION CELL8 15:2 Cell Voltage Measurement Result CELLn[13:0] contains the 14-bit measurement result for CELLn. Full-scale input range of 5V. If CELLEN = 0 and the measurement was skipped during the latest ADC scan, no internal data is updated and ALU/IIR readback will be determined by RDFILT. Read only. CELL9REG (0x4F) CELLn is a read-accessible register that holds the current value for each individual cell measurement result. BIT 15 14 13 12 11 10 9 8 Field CELL9[13:6] Reset 0b00000000000000 Access Type Read Only BIT 7 6 5 4 3 2 1 0 Field CELL9[5:0] – – Reset 0b00000000000000 – –

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 257 Access Type Read Only – – BITFIELD BITS DESCRIPTION CELL9 15:2 Cell Voltage Measurement Result CELLn[13:0] contains the 14-bit measurement result for CELLn. Full-scale input range of 5V. If CELLEN = 0 and the measurement was skipped during the latest ADC scan, no internal data is updated and ALU/IIR readback will be determined by RDFILT. Read only. CELL10REG (0x50) CELLn is a read-accessible register that holds the current value for each individual cell measurement result. BIT 15 14 13 12 11 10 9 8 Field CELL10[13:6] Reset 0b00000000000000 Access Type Read Only BIT 7 6 5 4 3 2 1 0 Field CELL10[5:0] – – Reset 0b00000000000000 – – Access Type Read Only – – BITFIELD BITS DESCRIPTION CELL10 15:2 Cell Voltage Measurement Result CELLn[13:0] contains the 14-bit measurement result for CELLn. Full-scale input range of 5V. If CELLEN = 0 and the measurement was skipped during the latest ADC scan, no internal data is updated and ALU/IIR readback will be determined by RDFILT. Read only.

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 258 CELL11REG (0x51) CELLn is a read-accessible register that holds the current value for each individual cell measurement result. BIT 15 14 13 12 11 10 9 8 Field CELL11[13:6] Reset 0b00000000000000 Access Type Read Only BIT 7 6 5 4 3 2 1 0 Field CELL11[5:0] – – Reset 0b00000000000000 – – Access Type Read Only – – BITFIELD BITS DESCRIPTION CELL11 15:2 Cell Voltage Measurement Result CELLn[13:0] contains the 14-bit measurement result for CELLn. Full-scale input range of 5V. If CELLEN = 0 and the measurement was skipped during the latest ADC scan, no internal data is updated and ALU/IIR readback will be determined by RDFILT. Read only. CELL12REG (0x52) CELLn is a read-accessible register that holds the current value for each individual cell measurement result. BIT 15 14 13 12 11 10 9 8 Field CELL12[13:6] Reset 0b00000000000000 Access Type Read Only BIT 7 6 5 4 3 2 1 0 Field CELL12[5:0] – – Reset 0b00000000000000 – –

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 259 Access Type Read Only – – BITFIELD BITS DESCRIPTION CELL12 15:2 Cell Voltage Measurement Result CELLn[13:0] contains the 14-bit measurement result for CELLn. Full-scale input range of 5V. If CELLEN = 0 and the measurement was skipped during the latest ADC scan, no internal data is updated and ALU/IIR readback will be determined by RDFILT. Read only. CELL13REG (0x53) CELLn is a read-accessible register that holds the current value for each individual cell measurement result. BIT 15 14 13 12 11 10 9 8 Field CELL13[13:6] Reset 0b00000000000000 Access Type Read Only BIT 7 6 5 4 3 2 1 0 Field CELL13[5:0] – – Reset 0b00000000000000 – – Access Type Read Only – – BITFIELD BITS DESCRIPTION CELL13 15:2 Cell Voltage Measurement Result CELLn[13:0] contains the 14-bit measurement result for CELLn. Full-scale input range of 5V. If CELLEN = 0 and the measurement was skipped during the latest ADC scan, no internal data is updated and ALU/IIR readback will be determined by RDFILT. Read only.

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 260 CELL14REG (0x54) CELLn is a read-accessible register that holds the current value for each individual cell measurement result. BIT 15 14 13 12 11 10 9 8 Field CELL14[13:6] Reset 0b00000000000000 Access Type Read Only BIT 7 6 5 4 3 2 1 0 Field CELL14[5:0] – – Reset 0b00000000000000 – – Access Type Read Only – – BITFIELD BITS DESCRIPTION CELL14 15:2 Cell Voltage Measurement Result CELLn[13:0] contains the 14-bit measurement result for CELLn. Full-scale input range of 5V. If CELLEN = 0 and the measurement was skipped during the latest ADC scan, no internal data is updated and ALU/IIR readback will be determined by RDFILT. Read only. BLOCKREG (0x55) BLOCK is a read-accessible register that holds the current value for the total block measurement result. BIT 15 14 13 12 11 10 9 8 Field VBLOCK[13:6] Reset 0b00000000000000 Access Type Read Only BIT 7 6 5 4 3 2 1 0 Field VBLOCK[5:0] – – Reset 0b00000000000000 – –

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 261 Access Type Read Only – – BITFIELD BITS DESCRIPTION VBLOCK 15:2 Block Voltage Measurement Result VBLOCK[13:0] contains the 14-bit measurement result for VBLK. Full-scale input range of 65V. If BLOCKEN = 0 and the measurement was skipped during the latest ADC scan, no internal data is updated and ALU/IIR readback will be determined by RDFILT. Read only. TOTALREG (0x56) TOTAL is a read-accessible register that holds the current value for the sum of all enabled measurement results within the stack. BIT 15 14 13 12 11 10 9 8 Field TOTAL[15:8] Reset 0x0000 Access Type Read Only BIT 7 6 5 4 3 2 1 0 Field TOTAL[7:0] Reset 0x0000 Access Type Read Only BITFIELD BITS DESCRIPTION TOTAL 15:0 Total Cell Voltage Measurement Result TOTAL[15:0] contains the 16-bit sum of all cell measurement results enabled during the last scan by MEASUREEN1. Full-scale range is 0.0 to 80.0V with a 1.22mV LSB (unipolar). Read only. Note the following behavior: Since disabled measurements retain their last results, it is possible there will be data in the result registers that was not included in the TOTAL result calculated for the last scan.

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 262 BITFIELD BITS DESCRIPTION If cell and bus-bar (unipolar and bipolar) measurements are mixed within a scan, the summation will be handled accordingly. Totals below 0V cannot be supported and will be clipped at 0x0000 (this may apply to scans using only bipolar measurements). DIAG1REG (0x57) DIAG1 is a read-only register that contains the diagnostic result requested by the DIAGCFG:DIAGSEL1 selection taken during the last ADC acquisition. BIT 15 14 13 12 11 10 9 8 Field DIAG1[13:6] Reset 0b00000000000000 Access Type Read Only BIT 7 6 5 4 3 2 1 0 Field DIAG1[5:0] – – Reset 0b00000000000000 – – Access Type Read Only – – BITFIELD BITS DESCRIPTION DIAG1 15:2 DIAG1 contains the 14-bit measurement result for the diagnostic selected by DIAGCFG:DIAGSEL1. DIAG2REG (0x58) DIAG2 is a read-only register that contains the diagnostic result requested by the DIAGCFG:DIAGSEL2 selection taken during the last ADC acquisition. BIT 15 14 13 12 11 10 9 8 Field DIAG2[13:6] Reset 0b00000000000000 Access Type Read Only BIT 7 6 5 4 3 2 1 0

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 263 Field DIAG2[5:0] – – Reset 0b00000000000000 – – Access Type Read Only – – BITFIELD BITS DESCRIPTION DIAG2 15:2 DIAG2 contains the 14-bit measurement result for the diagnostic selected by DIAGCFG:DIAGSEL2. AUX0REG (0x59) AUXn is a read-accessible register that holds the current value for each enabled individual auxiliary measurement result. BIT 15 14 13 12 11 10 9 8 Field AUX0[13:6] Reset 0b00000000000000 Access Type Read Only BIT 7 6 5 4 3 2 1 0 Field AUX0[5:0] – – Reset 0b00000000000000 – – Access Type Read Only – – BITFIELD BITS DESCRIPTION AUX0 15:2 Auxiliary Voltage Measurement Result AUXn[13:0] contains the 14-bit measurement result for AUXn. Full-scale input range of VAA for ratiometric operation, VREF for absolute operation. If the port is not configured as an AUXINn input (see AUXGPIOCFG), the result will read back 0x0000 for the unused channel. Otherwise if AUXEN = 0 and the measurement was skipped during the latest ADC scan, the previously determined result will remain. Read only. AUX1REG (0x5A) AUXn is a read-accessible register that holds the current value for each enabled individual auxiliary measurement result.

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 264 BIT 15 14 13 12 11 10 9 8 Field AUX1[13:6] Reset 0b00000000000000 Access Type Read Only BIT 7 6 5 4 3 2 1 0 Field AUX1[5:0] – – Reset 0b00000000000000 – – Access Type Read Only – – BITFIELD BITS DESCRIPTION AUX1 15:2 Auxiliary Voltage Measurement Result AUXn[13:0] contains the 14-bit measurement result for AUXn. Full-scale input range of VAA for ratiometric operation, VREF for absolute operation. If the port is not configured as an AUXINn input (see AUXGPIOCFG), the result will read back 0x0000 for the unused channel. Otherwise if AUXEN = 0 and the measurement was skipped during the latest ADC scan, the previously determined result will remain. Read only. AUX2REG (0x5B) AUXn is a read-accessible register that holds the current value for each enabled individual auxiliary measurement result. BIT 15 14 13 12 11 10 9 8 Field AUX2[13:6] Reset 0b00000000000000 Access Type Read Only BIT 7 6 5 4 3 2 1 0 Field AUX2[5:0] – – Reset 0b00000000000000 – – Access Type Read Only – –

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 265 BITFIELD BITS DESCRIPTION AUX2 15:2 Auxiliary Voltage Measurement Result AUXn[13:0] contains the 14-bit measurement result for AUXn. Full-scale input range of VAA for ratiometric operation, VREF for absolute operation. If the port is not configured as an AUXINn input (see AUXGPIOCFG), the result will read back 0x0000 for the unused channel. Otherwise if AUXEN = 0 and the measurement was skipped during the latest ADC scan, the previously determined result will remain. Read only. AUX3REG (0x5C) AUXn is a read-accessible register that holds the current value for each enabled individual auxiliary measurement result. BIT 15 14 13 12 11 10 9 8 Field AUX3[13:6] Reset 0b00000000000000 Access Type Read Only BIT 7 6 5 4 3 2 1 0 Field AUX3[5:0] – – Reset 0b00000000000000 – – Access Type Read Only – – BITFIELD BITS DESCRIPTION AUX3 15:2 Auxiliary Voltage Measurement Result AUXn[13:0] contains the 14-bit measurement result for AUXn. Full-scale input range of VAA for ratiometric operation, VREF for absolute operation. If the port is not configured as an AUXINn input (see AUXGPIOCFG), the result will read back 0x0000 for the unused channel. Otherwise if AUXEN = 0 and the measurement was skipped during the latest ADC scan, the previously determined result will remain. Read only.

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 266 AUX4REG (0x5D) AUXn is a read-accessible register that holds the current value for each enabled individual auxiliary measurement result. BIT 15 14 13 12 11 10 9 8 Field AUX4[13:6] Reset 0b00000000000000 Access Type Read Only BIT 7 6 5 4 3 2 1 0 Field AUX4[5:0] – – Reset 0b00000000000000 – – Access Type Read Only – – BITFIELD BITS DESCRIPTION AUX4 15:2 Auxiliary Voltage Measurement Result AUXn[13:0] contains the 14-bit measurement result for AUXn. Full-scale input range of VAA for ratiometric operation, VREF for absolute operation. If the port is not configured as an AUXINn input (see AUXGPIOCFG), the result will readback 0x0000 for the unused channel. Otherwise, if AUXEN = 0 and the measurement was skipped during the latest ADC scan, the previously determined result will remain. Read only. AUX5REG (0x5E) AUXn is a read-accessible register that holds the current value for each enabled individual auxiliary measurement result. BIT 15 14 13 12 11 10 9 8 Field AUX5[13:6] Reset 0b00000000000000 Access Type Read Only BIT 7 6 5 4 3 2 1 0

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 267 Field AUX5[5:0] – – Reset 0b00000000000000 – – Access Type Read Only – – BITFIELD BITS DESCRIPTION AUX5 15:2 Auxiliary Voltage Measurement Result AUXn[13:0] contains the 14-bit measurement result for AUXn. Full-scale input range of VAA for ratiometric operation, VREF for absolute operation. If the port is not configured as an AUXINn input (see AUXGPIOCFG), the result will read back 0x0000 for the unused channel. Otherwise, if AUXEN = 0 and the measurement was skipped during the latest ADC scan, the previously determined result will remain. Read only. POLARITYCTRL (0x5F) POLARITYCTRL is a read- and write-accessible register that governs the measurement type used during scans. In general, unipolar mode indicates a cell, and bipolar mode indicates a bus bar. BIT 15 14 13 12 11 10 9 8 Field MINMAXPOL – POLARITY[14:9] Reset 0b0 – 0b00000000000000 Access Type Write, Read – Write, Read BIT 7 6 5 4 3 2 1 0 Field POLARITY[8:1] Reset 0b00000000000000 Access Type Write, Read BITFIELD BITS DESCRIPTION MINMAXPOL 15 MIN/MAX Operating Mode 0 = Only Unipolar Cell Measurements are Included in MINCELL, MAXCELL, and ALRTMSMTCH Calculations (default) 1 = Only Bipolar Cell Measurements are Included in MINCELL, MAXCELL, and ALRTMSMTCH Calculations (useful in fuel cell applications) POLARITY 13:0 Cell Measurement Polarity Selection 0 = Unipolar 0 to 5V Input Range (default)

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 268 BITFIELD BITS DESCRIPTION 1 = Bipolar -2.5V to 2.5V Input Bipolar cells will be fault masked during BALSWDIAG ADC measurement scans. MINMAXPOL determines whether bipolar cells are included in MIN/MAXCELL and ALRTMSMTCH calculations. Bipolar cell measurements will be checked against BIPOVTH and BIPUVTH thresholds rather than OVTH and UVTH thresholds. Bipolar cells will not be included in comparator measurement scans: ALRTCOMPOV, ALRTCOMPUV, alerts will not be triggered. AUXREFCTRL (0x60) AUXREFCTRL is a read- and write-accessible register that governs the reference range used for enabled auxiliary channels during ADC and COMP acquisition sequences. BIT 15 14 13 12 11 10 9 8 BIT 7 6 5 4 3 2 1 0 Field – – AUXREFSEL[5:4] AUXREFSEL[3:0] Reset – – 0b00 0x0 Access Type – – Write, Read, Ext Write, Read, Ext BITFIELD BITS DESCRIPTION AUXREFSEL 5:4 Auxiliary Input Reference Selection 0 = Ratiometric, REF = VTHRM (default) 1 = Absolute, REF = VREF = 1.25V This bit selects the reference used and which set of AUX OV, UV, and OPN thresholds are used during ADC and comparator acquisition sequences. Note: If the respective GPIOEN bit is set (GPIO mode), this bit is ignored, but it will still read back the user setting. AUXREFSEL 3:0 Auxiliary Input Reference Selection 0 = Ratiometric, REF = VTHRM (default) 1 = Absolute, REF = VREF = 1.25V

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 269 BITFIELD BITS DESCRIPTION This bit selects the reference used and which set of AUX OV, UV, and OPN thresholds are used during ADC and comparator acquisition sequences. Note: If the I2CEN bit (Digital I2C mode, applies to [1:0] only), or the respective GPIOEN bit is set (GPIO mode), this bit is ignored, but will still read back the user setting. AUXTIMEREG (0x61) AUXTIMEREG is a read- and write-accessible register that governs the settling time allowed for biasing AUX/GPIO pins prior to measurements. BIT 15 14 13 12 11 10 9 8 Field – – – – – – AUXTIME[9:8] Reset – – – – – – 0b0000000000 Access Type – – – – – – Write, Read BIT 7 6 5 4 3 2 1 0 Field AUXTIME[7:0] Reset 0b0000000000 Access Type Write, Read BITFIELD BITS DESCRIPTION AUXTIME 9:0 AUX Preconversion Settling TIme Configures the preconversion settling time for all enabled AUXn inputs from 0µs (default) up to 6.138ms according to the equation: tSettle = (AUXTIME[9:0]) * 6µs This is to allow extra settling time if the application circuit requires it, since the THRM voltage is not driven out until the start of the acquisition (in auto mode). This time is inserted at the beginning of each requested scan. If AUXTIME has not expired, but no other scan measurement is active, the HVCP will be refreshed during AUXTIME. ACQCFG (0x62) ACQCFG is a read- and write-accessible register that governs several aspects of the measurement and acquisition procedure. BIT 15 14 13 12 11 10 9 8

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 270 Field ADCZSFSEN ADCCALEN COMPACCEN FOSR[1:0] THRMMODE[1:0] – Reset 0b0 0b0 0b0 0b00 0b00 – Access Type Write, Read Write, Read Write, Read Write, Read Write, Read – BIT 7 6 5 4 3 2 1 0 BITFIELD BITS DESCRIPTION ADCZSFSEN 15 End-of-Sequence ADC Stuck-at-Fault Diagnostic Enable 0 = Disable ADC ZS/FS Diagnostics (default) 1 = Enable ADC ZS/FS Diagnostics If enabled, at the end of any measurement sequence using the ADC (SCANCFG != 010), the ADC will automatically be tested with overdriven inputs designed to force outputs to zero-scale and full-scale. Any result other than 0x000 or 0xFFF will be reported through ALRTADCZS and ALRTADCFS, respectively. ADCCALEN 14 ADC Calibration Enable 0 = Calibration Not Applied to Scan Results 1 = Calibration Applied to Scan Results Does not impact comparator operations. COMPACCEN 13 End-of-Sequence Comparator Accuracy Diagnostic Enable 0 = Disable COMPACC Diagnostics (default) 1 = Enable COMPACC Diagnostics If enabled, at the end of any measurement sequence using the comparator (SCANCFG = 001 or 010), the comparator will automatically be tested with COMPIN = VREF through the LSA2 path (gain = 1/4) and DACREF = VREF against bracketing thresholds COMPACCOVTHR and COMPACCUVTHR. If an unexpected result is found, ALRTCOMPACCOV or ALRTCOMPACCUV will be issued. FOSR 12:11 Oversampling Frequency Selection 00 = fOSR = Frequency Determined by Selected Features 01 = fOSR = 1.60kHz, Useful for 50Hz Rejection 1x = fOSR = 1.92kHz, Useful for 60Hz Rejection For ADC and comparator scans, fOSR sets a specific effective sampling frequency for use with oversampled acquisitions (OVSAMPL > 000). This can be used to place nulls at n x (fOSR/OSR) to help reject noise at a given frequency. For example, with fOSR = 1.60kHz and OSR = 32, noise at 50Hz and its harmonics can be attenuated. Selection of 00 results in an arbitrary but maximum effective sampling frequency

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 271 BITFIELD BITS DESCRIPTION determined solely by the number of channels and diagnostics selected for measurement, in addition to analog overhead operations (such as HVCP refresh). Worst case is estimated at 2.2kHz with all features enabled. THRMMODE 10:9 Thermistor Bias Control Mode Controls application of VAA to the THRM pin through the internal switch to bias external thermistors for measurement. 0x - Automatic Mode (Switch ON During Acquisition Mode) 10 - Manual Off Mode (Switch Always OFF) 11 - Manual On Mode (Switch Always ON) BALSWDLY (0x63) BALSWDLY is a read- and write-accessible register that selects the delay intervals used within Manual and Automated Cell-Balancing operations when ADC measurements are requested. BIT 15 14 13 12 11 10 9 8 Field CELLDLY[7:0] Reset 0x00 Access Type Write, Read BIT 7 6 5 4 3 2 1 0 Field SWDLY[7:0] Reset 0x00 Access Type Write, Read BITFIELD BITS DESCRIPTION CELLDLY 15:8 Cell-Balancing Cell Path Recovery Delay Selection Time delay for C[n] (HVMUX) recovery from voltage drop during cell balancing prior to ADC measurement. Values of 0μs (default) to 24.480ms can be realized (96μs step size). This delay is used in Manual Cell-Balancing modes when using AUTOBALSWDIS = 1 and ALTMUXSEL = 0. Also used in Automatic Cell-Balancing and Discharge modes after each pair of even and odd discharge cycles when CBMEASEN = 1x and ALTMUXSEL = 0. SWDLY 7:0 Cell-Balancing Switch Path Recovery Delay Selection Time delay for SW[n] (ALTMUX) recovery from voltage drop during cell balancing prior

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 272 BITFIELD BITS DESCRIPTION to ADC measurement. Values of 0μs (default) to 24.480ms can be realized (96μs step size). This delay is used in Manual Cell-Balancing modes when using AUTOBALSWDIS = 1 and ALTMUXSEL = 1. Also used in Automatic Cell-Balancing and Discharge modes after each pair of even and odd discharge cycles when CBMEASEN = 1x and ALTMUXSEL = 1. MEASUREEN1 (0x64) MEASUREEN1 is a read- and write-accessible register that governs the channels measured during ADC and COMP acquisition sequences. BIT 15 14 13 12 11 10 9 8 Field – BLOCKEN CELLEN[14:9] Reset – 0b0 0b00000000000000 Access Type – Write, Read Write, Read BIT 7 6 5 4 3 2 1 0 Field CELLEN[8:1] Reset 0b00000000000000 Access Type Write, Read BITFIELD BITS DESCRIPTION BLOCKEN 14 Block Voltage Measurement Enable 0 = Disable VBLK/TOPBLOCK Measurement and Automatic Divider Connection (default) 1 = Enable VBLK/TOPBLOCK Measurement and Automatic Divider Connection Applies to ADC scans only; block is not subject to comparator measurements. In addition to enabling the ADC measurement, BLOCKEN will automatically engage the VBLOCK resistive divider for the duration of the scan. Note: In flexible-pack applications (FLXPCKEN1/2 = 1), the resistive divider is connected to a selected Cn pin, and the resulting bias current will impact the Cn result. Therefore, in flexible-pack applications, it is generally recommended to set BLOCKEN = 1 only for scans with ALTMUXSEL = 1. CELLEN 13:0 Cell Voltage Measurement Enable 0 = Disable CELLn Measurement (default)

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 273 BITFIELD BITS DESCRIPTION 1 = Enable CELLn Measurement Enables measurement of the respective cell in Acquisition mode. MEASUREEN2 (0x65) MEASUREEN2 is a read- and write-accessible register that governs the auxiliary channels measured during ADC and COMP acquisition sequences, as well as IIR initialization. BIT 15 14 13 12 11 10 9 8 Access Type Write, Read – – – – – – – BIT 7 6 5 4 3 2 1 0 Field – – AUXEN[5:4] AUXEN[3:0] Reset – – 0b00 0x0 Access Type – – Write, Read, Ext Write, Read, Ext BITFIELD BITS DESCRIPTION SCANIIRINIT 15 Sequencer IIR Initialization Request 0 = IIR Filter Continuation (default) 1 = IIR Filter Initialized In Continuation mode, the current value in the IIR accumulators is kept (presumably from previous cell measurements) and sequencer measurements are amended normally. In Initialization mode, the IIR accumulators will be reinitialized to the first measurement taken, and further cell-balancing measurements are amended normally. AUXEN 5:4 Auxiliary Input Measurement Enable 0 = Auxiliary ADC Measurement Disabled (default) 1 = Auxiliary ADC Measurement Enabled Enables measurement of the respective auxiliary inputs in Acquisition mode. Note: If the respective GPIOEN bit is set (GPIO mode), this bit is ignored, but will still read back the user setting. AUXEN 3:0 Auxiliary Input Measurement Enable 0 = Auxiliary ADC Measurement Disabled (default) 1 = Auxiliary ADC Measurement Enabled

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 274 BITFIELD BITS DESCRIPTION Enables measurement of the respective auxiliary inputs in Acquisition mode. Note: If the I2CEN bit (Digital I2C mode, applies to [1:0] only) or the respective GPIOEN bit is set (GPIO mode), this bit is ignored, but will still read back the user setting. SCANCTRL (0x66) SCANCTRL is a read- and write-accessible register which governs the internal measurement acquisitions (scan) requested of the device. The register also manages the handling of data generated as a result of any scan request. ADC scans are used for precision measurements of cell and auxiliary voltages. COMP scans are used for periodic safety/redundancy checking of ADC results and, in some cases, enhanced communication efficiency. On-Demand Calibration will run an internal calibration of the ADC and update the Calibration Data registers. All ADC measurements requested by Scan and Diagnostic Configuration and Control settings will be ignored. Balance Switch and Cell Sense-Wire Open ADC Diagnostic scans are a special class of ADC scan. Use of these settings temporarily overrides other Scan and Diagnostic Configuration and Control settings. See the BALSW Diagnostics section for details. BIT 15 14 13 12 11 10 9 8 Field SCANDONE SCANTIMEOUT DATARDY AUTOBALSWDIS ALRTFILTSEL AMENDFILT RDFILT SCANCFG[2] Reset 0b0 0b0 0b0 0b0 0b0 0b0 0b0 0b000 Access Type Write 0 to Clear, Read Write 0 to Clear, Read Write, Read, Ext Write, Read Write, Read Write, Read Write, Read Write, Read BIT 7 6 5 4 3 2 1 0 Field SCANCFG[1:0] OVSAMPL[2:0] ALTMUXSEL SCANMODE SCAN Reset 0b000 0b000 0b0 0b0 0b0 Access Type Write, Read Write, Read Write, Read Write, Read Write, Read, Pulse BITFIELD BITS DESCRIPTION SCANDONE 15 Acquisition Complete Indicator Bit 0 = Indicates an SCAN Acquisition is in Progress if Requested 1 = Indicates the SCAN Acquisition has Completed Once a SCAN acquisition is completed, the device will set this bit high to indicate completion.

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 275 BITFIELD BITS DESCRIPTION This bit is cleared by writing to 0. When this bit is high, further acquisitions requested using SCAN will be ignored. Writing to logic 1 has no internal effect. SCANTIMEOUT 14 Scan Timeout Indicator Bit Indicates the acquisition did not complete in the expected period of time. The timeout threshold depends on the oversampling configuration. If a SCANTIMEOUT is issued, the resulting partial data should be treated as suspect and ignored. In applications using the IIR, SCANIIRINIT should be issued to avoid any corruption resulting from the timeout event. The acquisition watchdog can be disabled by setting SCANTODIS in the DEVCFG2 register. Cleared by writing to logic 0 to allow detection of future timeout events. Writing to logic 1 has no internal effect. DATARDY 13 Data Ready Indicator Bit Indicates the measurement data from the acquisition has been transferred from the ALU to the data registers and may now be read. Data for all measurement registers and MIN/MAX/TOTAL is transferred at the same time. Cleared by writing to logic 0 to allow detection of the next data transfer. Writing to logic 1 has no internal effect. AUTOBALSWDIS 12 Automatic Balancing Switch Disable 0 = Cell-Balancing Operations not Impacted by Measurement Sequences (default) 1 = Cell-Balancing Manual Operations Temporarily Disabled during Measurement Sequences Enables automatic suspension of active manual cell-balancing operations during measurement sequences. The delay for cell recovery settling time and for the diagnostic recovery is selected automatically based on the ALTMUXSEL setting for the sequence as follows: 0 = CELLDLY is used 1 = SWDLY is used ALRTFILTSEL 11 Alert Filtering Selection 0 = Alert Issuance Based on Raw Sequencer Results (default) 1 = Alert Issuance Based on IIR Filter Results Determines whether the cell and block alerts are issued based on raw sequencer outputs (oversampling still applies) or IIR filtered outputs. If mode 1 is selected, MEASUREEN2:SCANIIRINIT should be used with the first scan to avoid triggering false alerts due to the IIR settling behavior. Note: This bit is ignored for measurement scans taken in automated cell-balancing modes (ALRTFILTSEL = 1 is used).

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 276 BITFIELD BITS DESCRIPTION AMENDFILT 10 Amend IIR Filter Enable 0 = ADC result is not included in the IIR accumulator (default). 1 = ADC result is included in the IIR accumulator. When set high, for ADC outputs that have IIR filters/accumulators, the new ADC conversion in the ALU is automatically scaled and transferred into the IIR accumulator at the end of the sequence. This is most often used for normal measurement sequences. When set low, the new ADC conversion in the ALU is not transferred into the IIR accumulator at the end of the sequence. This is most often used for diagnostic measurement sequences where the ADC result would corrupt the settled normal data. Note: This bit is ignored for measurement scans taken in automated cell-balancing modes (AMENDFILT = 1 is used). RDFILT 9 Read IIR Filter Selection 0 = Unfiltered ADC data is loaded into the output data registers (default). 1 = IIR Filtered ADC data is loaded into the output data registers. This bit chooses the source for data loaded to the cell and block registers for readback. The setting of this bit at the time of a measurement scan request (SCAN = 1) also determines the source data (filtered/unfiltered) used for TOTAL, MINCELL, MAXCELL, MSMTCH, and all OV/UV alert computations. SCANCFG 8:6 Scan Configuration Selects the type of scan to be performed based on the selections below. FOSR selection applies to all scans where oversampling applies. 000 = ADC only Scan 001 = ADC + COMP Scan (Pyramid only) 010 = COMP only Scan (Pyramid only) 011 = On-Demand Calibration 100 = Balancing Switch Short 101 = Balancing Switch Open 110 = Cell Sense Open Odds 111 = Cell Sense Open Evens Some of these selections are formatted by other register content. Some of these selections will temporarily modify/override other register content. See the register descriptions for further details. For COMP scans, polarity is always defaulted to unipolar, any cell measurements requested in bipolar mode will be skipped. On-Demand Calibration executes an automated routine that will update the contents of the CALOSADC, CALOSR, CALOSTHRM, CALGAINP, and CALGAINR correction coefficients. No other measurements are taken during this operation. Note: This bitfield is ignored for measurement scans taken in Automated Cell-Balancing modes (SCANCFG = 000 is used).

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 277 BITFIELD BITS DESCRIPTION OVSAMPL 5:3 Oversampling Selection for ADC Acquisitions 000 = Single Acquisition 001 = 4x Oversampling 010 = 8x Oversampling 011 = 16x Oversampling 100 = 32x Oversampling 101 = 64x Oversampling 11x = 128x Oversampling Note: This bitfield is ignored during calibration (SCANCFG = 011) scans. This bitfield is ignored for measurement scans taken in Automated Cell-Balancing modes (OVSAMPL = 011 is used). ALTMUXSEL 2 Cell Measurement Path Selection 0 = HVMUX Signal Path (default) 1 = ALTMUX Signal Path See the Diagnostics section. Note: Where ALTMUX settings disagree with SCANCFG (BALSWDIAG), SCANCFG takes precedence. SCANMODE 1 ADC Scan Mode Selection 0 = Pyramid Scan Mode (default) 1 = Ramp Scan Mode Ramp Scan mode is not supported for scans using the comparator or calibration scan requests - the setting will be ignored in these modes. Note: This bit is ignored for measurement scans taken in Automated Cell-Balancing modes (SCANMODE = 0 is used). SCAN 0 Scan (Measurement Sequence) Request 0 - Used to initiate a data transfer and/or setup measurement conditions without initiating a measurement sequence 1 - Used to request a new measurement sequence (scan) and initiate a data transfer Acts as a strobe bit and therefore does not need to be cleared (self-clearing). Always reads logic 0. Writes to SCANCTRL with SCAN = 1 requesting new scans are ignored if a scan is already in progress, or if SCANDONE is high. In this case, the content written to SCANCTRL[15:1] will be accepted, but the conflicting scan will not be executed and ALRTRJCT will be issued, notifying the user of the conflict. Note: The intended use of this bit is to enter/exit BALSWDIAG modes using SCANCFG, and allow the alternate conditions to settle prior to requesting the measurement (with a subsequent write to SCANCRTL with SCAN = 1). This bit can also be used to realize a variety of data move options (see DBLBUFEN and RDFILT for details) or to clear SCANDONE, SCANTIMEOUT, and DATARDY bits without requesting a measurement sequence/scan. ADCTEST1AREG (0x67) ADCTEST1A is a read- and write-accessible register that contains user-specified arguments used in ALU diagnostics.

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 278 BIT 15 14 13 12 11 10 9 8 Field ADCTSTEN – – – ADCTEST1A[11:8] Reset 0b0 – – – 0x000 Access Type Write, Read – – – Write, Read BIT 7 6 5 4 3 2 1 0 Field ADCTEST1A[7:0] Reset 0x000 Access Type Write, Read BITFIELD BITS DESCRIPTION ADCTSTEN 15 ADC/ALU Self Test Mode Enable 0 = Normal Operation (default) 1 = Enables the ALU Test Mode This mode feeds 12-bit data from the ADCTEST registers directly into the ALU instead of the ADC conversion data. Scans can then be performed, confirming proper operation of the ALU and calibration MAC. Notes: No calibration coefficients will be applied to ensure deterministic results (Gain = 1.0, Offset = 0.0). ADCTESTEN is ignored for On-Demand Calibration scans (SCANCFG = 011) to avoid miscalibration, and all scans performed during Automated Cell-Balancing modes to avoid inaccurate balancing results. ADCTEST1A 11:0 ALU ADC Input Argument 1A User-specified test data for the ALU diagnostic (ADCTESTEN = 1). This 12-bit data is fed into the ALU during the first conversion of odd-numbered samples (e.g., first sample). ADCTEST1BREG (0x68) ADCTEST1B is a read- and write-accessible register that contains user-specified arguments used in ALU diagnostics. BIT 15 14 13 12 11 10 9 8 Field – – – – ADCTEST1B[11:8] Reset – – – – 0x000 Access Type – – – – Write, Read

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 279 BIT 7 6 5 4 3 2 1 0 Field ADCTEST1B[7:0] Reset 0x000 Access Type Write, Read BITFIELD BITS DESCRIPTION ADCTEST1B 11:0 ALU ADC Input Argument 1B User-specified test data for the ALU diagnostic (ADCTEST = 1). This 12-bit data is fed into the ALU during the second conversion of odd-numbered samples (e.g., first sample). ADCTEST2AREG (0x69) ADCTEST2A is a read- and write-accessible register that contains user-specified arguments used in ALU diagnostics. BIT 15 14 13 12 11 10 9 8 Field – – – – ADCTEST2A[11:8] Reset – – – – 0x000 Access Type – – – – Write, Read BIT 7 6 5 4 3 2 1 0 Field ADCTEST2A[7:0] Reset 0x000 Access Type Write, Read BITFIELD BITS DESCRIPTION ADCTEST2A 11:0 ALU ADC Input Argument 2A User-specified test data for the ALU diagnostic (ADCTEST = 1). This 12-bit data is fed into the ALU during the first conversion of even-numbered samples in oversampling mode. ADCTEST2BREG (0x6A) ADCTEST2B is a read- and write-accessible register that contains user-specified arguments used in ALU diagnostics.

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 280 BIT 15 14 13 12 11 10 9 8 Field – – – – ADCTEST2B[11:8] Reset – – – – 0x000 Access Type – – – – Write, Read BIT 7 6 5 4 3 2 1 0 Field ADCTEST2B[7:0] Reset 0x000 Access Type Write, Read BITFIELD BITS DESCRIPTION ADCTEST2B 11:0 ALU ADC Input Argument 2B User-specified test data for the ALU diagnostic (ADCTEST = 1). This 12-bit data is fed into the ALU during the second conversion of even-numbered samples in oversampling mode. DIAGCFG (0x6B) DIAGCFG is a read- and write-accessible register that governs diagnostic source and mode options applied to the internal measurement acquisitions (scans). BIT 15 14 13 12 11 10 9 8 Field CTSTDAC[3:0] CTSTSRC MUXDIAGBUS MUXDIAGPAIR MUXDIAGEN Reset 0x0 0b0 0b0 0b0 0b0 Access Type Write, Read Write, Read Write, Read Write, Read Write, Read BIT 7 6 5 4 3 2 1 0 Field DIAGSEL2[3:0] DIAGSEL1[3:0] Reset 0x0 0x0 Access Type Write, Read Write, Read

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 281 BITFIELD BITS DESCRIPTION CTSTDAC 15:12 Current Level Configuration for all enabled test sources per the following table (6.25μA LSB for Cn, AUXIN, 3.125μA LSB for HVMUX) CTSTDAC TEST SOURCE CURRENT [3:0] Cn, AUXIN HVMUX 0x0 6.25μA 3.125μA 0x1 12.50μA 6.250μA 0x2 18.75μA 9.375μA 0xD 87.5μA 43.75μA 0xE 93.75μA 46.875μA 0xF 100μA 50μA CTSTSRC 11 Test Current Source Polarity 0 = Sink Current to GND (default) 1 = Source Current from VDDL Note: Polarity selection applies to AUX test current sources only. MUXDIAGBUS 10 Selects the HVMUX output to which the HVMUX test current source is connected, if MUXDIAGPAIR is enabled. 0 = Output Used for Even Cells, C0, and AGND 1 = Output Used for Odd Cells and REF, and ALTREF MUXDIAGPAIR 9 MUX Diagnostic Bus Configuration 0 = Both HVMUX test current sources are connected to both HVMUX outputs. (default) 1 = A single HVMUX test current source is connected to only one HVMUX output (as selected by MUXDIAGBUS). MUXDIAGEN 8 HVMUX Test Current Source(s) Enable 0 = Disable (default) 1 = Enable The current level is configured by CSTDAC and the connectivity is configured by MUXDIAGPAIR and MUXDIAGBUS DIAGSEL2 7:4 Acquisition Diagnostic2 Measurement Selection 0000 = No Diagnostic Requested 0001 = Die Temperature (ADCIN = VPTAT, ADCREF = VREF). 0010 = VAA (ADCIN = VREF through LSAmp, ADCREF = VAA) 0011 = Cell Signal Path ADC Fault, VALTREF (ADCIN = VALTREF (1V), ADCREF = VREF) 0100 = Comparator Cell Signal Path Fault (ADCIN = VREF through LSAmp2 - VDAC at DACCODE = 0x400 (1/4), ADCREF = DACREF = VREF, bipolar mode) 0101 = Cell Calibration (ADCIN = VREF through LSAmp, ADCREF = VREF). Calibration gain

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 282 BITFIELD BITS DESCRIPTION and offset coefficients and chopping applied according to SCANMODE selection. 0110 = Offset Calibration (ADCIN = Short (Pyramid) or ADCIN = Short through LSAmp (ramp), ADCREF = VREF, bipolar mode). Calibration offset coefficients applied according to SCANMODE selection. 0111 = 3/4-Scale DAC Test (DAC = 0xC00 ADCIN = VDAC, ADCREF = DACREF = VREF). 1000 = 1/4-Scale DAC Test (DAC = 0x3FF ADC.IN = VDAC, ADCREF = DACREF = VREF). 1001 = THRM Offset Calibration (ADCIN = short, ADCREF = VTHRM, bipolar mode). CALOSTHRM coefficient applied. 1101 = VDDL2/3 (ADCIN = VDDL2/3 through LSAmp, ADCREF = VREF) Selects the second diagnostic measurement appended to the acquisition, with the result stored in DIAG2. Appropriate calibrations (or factory defaults if ADCALEN = 0) and chopping are applied as needed. Detailed Diagnostics 1010 = Zero-Scale ADC Test (0x0000, ADCIN = -VAA, ADCREF = VREF, bipolar mode), full result available through DIAG. 1011 = Full-Scale ADC Test (0x3FFC, ADCIN = VAA, ADCREF = VREF, bipolar mode), full result available through DIAG. 1100 = LSAMP Offset (ADCIN = VLSA_0V, ADCREF = VREF. bipolar mode) Detailed diagnostics are normally performed at the end of an acquisition (with the exception of LSAMP offset, which is covered by the VALTREF diagnostic), and the pass/fail results are available in the FMEA2 BIST alerts. However, if it is deemed necessary to examine detailed results, these can be made available in the DIAG2 register using the modes above. DIAGSEL1 3:0 Acquisition Diagnostic1 Measurement Selection 0000 = No Diagnostic Requested 0001 = Die Temperature (ADCIN = VPTAT, ADCREF = VREF). 0010 = VAA (ADCIN = VREF through LSAmp, ADCREF = VAA) 0011 = Cell Signal Path ADC Fault, VALTREF (ADCIN = VALTREF (1V), ADCREF = VREF) 0100 = Comparator Cell Signal Path Fault (ADCIN = VREF through LSAmp2 - VDAC at DACCODE = 0x400 (1/4), ADCREF = DACREF = VREF, bipolar mode) 0101 = Cell Calibration (ADCIN = VREF through LSAmp, ADCREF = VREF). Calibration gain and offset coefficients and chopping applied according to SCANMODE selection. 0110 = Offset Calibration (ADCIN = Short (Pyramid) or ADCIN = Short through LSAmp (ramp), ADCREF = VREF, bipolar mode). Calibration offset coefficients applied according to SCANMODE selection. 0111 = 3/4-Scale DAC Test (DAC = 0xC00 ADCIN = VDAC, ADCREF = DACREF = VREF). 1000 = 1/4-Scale DAC Test (DAC = 0x3FF ADC.IN = VDAC, ADCREF = DACREF = VREF). 1001 = THRM Offset Calibration (ADCIN = Short, ADCREF = VTHRM, bipolar mode). CALOSTHRM coefficient applied. 1101 = VDDL2/3 (ADCIN = VDDL2/3 through LSAmp, ADCREF = VREF) Selects the first diagnostic measurement appended to the acquisition, with the result stored in DIAG1. Appropriate calibrations (or factory defaults if ADCALEN = 0) and chopping are applied as needed. Detailed Diagnostics 1010 = Zero-Scale ADC Test (0x0000, ADCIN = -VAA, ADCREF = VREF, bipolar mode), full result available through DIAG.

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 283 BITFIELD BITS DESCRIPTION 1011 = Full-Scale ADC Test (0x3FFC, ADCIN = VAA, ADCREF = VREF, bipolar mode), full result available through DIAG. 1100 = LSAMP Offset (ADCIN = VLSA_0V, ADCREF = VREF. bipolar mode) Detailed diagnostics are normally performed at the end of an acquisition (with the exception of LSAMP offset, which is covered by the VALTREF diagnostic), and the pass/fail results are available in the FMEA2 BIST alerts. However, if it is deemed necessary to examine detailed results, these can be made available in the DIAG1 register using the modes above. CTSTCFG (0x6C) CTSTCFG is a read- and write-accessible register that controls the application of diagnostic current sources to selected cell input channels. BIT 15 14 13 12 11 10 9 8 Field CELLOPNDIAGSEL CTSTEN[14:8] Reset 0b0 0b000000000000000 Access Type Write, Read Write, Read BIT 7 6 5 4 3 2 1 0 Field CTSTEN[7:0] Reset 0b000000000000000 Access Type Write, Read BITFIELD BITS DESCRIPTION CELLOPNDIAGSEL 15 Cell Open Diagnostic Mode Selection 0 - Normal Operation (default) 1 - Open Diagnostic Operation In Normal mode (0), measured CELLn channels are selected by CELLEN and measured with standard thresholds on a per channel basis for both ADC and comparator acquisition sequences. In Open Diagnostic mode (1), measured CELLn channels are selected by (CELLENn & !POLARITYn) on a per channel basis. Only low-side comparator checks will be performed using alternate Open (OPN) thresholds. Normally in Open Diagnostic modes, pull-down current sources are enabled on all measured channels using CTSTEN, and only comparator measurements are selcected (SCANCFG = 010).

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 284 BITFIELD BITS DESCRIPTION This mode is most often used with an appropriate Auxiliary Open Diagnostic mode (AUXDIAGSEL = 010 or 011). CTSTEN 14:0 Cell Diagnostic Current Source Enable Enables the current sources connected to the corresponding cell inputs for diagnostic testing. The current level is configured by the CTSTDAC in the DIAGCFG register. AUXTSTCFG (0x6D) AUXTSTCFG is a read- and write-accessible register that controls the application of diagnostic modes and current sources to selected auxiliary input channels. BIT 15 14 13 12 11 10 9 8 BIT 7 6 5 4 3 2 1 0 Field – – AUXTSTEN[5:4] AUXTSTEN[3:0] Reset – – 0b00 0x0 Access Type – – Write, Read, Ext Write, Read, Ext BITFIELD BITS DESCRIPTION AUXTSTEN 5:4 Auxiliary Diagnostic Current Source Enable Enables the current sources connected to the corresponding auxiliary input for diagnostic testing. The current level is configured by DIAGCFG:CTSTDAC, and the current direction is configured by DIAGCFG:CTSTSRC. Note: If the respective GPIOEN bit is set (GPIO mode), this bit is ignored, but will still read back the user setting. AUXTSTEN 3:0 Auxiliary Diagnostic Current Source Enable Enables the current sources connected to the corresponding auxiliary input for diagnostic testing. The current level is configured by DIAGCFG:CTSTDAC, and the current direction is configured by DIAGCFG:CTSTSRC. Note: If the I2CEN bit (Digital I2C mode, applies to [1:0] only) or the respective GPIOEN bit is set (GPIO mode), this bit is ignored, but will still read back the user setting.

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 285 DIAGGENCFG (0x6E) DIAGGENCFG is a read- and write-accessible register that controls the application of general diagnostic modes to the selected input paths. BIT 15 14 13 12 11 10 9 8 Field AUXDIAGSEL[2:0] – – – – – Access Type Write, Read – – – – – BIT 7 6 5 4 3 2 1 0 BITFIELD BITS DESCRIPTION AUXDIAGSEL 15:13 AUX Diagnostic Mode Selection 00x - Normal Operation (default) 010 - AUX Accelerated Discharge Operation (ratiometric only) 011 - THRM Output Connected to AGND 1xx - Reserved for Analog Devices Use Only Control bits used for AUXINn pin diagnostic testing. Only ports configured as AUXINn inputs are tested. BALSWCTRL (0x6F) BALSWCTRL is a read- and write-accessible register that governs the behavior of the Charge-Balancing Switches in Manual and Auto Cell-Balancing modes. Write access to this register is blocked during Automated Cell-Balancing operations (CBMODE = 001, 1xx). BIT 15 14 13 12 11 10 9 8 Field CBRESTART – BALSWEN[14:9] Reset 0b0 – 0b00000000000000 Access Type Write, Read, Pulse – Write, Read, Ext BIT 7 6 5 4 3 2 1 0

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 286 Field BALSWEN[8:1] Reset 0b00000000000000 Access Type Write, Read, Ext BITFIELD BITS DESCRIPTION CBRESTART 15 Watchdog Timer Restart for Manual Mode 0 - CBTIMER continues to run. 1 - CBTIMER is reset to zero. Acts as a strobe bit and therefore does not need to be cleared. Always reads logic 0. Accessible and applies in Manual mode only. Writing 1 to CBRESTART after cell-balancing timer expiration has no effect. To perform another Manual mode cell-balancing event, the user must issue a separate write to the BALCTRL register. BALSWEN 13:0 Balance Switch Enable BALSWEN[n] enables the balancing switch (allowing conduction) between SWn and SWn-1, balancing CELLn. BALEXP1 (0x70) BALEXPn is a read- and write-accessible register that holds the Cell-Balancing Expiration Time for CELLn (using the switch across SWn and SWn-1). BALEXP1 sets the Expiration Time for all Group Auto Cell-Balancing and Discharge modes and the watchdog timeout for Manual Cell-Balancing mode. Write access to this register is blocked during all cell-balancing operations (CBMODE != 000). BIT 15 14 13 12 11 10 9 8 Reset – – – – – – 0b0000000000 Access Type – – – – – – Write, Read, Ext BIT 7 6 5 4 3 2 1 0 Field CBEXP1[7:0] Reset 0b0000000000 Access Type Write, Read, Ext

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 287 BITFIELD BITS DESCRIPTION CBEXP1 9:0 Cell-Balancing Expiration Time Cell-Balancing Expiration Time for CELLn; unit (LSB = hour, minute, or second) determined by CBMODE. CBEXP1 is used as the controller/watchdog timeout setting for Manual, Discharge, and Auto Group Cell-Balancing modes. Value 0x3FF operates balancing indefinitely (no timer expiration). Default value 0x000 disables cell balancing (preconfigured timer expiration). BALEXP2 (0x71) BALEXPn is a read- and write-accessible register that holds the Cell-Balancing Expiration Time for CELLn (using the switch across SWn and SWn-1). Used in Individual Automated Cell-Balancing modes only. Write access to this register is blocked during Automated Cell-Balancing operations (CBMODE = 1xx). BIT 15 14 13 12 11 10 9 8 Reset – – – – – – 0b0000000000 Access Type – – – – – – Write, Read, Ext BIT 7 6 5 4 3 2 1 0 Field CBEXP2[7:0] Reset 0b0000000000 Access Type Write, Read, Ext BITFIELD BITS DESCRIPTION CBEXP2 9:0 Cell-Balancing Expiration Time Cell-Balancing Expiration Time for CELLn; unit (LSB = hour, minute, or second) determined by CBMODE. Value 0x3FF operates balancing indefinitely (no timer expiration). Default value 0x000 disables cell balancing (preconfigured timer expiration). BALEXP3 (0x72) BALEXPn is a read- and write-accessible register that holds the Cell-Balancing Expiration Time for CELLn (using the switch across SWn and SWn-1). Used in Individual Automated Cell-Balancing modes only.

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 288 Write access to this register is blocked during Automated Cell-Balancing operations (CBMODE = 1xx). BIT 15 14 13 12 11 10 9 8 Reset – – – – – – 0b0000000000 Access Type – – – – – – Write, Read, Ext BIT 7 6 5 4 3 2 1 0 Field CBEXP3[7:0] Reset 0b0000000000 Access Type Write, Read, Ext BITFIELD BITS DESCRIPTION CBEXP3 9:0 Cell-Balancing Expiration Time Cell-Balancing Expiration Time for CELLn; unit (LSB = hour, minute, or second) determined by CBMODE. Value 0x3FF operates balancing indefinitely (no timer expiration). Default value 0x000 disables cell balancing (preconfigured timer expiration). BALEXP4 (0x73) BALEXPn is a read- and write-accessible register that holds the Cell-Balancing Expiration Time for CELLn (using the switch across SWn and SWn-1). Used in Individual Automated Cell-Balancing modes only. Write access to this register is blocked during Automated Cell-Balancing operations (CBMODE = 1xx). BIT 15 14 13 12 11 10 9 8 Reset – – – – – – 0b0000000000 Access Type – – – – – – Write, Read, Ext BIT 7 6 5 4 3 2 1 0 Field CBEXP4[7:0] Reset 0b0000000000

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 289 Access Type Write, Read, Ext BITFIELD BITS DESCRIPTION CBEXP4 9:0 Cell-Balancing Expiration Time Cell-Balancing Expiration Time for CELLn; unit (LSB = hour, minute, or second) determined by CBMODE. Value 0x3FF operates balancing indefinitely (no timer expiration). Default value 0x000 disables cell balancing (preconfigured timer expiration). BALEXP5 (0x74) BALEXPn is a read- and write-accessible register that holds the Cell-Balancing Expiration Time for CELLn (using the switch across SWn and SWn-1). Used in individual Automated Cell-Balancing modes only. Write access to this register is blocked during Automated Cell-Balancing operations (CBMODE = 1xx). BIT 15 14 13 12 11 10 9 8 Reset – – – – – – 0b0000000000 Access Type – – – – – – Write, Read, Ext BIT 7 6 5 4 3 2 1 0 Field CBEXP5[7:0] Reset 0b0000000000 Access Type Write, Read, Ext BITFIELD BITS DESCRIPTION CBEXP5 9:0 Cell-Balancing Expiration Time Cell-Balancing Expiration Time for CELLn; unit (LSB = hour, minute, or second) determined by CBMODE. Value 0x3FF operates balancing indefinitely (no timer expiration). Default value 0x000 disables cell balancing (preconfigured timer expiration). BALEXP6 (0x75) BALEXPn is a read- and write-accessible register that holds the Cell-Balancing Expiration Time for CELLn (using the switch across SWn and SWn-1). Used in individual Automated Cell-Balancing modes only.

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 290 Write access to this register is blocked during Automated Cell-Balancing operations (CBMODE = 1xx). BIT 15 14 13 12 11 10 9 8 Reset – – – – – – 0b0000000000 Access Type – – – – – – Write, Read, Ext BIT 7 6 5 4 3 2 1 0 Field CBEXP6[7:0] Reset 0b0000000000 Access Type Write, Read, Ext BITFIELD BITS DESCRIPTION CBEXP6 9:0 Cell-Balancing Expiration Time Cell-Balancing Expiration Time for CELLn; unit (LSB = hour, minute, or second) determined by CBMODE. Value 0x3FF operates balancing indefinitely (no timer expiration). Default value 0x000 disables cell balancing (preconfigured timer expiration). BALEXP7 (0x76) BALEXPn is a read- and write-accessible register that holds the Cell-Balancing Expiration Time for CELLn (using the switch across SWn and SWn-1). Used in Individual Automated Cell-Balancing modes only. Write access to this register is blocked during Automated Cell-Balancing operations (CBMODE = 1xx). BIT 15 14 13 12 11 10 9 8 Reset – – – – – – 0b0000000000 Access Type – – – – – – Write, Read, Ext BIT 7 6 5 4 3 2 1 0 Field CBEXP7[7:0] Reset 0b0000000000

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 291 Access Type Write, Read, Ext BITFIELD BITS DESCRIPTION CBEXP7 9:0 Cell-Balancing Expiration Time Cell-Balancing Expiration Time for CELLn; unit (LSB = hour, minute, or second) determined by CBMODE. Value 0x3FF operates balancing indefinitely (no timer expiration). Default value 0x000 disables cell balancing (preconfigured timer expiration). BALEXP8 (0x77) BALEXPn is a read- and write-accessible register that holds the Cell-Balancing Expiration Time for CELLn (using the switch across SWn and SWn-1). Used in Individual Automated Cell-Balancing modes only. Write access to this register is blocked during Automated Cell-Balancing operations (CBMODE = 1xx). BIT 15 14 13 12 11 10 9 8 Reset – – – – – – 0b0000000000 Access Type – – – – – – Write, Read, Ext BIT 7 6 5 4 3 2 1 0 Field CBEXP8[7:0] Reset 0b0000000000 Access Type Write, Read, Ext BITFIELD BITS DESCRIPTION CBEXP8 9:0 Cell-Balancing Expiration Time Cell-Balancing Expiration Time for CELLn; unit (LSB = hour, minute, or second) determined by CBMODE. Value 0x3FF operates balancing indefinitely (no timer expiration). Default value 0x000 disables cell balancing (preconfigured timer expiration). BALEXP9 (0x78) BALEXPn is a read- and write-accessible register that holds the Cell-Balancing Expiration Time for CELLn (using the switch across SWn and SWn-1). Used in Individual Automated Cell-Balancing modes only.

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 292 Write access to this register is blocked during Automated Cell-Balancing operations (CBMODE = 1xx). BIT 15 14 13 12 11 10 9 8 Reset – – – – – – 0b0000000000 Access Type – – – – – – Write, Read, Ext BIT 7 6 5 4 3 2 1 0 Field CBEXP9[7:0] Reset 0b0000000000 Access Type Write, Read, Ext BITFIELD BITS DESCRIPTION CBEXP9 9:0 Cell-Balancing Expiration Time Cell-Balancing Expiration Time for CELLn; unit (LSB = hour, minute, or second) determined by CBMODE. Value 0x3FF operates balancing indefinitely (no timer expiration). Default value 0x000 disables cell balancing (preconfigured timer expiration). BALEXP10 (0x79) BALEXPn is a read- and write-accessible register that holds the Cell-Balancing Expiration Time for CELLn (using the switch across SWn and SWn-1). Used in individual Automated Cell-Balancing modes only. Write access to this register is blocked during Automated Cell-Balancing operations (CBMODE = 1xx). BIT 15 14 13 12 11 10 9 8 Field – – – – – – CBEXP10[9:8] Reset – – – – – – 0b0000000000 Access Type – – – – – – Write, Read, Ext BIT 7 6 5 4 3 2 1 0 Field CBEXP10[7:0] Reset 0b0000000000

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 293 Access Type Write, Read, Ext BITFIELD BITS DESCRIPTION CBEXP10 9:0 Cell-Balancing Expiration Time Cell-Balancing Expiration Time for CELLn; unit (LSB = hour, minute, or second) determined by CBMODE. Value 0x3FF operates balancing indefinitely (no timer expiration). Default value 0x000 disables cell balancing (preconfigured timer expiration). BALEXP11 (0x7A) BALEXPn is a read- and write-accessible register that holds the Cell-Balancing Expiration Time for CELLn (using the switch across SWn and SWn-1). Used in individual Automated Cell-Balancing modes only. Write access to this register is blocked during Automated Cell-Balancing operations (CBMODE = 1xx). BIT 15 14 13 12 11 10 9 8 Field – – – – – – CBEXP11[9:8] Reset – – – – – – 0b0000000000 Access Type – – – – – – Write, Read, Ext BIT 7 6 5 4 3 2 1 0 Field CBEXP11[7:0] Reset 0b0000000000 Access Type Write, Read, Ext BITFIELD BITS DESCRIPTION CBEXP11 9:0 Cell-Balancing Expiration Time Cell-Balancing Expiration Time for CELLn; unit (LSB = hour, minute, or second) determined by CBMODE. Value 0x3FF operates balancing indefinitely (no timer expiration). Default value 0x000 disables cell balancing (preconfigured timer expiration). BALEXP12 (0x7B) BALEXPn is a read- and write-accessible register that holds the Cell-Balancing Expiration Time for CELLn (using the switch across SWn and SWn-1). Used in individual Automated Cell-Balancing modes only.

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 294 Write access to this register is blocked during Automated Cell-Balancing operations (CBMODE = 1xx). BIT 15 14 13 12 11 10 9 8 Field – – – – – – CBEXP12[9:8] Reset – – – – – – 0b0000000000 Access Type – – – – – – Write, Read, Ext BIT 7 6 5 4 3 2 1 0 Field CBEXP12[7:0] Reset 0b0000000000 Access Type Write, Read, Ext BITFIELD BITS DESCRIPTION CBEXP12 9:0 Cell-Balancing Expiration Time Cell-Balancing Expiration Time for CELLn; unit (LSB = hour, minute, or second) determined by CBMODE. Value 0x3FF operates balancing indefinitely (no timer expiration). Default value 0x000 disables cell balancing (preconfigured timer expiration). BALEXP13 (0x7C) BALEXPn is a read- and write-accessible register that holds the Cell-Balancing Expiration Time for CELLn (using the switch across SWn and SWn-1). Used in Individual Automated Cell-Balancing modes only. Write access to this register is blocked during Automated Cell-Balancing operations (CBMODE = 1xx). BIT 15 14 13 12 11 10 9 8 Field – – – – – – CBEXP13[9:8] Reset – – – – – – 0b0000000000 Access Type – – – – – – Write, Read, Ext BIT 7 6 5 4 3 2 1 0 Field CBEXP13[7:0] Reset 0b0000000000

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 295 Access Type Write, Read, Ext BITFIELD BITS DESCRIPTION CBEXP13 9:0 Cell-Balancing Expiration Time Cell-Balancing Expiration Time for CELLn; unit (LSB = hour, minute, or second) determined by CBMODE. Value 0x3FF operates balancing indefinitely (no timer expiration). Default value 0x000 disables cell balancing (preconfigured timer expiration). BALEXP14 (0x7D) BALEXPn is a read- and write-accessible register that holds the Cell-Balancing Expiration Time for CELLn (using the switch across SWn and SWn-1). Used in Individual Automated Cell-Balancing modes only. Write access to this register is blocked during Automated Cell-Balancing operations (CBMODE = 1xx). BIT 15 14 13 12 11 10 9 8 Field – – – – – – CBEXP14[9:8] Reset – – – – – – 0b0000000000 Access Type – – – – – – Write, Read, Ext BIT 7 6 5 4 3 2 1 0 Field CBEXP14[7:0] Reset 0b0000000000 Access Type Write, Read, Ext BITFIELD BITS DESCRIPTION CBEXP14 9:0 Cell-Balancing Expiration Time Cell-Balancing Expiration Time for CELLn; unit (LSB = hour, minute, or second) determined by CBMODE. Value 0x3FF operates balancing indefinitely (no timer expiration). Default value 0x000 disables cell balancing (preconfigured timer expiration). BALAUTOUVTHR (0x7E) BALAUTOUVTHR is a read- and write-accessible register that selects the cell undervoltage exit threshold for the ADC when used in Automated Cell-Balancing operations.

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 296 A write to this register allows direct setting or automatic selection of this threshold. Write access to this register is blocked during Automated Cell-Balancing operations (CBMODE = 1xx). Also, during active measurement scans, all writes with CBUVMINCELL = 1 will be blocked and will result in ALRTRJCT being issued (since the MINCELL data may be altered as a result of the scan in progress). A read from this register will display the current value of the threshold and the method used for its selection. BIT 15 14 13 12 11 10 9 8 Field CBUVTHR[13:6] Reset 0b11111111111111 Access Type Write, Read, Ext BIT 7 6 5 4 3 2 1 0 Field CBUVTHR[5:0] – CBUVMINCELL Reset 0b11111111111111 – 0b0 Access Type Write, Read, Ext – Write, Read, Ext BITFIELD BITS DESCRIPTION CBUVTHR 15:2 Cell-Balancing Undervoltage Threshold 14-bit ADC threshold,of a 5V input range, below which cell-balancing operations will be suspended on each CELL. Default of 0x3FFF, ensures no cell balancing will occur without prior configuration. CBUVMINCELL 0 Cell-Balancing Undervoltage Threshold Selection 0 = User-Defined CBUVTHR 1 = MINCELL-Defined CBUVTHR In mode 0, the value written to CBUVTHR during a valid write to BALAUTOUVTHR will be loaded to CBUVTHR. In mode 1, the current value in the CELLn register corresponding to the MINCELL address will be automatically loaded to CBUVTHR during a valid write to BALAUTOUVTHR (and the content in CBUVTHR during the write will be ignored). Note: Automated Cell Balancing with CBUVTHR checking is only supported for unipolar cell measurements. If CBUVMINCELL = 1 is written while MINMAXPOL = 1, CBUVTHR will be set to 0x3FFF\\h as a result.

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 297 BALDLYCTRL (0x7F) BALDLYCTRL is a read- and write-accessible register that selects the delay/timing intervals used within Automated Cell-Balancing operations. Write access to this register is blocked during Automated Cell-Balancing operations (CBMODE = 001, 1xx). BIT 15 14 13 12 11 10 9 8 Field – – – – – – CBNTFYCFG[1:0] Access Type – – – – – – Write, Read, Ext BIT 7 6 5 4 3 2 1 0 Field – – – – – CBCALDLY[2:0] Access Type – – – – – Write, Read, Ext BITFIELD BITS DESCRIPTION CBNTFYCFG 9:8 Cell-Balancing Notification Alert Configuration 00 = Disable Cell-Balancing Notification Alert (default) 01 = Nofication Issued every 1hr 10 = Nofication Issued every 2hr 11 = Nofication Issued every 4hr In Automatic and Discharge modes, the Cell-Balancing Notification Alert (ALRTCBNTFY) can be issued to confirm normal progression of automated operations. The frequency of issuance is selected as described above, in real time (i.e., not CBDUTY-adjusted). Notification alerts will continue to be issued during HOLDSHDNL. CBCALDLY 2:0 Cell-Balancing Calibration Period Selection In Automatic and Discharge modes, after each pair of Even and Odd Cell-Balancing periods, a supervisory ADC measurement is taken (and checked against CBUVTHR, if enabled/applicable). CBCALDLY allows a calibration operation to be substituted in place of a measurement at the frequency indicted below. A value of 000 (default) disables CAL operations (only ADC operations are performed). 000 - Periodic Calibration Disabled 001 - 2 (every other) cycle 010 - 4 (every fourth) cycle 011 - 8 cycles 100 - 12 cycles 101 - 16 cycles 110 - 24 cycles

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 298 BITFIELD BITS DESCRIPTION 111 - 32 cycles If CBMEASEN = 0x (ADC/CAL measurements disabled), this bitfield is ignored and has no effect. BALCTRL (0x80) BALCTRL is a read- and write-accessible register that initiates and controls all internal cell-balancing modes and operations. Any write to this register to a mode other than CBMODE = 000 (disable) will restart the CBTIMER at 0 and launch the requested mode of operation. BIT 15 14 13 12 11 10 9 8 Field CBACTIVE[1:0] CBMODE[2:0] CBIIRINIT HOLDSHDNL[1:0] Reset 0b00 0b000 0b0 0b00 Access Type Read Only Write, Read, Ext Write, Read Write, Read BIT 7 6 5 4 3 2 1 0 Field CBDUTY[3:0] CBDONEALRTEN CBTEMPEN CBMEASEN[1:0] Reset 0x0 0b0 0b0 0b00 Access Type Write, Read Write, Read Write, Read Write, Read BITFIELD BITS DESCRIPTION CBACTIVE 15:14 Cell-Balancing Timer Active Indicator 00 = Cell Balancing is Disabled (default) 01 = Cell-Balancing Operations are Active 10 = Cell Balancing Completed Normally due to Reaching CBUVTHR or CBEXP Exit Conditions 11 = Cell Balancing Halted Unexpectedly due to Thermal Exit (ALRTCBTEMP), Time Out (ALRTCBTIMEOUT), or Calibration Fault (ALRTCBCAL) Conditions Read only. CBMODE 13:11 Cell-Balancing Mode Selection 000 = Cell Balancing Disabled (default) 001 = Emergency/EOL Discharge by Hour 010 = Manual Cell Balancing by Second 011 = Manual Cell Balancing by Minute 100 = Auto Individual Cell Balancing by Second 101 = Auto Individual Cell Balancing by Minute

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 299 BITFIELD BITS DESCRIPTION 110 = Auto Group Cell Balancing by Second 111 = Auto Group Cell Balancing by Minute CBIIRINIT 10 Cell-Balancing IIR Initialization Request 0 = IIR Filter Continuation (default) 1 = IIR Filter Initialized If enabled, the IIR filter contents will be initialized during the first measurement scan and CBUVTHR checks will be suspended for 16 measurement scans, giving the IIR time to settle. HOLDSHDNL 9:8 SHDNL Hold Mode Enable 00 = No Hold (default) 01 = SHDNL Held High for the Duration of Automated Cell Balancing or Discharge Operations 10 = SHDNL Held High for Duration of Automated Cell Balancing or Discharge Operations, plus 5min or 6.25% of the Maximum Applicable CBEXP Interval (whichever is greater) 11 = SHDNL Held High for Duration of Automated Cell Balancing or Discharge Operations, and until Removed CBDUTY 7:4 Cell-Balancing Duty Cycle Sets the active duty-cycle within each tCBEO period. 0000 = 6.25% (default) 0001 = 12.5% ... 1110 = 93.75% 1111 = 100%, less NOL and measurement/calibration overhead. CBDONEALRTEN 3 Cell-Balancing Complete Alert Enable 0 = ALRTCBDONE Masked in STATUS1:ALRTCBAL (default) 1 = ALRTCBDONE Included in STATUS1:ALRTCBAL Masking of this alert component allows the user the choice to be notified only for unexpected exits, or normal completions as well. CBTEMPEN 2 Cell-Balancing Thermal Exit Enable 0 = Cell Balancing Not Impacted by ALRTTEMP (default) 1 = Cell Balancing Halts in Response to ALRTTEMP CBMEASEN 1:0 Cell-Balancing Measurement Enable 0x = Embedded ADC/CAL Measurements and CBUVTHR Checking Disabled (default) 10 = Embedded ADC/CAL Measurements Enabled, CBUVTHR Checking Disabled 11 = Embedded ADC/CAL Measurements Enabled, CBUVTHR Checking Enabled Note: Automated cell balancing with CBUVTHR checking is only supported for unipolar cell measurements. BALSTAT (0x81) BALSTAT is a read-accessible register that allows the monitoring of any Automated Cell-Balancing operations currently in progress.

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 300 Once a CBMODE is initiated, all status bits persist and are cleared only when CBMODE is written to 000 (disabled) or when a new CBMODE operation is initiated through CBSTART. BIT 15 14 13 12 11 10 9 8 Field CBACTIVE_M1[1:0] CBUNIT[1:0] CBCNTR[1:0] CBTIMER[9:8] Reset 0b00 0b00 0b00 0b0000000000 Access Type Read Only Read Only Read Only Read Only BIT 7 6 5 4 3 2 1 0 Field CBTIMER[7:0] Reset 0b0000000000 Access Type Read Only BITFIELD BITS DESCRIPTION CBACTIVE_M1 15:14 Cell-Balancing Timer Active Indicator (Mirror) 00 = Cell Balancing is Disabled (default) 01 = Cell-Balancing Operations are Active 10 = Cell Balancing Completed Normally due to Reaching CBUVTHR or CBEXP Exit Conditions 11 = Cell Balancing Halted Unexpectedly due to Thermal Exit (ALRTCBTEMP), Timeout (ALRTCBTIMEOUT), or Calibration Fault (ALRTCBCAL) Conditions Read only. CBUNIT 13:12 Cell-Balancing Timer Unit Indicator 00 = Cell Balancing is Disabled (default) 01 = CBTIMER Measures Seconds 10 = CBTIMER Measures Minutes 11 = CBTIMER Measures Hours Allows confirmation of Cell-Balancing Timer operating mode (LSB weight). Read only, CBCNTR 11:10 Cell-Balancing Active Counter 1Hz counter that can be read to verify CBTIMER operation/activity when the CBTIMER is operated in minute or hour modes. The counter counts from 0 to 3, rolling over to 0 approximately every 4 seconds in all active cell-balancing modes (CBMODE != 000). Read only. Notes: During Hold SHDNL extension periods (HOLDSHDNL = 1x), CBCNTR will continue to run.

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 301 BITFIELD BITS DESCRIPTION If the governing CBEXP setting is set to 0x3FF (infinite), this counter will continue to run, even though it has no impact on the active cell-balancing mode. CBTIMER 9:0 Cell-Balancing Timer Value Reads the current cell-balancing timer value in seconds, minutes, or hours, depending on CBMODE, as indicated by CBUNIT. Read only. Notes: During SHDNL hold/extension periods (HOLDSHDNL = 1x), CBTIMER will read back the governing expiration time (CBEXP), indicating that the requested balancing operation has completed. If the governing CBEXP setting is set to 0x3FF (infinite), this timer will still run and roll over, even though it has no impact on the active cell-balancing mode. BALUVSTAT (0x82) BALUVSTAT is a read-accessible register that relates current summary information on the cell voltages vs. the CBUVTHR undervoltage threshold. BIT 15 14 13 12 11 10 9 8 Field CBACTIVE_M2[1:0] CBUVSTAT[14:9] Reset 0b00 0b00000000000000 Access Type Read Only Read Only BIT 7 6 5 4 3 2 1 0 Field CBUVSTAT[8:1] Reset 0b00000000000000 Access Type Read Only BITFIELD BITS DESCRIPTION CBACTIVE_M2 15:14 Cell-Balancing Timer Active Indicator (Mirror) 00 = Cell Balancing is Disabled (default) 01 = Cell-Balancing Operations are Active 10 = Cell Balancing Completed Normally due to Reaching CBUVTHR or CBEXP Exit Conditions 11 = Cell Balancing Halted Unexpectedly due to Thermal Exit (ALRTCBTEMP), Timeout (ALRTCBTIMEOUT), or Calibration Fault (ALRTCBCAL) Conditions Read only.

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 302 BITFIELD BITS DESCRIPTION CBUVSTAT 13:0 Cell-Balancing CBUVTHR Check Status CBUVSTAT[n] = 1 indicates the corresponding CELLn result falls below the threshold specified by CBUVTHR and that Cell-Balancing operations on that cell have ended. Cleared only when CBMODE is written to 000 (disabled) or when a new CBMODE operation is initiated through a write to BALCTRL. Read only. Note: Automated Cell Balancing with CBUVTHR checking is only supported for unipolar cell measurements in locations with BALSWENn = 1. The user must also ensure CELLENn = 1 and POLARITYn = 0 to allow the required measurement updates; if the measurement is not supported, balancing of the cell automatically ends with a CBUVSTATn = 1 exit condition. BALDATA (0x83) BALDATA is a read-accessible register that relates current summary information on the cell voltages vs. the CBUVTHR undervoltage threshold. BIT 15 14 13 12 11 10 9 8 Field CBACTIVE_M3[1:0] DATARDY_M – – – – – Access Type Read Only Write, Read, BIT 7 6 5 4 3 2 1 0 Access Type – – – – – – – Write, Read, Pulse BITFIELD BITS DESCRIPTION CBACTIVE_M3 15:14 Cell-Balancing Timer Active Indicator (Mirror) 00 = Cell Balancing is Disabled (default) 01 = Cell-Balancing Operations are Active 10 = Cell Balancing Completed Normally due to Reaching CBUVTHR or CBEXP Exit Conditions 11 = Cell Balancing Halted Unexpectedly due to Thermal Exit (ALRTCBTEMP), Timeout (ALRTCBTIMEOUT), or Calibration Fault (ALRTCBCAL) Conditions

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 303 BITFIELD BITS DESCRIPTION Read only. DATARDY_M 13 Data Ready Indicator Bit (Mirror) Indicates the measurement data from the acquisition has been transferred to the data registers and may now be read. Data for all measurement registers and MIN/MAX/TOTAL is transferred at the same time. Cleared by writing to logic 0 to allow detection of the next data transfer. Writing to logic 1 has no internal effect. This is a mirror of the DATARDY bit in SCANCFG, provided to support readback of measurement results taken during Automated and Discharge Cell-Balancing modes. CBSCAN 0 Manually Transfer Measurement Results from IIR to Data registers 0 = No transfer requested 1 = Measurement transferred from the IIR (regardless of RDFILT setting) to data registers; once transfer is complete, DATARDY bit is set. Acts as a strobe bit and therefore does not need to be cleared (self-clearing). This bit has no effect in Cell-Balancing Manual or Disable mode, or when CBMEASEN = 0x. Always reads logic 0. I2CPNTR (0x84) I2CPTNR is a read- and write-accessible register that contains two pointer bytes (register addresses) available for I2C controller transactions. Once I2CSEND initiates a read or write transaction, attempts to write I2CPNTR during the transaction will be ignored and will cause an I2CRJCT fault to be issued. BIT 15 14 13 12 11 10 9 8 Field I2CPBYTE1[7:0] Reset 0xFF Access Type Write, Read BIT 7 6 5 4 3 2 1 0 Field I2CPBYTE0[7:0] Reset 0xFF Access Type Write, Read

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 304 BITFIELD BITS DESCRIPTION I2CPBYTE1 15:8 I2C Pointer Address Byte 1 This is the Pointer (Register) Address Byte 1 available for I2C controller transactions. I2CPBYTE0 7:0 I2C Pointer Address Byte 0 This is the Pointer (Register) Address Byte 0 available for I2C controller transactions. I2CWDATA1 (0x85) I2CWDATA1 is a read- and write-accessible register that contains the upper data bytes available for I2C controller Write mode transactions. Once I2CSEND initiates an I2C read or write transaction, attempts to write I2CWDATA1 during the transaction will be ignored and will cause an I2CRJCT fault to be issued. BIT 15 14 13 12 11 10 9 8 Field I2CWBYTE3[7:0] Reset 0xFF Access Type Write, Read BIT 7 6 5 4 3 2 1 0 Field I2CWBYTE2[7:0] Reset 0xFF Access Type Write, Read BITFIELD BITS DESCRIPTION I2CWBYTE3 15:8 I2C Write Data Byte 3 This is the 3rd (MS) byte available for I2C Controller Write mode transactions. I2CWBYTE2 7:0 I2C Write Data Byte 2 This is the 2nd byte available for I2C Controller Write mode transactions. I2CWDATA2 (0x86) I2CWDATA2 is a read- and write-accessible register that contains the lower data bytes available for I2C controller Write mode transactions. Once I2CSEND initiates an I2C read or write transaction, attempts to write I2CWDATA2 during the transaction will be ignored and will cause an I2CRJCT fault to be issued. BIT 15 14 13 12 11 10 9 8

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 305 Field I2CWBYTE1[7:0] Reset 0xFF Access Type Write, Read BIT 7 6 5 4 3 2 1 0 Field I2CWBYTE0[7:0] Reset 0xFF Access Type Write, Read BITFIELD BITS DESCRIPTION I2CWBYTE1 15:8 I2C Write Data Byte 1 This is the 1st byte available for I2C Controller Write mode transactions. I2CWBYTE0 7:0 I2C Write Data Byte 0 This is the 0th (LS) byte available for I2C Controller Write mode transactions. I2CRDATA1 (0x87) I2CRDATA1 is a read-accessible register that contains the upper data bytes received for I2C Controller Read mode transactions. Note: During I2C read transactions, data is updated as each byte is received/acknowledged, so reading back this register during active I2C read transactions will cause an I2CRJCT fault to be issued. BIT 15 14 13 12 11 10 9 8 Field I2CRBYTE3[7:0] Reset 0xFF Access Type Read Only BIT 7 6 5 4 3 2 1 0 Field I2CRBYTE2[7:0] Reset 0xFF Access Type Read Only

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 306 BITFIELD BITS DESCRIPTION I2CRBYTE3 15:8 I2C Read Data Byte 3 This is the 3rd (MS) byte space available for use by I2C Controller Read mode transactions. I2CRBYTE2 7:0 I2C Read Data Byte 2 This is the 2nd byte space available for use by I2C Controller Read mode transactions. I2CRDATA2 (0x88) I2CRDATA2 is a read-accessible register that contains the lower data bytes received for I2C Controller Read mode transactions. Note: During I2C read transactions, data is updated as each byte is received/acknowledged, so reading back this register during active I2C read transactions will cause an I2CRJCT fault to be issued. BIT 15 14 13 12 11 10 9 8 Field I2CRBYTE1[7:0] Reset 0xFF Access Type Read Only BIT 7 6 5 4 3 2 1 0 Field I2CRBYTE0[7:0] Reset 0xFF Access Type Read Only BITFIELD BITS DESCRIPTION I2CRBYTE1 15:8 I2C Read Data Byte 1 This is the 1st byte space available for use by I2C Controller Read mode transactions. I2CRBYTE0 7:0 I2C Read Data Byte 0 This is the 0th (LS) byte space available for use by I2C Controller Read mode transactions. I2CCFG (0x89) I2CCFG is a read- and write-accessible register that configures I2C controller modes and transaction formats. Once I2CSEND initiates a read or write transaction, attempts to write I2CCFG during the transaction will be ignored and will cause an I2CRJCT fault to be issued.

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 307 BIT 15 14 13 12 11 10 9 8 Field I2CFSCL I2CWALT I2CRFMT I2C10BIT I2CPNTRLNGTH I2CALRTEN – – Reset 0b1 0b0 0b1 0b0 0b0 0b0 – – Access Type Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read – – BIT 7 6 5 4 3 2 1 0 Field – – I2CANACONTEN I2CCONTEN I2CGLITCHEN I2CNOISEEN I2CRDTREN I2CTOEN Reset – – 0b0 0b0 0b0 0b0 0b0 0b0 Access Type – – Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read BITFIELD BITS DESCRIPTION I2CFSCL 15 I2C Controller SCL Speed Selection 0 = fSCL = 100kHz 1 = fSCL = 400kHz (default) This bit determines fSCL used for the transaction initiated by the I2C controller in response to a write to I2CSEND. I2CWALT 14 I2C Controller Alternate Write Mode Selection 0 = Normal Mode (1, 2, 3, or 4 Byte Data) 1 = Alternate Mode (1, 2, 0, or 4 Byte Data) This bit determines the data lengths available in Write mode using I2CDATALNGTH selection bits. I2CRFMT 13 I2C Controller Read Format Selection 0 = Normal Format 1 = Combined Format (default) This bit determines the format used for Read mode transactions initiated by the I2C controller in response to a write to I2CSEND (does not impact Write mode transactions). I2C10BIT 12 I2C Controller Address Mode Selection 0 = 7-Bit Addressing (default) 1 = 10-Bit Addressing This bit determines the address format used for the transaction initiated by the I2C controller in response to a write to I2CSEND. I2CPNTRLNGTH 11 I2C Transaction Pointer Length Selection 0 - 1-Byte Pointer (default) 1 - 2-Byte Pointer This is the pointer length used for the requested I2C controller transactions. If 1-Byte Pointer mode is used (default, standard), both pointer bytes are available for use in I2C controller transactions using I2CPNTRSEL (minimizing configuration time). I2CALRTEN 10 I2C Alert Enable 0 = ALRTI2C Reporting Disabled (default)

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 308 BITFIELD BITS DESCRIPTION 1 = ALRTI2C Reporting Enabled If enabled, STATUS2:ALRTI2C reflects the bitwise OR of enabled/unmasked I2C fault indicators I2CSTAT[8:0]. The alert can be masked by setting I2CALRTEN = 0. The alert will be cleared when I2CSTAT is cleared and no new faults have been reported. I2CANACONTEN 5 I2C Bus Analog Contention Report Enable 0 = Bus Contention Monitoring Masked (default) 1 = Bus Contention Monitoring Reported See the data sheet for a detailed explanations of bus monitoring operations and limitations (such as setup and hold timing violations, glitch detection, and noise handling). A zero selection will still allow the monitor circuitry to run and report results in I2CSTAT:I2CCONT, but the monitored condition will not trigger an ALRTI2C issuance or an I2CSTAT:I2CSTATUS Transaction Error (10). I2CCONTEN 4 I2C Bus Digital Contention Report Enable 0 = Bus Contention Monitoring Masked (default) 1 = Bus Contention Monitoring Reported See the data sheet for a detailed explanations of bus monitoring operations and limitations (such as setup and hold timing violations, glitch detection, and noise handling). A zero selection will still allow the monitor circuitry to run and report results in I2CSTAT:I2CCONT, but the monitored condition will not trigger an ALRTI2C issuance or an I2CSTAT:I2CSTATUS Transaction Error (10). I2CGLITCHEN 3 I2C Bus Glitch Report Enable 0 = Bus Glitch Monitoring Masked (default) 1 = Bus Glitch Monitoring Reported See the data sheet for a detailed explanations of bus monitoring operations and limitations (such as setup and hold timing violations, glitch detection, and noise handling). A zero selection will still allow the monitor circuitry to run and report results in I2CSTAT:I2CGLITCH, but the monitored condition will not trigger an ALRTI2C issuance or an I2CSTAT:I2CSTATUS Transaction Error (10). I2CNOISEEN 2 I2C Bus Noise Report Enable 0 = Bus Noise Monitoring Masked (default) 1 = Bus Noise Monitoring Reported See the data sheet for a detailed explanations of bus monitoring operations and limitations (such as setup and hold timing violations, glitch detection, and noise handling).

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 309 BITFIELD BITS DESCRIPTION A zero selection will still allow the monitor circuitry to run and report results in I2CSTAT:I2CNOISE, but the monitored condition will not trigger an ALRTI2C issuance or an I2CSTAT:I2CSTATUS Transaction Error (10). I2CRDTREN 1 I2C Redundant Read Check Enable 0 = Redundant Read Check Disabled (default) 1 = Redundant Read Check Enabled See the data sheet for a detailed explanation of redundant read check operations and limitations. This bit enables both Redundant Read transactions as well as discrepancy reporting. I2CTOEN 0 I2C Timeout Enable 0 = DIsable I2C Transaction Watchdog (default) 1 = Enable I2C Transaction Watchdog I2CSTAT (0x8A) I2CSTAT is a read- and write-accessible register that shows the current status of the I2C controller. The I2CSTATUS bits are updated in real time, indicating the current state of the I2C controller and any requested transaction. This status content can be cleared by write operations and modified by transaction progress or subsequent transaction requests. The second byte contains I2C fault bits, indicating a fault was observed during an I2C transaction. These bits are updated as they occur and are only cleared by writing to 0. Several faults may occur during a corrupted transaction, so it is best to wait until I2CSTATUS reads 10 (Transaction Error) to ensure all errors have been reported. While not advisable, if further I2C transactions are requested before the I2C fault bits from previous transactions are read back and cleared, a cumulative history of faults will be listed, even if subsequent transactions are successful. BIT 15 14 13 12 11 10 9 8 Field I2CSTATUS[1:0] – – – – – I2CRJCT Access Type Write, Read, Ext – – – – – Write, Read, Ext BIT 7 6 5 4 3 2 1 0 Field I2CDEVNACK I2CDATANACK I2CANACONT I2CCONT I2CGLITCH I2CNOISE I2CRDTRERR I2CTIMEOUT Reset 0b0 0b0 0b0 0b0 0b0 0b0 0b0 0b0 Access Type Write 0 to Clear, Read Write 0 to Clear, Read Write 0 to Clear, Read Write 0 to Clear, Read Write 0 to Clear, Read Write 0 to Clear, Read Write 0 to Clear, Read Write 0 to Clear, Read

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 310 BITFIELD BITS DESCRIPTION I2CSTATUS 15:14 I2C Status Indicator 00 - No Transaction Requested (default) 01 - Transaction in Progress 10 - Transaction Error 11 - Transaction Complete I2CSTATUS indicates the current status of the I2C controller. These status bits will be cleared when written to 0 or when a new transaction is begun using I2CSEND. Writing to a logic 1 has no effect. Note specific clear/update behavior. I2CRJCT 8 I2C Transaction Reject Error Indicator 0 = No Error Reported (default) 1 = I2C Operation Rejected Indicates one or more I2C controller operations were rejected because 1) a user Write to I2CSEND requested a new I2C transaction during an active I2C transaction, 2) a user Write to a protected I2C controller register was attempted during an active I2C transaction, or 3) a user Read from an I2CRDATA register was requested during an active I2C Read transaction. See I2C controller register descriptions for complete details. Cleared only by writing to a logic 0. Writing to a logic 1 has no effect. I2CDEVNACK 7 I2C Device ID Not Acknowledged Indicator 0 = No Error Reported (default) 1 = Target Address Not Acknowledged Indicates the I2C transaction Device ID byte(s) were not acknowledged by a target. This may indicate the target is malfunctioning or not present on the bus. For Combined Format Read transactions, both target address acknowledge pulses are required to avoid an error. Cleared only by writing to a logic 0. Writing to a logic 1 has no effect. I2CDATANACK 6 I2C Data Not Acknowledged Inidcator 0 = No Error Reported (default) 1 = Data Byte Not Acknowledged Indicates one or more I2C transaction data byte(s) written were not acknowledged by a target. This may indicate the target is malfunctioning, not present on the bus, is busy, or has rejected an unsupported transaction. Cleared only by writing to a logic 0. Writing to a logic 1 has no effect. I2CANACONT 5 I2C Bus Analog Contention Error 0 = No Error Reported (default) 1 = I2C Bus Contention Error Reported

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 311 BITFIELD BITS DESCRIPTION Indicates an analog bus contention condition was observed. Analog contention is reported when the sampled SDA value does not match the value driven by the I2C controller. This monitor observes the analog-filtered SDA port sampled by the analog- filtered SCL port when driven by the I2C controller, emulating the filter circuitry typically used in I2C target devices. Note that incoming SDA data from targets in Read mode is latched using the analog- filtered versions of SDA and SCL. Cleared only by writing to a logic 0. Writing to a logic 1 has no effect. I2CCONT 4 I2C Bus Digital Contention Error 0 = No Error Reported (default) 1 = I2C Bus Contention Error Reported Indicates a bus contention condition was observed. Digital contention is reported when a digital oversampled port result does not match the value driven by the I2C controller. This monitor observes the unfiltered SCL port and the SDA port when driven by the I2C controller during periods when the signals should be settled. Digitally oversampled contention is more sensitive than analog contention (which employs analog filters). Cleared only by writing to a logic 0. Writing to a logic 1 has no effect. I2CGLITCH 3 I2C Bus Glitch Error 0 = No Error Reported (default) 1 = I2C Bus Glitch Error Reported Indicates a bus glitch condition was observed. A glitch is reported when a digitally oversampled port monitor reports two or more consecutive samples that disagree with the digitally evaluated filter value. This condition may also be reported if slow transition times, setup time, or hold time violations occur (outside I2C specifications). This monitor observes the unfiltered SCL port and the SDA port outside specified transition intervals. Cleared only by writing to a logic 0. Writing to a logic 1 has no effect. I2CNOISE 2 I2C Bus Noise Error 0 = No Error Reported (default) 1 = I2C Bus Noise Error Reported Indicates a noisy bus condition was observed. A noise condition is reported when a digitally oversampled port monitor reports a large amount of samples (>25%) that disagree with the evaluated filter value. This condition may also be reported if slow transition times, setup time, or hold time violations occur (outside I2C specifications). This monitor observes the unfiltered SCL port and the SDA port outside specified transition intervals.

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 312 BITFIELD BITS DESCRIPTION Cleared only by writing to a logic 0. Writing to a logic 1 has no effect. I2CRDTRERR 1 I2C Redundant Read Error Inidcator 0 = No Error Reported (default) 1 = I2C Redundant Read Error Reported Indicates the results of an I2C Redundant Read Transaction Check failed. This means the data read back in the first read transaction did not match the data in the second read transaction. This function is only enabled if I2CRDTREN = 1. Cleared only by writing to a logic 0. Writing to a logic 1 has no effect. I2CTIMEOUT 0 I2C Time Out Error Inidcator 0 = No Error Reported (default) 1 = I2C Transaction Timed Out Indicates the transaction did not complete in the expected period of time. This function is only enabled if I2CTOEN = 1. Cleared only by writing to a logic 0. Writing to a logic 1 has no effect. I2CSEND (0x8B) I2CSEND is a read- and write-accessible register that configures and initiates an I2C controller transaction. A write to this register will initiate an I2C controller transaction. Only one transaction is supported at any given time. If a write to I2CSEND occurs during an active I2C transaction already in progress, the latest transaction request will be ignored and the I2CSEND contents will not be updated. If this occurs, an I2CRJCT fault will be issued. A read from this register will readback the current contents. This will represent the last transaction request accepted by the I2C controller. BIT 15 14 13 12 11 10 9 8 Field I2CPNTRSEL I2CDATALNGTH[1:0] I2CDATASEL[1:0] I2CDEVIDEXT[2:0] Reset 0b0 0b01 0b01 0b000 Access Type Write, Read Write, Read Write, Read Write, Read BIT 7 6 5 4 3 2 1 0 Field I2CDEVID[6:0] I2CRWB Reset 0b0000000 0b0

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 313 Access Type Write, Read Write, Read, Ext BITFIELD BITS DESCRIPTION I2CPNTRSEL 15 I2C Transaction Pointer Selection 0 - Use I2CPBYTE0 1 - Use I2CPBYTE1 Selects the Pointer byte used for the requested I2C Controller Write mode or Combined Format Read mode transaction. If I2CPNTRLNGTH = 1 (2-byte pointer mode), this bit is ignored and both bytes are sent. I2CDATALNGTH 14:13 I2C Transaction Data Length 00 - 1-Byte Read and Write 01 - 2-Byte Read and Write (default) 10 - 3-Byte Read, 3- or 0-Byte Write 11 - 4-Byte Read and Write This is the data length used for the requested I2C controller transaction. When I2CWALT mode is engaged, the 3-Byte Data Length option is replaced by a 0- Byte Data option for Write mode only. I2CDATASEL 12:11 I2C Data Location Selection 00 - Byte 0 01 - Byte 1 (default) 10 - Byte 2 11 - Byte 3 Selects the location of the data bytes(s) to be transferred during Write transactions and the target location for data byte(s) used for storage during Read transactions. The selection indicates the location of the MSB of the data space used during the transaction; the number of bytes used is set by I2CDATALNGTH. Some limitations do apply; see the data sheet for details. I2CDEVIDEXT 10:8 I2C Device ID Extension This is the 3-Bit Device ID Extension (Target Address[9:7]) available for I2C controller transactions in 10-Bit Address mode. This content is ignored in 7-Bit Address mode. I2CDEVID 7:1 I2C Device ID This is the Device ID (Target Address[6:0]) used for the requested I2C controller transaction. I2CRWB 0 I2C R/WB Controller Transaction Type 0 = Write Mode Transaction (default) 1 = Read Mode Transaction This bit determines transaction type initiated by the I2C controller in response to a write to I2CSEND. ID1 (0x8C) ID1 is a read-accessible register that contains the 2 LSBs of the unique device ID stored in ROM, and is subject to ROMCRC validation.

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 314 BIT 15 14 13 12 11 10 9 8 Field DEVID[15:8] Reset 0x00 Access Type Read Only BIT 7 6 5 4 3 2 1 0 Field DEVID[7:0] Reset 0x00 Access Type Read Only BITFIELD BITS DESCRIPTION DEVID 15:0 Device ID (partial) The 1 LSB of the 40-bit factory-programmed device ID. ID1[0] always reads logic 1. A valid device ID has two or more bits set to logic 1. Read only. ID2 (0x8D) ID2 is a read-accessible register that contains the 2 MSBs of the unique device ID stored in ROM, and is subject to ROMCRC validation. BIT 15 14 13 12 11 10 9 8 Field DEVID[31:24] Reset 0x00 Access Type Read Only BIT 7 6 5 4 3 2 1 0 Field DEVID[23:16] Reset 0x00 Access Type Read Only

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 315 BITFIELD BITS DESCRIPTION DEVID 15:0 Device ID (partial) Two bytes of the 40-bit factory-programmed device ID. A valid device ID has two or more bits set to logic 1. Read only. ID3 (0x8E) ID3 is a read-accessible register that contains the MSB of the unique device ID and factory calibration data stored in ROM, and is subject to ROMCRC validation. BIT 15 14 13 12 11 10 9 8 Field OTP2[7:0] Reset 0x00 Access Type Read Only BIT 7 6 5 4 3 2 1 0 Field DEVID[39:32] Reset 0x00 Access Type Read Only BITFIELD BITS DESCRIPTION OTP2 15:8 Factory Calibration Data Read only. DEVID 7:0 Device ID (partial) The MSB of the 40-bit factory-programmed device ID. A valid device ID has two or more bits set to logic 1. Read only. OTP3REG (0x8F) Factory Calibration Data ROM and subject to ROMCRC validation. BIT 15 14 13 12 11 10 9 8 Field OTP3[15:8] Reset 0x0000 Access Type Read Only

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 316 BIT 7 6 5 4 3 2 1 0 Field OTP3[7:0] Reset 0x0000 Access Type Read Only BITFIELD BITS DESCRIPTION OTP3 15:0 Factory Calibration Data Read only. OTP4REG (0x90) Factory Calibration Data ROM and subject to ROMCRC validation. BIT 15 14 13 12 11 10 9 8 Field OTP4[1:0] ALTREF_OTP[13:8] Reset 0b00 0b00000000000000 Access Type Read Only Read Only BIT 7 6 5 4 3 2 1 0 Field ALTREF_OTP[7:0] Reset 0b00000000000000 Access Type Read Only BITFIELD BITS DESCRIPTION OTP4 15:14 Factory Calibration Data Read only. ALTREF_OTP 13:0 Factory Calibration Data Read only. OTP5REG (0x91) Factory Calibration Data ROM and subject to ROMCRC validation. BIT 15 14 13 12 11 10 9 8

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 317 Field OTP5[15:8] Reset 0x0000 Access Type Read Only BIT 7 6 5 4 3 2 1 0 Field OTP5[7:0] Reset 0x0000 Access Type Read Only BITFIELD BITS DESCRIPTION OTP5 15:0 Factory Calibration Data Read only. OTP6REG (0x92) Factory Calibration Data ROM and subject to ROMCRC validation. BIT 15 14 13 12 11 10 9 8 Field OTP6[15:8] Reset 0x0000 Access Type Read Only BIT 7 6 5 4 3 2 1 0 Field OTP6[7:0] Reset 0x0000 Access Type Read Only BITFIELD BITS DESCRIPTION OTP6 15:0 Factory Calibration Data Read only.

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 318 OTP7REG (0x93) Factory Calibration Data ROM and subject to ROMCRC validation. BIT 15 14 13 12 11 10 9 8 Field OTP7[15:8] Reset 0x0000 Access Type Read Only BIT 7 6 5 4 3 2 1 0 Field OTP7[7:0] Reset 0x0000 Access Type Read Only BITFIELD BITS DESCRIPTION OTP7 15:0 Factory Calibration Data Read Only. OTP8REG (0x94) Factory Calibration Data ROM and subject to ROMCRC validation. BIT 15 14 13 12 11 10 9 8 Field OTP8[15:8] Reset 0x0000 Access Type Read Only BIT 7 6 5 4 3 2 1 0 Field OTP8[7:0] Reset 0x0000 Access Type Read Only

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 319 BITFIELD BITS DESCRIPTION OTP8 15:0 Factory Calibration Data Read only. OTP9REG (0x95) Factory Calibration Data ROM and subject to ROMCRC validation. BIT 15 14 13 12 11 10 9 8 Field OTP9[15:8] Reset 0x0000 Access Type Read Only BIT 7 6 5 4 3 2 1 0 Field OTP9[7:0] Reset 0x0000 Access Type Read Only BITFIELD BITS DESCRIPTION OTP9 15:0 Factory Calibration Data Read only. OTP10REG (0x96) Factory Calibration Data ROM and subject to ROMCRC validation. BIT 15 14 13 12 11 10 9 8 Field OTP10[15:8] Reset 0x0000 Access Type Read Only BIT 7 6 5 4 3 2 1 0 Field OTP10[7:0] Reset 0x0000

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 320 Access Type Read Only BITFIELD BITS DESCRIPTION OTP10 15:0 Factory Calibration Data Read Only. OTP11REG (0x97) Factory Calibration Data ROM and subject to ROMCRC validation. BIT 15 14 13 12 11 10 9 8 Field OTP11[15:8] Reset 0x0000 Access Type Read Only BIT 7 6 5 4 3 2 1 0 Field OTP11[7:0] Reset 0x0000 Access Type Read Only BITFIELD BITS DESCRIPTION OTP11 15:0 Factory Calibration Data Read Only. OTP12REG (0x98) Factory Calibration Data ROM and subject to ROMCRC validation. BIT 15 14 13 12 11 10 9 8 Field ROMCRC[7:0] Reset 0x00 Access Type Read Only BIT 7 6 5 4 3 2 1 0

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756 www.analog.com Analog Devices | 321 Field OTP12[7:0] Reset 0x00 Access Type Read Only BITFIELD BITS DESCRIPTION ROMCRC 15:8 ROM CRC Value 8-bit CRC value computed from the onboard read-only memory content. ID and OTP ROM output data content is protected by a 8-bit CRC with polynomial 0xA6 (x8 + x6+ x3 + x2 + 1). Read only. OTP12 7:0 Factory Calibration Data Read Only.

Ordering Information

PART NUMBER TEMP RANGE PIN-PACKAGE ADES1754GCB/V+ -40°C to +105°C 64 LQFP ADES1754GCB/V+T -40°C to +105°C 64 LQFP ADES1755GCB/V+ -40°C to +105°C 64 LQFP ADES1755GCB/V+T -40°C to +105°C 64 LQFP ADES1756GCB/V+ -40°C to +105°C 64 LQFP ADES1756GCB/V+T -40°C to +105°C 64 LQFP + Denotes a lead(Pb)-free/RoHS-compliant package. T Denotes tape-and-reel. Chip Information PROCESS: BiCMOS

14-Channel, High-Voltage Data- Acquisition Systems ADES1754/ADES1755/ADES1756

Revision History

0 11/23 Initial release — Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. w w w . a n a l o g . c o m Analog Devices | 322

Product Information

ADES1754 specifications and overview.

Summary

14-Channel, High-Voltage Data- Acquisition Systems 19-101802; Rev 0; 11/23

Description

14-Channel, High-Voltage Data- Acquisition Systems 19-101802; Rev 0; 11/23

Source title ADES1754 Datasheet(PDF) - Analog Devices

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