ADEMA124/ADEMA127 (Rev.A)
Document overview
- Manufacturer or author: Analog Devices, Inc.
- PDF pages: 78
Technical content
Simultaneously Sampling 4- and 7-Channel ΣΔ ADC with SPI Rev. A DOCUMENT FEEDBACK TECHNICAL SUPPORT Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. All Analog Devices products contained herein are subject to release and availability.
FEATURES
►4- or 7-channel high performance, simultaneous sampling Σ-Δ ADCs ►SNR up to 105dB ►Programmable sample rate of up to 64kSPS ►Wide input-voltage range: ±1.2VPK, 848mVRMS full-scale ►High impedance, differential inputs ►Internal voltage reference temperature coefficient: 5ppm/°C typi- cal ►Integrated digital integrator and high-pass filter for use with Rogowski coils ►Fast start-up with first samples in 0.5ms after valid supply ►Tamper detect mode, low power for battery back-up ►4-wire SPI with bidirectional CRC and daisy-chain functionality ►Simple synchronization of multiple ADC devices ►Gain, phase, and offset compensation for each channel ►Unique SPI readable part ID registers ►Only 18mW power consumption with 7-channel ADC ►Wide temperature range: −40°C to +125°C ►Compact 32-lead, 5mm x 5mm LFCSP
APPLICATIONS
►Polyphase energy meters ►Split-phase energy meters ►Branch circuit monitoring ►Power distribution units ►Power quality monitoring ►Circuit breakers ►Protection relays ►Electric vehicle supply equipment GENERAL DESCRIPTION The ADEMA124/ADEMA127 are 4- and 7-channel simultaneously sampling 24-bit sigma delta analog-to-digital converters (ADC), ide- al for use in polyphase or split-phase energy metering applications. The ADEMA124/ADEMA127 are compatible with voltage dividers, shunts, and isolated current sensors such as current transformers and Rogowski coils. The ADEMA124/ADEMA127 include independent hardware and DSP filters enabling gain, phase and offset compensation on each ADC channel. The ADEMA124/ADEMA127 also have bespoke compensation and DSP features, which include an integrator and second-order high-pass filter to allow streamlined Rogowski sensor implementations. DSP filter coefficients for typical use cases are automatically loaded and are accessible for customization of filter characteristics. The sinc compensation, LPF, and DSP decimate-by-2 feature ex- tend the usable analog bandwidth by up to 70% for a given output sample rate. The high bandwidth makes ADEMA124/ADEMA127 suitable for IEC 61000-4-30 Power Quality Class A and Class S meters. The ADEMA124/ADEMA127 can be used in systems compliant to active energy standards IEC 62053-21, IEC 62053-22, OIML R46, and ANSI C12.1, and reactive energy standards IEC 62053-23, IEC 62053-24, and EN 50470-3. The ADEMA124/ADE- MA127 can be used in circuit breakers and protection relays, particularly with a Rogowski sensor due to a 0.5ms fast start-up time. The ADEMA124/ADEMA127 have a flexible SPI interface for con- figuration and data retrieval. The daisy-chain SPI interface allows multiple compatible ADCs to be serviced simultaneously by a single SPI port, which saves many pins on the host microcontroller. Additionally, the SPI port is daisy-chain compatible with the 2- and 3-channel isolated ADC, ADE9112/ADE9113. To maintain integrity of ADC waveform data, independent cyclic redundancy checks (CRC) are available to detect errors in inbound and outbound SPI packets, and incidental changes of configuration registers. Table 1. Product Comparison
Data Sheet ADEMA124/ADEMA127 TABLE OF CONTENTS analog.com Rev. A | 2 of 78
REVISION HISTORY
11/2025—Rev. 0 to Rev. A Changes to ADC Gain Drift over Temperature Parameter; ADC Transfer Function Parameter; and 7/2025—Revision 0: Initial Version
VDD = 3.3V ± 10%, GND = 0V, on-chip reference, fXTALIN = 16.384MHz, TMIN to TMAX = −40°C to +125°C , TA = 25°C (typical). Output rate 4kHz. Values are based off full performance mode, ADC_POWER_MODE = 11, unless otherwise specified. Table 2. Electrical Characteristics
Table 2. Electrical Characteristics (Continued)
1 Guaranteed by design. Not subject to production test. 2 The reference temperature coefficient is trimmed in production test to optimize channel gain.
All specifications typical figures for fXTALIN = 16.384MHz and default DSP filter coefficients. Table 3. Bandwidth and Pass-Band Flatness Characteristics 1 N/A means not applicable. This is not a valid configuration.
Table 5. ADEMA124/ADEMA127 Absolute Maximum Ratings
1 Analog Devices recommends that reflow profiles used in soldering RoHS com-
this standard, refer to the JEDEC. ing conditions for extended periods may affect product reliability. environment. Careful attention to PCB thermal design is required. Table 6. Thermal Resistance
1 Test condition 1: Thermal impedance simulated values are based upon use of
devices and circuit boards can discharge without detection. taken to avoid performance degradation or loss of functionality.
Table 7. Pin Function Descriptions (Continued) signal to synchronize the reading of ADC outputs. more details, see the Tamper Detect Mode section. clock at the XTALIN pin. Use CLKOUT to provide a clock to other devices. 17 17 MOSI Data Input for SPI Port. 18 18 MISO Data Output for SPI Port. 19 19 SCLK Serial Clock Input for SPI Port. All serial data transfers are synchronized to this clock. 20 20 CS Chip Select for SPI Port. 21 21 VLDOOUT 1.9V Output of Digital Low Dropout (LDO) Regulator. 23 23 DGND Digital Ground Reference. 24 24 NC No Connect. This pin has an internal connection. Connect to DGND. a crystal across XTALIN and XTALOUT to provide a clock source for the ADEMA124/ADEMA127. The XTALOUT pin must float when unused. 26 26 XTALIN Controller Clock Input. Alternatively, a crystal can be connected across XTALIN and XTALOUT. unused. For more details, see the Standby Mode section. 29, 30 29, 30 V0P, V0M Analog Inputs for ADC Channel 0. 31, 32 V4P, V4M Analog Inputs for ADC Channel 4. EPAD Exposed Pad. The exposed pad must be connected to DGND.
Figure 37. Sample Count Convergence to Specified Gain Error, TDM to CCM,
Figure 38. ADEMA127 Test Circuit, 3PH Voltage and Current
Data Sheet ADEMA124/ADEMA127 TERMINOLOGY analog.com Rev. A | 19 of 78 Crosstalk Crosstalk is measured by grounding 1-channel and applying a full- scale 50Hz or 60Hz signal on all the other channels. The crosstalk is equal to the ratio between the grounded ADC output value and its ADC full-scale output value. The ADC outputs are acquired for 100sec. Crosstalk is expressed in decibels. Differential Input Impedance (DC) The differential input impedance represents the impedance be- tween the pair VxP and VxM. It varies with the ADC_GAIN_CHx gain selection, as shown in Differential Input Impedance specifica- tion in Table 2. ADC Offset Error ADC offset error is the difference between the average measured ADC output code with both inputs connected to AGND and the ideal ADC output code of zero. ADC offset is expressed in μV. ADC Offset Drift Over Temperature The ADC offset drift is the change in offset over temperature. It is measured at −40°C, +25°C, and +125°C. Calculate the offset drift over temperature as follows: Dr i f t = max O f fs et − 40 ° C − O f f s et + 25° C O f fs et + 125 ° C − O f f s et + 25° C + 125 ° C − + 25 ° C (1) Offset drift is expressed in nV/°C. ADC Gain Error The gain error in the ADCs represents the difference between the measured ADC output code (minus the offset) and the ideal output code when an external voltage reference of 1.25V is used. The difference is expressed as a percentage of the ideal code. It represents the overall gain error of 1-channel. ADC Gain Drift Over Temperature This temperature coefficient includes the temperature variation of the ADC gain while using an external voltage reference of 1.25V. It represents the overall temperature coefficient of one current or voltage channel. With an external voltage reference of 1.25V in use, the ADC gain is measured at −40°C, +25°C, and +125°C. Then the temperature coefficient is computed as follows: Dri ft = m ax G ai n − 40 ° C − G ai n + 25° C G ai n + 25° C × − 40° C − + 25 ° C , G ai n + 125 ° C − G ai n + 25 ° C G ai n + 25 ° C × + 125 ° C − + 25° C (2) Gain drift is measured in ppm/°C. AC Power-Supply Rejection Ratio (PSRR) AC PSRR quantifies the measurement error as a percentage of reading when the DC power supply is nominal (VNOM) and modu- lated with AC, and the inputs are grounded. For the AC PSRR measurement, 20sec samples are captured with nominal supplies (3.3V, which is V1) and a second set (V2) is captured with an addi- tional AC signal (120mVrms at 50Hz) introduced onto the supplies. Then, the PSRR is expressed as PSRR = 20log10(V2/V1). Signal-to-Noise Ratio (SNR) SNR is calculated by inputting a 50Hz signal, and samples are acquired for 8sec. The amplitudes for each frequency up to the bandwidth given in Table 1 as the ADC output bandwidth (−3dB) are calculated. To determine the SNR, the signal at 50Hz is com- pared to the sum of the power from all the other frequencies, re- moving power from its harmonics. The value for SNR is expressed in decibels. Signal-to-Noise and Distortion Ratio (SINAD) SINAD is calculated by inputting a 50Hz signal, and samples are acquired for 8sec. To determine the SINAD, the signal at 50Hz is compared to the sum of the power from all the other frequencies. The value for SINAD is expressed in decibels. Total Harmonic Distortion (THD) THD is calculated by inputting a 50Hz signal, and samples are acquired for over 8sec. To determine the THD, the amplitudes of the 50Hz harmonics up to the bandwidth are root sum squared. The value for THD is expressed in decibels. Spurious-Free Dynamic Range (SFDR) SFDR is calculated by inputting a 50Hz signal, and samples are acquired for over 8sec. To determine the SFDR, the amplitude of the largest signal that is not a harmonic of 50Hz is recorded. The value for SFDR is expressed in decibels. ADC Pass-Band Flatness The bandwidth to which the ADC output is within 0.1dB of a 50Hz reference signal input. ADC Output Bandwidth The ADC output bandwidth is the bandwidth within −3dB, resulting from the digital filtering in the sinc3 and enabled DSP features.
Data Sheet ADEMA124/ADEMA127 THEORY OF OPERATION analog.com Rev. A | 20 of 78 Accurate measurement, real-time monitoring, and comprehensive management of energy flow is required across the electrical power distribution networks. The ADEMA124 and ADEMA127 are 4- and 7-channel simultaneously sampling ADCs designed with features specifically for energy metering. All ADC channels have fully-differ- ential inputs, identical dynamic range, programmable gain, and an independent 24-bit sigma delta ADC. Each ADC channel of the ADEMA124/ADEMA127 can directly support shunts, current transformers (CTs), and with the on-board digital integrators and HPFs, Rogowski sensors. The ADEMA124/ADEMA127 ADCs are flexible and scalable com- ponents in energy metrology systems. The daisy-chain communica- tion interface simplifies system architecture and allows a microcon- troller to service a series of ADEMA124/ADEMA127 as though they are a single device. Synchronization of the multiple ADCs is simplified to a SPI write to the SYNC_SNAP register of each ADC followed by a simultaneous assertion of the CS pins. The integrated gain, phase, and offset compensation along with other DSP fea- tures reduce processing resources of the host microcontroller and make processed ADC waveform samples immediately available to the system. The DSP decimate-by-2 enables higher bandwidth for reliable measurement of harmonics and, thus, superior power quality analy- sis for renewable energy resources, more efficient power delivery across the grid, and improved longevity of devices. GAIN AND OFFSET CORRECTION Gain and offset correction is commonly required in metrology sys- tems. The ADEMA124/ADEMA127 provide gain and offset calibra- tion bit fields for each ADC channel, which reduces the required processing burden of the host microcontroller. QUICK START GUIDE Upon providing the ADEMA124/ADEMA127 a 3.3V power supply and clock, the ADC immediately begins to produce samples per default configurations as shown in Figure 40. All communication with the ADEMA124/ADEMA127 is via SPI port. For more details, see the Fast Start-Up section. The typical use case provides a valid supply and clock, configures the datapath, write locks the configuration, and then harvests ADC waveform data in response to DREADY pin low transitions. It is most efficient to retrieve ADC waveform samples with long format SPI operations. The CRC checksums, STATUS0 and STATUS1 registers are returned alongside ADC waveform data from all chan- nels with long format SPI responses. The recommended repeated command is a long format SPI read of the STATUS2 register so all ADEMA124/ADEMA127 status information is continually returned to the microcontroller. The DATAPATH_CONFIG_LOCK and DSP_MEM_ACCESS_REQ have multiple functions but both bits are SPI write locks that protect their spaces by default. The functions of these bits is fully described in Configuration Lock and Access Bits section. The ADEMA124/ADEMA127 has an 8-bit register called SCRATCH that is not write protected and can be used for test SPI writes and reads. There are debug features to verify the 24-bit ADC waveform samples are being reliably retrieved by the system discussed in Communication Debug Features section. All values in DSP RAM are overwritten when any configuration of the MMR occurs. Configuration of the ADEMA124/ADEMA127 requires MMR addresses to be configured before DSP RAM ad- dresses. All default DSP filter coefficients loaded into DSP RAM are based on the typical 16.384MHz fXTALIN. The DSP coefficients can be modified. Writing the Lock Key to the WR_LOCK prevents unintended SPI writes to the ADEMA124/ADEMA127 configuration registers. The CRC_CHG bits in STATUS0 is set high if a change in configurations has occurred and can be monitored by the microcontroller.
oscillator circuit to generate a clock from an external crystal. Figure 39. Fast Start-Up Timing
low. Set the STDBY pin high to exit standby mode. values and require reconfiguration upon exit of standby mode. ADEMA124/ADEMA127 sample at a fixed 7.227kSPS rate in TDM. The input threshold is set with the 12-bit TDM_THRSH bit field. STDBY pin state, the CS pin state, or if a tamper is detected. TDM_ALLCH bit fields are shown in Table 29. enter CCM immediately after exiting a TDM cycle. Figure 42. TDM Entry and Event Detection
Data Sheet ADEMA124/ADEMA127 APPLICATIONS INFORMATION analog.com Rev. A | 24 of 78 Software Reset The SWRST register manages the software reset functionality. If this register is set to software reset command value of 0xD6, the ADEMA124/ADEMA127 enter the software reset state. In this state, all registers are reset to default values. When the software reset ends, the SWRST register clears automatically, and RESET_DONE bit in the STATUS0 register is set. The SWRST register is protected from writes when the lock key is set in the WR_LOCK register; First unlock the registers before initiating a software reset. For more details on WR_LOCK, see the Full Configuration Lock section. Do not write SPI commands before the SPI port is indicated as ready by the DREADY pin, SPI ready is shown in Figure 40. Any attempt to initiate a subsequent SPI command during software reset processing results in a failed SPI transaction. The ADEMA124/ADEMA127 have internal control blocks, regulators, and references not affected by software reset. After software reset, one of the procedures shown in the Start-Up Sequence and Timing section must be followed to initialize the ADEMA124/ADEMA127. On reset, the default retained MMR and MMR values are restored. The values in DSP RAM are initialized to default values when a DSP filter is enabled and the DATA- PATH_CONFIG_LOCK bit is set to 1. Hardware Reset The ADEMA124/ADEMA127 enter the reset state when the RESET pin is low. All retained MMR and MMR registers are initialized to the default values when the device exits the reset state. DSP RAM values are initialized when a DSP filter is enabled and the DATAPATH_CONFIG_LOCK bit is set to 1.
Table 8. SPI Command Bit Fields
31 RWB Set this bit to 1 if an SPI read
operation is to be executed. operation is to be executed.
30 LONG Set this bit to 1 for a long frame
Table 9. SPI Command Echo Bit Fields 7 ECHO_RWB Echo of last issued command. 6 ECHO_LONG Echo of requested command format. 2 RSRVD Reserved. This bit is set to 0.
1 CMD_CRC_ERRCRC check on the corresponding
0 IRQ Command response interrupt bit. 0 indicates that no interrupt is raised. configured interrupt has been raised. Table 10. Response Frame Types Default Response Transmitted between PoR release and MCLK on. the Long Format Operation section. Command Error Response Frame section.
Table 12. ADEMA124 Long Format Response Bit Fields [159:152] CMD ECHO [7:0] CMD ECHO [7:0] For more details, see Figure 45 and Table 9. [127:120] STATUS0 [7:0] STATUS0 [7:0] For more details, see Table 30. [95:88] STATUS1 [7:0] STATUS1 [7:0] For more details, see Table 30. [63:56] RESERVED [7:0] RESERVED [7:0] 0x00 is transmitted.
- ADDR [7:0] LSB of requested write address echoed back.
format and SPI short format operation.
- Set STREAM_DBG = Static Mode.
- Wait for DREADY pin to go low.
- Write to required values to ADC waveform data registers.
- DREADY is asserted according to the set sample rate.
the DREADY signal to avoid an unexpected increment.
- Set STREAM_DBG = Static Mode.
- Write to required values to ADC waveform data registers.
- Set STREAM_DBG = Count Mode.
- DREADY is asserted according to the set sample rate. On each
MA127 to exit either debug mode. Table 13. STREAM_DBG Bit Configuration
filters are available at any configured output sample rate. Access Bits and Full Configuration Lock sections. RAM, see the DSP RAM Details section. of Multiple Devices section. Figure 58. ADEMA124/ADEMA127 Datapath
Data Sheet ADEMA124/ADEMA127 APPLICATIONS INFORMATION analog.com Rev. A | 34 of 78 Analog Input Each ADEMA124/ADEMA127 channel has an independent, sec- ond-order, simultaneously sampling Σ-Δ converter. Each ADC chan- nel supports fully differential and pseudodifferential input configura- tions, each of which can go above and below AGND. General guidance on sensor connection and external circuitry are shown in the Sensor to ADC Interface section. Selectable Gain Each ADC has an independent selectable gain of 1 or 2 set by the corresponding ADC_GAIN_CHx bit in the ADC_GAIN register. The differential voltage range and single-ended voltage range is simultaneously adjusted based on the selected gain setting. For specifications, see differential voltage range and single-ended volt- age range in Table 2. Overranging of the ADC input results in saturation of the full-scale codes. There are no overwraps or sign changes. Overranging sets the Vx_WAV_OVRNG bit corresponding to the ADC channel the event occurred on. For more details on overrange indication, see Figure 58 and Figure 61. Common-Mode Each ADC channel has an independent common-mode range set- ting bit, ADC_CMI_CHx, in the ADC_CMI register. The typical CT and voltage divider sensors of AC measurement systems oscillate around AGND/DGND and do not require a common-mode offset. This is the default configuration. This feature enables the use of external amplifiers with a com- mon-mode offset of 1.2V to better interface with Rogowski coil sensors requiring a preamplifier. The feature is only available when the channel gain is 1. Setting both ADC_GAIN_CHx = 1 and ADC_CMI_CHx = 1 on a given channel is an invalid configuration. Invert Inversion of the ADC inputs allows for easy correction of inadver- tent assembly miswires or can be used as a design choice for more convenient PCB layout. Inversion of individual ADC channels is possible either by setting a negative gain value in the gain com- pensation or by setting corresponding bits in the ADC_INV register. Setting ADC_INV_CHx bits allows the ADC channels to be inverted without the increased power consumption associated with an ena- bled DSP filter. It is recommend to use the ADC_INV_CHx bit for an ADC channel rather than setting the associated GAIN[23:0] bit field to −1. Details on the gain compensation is shown in the Gain, Offset, and Crosstalk Compensation section. Bit field settings for the ADC_INV register is shown in Table 29. Voltage Reference The ADEMA124/ADEMA127 include a low noise, low drift, inter- nal band gap reference. The internal reference voltage of the ADEMA124/ADEMA127 is production trimmed to 1.25V. The ADE- MA124/ADEMA127 have a 1.25V internal voltage reference ena- bled by default as the voltage reference (VREF) for all ADC chan- nels. An external voltage reference may be routed to the REFOUT pin. To disable the internal reference and prevent contention between the internal and external voltage references, both the REF_PD_HP_REF bit and the REF_PD_BUFFER bit in the CON- FIG0 register must be set to 0. The REFOUT pin input impedance is shown in Table 2.
DSP RAM. Both bits prevent SPI writes to their spaces by default. Table 14. DATAPATH_CONFIG_LOCK Functions
1 SPI write protect for the datapath
1->0 ADC conversion process halted.
0 SPI writes to configuration bit fields in
Retained MMR and MMR allowed.
- ADC conversion process begins.
1 All default DSP filter coefficients loaded into DSP RAM are based on a
Table 15. DSP_MEM_ACCESS_REQ Functions
0 SPI write protect for the datapath
regardless of bit field content.
1 SPI writes to configuration bit fields in
see the Configuration Procedure section. the Full Configuration Lock section. Calibration Guide for gain calibration guidance. STATUS1 register bit is cleared. default settings reduces the maximum valid fMOD frequency.
The fs of ADEMA124/ADEMA127 is Equation 8. and details, see the DATARATE register in Table 30 . to 1 to prevent foldback from above the Nyquist frequency. Table 16. Recommended DATARATE Settings for Full Performance Mode phase error and datapath latencies between channels. the ADC sample set used to generate the ADC waveform data. multiple of the sample period different (1/fs). sigma delta modulator samples. integer multiple of the resolution. order CIC filter for over sample rates of 1024 and above.
Table 20. Digital High-Pass Filter Phase Response is specifically designed for Rogowski coil sensor compensation. gain with a phase shift of approximately −90°. DATAPATH_CONFIG_LOCK is set to 1. reduce quantization noise that otherwise occurs with small signals. grator is enabled. SHIFT is set to 0x1 by default. errors from the sinc and band-limiting filter. pass filter to be activated. details, see the WR_LOCK row of Table 30. restart data conversion with the new register settings applied.
- Unlock the datapath. Set DATAPATH_CONFIG_LOCK = 0.
- Make all changes to datapath configuration registers.
- Lock the datapath. Set DATAPATH_CONFIG_LOCK = 1.
- Wait for DREADY pin to be set low. The DREADY pin low
before the process is completed. using the DSP_MEM_ACCESS_REQ bit.
- Unlock the datapath. Set DATAPATH_CONFIG_LOCK = 0.
- Make all changes to datapath configuration registers.
- Lock the datapath. Set DATAPATH_CONFIG_LOCK = 1.
- Wait for DREADY pin to be set low. The DREADY pin low
before the process is completed.
- Request DSP memory access. Set DSP_MEM_ACCESS_REQ
- Wait for DSP actions to halt. Read from STATUS2 register until
- Make all changes to the DSP coefficients in Table 33 and Table
- Set DSP_MEM_ACCESS_REQ = 0.
- ADC waveform samples are immediately valid, however, filters
have a settling time based on the datapath configuration. ing bits in the MASK0, MASK1, and MASK2 registers to 1.
- SPI operations return different levels of status register detail, as
Table 21. Status Registers and IRQ by SPI Operation Figure 61. IRQ Generation short format waveform register reads. received by the ADEMA124/ADEMA127. STATUS1 contains the overrange status of all of the ADC channels.
The WATCHDOG_ERR bit may be set after a fatal fault condition. sample rate when triggered during hardware development. these bits are shown in Configuration Procedure section. frame is transmitted by the ADEMA124/ADEMA127 in response. Table 22. SPI Command CRC mat command to disable the CRC in hexadecimal is 00 02 C0 31. The long format disable is 40 02 C0 B7.
ensures a nonzero output with zero input. Table 23. SPI Command Response CRC packet on must be adjusted to compensate for the shorted packet. Figure 62. ADEMA127 Long Format, 16-Bit CRC_CCITT not Retrieved
Figure 69. Crystal Application Circuit OUT pins to provide a clock source for the ADEMA124/ADEMA127. ►ESRMAX is the maximum ESR, expressed in ohms. ►fCLK is 16.384MHz expressed in Hz as 16.384 × 106. ►C0 is the maximum shunt capacitance, expressed in farads. ►CL is the load capacitance, expressed in farads. to printed circuit board (PCB) traces. pins respectively, and shown in Table 2. load capacitors such that C1 = C2. register settings and provide each with a shared input clock source. devices must be ready for waveform data retrieval simultaneously. time the ADEMA124/ADEMA127 are in CCM. shown in Figure 70 and Figure 71.
Figure 74. 3-Phase Energy Meter with Isolated Voltage Sense
Data Sheet ADEMA124/ADEMA127 HARDWARE IDENTIFIERS analog.com Rev. A | 50 of 78 PRODUCT_ID register identifies the ADEMA124/ADEMA127 de- vice. The SILICON_REVISION register identifies the version of the ADE- MA124/ADEMA127. The UNIQUE_PART_ID_5 to UNIQUE_PART_ID_0 registers are a 48-bit unique ID number for each device, which enables traceability of all devices even after these devices are deployed.
The ADEMA124/ADEMA127 has 8-bit SPI accessible register and RAM addresses. Table 25. Memory Map - Registers ADEMA124/ADEMA127 enter and exit standby mode. the Configuration Lock and Access Bits. when the ADEMA124/ADEMA127 enter standby mode. the Configuration Lock and Access Bits. Table 26. Memory Map - DSP RAM functions are shown in Table 33. Configuration Lock and Access Bits. operations. See the Configuration Procedure section. register functions are shown in Table 34. Configuration Lock and Access Bits. operations. See the Configuration Procedure section.
Table 27. Retained MMR Summary Table 28. MMR Summary
Table 28. MMR Summary (Continued) 1 The default value is unique to every individual IC. 2 Subject to change with each silicon revision.
Data Sheet ADEMA124/ADEMA127 REGISTER SUMMARY analog.com Rev. A | 54 of 78 3 Default value follows product version.
Table 29. Retained MMR Details 0x00 Software Reset Register NOP. 00 Quarter Power Mode. fMOD ADC up to 0.512MHz supported. 10 Half Power Mode. fMOD ADC up to 1.024MHz supported. 11 Full Performance Mode. fMOD ADC up to 2.048MHz supported. 5 REF_PD_HP_REF Power Down Bit for the Reference Core. Active high control bit. is powered down, the buffer also needs to be powered down. ADEMA124/ADEMA127 and the communications host. 00 Normal Mode. x_WAV_x registers contain conversion results. 11 Reserved. Same as functional mode.
Table 29. Retained MMR Details (Continued)
1 CRC_DONE_MMR_RETAI
0 CRC_FORCE_MMR_RETA
Force Background Retained Register Map CRC Recalculation. Automatically clears when CRC recalculation has completed. to trigger a Tamper Detect Event. enabled channels' tamper detect flags go high. [2:0] TDM_NUM Tamper Detect Number of Samples Exceeding Threshold. Tamper Detect Event to be triggered.
absolute value of the 24 bit ADC data value. absolute value of the 24 bit ADC data value. configuration, and counters. Table 30. MMR Details refresh, this bit auto-clears and the reset_done IRQ is issued. request read and write access to the DSP memory. be read/written but has no other function. several chips simultaneously connected to a single SPI main.
Table 30. MMR Details (Continued) This bit clears itself back to 0 after one fXTALIN cycle. system latch internal counters to SNAPSHOT_COUNT_LO/HI. This bit clears itself back to 0 after one fXTALIN cycle. timing controller counter used in synchronization operation. timing controller counter used in synchronization operation. to be sent as part of SPI command response.
4 CRC_CHG_MMR_RETAIN
source to be sent as part of SPI command response. source to be sent as part of SPI command response. source to be sent as part of SPI command response. source to be sent as part of SPI command response. source to be sent as part of SPI command response. source to be sent as part of SPI command response. source to be sent as part of SPI command response. source to be sent as part of SPI command response. source to be sent as part of SPI command response.
0 SYNC_SNAP_REQUESTE
3 ECC_ERR_CORRECTED_
interrupt source to be sent as part of SPI command response.
0 DSP_MEM_ACCESS_REA
to writable registers of address of DSP RAM (0x400 to 0x7FF). back as the lock or unlock key depending on the state. 5 RESET_DONE Reset Done or Efuse Refresh Done. Non-maskable interrupt. Retained Register Map Background CRC Change Interrupt. changed. The new CRC value is located in CRC_RESULT. new CRC value is located in CRC_RESULT. ble error in the EFUSE memory. If this condition persists, it is recommended to issue a reset. set on the SPI read response.
counter value to be latched in SNAPSHOT_COUNT_LO/HI.
4 PROGRAM_ROM_ECC_E
data in response to data available from the ADCs. recalculation has yielded an updated CRC. 0 CRC_FORCE_MMR Force Background Register Map CRC Recalculation. Automatically clears when CRC recalculation has completed.
0 DATAPATH_CONFIG_LOC
sample rate, but maintains the signal bandwidth. scaler + 5 + decimation_rate + dsp_decimation_x2)). clock to the ADC sampling rate. tion_rate + dsp_decimation_x2 )). For more details, see the Datapath Configuration section. decimation_rate + dsp_decimation_x2 )). input clock frequency must be provided. For more details, see the Datapath Configuration section.
Select either allpass_en_chx or scf_en_chx. 1 External BLF and Sinc Droop.
0 GAIN_OFFSET_XT_EN_C
Select either allpass_en_chx or scf_en_chx.
1 External BLF and Sinc Droop. Select either allpass_en_chx or scf_en_chx. 1 External BLF and Sinc Droop. Select either allpass_en_chx or scf_en_chx. 1 External BLF and Sinc Droop. Select either allpass_en_chx or scf_en_chx. 1 External BLF and Sinc Droop.
Select either allpass_en_chx or scf_en_chx. 1 External BLF and Sinc Droop. Select either allpass_en_chx or scf_en_chx. 1 External BLF and Sinc Droop. maximum value of 0x1FFF, the 3MSBs are not used. maximum value of 0x1FFF, the 3MSBs are not used. maximum value of 0x1FFF, the 3MSBs are not used. maximum value of 0x1FFF, the 3MSBs are not used.
maximum value of 0x1FFF, the 3MSBs are not used. maximum value of 0x1FFF, the 3MSBs are not used. maximum value of 0x1FFF, the 3MSBs are not used. maximum value of 0x1FFF, the 3MSBs are not used. maximum value of 0x1FFF, the 3MSBs are not used. maximum value of 0x1FFF, the 3MSBs are not used. maximum value of 0x1FFF, the 3MSBs are not used. maximum value of 0x1FFF, the 3MSBs are not used. maximum value of 0x1FFF, the 3MSBs are not used. maximum value of 0x1FFF, the 3MSBs are not used.
0x16 7-Channel ADEMA127 ADC. 0x13 4-Channel ADEMA124 ADC.
the DSP RAM based on configured DSP options and the DECIMATION_RATE register setting. For the DSP RAM update procedure, see the Configuration Lock and Access Bits and Configuration Procedure sections. Table 31. DSP RAM Summary - Independent Per ADC Channel
Table 31. DSP RAM Summary - Independent Per ADC Channel (Continued) Table 32. DSP RAM Summary - Common for all ADC Channels
Table 32. DSP RAM Summary - Common for all ADC Channels (Continued)
the DSP RAM based on configured DSP options and the DECIMATION_RATE register setting. For the DSP RAM update procedure, see the Configuration Lock and Access Bits and Configuration Procedure sections. Table 33. DSP RAM Details - Independent Per ADC Channel
Table 33. DSP RAM Details - Independent Per ADC Channel (Continued)
5 XT_COMP_EN Crosstalk
1 Register values updated from ROM when corresponding DSP filter is enabled. Table 34. DSP RAM Details - Common for all ADC Channels
Table 34. DSP RAM Details - Common for all ADC Channels (Continued)
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