ADEL2020

ADEL2020 Improved Second Source to the EL2020 Data Sheet (REV. A)

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• Manufacturer or author: Analog Devices
• PDF pages: 12

Technical content

REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved. ADEL2020 Improved Second Source to the EL2020

FEATURES

Ideal for Video Applications 0.02% Differential Gain 0.04/H11543 Differential Phase 0.1 dB Bandwidth to 25 MHz (G = +2) High Speed

90 MHz Bandwidth (–3 dB)

500 V/ /H9262s Slew Rate

60 ns Settling Time to 0.1% (V O = 10 V Step) Low Noise 2.9 nV/ √Hz Input Voltage Noise Low Power 6.8 mA Supply Current 2.1 mA Supply Current (Power-Down Mode) High Performance Disable Function Turn-Off Time of 100 ns Input to Output Isolation of 54 dB (Off State) CONNECTION DIAGRAMS 8-Lead PDIP (N) 20-Lead SOIC (R) 1 8 4 5 3 6 2 7 ADEL2020 OUTPUT BAL BAL –IN +IN DISABLE OUTPUT BAL BAL –IN +IN DISABLE NCNC NCNC NCNC NCNC NCNC NCNC NC = NO CONNECT 1 20 4 17 3 18 5 16 8 13 7 14 6 15 9 12 10 11 2 19 TOP VIEW ADEL2020 TOP VIEW GENERAL DESCRIPTION The ADEL2020 is an improved second source to the EL2020. This op amp improves on all the key dynamic specifications while offering lower power and lower cost. The ADEL2020 offers 50% more bandwidth and gain flatness of 0.1 dB to beyond 25 MHz. In addition, differential gain and phase are less than 0.05% and 0.05 ° while driving one back terminated cable (150 Ω). FREQUENCY – Hz +0.1 100k 1M 10M 100M NORMALIZED GAIN – dB –0.1 RL = 150/H9024 /H1155015V /H115505V +0.1 –0.1 RL = 1k/H9024 /H1155015V /H115505V Figure 1. Fine-Scale Gain (Normalized) vs. Frequency and comes in both PDIP and SOIC packages.

100 IRE

Figure 2. Differential Gain and Phase vs. Supply Voltage

REV. A–2– ADEL2020–SPECIFICATIONS ADEL2020A Parameter Conditions Temperature Min Typ Max Unit INPUT OFFSET VOLTAGE 1.5 7.5 mV TMIN to TMAX 2.0 10.0 mV Offset Voltage Drift 7 µV/°C COMMON-MODE REJECTION V CM = ± 10 V VOS TMIN to TMAX 50 64 dB ±Input Current T MIN to TMAX 0.1 1.0 µA/V POWER SUPPLY REJECTION V S = ±4.5 V to ±18 V VOS TMIN to TMAX 65 72 dB ±Input Current T MIN to TMAX 0.05 0.5 µA/V INPUT BIAS CURRENT –Input T MIN to TMAX 0.5 7.5 µA +Input T MIN to TMAX 11 5 µA INPUT CHARACTERISTICS +Input Resistance 1 10 M Ω –Input Resistance 40 Ω +Input Capacitance 2p F OPEN-LOOP TRANSRESISTANCE V O = ±10 V RL = 400 Ω TMIN to TMAX 1 3.5 M Ω OPEN-LOOP DC VOLTAGE GAIN R L = 400 Ω, VOUT = ±10 V T MIN to TMAX 80 100 dB RL = 100 Ω, VOUT = ±2.5 V T MIN to TMAX 76 88 dB OUTPUT VOLTAGE SWING R L = 400 Ω TMIN to TMAX ±12.0 ±13.0 V Short-Circuit Current 150 mA Output Current T MIN to TMAX 30 60 mA POWER SUPPLY Operating Range ±3.0 ±18 V Quiescent Current T MIN to TMAX 6.8 10.0 mA Power-Down Current T MIN to TMAX 2.1 3.0 mA Disable Pin Current Disable Pin = 0 V T MIN to TMAX 290 400 µA Min Disable Pin Current to Disable T MIN to TMAX 30 µA DYNAMIC PERFORMANCE 3 dB Bandwidth G = +1; R FB = 820 90 MHz G = +2; RFB = 750 70 MHz G = +10; RFB = 680 30 MHz 0.1 dB Bandwidth G = +2; R FB = 750 25 MHz Full Power Bandwidth V O = 20 V p-p, RL = 400 Ω 8 MHz Slew Rate R L = 400 Ω, G = +1 500 V/ µs Settling Time to 0.1% 10 V Step, G = –1 60 ns Differential Gain f = 3.58 MHz 0.02 % Differential Phase f = 3.58 MHz 0.04 Degree INPUT VOLTAGE NOISE f = 1 kHz 2.9 nV/ √Hz INPUT CURRENT NOISE –I IN, f = 1 kHz 13 pA/ √Hz +IIN, f = 1 kHz 1.5 pA/ √Hz OUTPUT RESISTANCE Open Loop (5 MHz) 15 Ω Specifications subject to change without notice. (@ TA = 25/H11543C, VS = /H1155015 V dc, RL = 150 Ω, unless otherwise noted.)

REV. A–4– ADEL2020–Typical Performance Characteristics FREQUENCY – MHz 1 1000 CLOSED-LOOP GAIN – dB 10 100 –90 –180 –45 –135 –225 –270 PHASE SHIFT – Degrees GAIN = +1 RL = 150/H9024 GAIN PHASE VS = /H1155015V /H115505V VS = /H1155015V /H115505V TPC 1. Closed-Loop Gain and Phase vs. Frequency, G = + 1, RL = 150 Ω, RF = 1 kΩ for ±15 V, 910 Ω for ±5 V SUPPL Y VOL T AGE – /H11550V 02 0 –3dB BANDWIDTH – MHz GAIN = +1 RL = 150/H9024 VO = 250mV p-p 2468 1 0 1 2 1 4 1 6 1 8 100 110 RF = 750/H9024 RF = 1k/H9024 RF = 1.5k/H9024 PEAKING < 1.0dB PEAKING < 0.1dB TPC 2. –3 dB Bandwidth vs. Supply Voltage, Gain = +1, RL = 150 Ω FREQUENCY – MHz 1 1000 CLOSED-LOOP GAIN – dB 10 100 180 135 –45 PHASE SHIFT – Degrees GAIN = –1 RL = 150/H9024 GAIN PHASE VS = /H1155015V /H115505V VS = /H1155015V /H115505V TPC 3. Closed-Loop Gain and Phase vs. Frequency, G = –1, RL = 150 Ω, RF = 680 Ω for ±15 V, 620 Ω for ±5 V FREQUENCY – MHz 1 1000 CLOSED-LOOP GAIN – dB 10 100 –90 –180 –45 –135 –225 –270 PHASE SHIFT – Degrees GAIN = +1 RL = 1k/H9024 GAIN PHASE VS = /H1155015V /H115505V VS = /H1155015V /H115505V TPC 4. Closed-Loop Gain and Phase vs. Frequency, G = +1, RL = 1 kΩ, RF = 1 kΩ for ±15 V, 910 Ω for ±5 V SUPPL Y VOL T AGE – /H11550V 02 0 –3dB BANDWIDTH – MHz GAIN = –1 RL = 150/H9024 VO = 250mV p-p 2468 1 0 1 2 1 4 1 6 1 8 100 110 RF = 499/H9024 RF = 681/H9024 RF = 1k/H9024 PEAKING < 1.0dB PEAKING < 0.1dB TPC 5. –3 dB Bandwidth vs. Supply Voltage, Gain = –1, RL = 150 Ω FREQUENCY – MHz 1 1000 CLOSED-LOOP GAIN – dB 10 100 180 135 –45 PHASE SHIFT – Degrees GAIN = –1 RL = 1k/H9024 GAIN PHASE VS = /H1155015V /H115505V VS = /H1155015V /H115505V TPC 6. Closed-Loop Gain and Phase vs. Frequency, G = –1, RL = 1 kΩ, RF = 680 Ω for VS = ±15 V, 620 Ω for ±5 V

REV. A ADEL2020 –5– FREQUENCY – MHz 1 1000 CLOSED-LOOP GAIN – dB 10 100 –90 –180 –45 –135 –225 PHASE SHIFT – Degrees GAIN = +2 RL = 150/H9024 GAIN PHASE VS = /H1155015V /H115505V VS = /H1155015V /H115505V –270 TPC 7. Closed-Loop Gain and Phase vs. Frequency, G = +2, RL = 150 Ω, RF = 750 Ω for ±15 V, 715 Ω for ±5 V SUPPL Y VOL T AGE – /H11550V 02 0 –3dB BANDWIDTH – MHz GAIN = +2 RL = 150/H9024 VO = 250mV p-p 2468 1 0 1 2 1 4 1 6 1 8 100 110 RF = 500/H9024 RF = 750/H9024 RF = 1k/H9024 PEAKING < 1.0dB PEAKING < 0.1dB TPC 8. –3 dB Bandwidth vs. Supply Voltage, Gain = +2, RL = 150 Ω FREQUENCY – MHz 1 1000 CLOSED-LOOP GAIN – dB 10 100 –90 –180 –45 –135 –225 PHASE SHIFT – Degrees GAIN = +10 RF = 270/H9024 RL = 150/H9024 GAIN PHASE VS = /H1155015V /H115505V VS = /H1155015V /H115505V –270 TPC 9. Closed-Loop Gain and Phase vs. Frequency, G = +10, RL = 150 kΩ FREQUENCY – MHz 1 1000 CLOSED-LOOP GAIN – dB 10 100 –90 –180 –45 –135 –225 PHASE SHIFT – Degrees GAIN = +2 RL = 1k/H9024 GAIN PHASE VS = /H1155015V /H115505V VS = /H1155015V /H115505V –270 TPC 10. Closed-Loop Gain and Phase vs. Frequency, G = +2, RL = 1 kΩ, RF = 750 Ω for ±15 V, 715 Ω for ±5 V SUPPL Y VOL T AGE – /H11550V 02 0 –3dB BANDWIDTH – MHz GAIN = +10 RL = 150/H9024 VO = 250mV p-p 2468 1 0 1 2 1 4 1 6 1 8 100 110 RF = 232/H9024 RF = 442/H9024 RF = 1k/H9024 PEAKING < 0.5dB PEAKING < 0.1dB TPC 11. –3 dB Bandwidth vs. Supply Voltage, Gain = +10, RL = 150 Ω FREQUENCY – MHz 1 1000 CLOSED-LOOP GAIN – dB 10 100 –90 –180 –45 –135 –225 PHASE SHIFT – Degrees GAIN = +10 RF = 270/H9024 RL = 1k/H9024 GAIN PHASE VS = /H1155015V /H115505V VS = /H1155015V /H115505V –270 TPC 12. Closed-Loop Gain and Phase vs. Fre- quency, G = +10, R L = 1 kΩ

REV. A–6– ADEL2020 FREQUENCY – Hz 100k 100M OUTPUT VOL T AGE – V p-p 1M 10M OUTPUT LEVEL FOR 3% THD VS = /H115505V VS = /H1155015V TPC 13. Maximum Undistorted Output Voltage vs. Frequency FREQUENCY – Hz 10k 100M POWER SUPPL Y REJECTION – dB 1M 10M 100k CURVES ARE FOR WORST -CASE CONDITION WHERE ONE SUPPL Y IS VARIED WHILE THE OTHER IS HELD CONST ANT VS = /H1155015V VS = /H115505V RF = 715/H9024 AV = +2 TPC 14. Power Supply Rejection vs. Frequency FREQUENCY – Hz 10 100k VOLTAG E NOISE – nV/ Hz 1k 10k 100 100 CURRENT NOISE – pA/ Hz 100 VS = /H115505V TO /H1155015V INVERTING INPUT CURRENT VOLTAGE NOISE NONINVERTING INPUT CURRENT TPC 15. Input Voltage and Current Noise vs. Frequency FREQUENCY – Hz 10k 100M CLOSED-LOOP OUTPUT RESIST ANCE – /H9024 0.01 0.1 1M 10M 100k VS = /H1155015V VS = /H115505V GAIN = +2 RF = 715/H9024 TPC 16. Closed-Loop Output Resistance vs. Frequency JUNCTION TEMPERA TURE – /H11543C –60 140 SUPPL Y CURRENT – mA –40 –20 0 20 40 60 80 100 120 VS = /H1155015V VS = /H115505V TPC 17. Supply Current vs. Junction Temperature SUPPL Y VOL T AGE – /H11550V 02 0 SLEW RA TE – V//H9262s 800 400 200 1000 600 300 2468 1 0 1 2 1 4 1 6 1 8 1200 700 900 500 1100 RL = 400/H9024 GAIN = +10 GAIN = +2 GAIN = –10 TPC 18. Slew Rate vs. Supply Voltage

REV. A–8– ADEL2020 GENERAL DESIGN CONSIDERATIONS The ADEL2020 is a current feedback amplifier optimized for use in high performance video and data acquisition systems. Since it uses a current feedback architecture, its closed-loop bandwidth depends on the value of the feedback resistor. The –3 dB bandwidth is also somewhat dependent on the power supply voltage. Lowering the supplies increases the values of internal capacitances, reducing the bandwidth. To compen- sate for this, smaller values of feedback resistors are used at lower supply voltages. POWER SUPPLY BYPASSING Adequate power supply bypassing can be critical when optimiz- ing the performance of a high frequency circuit. Inductance in the power supply leads can contribute to resonant circuits that produce peaking in the amplifier’s response. In addition, if large current transients must be delivered to the load, then bypass capacitors (typically greater than 1 µF) will be required to provide the best settling time and lowest distortion. Although the recommended 0.1 µF power supply bypass capacitors will be sufficient in most applications, more elaborate bypassing (such as using two paralleled capacitors) may be required in some cases. CAPACITIVE LOADS When used with the appropriate feedback resistor, the ADEL2020 can drive capacitive loads exceeding 1000 pF directly without oscillation. Another method of compensating for large load capacitance is to insert a resistor in series with the loop output. In most cases, less than 50 Ω is all that is needed to achieve an extremely flat gain response. OFFSET NULLING A 10 kΩ pot connected between Pins 1 and 5, with its wiper con- nected to V+, can be used to trim out the inverting input current (with about ±20 µA of range). For closed-loop gains above about 5, this may not be sufficient to trim the output offset voltage to zero. Tie the pot’s wiper to ground through a large value resistor (50 kΩ for ±5 V supplies, 150 kΩ for ±15 V supplies) to trim the output to zero at high closed-loop gains. OPERATION AS A VIDEO LINE DRIVER The ADEL2020 is designed to offer outstanding performance at closed-loop gains of 1 or greater. At a gain of 2, the ADEL2020 makes an excellent video line driver. The low differential gain and phase errors and wide –0.1 dB bandwidth are nearly inde- pendent of supply voltage and load. For applications requiring widest 0.1 dB bandwidth, it is recommended to use 715 Ω feed- back and gain resistors. This will result in about 0.05 dB of peaking and a –0.1 dB bandwidth of 30 MHz on ±15 V supplies. DISABLE MODE By pulling the voltage on Pin 8 to common (0 V), the ADEL2020 can be put into a disabled state. In this condition, the supply current drops to less than 2.8 mA, the output becomes a high impedance, and there is a high level of isolation from input to output. In the case of a line driver, for example, the output impedance will be about the same as that for a 1.5 k Ω resistor (the feedback plus gain resistors) in parallel with a 13 pF capacitor (due to the output), and the input to output isolation will be better than 50 dB at 10 MHz. Leaving the disable pin disconnected (floating) will leave the part in the enabled state. In cases where the amplifier is driving a high impedance load, the input to output isolation will decrease significantly if the input signal is greater than about 1.2 V p–p. The isolation can be restored to the 50 dB level by adding a dummy load (say 150 Ω) at the amplifier output. This will attenuate the feedthrough signal. (This is not an issue for multiplexer applications where the outputs of multiple ADEL2020s are tied together as long as at least one channel is in the ON state.) The input impedance of the disable pin is about 35 k Ω in parallel with a few pF. When grounded, about 50 µA flows out of the disable pin for ±5 V supplies. Break-before-make operation is guaranteed by design. If driven by standard CMOS logic, the disable time (until the output is high impedance) is about 100 ns and the enable time (to low impedance output) is about 160 ns. Since it has an internal pull- up resistor of about 35 k Ω, the ADEL2020 can be used with open drain logic as well. In that case, the enable time increases to about 1 µs. If there is a nonzero voltage present on the amplifier’s output at the time it is switched to the disabled state, some additional decay time will be required for the output voltage to relax to zero. The total time for the output to go to zero will normally be about 250 ns; it is somewhat dependent on the load impedance.

REV. A ADEL2020 –9– OUTLINE DIMENSIONS 8-Lead Plastic Dual-in-Line Package [PDIP] (N-8) Dimensions shown in inches and (millimeters) SEATING PLANE 0.015 (0.38) MIN 0.180 (4.57) MAX 0.150 (3.81) 0.130 (3.30) 0.110 (2.79) 0.060 (1.52) 0.050 (1.27) 0.045 (1.14) 1 4 5 0.295 (7.49) 0.285 (7.24) 0.275 (6.98) 0.100 (2.54) BSC 0.375 (9.53) 0.365 (9.27) 0.355 (9.02) 0.150 (3.81) 0.135 (3.43) 0.120 (3.05) 0.015 (0.38) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN COMPLIANT TO JEDEC STANDARDS MO-095AA 20-Lead Standared Small Outline Pacakge [SOIC] Wide Body (R-20) Dimensions shown in millimeters and (inches) CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN COMPLIANT TO JEDEC STANDARDS MS-013AC 0.75 (0.0295) 0.25 (0.0098) 20 11 101 0.32 (0.0126) 0.23 (0.0091) 8/H11543 0/H11543 /H11547 45/H11543 1.27 (0.0500) 0.40 (0.0157) SEATING PLANE 0.30 (0.0118) 0.10 (0.0039) 0.51 (0.0201) 0.33 (0.0130) 2.65 (0.1043) 2.35 (0.0925) 1.27 (0.0500) BSC 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 13.00 (0.5118) 12.60 (0.4961) COPLANARITY 0.10

REV. A–10– ADEL2020

Revision History

1/03—Data Sheet changed from REV. 0 to REV. A.

–11–

C03445–0–1/03(A) PRINTED IN U.S.A. –12–