ADE9178GTL+

Analog Devices

Energy Management DSP with PEN Fault Detection Rev A 3/25

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Energy Management DSP with PEN Fault Detection 19-101907; Rev A; 3/25 DOCUMENT FEEDBACK TECHNICAL SUPPORT Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. T rademarks and registered trademarks are the property of their respective owners.All Analog Devices products contained herein are subject to release and availability.

FEATURES

► Metrology chip for use with any combination of the following AFEs ► ADE9113 (3-channel, isolated, Σ-Δ ADC) ► ADE9112 (2-channel, isolated, Σ-Δ ADC) ► ADE9103 (3-channel, non-isolated, Σ-Δ ADC) ► Can support up to four ADE9113/ADE9112/ADE9103 daisy- chained ADCs through 4-wire SPI ► Supports up to a total of 12 ADC channels of data ► 4-wire SPI for Host MCU communications up to 25 MHz ► Total active energy calculation ► Class C accuracy (0.5%), supports the following ► MID 2014/32/EU Annex V ► EN 50470-1:2006 ► EN 50470-3:2006 ► EN 50470-3:2022 ► IEC 62052-11:2020 ► IEC 62053-21:2020 ► OIML G 22:2022 ► NIST Handbook 44:2023 ► Total apparent energy calculation using filtered RMS ► Energy accumulation, import and export for reverse power/vehi- cle to grid (V2G) applications ► Basic power quality features ► Short-duration undervoltage or overvoltage (dip/swell) detec- tion ► Short-duration undercurrent or overcurrent (dip/swell) detec- tion ► Line frequency calculation with 10 mHz accuracy ► Angles between phase voltages and currents ► Power-factor calculation ► Configurable phase, gain and offset calibration registers for all ADC channels ► Two configurable calibration frequency (CF) pulse outputs ► Configurable: no load detection ► Phase-sequence detection ► RMS on full cycle, half cycle and filtered RMS on all ADC channels ► Supported frequency range: 45 Hz to 65 Hz ► Four user-programmable interrupt outputs (IRQs) ► PEN open fault detection (BS 7671:2018 Amendment 1:2020) ► Waveform streaming through UART transmit pin ► Datapath multiplexing to allow any ADC data to be used for any data processing path ► Temperature range: −40°C to +105°C ► Available in 5 mm × 5 mm, 40-lead LFCSP package

APPLICATIONS

► Electric vehicle supply equipment ► Shunt-based polyphase meters ► Solar inverters ► Energy and power monitoring GENERAL DESCRIPTION The ADE9178 is a metrology digital signal processor (DSP) for use with a combination of ADE9113/ADE9112/ADE9103 sigma delta an- alog-to-digital converters (ADCs). The ADE9178 is a high accuracy, 3-phase electrical energy measurement IC primarily for the electric vehicle supply equipment (EVSE) market with serial peripheral interface (SPI) and two flexible pulse outputs. The ADE9178 can in- terface with up to four daisy-chained ADE9113/ADE9112/ADE9103 devices through SPI protocol. The ADE9178 incorporates all the signal processing required to perform total active energy, apparent energy measurements, and root mean square (RMS) calculations. A fixed function DSP executes this signal processing. The ADE9178 is well-suited for the EVSE market due to its broad feature set such as protective earth and neutral (PEN) open fault detection without the need for any additional hardware, overcurrent, and overvoltage detection using RMS of half cycle/one cycle and vehicle to grid/home (V2X) capabilities. The ADE9178 measures active and apparent energy in various 3-phase configurations, such as wye or delta services, with both three and four wires, single phase, and split phase while supporting both 50 Hz and 60 Hz line frequencies. The ADE9178 provides gain, offset, and phase calibration features for each ADC channel. The CF1 and CF2 logic outputs provide power information that is proportional to the measured accumulated energy. The ADE9178 incorporates some basic power quality measurement features, such as short-duration undervoltage/undercurrent or over- voltage/overcurrent detection, line voltage period measurements, and angles between phase voltages and currents. A Host microcon- troller unit (MCU) can be used to communicate with the ADE9178 through 4-wire SPI. Waveform streaming can be accessed by the Host MCU through the WAVEFORM_TX pin of the ADE9178. The ADE9178 also has four user-programmable interrupt pins, IRQ0, IRQ1, IRQ2, and IRQ3, to indicate that an enabled interrupt event has occurred. The ADE9178 is available in a 40-lead, LFCSP package. For more details on how to setup the ADE9178 in an EVSE application, refer to the application note Using ADE9178 for EV Charger Metrology Solution.

analog.com Rev. A | 2 of 122 System Specifications for ADE9178, Energy Linearity Over Supply and Energy Error Over Frequency and Power RMS Linearity Over Temperature and RMS CF vs. Energy Register Correlation and CF Full-Scale Codes And Conversion Equations.. 31

REVISION HISTORY

3/2025—Rev. 0 to Rev. A 7/2024—Revision 0: Initial release

Figure 1. Typical Applications Circuit

Figure 2. Functional Block Diagram

Table 1. System Specifications

65 Hz, phase angle = 0° to 360°, HPF on

Table 1. System Specifications (Continued)

Table 2. ADE9178 Specifications

Table 3. SPI Timing Parameters Figure 3. SPI Timing Diagram

TA = 25°C, unless otherwise noted. Table 4. Absolute Maximum Ratings ing conditions for extended periods may affect product reliability. junction-to-case thermal resistance. Table 5. Thermal Resistance damage may occur on devices subjected to high energy ESD. performance degradation or loss of functionality.

Figure 4. Pin Configuration Table 6. Pin Function Descriptions 5 PULL_UP N/A1 N/A1 10 kΩ Pull-Up to VDD. 6 ADC_MISO Input Active High Data Input for the ADC SPI Port to the supported Analog Front End (AFEs). 7 ADC_MOSI Output Active High Data Output for the ADC SPI Port from the supported AFEs. 8 ADC_SCLK Output Active High Serial-Clock Output for the ADC SPI Port. 9 ADC_CS Output Active Low Chip Select for ADC SPI Port. Output Active Low User-Programmable Interrupt Request Output. 18 WAVEFORM_TXOutput Active High Waveform Streaming through a UART transmit pin. is used for operational and calibration purposes. 26 HOST_MISO Output Active High Data Output for the SPI Port to the Host MCU. 27 HOST_MOSI Input Active High Data Input for the SPI Port from the Host MCU. 28 HOST_SCLK Input Active High Serial-Clock Input from the Host MCU. 29 HOST_CS Input Active Low Chip-Select Input for Host SPI Port. 31 HOST_ERR Output Active Low Flag to let the Host MCU know that there is an error during the Command processing. 32 DVDDOUT2 N/A1 N/A1 Bypass with 4.7 nF to GND. N/A1 N/A1 1 kΩ Pull-Down to GND. (resetting all logic) and begins execution. 22 pF and 0.1 µF to GND. 36 GND N/A1 N/A1 Ground Reference for the Input Circuitry. to 150 mΩ equivalent series resistance (ESR) to GND.

Table 6. Pin Function Descriptions (Continued) 40 DVDDOUT1 N/A1 N/A1 Bypass with 100 nF to GND and 1 μF with 10 mΩ to 150 mΩ ESR to GND. EP EPAD N/A1 N/A1 Exposed pad. The exposed pad must be connected to the ground.

Figure 11. Total Active Energy Error as a Percentage of Full-Scale Current

Figure 28. CF2 Jitter Over Current Full Scale, CF2_THR = d22351312,

Figure 29. ADE9178 + ADE91xx Test Circuit

analog.com Rev. A | 21 of 122 For the common terminology, refer to the Analog Wiki.

Table 7. ADC Channel to ADE9178 SLOT Mapping for Four and Three ADC Configurations ADE9178 MISO connected to the last ADE91xx in the chain). Table 8. Default ADC_REDIRECTx Values Figure 32. ADC to ADE9178 Channel Mapping for ~1 ms during synchronization if it is required.

Table 11. Status Code Description 0x8 Command failed to execute.ADC_CONTROL = 0x2 Initialize ADC ADC_INIT_ERROR Retry the command. Read/Write ADE9178 Register N/A1 Check CRC header values. issued. Wait for it to complete. issued. Wait for it to complete.

Table 11. Status Code Description (Continued) ADE9178 if the error persists.

initial value 0xFFFF is used for this purpose. Register Details: ADE9178 section. 0x0 to the CONFIG_LOCK register. ranges supported by the ADE9178, which are shown in Table 12. Table 12. Burst Read Address Ranges register but the value is undefined. registers from 0x284 to 0x287. register is cleared and there is no way to retrieve the data. whether channels are current, voltage, or auxiliary, respectively. XFS_CODES, where X can vary based on type of the register.

Table 13. Terminology and Full-Scale Codes (IP) inputs of ±31.25 mV peak to peak. details, see the example system configuration. Depends on shunt resistor size. Depends on system parameters. is applied to the ADC input. frequency of the CF pulse output. use the following equations shown in Table 14. Table 14. Conversion Equations are phase voltage or currents.

analog.com Rev. A | 33 of 122 Worked Examples This section gives example calculations for the above conversion equations with the following system parameters. System Parameters: ►VNOMINAL = 220 VRMS ►INOMINAL = 10 ARMS ►Line Frequency = 50 Hz ►Shunt Resistor = 500 μΩ ►Voltage Divider ►R1 = 990 kΩ ►R2 = 1 kΩ ►Divider Ratio = 0.001 T ℎ eoretical Full ‐ Scale Voltage = V F S _ T = V ADC _ F S Di v i der _ Rati o ÷ 2 = 1 0 . 001 ÷ 2 = 707 V RMS (6) Maxi m um I np u t Vo l t age Ps eud o Di f f eren t ia l = V M A X = V AD C _ F S _ PSE U DO Di v i d er _ Rat i o ÷ 2 = 0 . 5 0 . 001 ÷ 2 = 353.5 V RMS (7) Note that the ADE91xx has two different full-scale voltages, ±1 V peak to peak for fully differential and ±0.5 V peak to peak for pseudo differential (for more details, refer to the Signal Voltage Range Between the IP and IM, V1P and V1M, and V2P and V2M Pins section in the ADE91xx data sheet). The full-scale codes defined in the Table 13 table are related to the fully differential setup of the ADC (±1 V peak to peak), therefore, any calculation that includes full-scale codes must use VFS_T calculated above. Note that do not use the pseudo differential full-scale voltage as this leads to incorrect conversions. As in most applications, the voltage is measured using a resistor-di- vider ladder, the ADC is being used with a pseudo differential input rather than a fully differential input. This means that the max voltage allowed into the voltage ADC input is ±0.5 V peak to peak, therefore the max voltage that can be applied to the input of the potential divider is VFS_T/2 = 353.5 VRMS. Any voltage above this throws the clipping and measurement errors. Full ‐ Scale Current = I FS = I A DC _ F S S ℎ un t _ Res i s t an c e ÷ 2 = 0 . 03125 500 × 10 − 6 ÷ 2 = 44.188 A R MS (8) RMS Output Calculation: If AIRMS = 24285092 decimal, then: A I RMS C ON VE RTE D = I F S RMS F S _ C ODE S × A I RMS = 44 . 188 107310840 × 24285092 = 10.00 A R MS (9) If AVRMS = 33394314 decimal, then: A VRM S C ONV ER TED = V F S _ T RMS FS _ C OD ES × AVR MS = 707 107310840 × 33394314 = 220.013 V RMS (10) Power Calculation: If AWATT = 6044931 decimal, then: AW ATT C ONV ERT ED = I F S × V FS _ T PO W F S _ C ODE S × A W ATT = 44 . 188 × 707 85829040 × 6044931 = 2200.295 Watts (11) If AVA = 6038115 decimal, then: AV A C ONV ERT ED = I F S × V FS _ T PO W F S _ C ODE S × A V A = 44 . 188 × 707 85829040 × 6038115 = 2197.814 VA (12) Energy Calculation: If AWATTHR_POS_HI = 2950618 decimal and AWATTHR_POS_LO = 7367 decimal, then: E n erg y = I FS × V F S _ T POW FS _ C OD ES × X HI ≪ 13 + X L O 4000 = 44 . 188 × 707 85829040 × 2950618 ≪ 13 + 7367 4000 = 2199.54 Watt Seconds (13) If AVAHR_HI = 2950549 decimal and AVAHR_LO = 7354 decimal, then: E ner g y = I F S × V FS _ T PO W F S _ C ODE S × X HI ≪ 13 + X L O 4000 = 44 . 188 × 707 85829040 × 2950549 ≪ 13 + 7354 4000 = 2199.49 Watt Seconds (14) Period Calculation: If APERIOD = 5242710 decimal, then: A PER IO D C ONV ERT ED = A PER IO D + 1 4000 × 2 16 = 5242710 + 1 4000 × 2 16 = 19.9994 ms = 50.0015 Hz (15) Angle Calculation: If ANGL_AV_BV = 6826 decimal and APERIOD = 5242738 deci- mal, then: An gl e = 2 π A NG L XY × 256 xPER I OD + 1 − 2π = 2 π 6826 × 256 5242738 + 1 − 2π = − 4 .189 radians = − 240 .012 degrees (16) Therefore, phase B voltage is lagging phase A voltage by 240.012°.

analog.com Rev. A | 34 of 122 Power-Factor (PF) Calculation: If APF = 67114928 decimal, then: A PF CO NV ERT ED = A PF × 2 − 27 = 67114928 × 2 − 27 = 0 . 50005 (17) To determine if the PF is leading or lagging, find the angle between voltage and current (ANGL_xV_xI) by using the Angle Calculation shown in this section. If the angle lies between 0° and −180°, then the PF is lagging. If the angle lies between −180° and −360°, then the PF is leading. For more details, refer to the Conversion equation tab in the Calibration and Conversion excel for calculators, available on the product webpage.

Table 15. Calibration Registers Clamp Values configured with the HPF_CRN bits in the CONFIG0 register. Table 16. HPF Corner Gain with 50 Hz Input Signal 1 It is recommended to leave HPF_CRN as default. If HPF_CRN is changed, then a recalibration is required. correction (ϕ)° angle for current with respect to its voltage. before HPF or after phase compensation. ZX_SRC_SEL, and HPFDIS are common for all channels.

and harmonic components of the voltages and currents. datapath is shown in Figure 50. Figure 50. Total Active Power Datapath in the CONFIG0 register to obtain instantaneous total active power. Figure 51. LPF Diagram in PWR_SETTLE register, then starts power calculations. Table 17. Total Active Power Settling Time for 50 Hz Input The ADE9178 computes total apparent power on up to 3-phases. register for the apparent power signal processing. VNOM RMS is multiplied with xIRMS to calculate xVA.

707 V, VNOM is calculated as:

tive and negative energy outputs, respectively. energy output (xVAHR_HI and xVAHR_LO) exists. absolute accumulation mode. For more details, see Figure 53. Table 19. No Load Detection Table

7 No load disabled No load disabled

to apparent energy values as well. Figure 55. No Load Behavior shown in the Full-Scale Codes And Conversion Equations section.

that are proportional to the energy accumulation. from the falling edge of the signal. Table 20. WIDTHSEL Configuration

1 CF_LTMR (in μs) 50% of period

and can be obtained from full-scale code documentation. for single-phase accumulation and more than assuming FS inputs. for 3-phase accumulation assuming FS inputs. updated when the CFx pin goes from high to low. phase), expected CF pulse output is 1.9167 Hz.

where, xRMS0 is the initial xRMS value before offset calibration. Figure 58. Common RMS Datapath expected to use signal gain xxGAIN for gain adjustments. This feature calculates RMS over every period of input signal. over 16 samples. This reduces the period jitter. in RMSHALF_CONFIG register to choose between the two modes. after the xRMSHALF registers are updated. USER_PERIOD_HALF register, which is used for measurement. In this case, the output is not synchronized with zero crossings. This mode can be used when measuring non periodic signals.

Table 22. Zero-Crossing Use in Other Functions missing then SEQERR bit is not set. more details, see Table 30). as the basis for these calculations.

70 Hz range, the line period used

N/A2 N/A2 Does not update, keeps last value. 1 The ZX output from ADE9178 has very high jitter, hence it is not intended for external use.

Figure 67. 4-Wire WYE, 4-Wire Delta Phase-Sequence Error from a Phase ISUMRMSOS register allows offset calibration of this measurement. configuring ISUM_CFG bits in CONFIG0 register. threshold value can be set in the ISUMLVL register. BS7671:2018 Amendment 1:2020 standard.

VSUMRMSONE = (PEN_CHANA + PEN_CHANB +
VABRMSONE = PEN_CHANA − PEN_CHANB
VACRMSONE = PEN_CHANA − PEN_CHANC
VBCRMSONE = PEN_CHANB − PEN_CHANC

the same as the other RMS offset registers (xxRMSOS). RMS values (VABRMSONE, VACRMSONE, and VBCRMSONE).

details, see the Dip and Swells section). of at least 3072000 is required to stream all channels together. WFS_CONFIG register, error pin is asserted.

Skip the bytes from UART till 0x0 is encountered.
Once 0x0 is received at the Nth byte, check if N + 4th byte is

The lowest byte of each 32-bit word is sent first through UART. Table 23. Transmission Format Table 24. Transmission Format with Only AV, BV, and CV are Enabled Figure 68. Waveform Streaming UART Transmission Format Table 25. Minimum Baud Rate Requirements

Table 26. Update Rates

the corresponding bit in the STATUS register. to IRQ0 or IRQ1 for these events. only if the corresponding bit is set in the ERROR_MASK register. ERROR_STATUS register to determine the cause of the interrupt. Figure 69. ADC_STATUSX to ERROR_STATUS Register Mapping

Table 27. ERROR_STATUS Register Table

Check signal integrity of
See the Quick Start section

register after ADE9178 reset. register after ADE9178 reset. ERROR0[1] Internal Error Occurred. Reset the ADE9178 and ADCs. ERROR1[2] Internal Error Occurred. Reset the ADE9178 and ADCs. ERROR2[3] Internal Error Occurred. Reset the ADE9178 and ADCs. ERROR3[4] Internal Error Occurred. Reset the ADE9178 and ADCs. ERROR4[5] Internal Error Occurred. Reset the ADE9178 and ADCs.

Check signal integrity of
Ensure that the ADC related

as per the Quick Start section. perform ADC initialization again. ERROR5[7] Internal Error Occurred. Reset the ADE9178 and ADCs.

Check signal integrity of the

Table 27. ERROR_STATUS Register Table (Continued) register after ADE9178 reset. register after ADE9178 reset. STATUS0[0:5] of ADC0 is set. refer to the Register Details section of the ADE91xx data sheet. STATUS1[1:3] of ADC0 is set. refer to the Register Details section of the ADE91xx data sheet. refer to the Register Details section of the ADE91xx data sheet. STATUS0[0:5] of ADC1 is set. refer to the Register Details section of the ADE91xx data sheet. STATUS1[1:3] of ADC1 is set. refer to the Register Details section of the ADE91xx data sheet. refer to the Register Details section of the ADE91xx data sheet. STATUS0[0:5] of ADC2 is set. refer to the Register Details section of the ADE91xx data sheet. STATUS1[1:3] of ADC2 is set. refer to the Register Details section of the ADE91xx data sheet. refer to the Register Details section of the ADE91xx data sheet. STATUS0[0:5] of ADC3 is set. refer to the Register Details section of the ADE91xx data sheet. STATUS1[1:3] of ADC3 is set. refer to the Register Details section of the ADE91xx data sheet. refer to the Register Details section of the ADE91xx data sheet. ERROR6[21] Internal Error Occurred. Reset the ADE9178 and ADCs.

ERROR7[22] Internal Error Occurred. Reset the ADE9178 and ADCs.

user-configurable value as shown in Table 28. Table 28. Reoccurrence Behavior DIP_SWELL_x_IRQ_MODE configuration bit in CONFIG0 register. as the channel is in dips/swells condition. perform a hardware reset, see the Hardware Reset section. connected together as shown in the Test Circuit section. how to configure the ADE9178, see the Quick Start section.

analog.com Rev. A | 55 of 122 CALIBRATION METHOD The system is calibrated at nominal operating voltage and current using an accurate source. The worked out example is shown only for phase A. The calculation remains same for other channels as well. All calibration steps involve providing a known signal to the relevant ADC channels and compare one of the output registers to the expected value of the register. System Parameters: ►VNOMINAL = 220 VRMS ►INOMINAL = 10 ARMS ►Line Frequency = 50 Hz ►Shunt Resistor = 500 µΩ ►Voltage Divider ►R1 = 990 kΩ ►R2 = 1 kΩ ►Divider Ratio = 0.001 Theoretical Full-Scale Voltage = V F S _ T = V AD C _ F S Di v i d er _ Rat i o ÷ 2 = 1 0 . 001 ÷ 2 = 707 V R MS (37) Note that the fully-differential VFS_T is used for this calculation. See the Worked Examples section on how to calculate VFS_T for the system. Full-Scale Current = I FS = I AD C _ F S S ℎ un t _ Res i s tan c e ÷ 2 = 0 . 03125 500 × 10 − 6 ÷ 2 = 44.188 A RMS (38) Gain Calibration This section explains how to calculate the xxGAIN register, which affects all output parameters of the ADE9178. RMS values are used to calibrate the gain. With the nominal voltage and current inputs, read the appropriate RMS register (for example, AIRMS, AVRMS, or AUXRMS). It is recommended to read the RMS values once per zero crossings for 1 sec and average them for better accuracy. The expected RMS register value for given voltage and current can be calculated as follows: xRMS E XPEC TE D = RMS F S _ CO DE S × X NO MI N A L X F S (39) where, XNOMINAL is the nominal signal applied at the ADC input and XFS is either VFS_T, IFS, or AUXFS. The xxGAIN register can be calculated from expected and ob- served RMS register as follows: xxG A IN = xRMS E XPEC TE D xRMS ME ASU R ED − 1 × 2 27 (40) Example With the given example system parameters, the following equation shows the calculations for AV channel gain: AV RMS E XPEC TE D = 107310840 × 220 707 = 33392341 decimal (41) If AVRMSMEASURED = 33512088 decimal, then: AV G AI N = 33392341 33512088 − 1 × 2 27 = − 479595 dec i ma l = 0 × FF F 8 AE 96 (42) DC Offset Calibration All xOS registers must be 0 for AC metrology applications. RMS Offset Calibration To calibrate RMS offset register, apply a small signal typically at 2000:1 or less dynamic range to the channel the user is trying to calibrate. It is recommended to keep the other channel as nominal. In this example, to calibrate the current offset, the calibration current is set to 20 mA and the voltage is kept at nominal. Read the RMS values once per zero crossings for 1 sec and average them for better accuracy. The expected RMS register value for given input can be calculated as follows: xRMS E XPE CT ED = RMS F S _ C OD ES × X R ED U CE D X F S (43) where, XREDUCED is the reduced calibration signal applied at the ADC input and XFS is either VFS_T, IFS, or AUXFS. The xxRMSOS register can be calculated from expected and ob- served RMS register as follows: x xRMSO S = x RMS E XPE C TED 2 − x RMS ME ASU RE D 2 2 15 (44) Example With the reduced input current to 20 mV, the following equation shows the calculations for AI channel offset: A I RMS E XPE C TED = 107310840 × 0 . 02 44 . 188 = 48570 decimal (45) If AIRMSMEASURED = 48733 decimal, then: AI RMS OS = 48570 2 − 48733 2 2 15 = − 484 dec i m al = 0 × F FF F F E 1 D (46)

analog.com Rev. A | 56 of 122 Power Gain Calibration xPGAIN is the gain calibration register for phase x. The active and apparent powers in each phase have a common gain register. To configure the ADE9178, do the following steps: 1. Apply nominal voltage and current at power factor = 1. 2. Set EP_CFG = 0x15 and EGY_TIME = 999d (1 sec accumula- tion). 3. Read the xWATTHR_SIGNED_HI register (throw away first sample). The expected xWATTHR_SIGNED_HI register value for nominal inputs can be calculated as follows: xW A TTHR _ SI G NE D _ HI E XPE CT ED = I FS P × V F S _ TP × POW F S _ CO DE S × Ac c u mu l at i on _ Ti me × 4000 × 2 − 13 (47) where, IFSP is the nominal current as a fraction of full scale and VFS_TP is the nominal voltage as a fraction of full scale. The xPGAIN register value can be obtained as follows: xPG A I N = xW AT THR _ SI G NE D _ HI E XPE C TED xW AT THR _ SI G NE D _ HI ME A SU RE D − 1 × 2 27 (48) Example With the given example system parameters, the following equations show the calculations for APGAIN: I F SP = 10 44 . 188 = 0 . 22631 (49) V F S _ TP = 220 707 = 0 . 31117 (50) AW AT THR _ SI G NE D _ HI E XPE CTE D = 0 . 22631 × 0 . 31117 × 85829040 × 1 × 4000 × 2 − 13 = 2951248 decimal (51) If AWATTHR_SIGNED_HIMEASURED = 2846714 decimal, then: APG AI N = 2951248 2846714 − 1 × 2 27 = 4928600 dec i m al = 0 × 4 B 313 D (52) Power Offset Calibration Like the RMS offset calibration, the power offset calibration is performed with a small current at 5000:1 or less dynamic range. In this example, the offset calibration current is 20 mA and the voltage is 220 V. To configure the ADE9178, do the following steps: 1. Apply nominal voltage and offset calibration current at power factor = 1. 2. Set EP_CFG = 0x15 and EGY_TIME = 9999d (10 sec accumu- lation). 3. Read the xWATTHR_SIGNED_HI register (throw away first sample). The expected xWATTHR_SIGNED_HI register value for nominal inputs can be calculated as follows: x W ATTHR _ SI G N ED _ HI E XPEC TE D = I F SP × V F S _ TP × POW F S _ C ODE S × Ac c u mu l at i on _ Ti me × 4000 × 2 − 13 (53) where, IFSP is the nominal current as a fraction of full scale and VFS_TP is the nominal voltage as a fraction of full scale. The xWATTOS register value can be obtained as follows: xWATTOS xW ATT HR _ S I G NE D _ H I E XPE CT ED − xW A TTHR _ SI G NE D _ HI ME ASU RE D Ac c u mu l ati o n _ T im e × 4000 × 2 − 13 Example With the given example system parameters, the following equations show the calculations for APGAIN: I F SP = 0 . 02 44 . 188 = 0 . 00045 (54) V F S _ TP = 220 707 = 0 . 31117 (55) A W ATTHR _ S IG N ED _ HI E XPEC TE D = 0 . 00045 × 0 . 31117 × 85829040 × 10 × 4000 × 2 − 13 = 59025 decimal (56) If AWATTHR_SIGNED_HIMEASURED = 58134 decimal, then: AW A TTOS = 59025 − 58134 10 × 4000 × 2 − 13 = 182 decimal = 0 × B 6 (57) Phase Calibration It is recommended to keep the voltage channel xVPHCAL as default value (0). To calculate xIPHCAL, apply a nominal current and voltage at lagging power factor of 0.5, calculate phase error from power factor xPF measured as follows: ϕ = π 3 − cos − 1 xP F ME AS U RED 2 27 × − 1 (58) The xIPHCAL register can be calculated as follows: xI PHC A L = sin ϕ − ω + sin ω sin 2 ω − ϕ × 2 27 , w ℎ ere , ω = 2 π × f L IN E × 1 4000 (59)

analog.com Rev. A | 57 of 122 Example If APFMEASURED = 67144872 decimal, then: ϕ = π 3 − cos − 1 67144872 2 27 × − 1 = − 0 . 00031 (60) For 50 Hz signal: ω = 2π × 50 × 1 4000 = 0 . 07854 (61) AI PHC A L = sin − 0 . 00031 − 0 . 07854 + sin 0 . 07854 sin 2 × 0 . 07854 − − 0 . 00031 × 2 27 = − 264472 d ec i mal = 0 × F F F BF 6 E 8 (62) QUICK START This section describes how to setup the ADE9178 and ADE91xx chipset for a 3-phase and 4-wire measurement. To setup, do the following steps: 1. Configure the Host MCU to monitor to IRQ0, IRQ1, HOST_RDY, and HOST_ERR pins of the ADE9178. 2. Issue a hardware reset to ADE9178 and ADCs by toggling corresponding reset pins. For more details, see the Hardware Reset section. 3. The ADE9178 checks the integrity during boot time and both HOST_RDY and HOST_ERR pins go low if the integrity error is detected. If this happens, then toggle the hardware reset pin of the ADE9178. If the error persists, contact support team. 4. Wait for IRQ0 interrupt from the ADE9178 and: a. Read the STATUS0 register and check that the RSTDONE bit is set. Note that once the hardware reset is initiated, it takes 16 ms before IRQ0 is asserted. Otherwise, there is an internal error and it is recommended to reset the ADE9178. b. Clear RSTDONE interrupt by writing 1 to the RSTDONE bit in the STATUS0 register. 5. By default all error interrupts in the ERROR_STATUS register are enabled and IRQ1 is triggered if there is an error. The de- tails of the error can be obtained by reading ERROR_STATUS register. For more details, see the Interrupts and Status Outputs section. 6. If energy is monitored using the CF outputs, configure the following registers (skip this step if the CF outputs are not used): a. Configure the PWRSEL bits in the CFx_CONFIG register to select the energy type to monitor. b. Configure the PHASESEL bits in the CFx_CONFIG register to select the phases to include in the CF calculation. c. Configure the ACCMODE bits in the CFx_CONFIG register to select the accumulation mode. d. Set the CFx_THR register based on the required impulses per kilowatt-hour. For CFx_THR formula, see the CF Pulse Generation section. e. Configure the WIDTHSEL bit in the CFx_CONFIG register to set the low-pulse width. For more details, see Table 20. f. Enable the CF by clearing the CFDIS bit in the CFx_CON- FIG register to 0. 7. If energy is monitored using energy registers, configure the following registers: a. Configure the EGY_TMR_MODE bit in the EP_CFG register to select time-based accumulation mode (EGY_TMR_MODE = 0). Set the required samples in the EGY_TIME register (N − 1 ms). 1. It is recommended to use time-based accumulation mode (for more details, see Table 30). b. Configure the EGY_LD_ACCUM bit in the EP_CFG register to add the internal energy register to user energy register on EGYRDY (EGY_LD_ACCUM = 0), or to overwrite the user energy register with the internal energy register value (EGY_LD_ACCUM = 1). c. Configure the RD_RST_EN bit in the EP_CFG register to enable reset of user energy registers on read (RD_RST_EN = 1), or to disable reset of user energy registers on read (RD_RST_EN = 0). d. Configure the NOLOAD_TMR bits in the EP_CFG register and set the ACT_NL_LVL and APP_NL_LVL level registers to detect no load and prevent energy accumulation of noise. For more details, see the No Load Detection section. 8. The ADE9178 can provide interrupts for a variety of events on the IRQ0, IRQ1, IRQ2, and IRQ3 pins. The MASK0, MASK1, MASK2, MASK3, or ERROR_MASK and STATUS0, STATUS1, STATUS2, STATUS3, or ERROR_STATUS registers manage the respective interrupt pins. For more details, see the Inter- rupts and Status Outputs section. 9. Write calibration coefficient registers to the ADE9178. For more details, see the Calibration Method section. 10.Configure ADC related parameters and start the data process- ing as follows: a. Configure number of ADCs connected by writing to the NUM_ADC bits in the ADC_CONFIG register. b. Review ADC_REDIRECT1 and ADC_REDIRECT2 default values and update if the channel mapping required is different to default. Note that the ADC_REDIRECT1 and ADC_REDIRECT2 must be updated if the number of ADCs present is different than the default 4. For more details, see Table 8. c. Initialize the ADCs by setting ADC_INIT bit in the ADC_CONTROL register to 1 (Auto Clears). d. Separately, enable data capture and processing by setting the ADC_RUN bit in the ADC_CONTROL register to 1 (Auto Clears is setting ADC_RUN = 1 fails).

analog.com Rev. A | 58 of 122 11.See the following sections to set up other metrology features: a. Total Active Power b. Total Apparent Power c. Line Period Calculation: 1. It is recommended to configure CONFIG0:PERI- OD_AVG_CFG[4:3] to 0x2 to average the period over 16 samples. This reduces the period jitter. d. RMS of One Cycle: 1. It is recommended to configure CON- FIG0:RMSONE_SRC_SEL[11] to 0x1 to use data from before the HPF for the fastest response time. 2. It is recommended to configure CONFIG0:PERI- OD_AVG_CFG[4:3] to 0x2 to average the period over 16 samples. This reduces the period jitter. e. RMS of Half Cycle: 1. It is recommended to configure CON- FIG0:RMSHALF_SRC_SEL[11] to 0x1 to use data from before the HPF for the fastest response time. 2. It is recommended to configure CONFIG0:PERI- OD_AVG_CFG[4:3] to 0x2 to average the period over 16 samples. This reduces the period jitter. f. Peak Detection g. Dip and Swells h. Phase-Sequence Error Detection i. Zero-Crossing Timeout j. Neutral Current Mismatch k. PEN Fault Detection l. Waveform Streaming 12.Enable energy accumulation by setting the EGY_PWR_EN bit in the EP_CFG register to 1. 13.It is recommended to enable CRC check of the configuration registers. For more details, see the CRC of Configuration Reg- isters section. 14.To prevent any changes to the ADE9178 configuration, enable write protection by writing 1 to the CONFIG_LOCK register. For more details, see the Configuration Lock section. 15.After the RUN bit of ADC_CONTROL (set in Step 10 Part d) is set, the output registers update at a frequency shown in Table 26. For more details, see the Output Register Update Rates section. For more detailed information on how to set up the ADE9178 in an EVSE application, refer to the application note, Using ADE9178 for EV Charger Metrology Solution. LAYOUT GUIDELINES For layout guidelines, refer to the application note Using ADE9178 for EV Charger Metrology Solution.

analog.com Rev. A | 59 of 122 This anomaly list describes the known issues with the ADE9178 silicon identified by the version2 register (Address 0x40B) being equal to 0x09FD5D0D. Table 29. ADE9178 Functionality Issues Table 30. err001: No Load with Line-Cycle Accumulation

Description

Background When ADE9178 is in a no load condition (for more details, see No Load Detection section), no energy should be accumulating into the output energy registers. Issue When ADE9178 is in a no load condition and ADE9178 is configured for line-cycle accumulation mode (EP_CFG: EGY_TMR_MODE[1] =0x1), some residual energy is accumulated into the output energy registers, which could cause errors over time. Workaround Use time based accumulation (EP_CFG: EGY_TMR_MODE[1] =0x0). Related Issues None.

Table 31 shows if the number is signed/unsigned and specifies the valid range for input registers. Table 31. Register Number Format

Table 31. Register Number Format (Continued)

Table 32. Access Mode Description R/W Register has Read and Write access. R Register has Read access only. R/W1C Register has Read access and Write 1 to clear. Table 33. ADE9178 Register Summary

Table 33. ADE9178 Register Summary (Continued)

Table 34 shows the registers of the ADE9178 that have bitfields. Additional registers listed in Table 33 table do not have bit fields. Table 34. ADE9178 Register Details

28 ICONSEL Phase B Current Calculation

001 3-Wire Delta. BV' = AV − CV.

000 Auxiliary 0 Channel Used in

001 Auxiliary 1 Channel Used in

010 Auxiliary 2 Channel Used in

011 Auxiliary 3 Channel Used in

100 Auxiliary 4 Channel Used in

101 Auxiliary 5 Channel Used in

00 ISUM = AI_PCF +

01 ISUM = AI_PCF + BI_PCF

10 ISUM = AI_PCF + BI_PCF

19 DIP_SWELL_ONE_IRQ_MODE Dip and Swell One-Cycle

Table 34. ADE9178 Register Details (Continued)

18 DIP_SWELL_HALF_IRQ_MODE Dip and Swell Half-Cycle

[17:16] PWR_SETTLE Power Settling Time Selection. energy and CF accumulations.

15 VNOMC_EN Nominal Phase Voltage RMS

14 VNOMB_EN Nominal Phase Voltage RMS

13 VNOMA_EN Nominal Phase Voltage RMS

12 ZX_SRC_SEL Zero-Crossing Source Select.

11 RMSONE_SRC_SEL RMSONE Sample Source

0 Samples After HPF Used for

1 Samples Before HPF Used for

10 RMSHALF_SRC_SEL Fast RMSHALF Sample

total active power datapath. disable HPF for all channels.

1 SELFREQ Line-Cycle Frequency

monitored for peak detection. Selection for Current Channels. Selection for Voltage Channels. monitored for peak detection.

00 Line Period Measurement from

01 Line Period Measurement from

10 Line Period Measurement from

11 Line Period Measurement from

0000 AV Data Processing Path. 0001 AI Data Processing Path. 0010 BV Data Processing Path. 0011 BI Data Processing Path. 0100 CV Data Processing Path. 0101 CI Data Processing Path. 0110 AUX0 Data Processing Path. 0111 AUX1 Data Processing Path. 1000 AUX2 Data Processing Path. 1001 AUX3 Data Processing Path. 1010 AUX4 Data Processing Path. 1011 AUX5 Data Processing Path. 0000 AV Data Processing Path. 0001 AI Data Processing Path. 0010 BV Data Processing Path. 0011 BI Data Processing Path. 0100 CV Data Processing Path. 0101 CI Data Processing Path. 0110 AUX0 Data Processing Path. 0111 AUX1 Data Processing Path. 1000 AUX2 Data Processing Path. 1001 AUX3 Data Processing Path. 1010 AUX4 Data Processing Path. 1011 AUX5 Data Processing Path. 0000 AV Data Processing Path. 0001 AI Data Processing Path. 0010 BV Data Processing Path. 0011 BI Data Processing Path. 0100 CV Data Processing Path. 0101 CI Data Processing Path. 0110 AUX0 Data Processing Path.

0111 AUX1 Data Processing Path. 1000 AUX2 Data Processing Path. 1001 AUX3 Data Processing Path. 1010 AUX4 Data Processing Path. 1011 AUX5 Data Processing Path. 10 ACC_CLEAR Clear CF1 Accumulator. 00 Signed Accumulation Mode. 10 Positive Accumulation Mode. 11 Negative Accumulation Mode. the CF1 outputs calculations. digital to frequency converter. 10 ACC_CLEAR Clear CF2 Accumulator.

00 Signed Accumulation Mode. 10 Positive Accumulation Mode. 11 Negative Accumulation Mode. the CF2 outputs calculations. digital to frequency converter.