ADE9000

Analog Devices

High Performance, Multiphase Energy Power Quality Monitoring IC Rev. A

Manufacturer: Analog Devices

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ADE9000 (Rev.B)

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Manufacturer or author: Analog Devices, Inc.
PDF pages: 79

Technical content

High Performance, Multiphase Energy, and Power Quality Monitoring IC Rev. B DOCUMENT FEEDBACK TECHNICAL SUPPORT Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. All Analog Devices products contained herein are subject to release and availability.

FEATURES

►7 high performance ADCs ►101 dB SNR ►Wide input voltage range: ±1 V, 707 mV rms FS at gain = 1 ►Differential inputs ►±25 ppm/°C maximum channel drift (including ADC, internal VREF, PGA drift) enabling 10000:1 dynamic input range Class 0.2 metrology with standard external components ►Power quality measurements ►Enables implementation of IEC 61000-4-301 ►VRMS ½, IRMS ½ rms voltage refreshed each half cycle ►10 cycle rms/12 cycle rms ►Dip and swell monitors ►Line frequency—one per phase ►Zero crossing, zero-crossing timeout ►Phase angle measurements ►Supports CTs and Rogowski coil (di/dt) sensors ►Multiple range phase/gain compensation for CTs ►Digital integrator for Rogowski coils ►Flexible waveform buffer ►Able to resample waveform to ensure 128 points per line cycle for ease of external harmonic analysis ►Events, such as dip and swell, can trigger waveform storage ►Simplifies data collection for IEC 61000-4-7 harmonic analysis ►Advanced metrology feature set ►Total and fundamental active power, volt amperes reactive (VAR), volt amperes (VA), watthour, VAR hour, and VA hour ►Total and fundamental IRMS, VRMS ►Total harmonic distortion ►Power factor ►Supports active energy standards: IEC 62053-21 and IEC 62053-22; EN50470-3; OIML R46; and ANSI C12.20 ►Supports reactive energy standards: IEC 62053-23, IEC 62053-24 ►High speed communication port: 20 MHz serial port interface (SPI) ►Integrated temperature sensor with 12-bit successive approxima- tion register (SAR) ADC ►±3°C accuracy from −40°C to +85°C

APPLICATIONS

►Energy and power monitoring ►Power quality monitoring ►Protective devices ►Machine health ►Smart power distribution units ►Polyphase energy meters 1 For IEC 61000-4-30 Class S implementation, refer to the ADE9430 IC data sheet.

analog.com Rev. B | 2 of 79 Energy Linearity over Supply and Energy Error over Frequency and Power RMS Linearity over Temperature and RMS Energy and RMS Linearity with Integrator On..23 Energy and RMS Error over Frequency with Additional Communication Verification

REVISION HISTORY

6/2025—Rev. A to Rev. B 6/2017—Rev. 0 to Rev. A

analog.com Rev. B | 3 of 79 1/2017—Revision 0: Initial Version

analog.com Rev. B | 4 of 79 The ADE90002 is a highly accurate, fully integrated, multiphase en- ergy and power quality monitoring device. Superior analog perform- ance and a digital signal processing (DSP) core enable accurate energy monitoring over a wide dynamic range. An integrated high end reference ensures low drift over temperature with a combined drift of less than ±25 ppm/°C maximum for the entire channel including a programmable gain amplifier (PGA) and an analog-to- digital converter (ADC). The ADE9000 offers complete power monitoring capability by pro- viding total as well as fundamental measurements on rms, active, reactive, and apparent powers and energies. Advanced features such as dip and swell monitoring, frequency, phase angle, voltage total harmonic distortion (VTHD), current total harmonic distortion (ITHD), and power factor measurements enable implementation of power quality measurements. The ½ cycle rms and 10 cycle rms/12 cycle rms, calculated according to IEC 61000-4-30, provide instantaneous rms measurements for real-time monitoring. The ADE9000 offers an integrated flexible waveform buffer that stores samples at a fixed data rate of 32 kSPS or 8 kSPS, or a sampling rate that varies based on line frequency to ensure 128 points per line cycle. Resampling simplifies fast Fourier trans- form (FFT) calculation of at least 50 harmonics in an external processor. The ADE9000 simplifies the implementation of energy and power quality monitoring systems by providing tight integration of acquisi- tion and calculation engines. The integrated ADCs and DSP engine calculate various parameters and provide data through user acces- sible registers or indicate events through interrupt pins. With seven dedicated ADC channels, the ADE9000 can be used on a 3-phase system or up to three single-phase systems. It supports current transformers (CTs) or Rogowski coils for current measurements. A digital integrator eliminates a discrete integrator required for Rogowski coils. The ADE9000 absorbs most complexity in calculations for a pow- er monitoring system. With a simple host microcontroller, the ADE9000 enables the design of standalone monitoring or protection systems, or low cost nodes uploading data into the cloud. Note that throughout this data sheet, multifunction pins, such as CF4/EVENT/DREADY, are referred to either by the entire pin name or by a single function of the pin, for example, EVENT, when only that function is relevant. 2 Protected by U.S. Patents 8,350,558; 8,010,304. Other patents are pending.

Figure 1. Typical Applications Circuit

analog.com Rev. B | 6 of 79 VDD = 2.97 V to 3.63 V, GND = AGND = DGND = 0 V, on-chip reference, CLKIN = 24.576 MHz crystal (XTAL), TMIN to TMAX = −40°C to +85°C, TA = 25°C (typical), unless otherwise noted. Table 1. Parameter Min Typ Max Unit Test Conditions/Comments ACCURACY (MEASUREMENT ERROR PER PHASE) Total Active Energy 0.1 % Over a dynamic range of 5000 to 1, 10 sec accumulation 0.2 % Over a dynamic range of 10,000 to 1, 20 sec accumulation 0.1 % Over a dynamic range of 1000 to 1, 2 sec accumulation, PGA = 4, integrator on, high-pass filter (HPF) corner = 4.98 Hz 0.2 % Over a dynamic range of 5000 to 1, 10 sec accumulation, PGA = 4, integrator on, HPF corner = 4.98 Hz Total Reactive Energy 0.1 % Over a dynamic range of 5000 to 1, 10 sec accumulation 0.2 % Over a dynamic range of 10,000 to 1, 20 sec accumulation 0.1 % Over a dynamic range of 1000 to 1, 2 sec accumulation, PGA = 4, integrator on, HPF corner = 4.98 Hz 0.2 % Over a dynamic range of 5000 to 1, 10 sec accumulation, PGA = 4, integrator on, HPF corner = 4.98 Hz Total Apparent Energy 0.1 % Over a dynamic range of 1000 to 1, 2 sec accumulation 0.5 % Over a dynamic range of 5000 to 1, 10 sec accumulation 0.1 % Over a dynamic range of 500 to 1, 1 sec accumulation, PGA = 4, integrator on, HPF corner = 4.98 Hz 0.5 % Over a dynamic range of 1000 to 1, 2 sec accumulation, PGA = 4, integrator on, HPF corner = 4.98 Hz Fundamental Active Energy 0.1 % Over a dynamic range of 5000 to 1, 2 sec accumulation 0.2 % Over a dynamic range of 10,000 to 1, 10 sec accumulation 0.1 % Over a dynamic range of 1000 to 1, 2 sec accumulation, PGA = 4, integrator on, HPF corner = 4.98 Hz 0.2 % Over a dynamic range of 5000 to 1, 10 sec accumulation, PGA = 4, integrator on, HPF corner = 4.98 Hz Fundamental Reactive Energy 0.1 % Over a dynamic range of 5000 to 1, 2 sec accumulation 0.2 % Over a dynamic range of 10,000 to 1, 10 sec accumulation

Table 1. (Continued)

50 Hz fundamental and ninth harmonic

50 Hz fundamental and 31st harmonic, both at

1 Enables implementation of IEC 61000-4-30. 2 Tested during device characterization.

Figure 2. SPI Interface Timing Diagram

TA = 25°C, unless otherwise noted.

1 Analog Devices recommends that reflow profiles used in soldering RoHS

the latest revision of this standard. 2 Applicable standard: ANSI/ESDA/JEDEC JS-001-2014.

3 Applicable standard: JESD22-A115-A (ESD machine model standard of JE-

4 Applicable standard: JESD22-C101F (ESD FICDM standard of JEDEC). ing conditions for extended periods may affect product reliability. device soldered in a circuit board for surface-mount packages. Table 4. Thermal Resistance

1 The junction to air measurement uses a 2S2P JEDEC test board with 4 × 4

test board with 4 × 4 standard JEDEC vias. See JEDEC standard JESD51-2. damage may occur on devices subjected to high energy ESD. performance degradation or loss of functionality.

Figure 3. Pin Configuration Table 5. Pin Function Descriptions 1 PULL_HIGH Pull High. Tie this pin to VDD. (GND, AGND, DGND, and REFGND) together at one point. 4 PM0 Power Mode Pin 0. PM0, combined with PM1, defines the power mode. For normal operation, ground PM0 and PM1. 5 PM1 Power Mode Pin 1. PM1 combined with PM0, defines the power mode. For normal operation, ground PM0 and PM1. 6 RESET Reset Input, Active Low. This pin must stay low for at least 1 µs to trigger a hardware reset. differential level of ±1 V. This channel also has an internal PGA of 1, 2, or 4. differential level of ±1 V. This channel also has an internal PGA of 1, 2, or 4. differential level of ±1 V. This channel also has an internal PGA of 1, 2, or 4. differential level of ±1 V. This channel also has an internal PGA of 1, 2, or 4. 15 REFGND Ground Reference, Internal Voltage Reference. Connect all grounds (GND, AGND, DGND, and REFGND) together at one point. internal voltage reference with external circuits, a buffer is required. 17 NC1 No Connection. It is recommended to tie this pin to ground. 18 NC2 No Connection. It is recommended to tie this pin to ground. differential level of ±1 V. This channel also has an internal PGA of 1, 2, or 4. differential level of ±1 V. This channel also has an internal PGA of 1, 2, or 4. differential level of ±1 V. This channel also has an internal PGA of 1, 2, or 4. 4.7 µF ceramic capacitor. Do not connect external active circuitry to this pin. 26 AGND Analog Ground Reference. Connect all grounds (GND, AGND, DGND, and REFGND) together at one point.

Table 5. Pin Function Descriptions (Continued) 28 GND Supply Ground Reference. Connect all grounds (GND, AGND, DGND, and REFGND) together at one point. provided at this logic input. circuits, connect an external buffer. writing to the CFxDEN registers (see the Digital to Frequency Conversion—CFx Output section). 34 CF2 CF Logic Output 2. This pin indicates CF2. 35 CF3/ZX CF Logic Output 3/Zero Crossing. This pin indicates CF3 or zero crossing. 36 CF4/EVENT/DREADY CF Logic Output 4/Event Pin/Data Ready. This pin indicates CF4, events, or when new data is ready. 37 SCLK Serial Clock Input for the SPI Port. All serial data transfers synchronize to this clock (see the Accessing On-Chip Data section). 38 MISO Data Output for the SPI Port. 39 MOSI Data Input for the SPI Port. 40 SS Slave Select for the SPI Port.

Figure 54. SNR Histogram of ADC SNR for 1000 Devices Tested at TA = 25°C

Figure 55. Test Circuit

analog.com Rev. B | 29 of 79 Crosstalk Crosstalk is measured by grounding one channel and applying a full-scale 50 Hz or 60 Hz signal on all the other channels. The crosstalk is equal to the ratio between the grounded ADC output value and its ADC full-scale output value. The ADC outputs are acquired for 100 sec. Crosstalk is expressed in decibels. Differential Input Impedance DC The differential input impedance represents the impedance be- tween the pair IxP and IxN or VxP and VxN. It varies with the PGA gain selection as indicated in . ADC Offset ADC offset is the difference between the average measured ADC output code with both inputs connected to GND and the ideal ADC output code of zero. ADC offset is expressed in mV. ADC Offset Drift over Temperature The ADC offset drift is the change in offset over temperature. It is measured at −40°C, +25°C, and +85°C. Calculate the offset drift over temperature as follows: Dr i f t = max O f f s et − 40°C − O f f s et + 25 ° C O f f s et + 85°C − O f f s et + 25°C + 85 ° C − + 25°C (1) Offset drift is expressed in µV/°C. ADC Gain Error The gain error in the ADCs represents the difference between the measured ADC output code (minus the offset) and the ideal output code when an external voltage reference of 1.2 V is used. The difference is expressed as a percentage of the ideal code. It represents the overall gain error of one channel. ADC Gain Drift over Temperature This temperature coefficient includes the temperature variation of the ADC gain while using an external voltage reference of 1.2 V. It represents the overall temperature coefficient of one current or voltage channel. With an external voltage reference of 1.2 V in use, the ADC gain is measured at −40°C, +25°C, and +85°C. Then the temperature coefficient is computed as follows: Dr i f t = max Ga in − 40 ° C − G ai n + 25°C G ai n + 85 °C − Ga in + 25 ° C (2) Gain drift is measured in ppm/°C. AC Power Supply Rejection (PSRR) AC PSRR quantifies the measurement error as a percentage of reading when the dc power supply is nominal (VNOM) and modu- lated with ac, and the inputs are grounded. For the ac PSRR measurement, 20 sec samples are captured with nominal supplies (3.3 V, which is V1) and a second set (V2) is captured with an additional ac signal (330 mV peak at 50 Hz) introduced onto the supplies. Then, the PSRR is expressed as PSRR = 20 log10(V2/ V1). Signal-to-Noise Ratio SNR SNR is calculated by inputting a 50 Hz signal, and samples are acquired for 2 sec. The amplitudes for each frequency up to the bandwidth given in as the ADC output bandwidth (−3 dB) are calculated. To determine the SNR, the signal at 50 Hz is compared to the sum of the power from all the other frequencies, removing power from its harmonics. The value for SNR is expressed in decibels. Signal-to-Noise-and-Distortion Ratio SINAD SINAD is calculated by inputting a 50 Hz signal, and samples are acquired for 2 sec. The amplitudes for each frequency up to the bandwidth given in as the ADC output bandwidth (−3 dB) are calculated. To determine the SINAD, the signal at 50 Hz is compared to the sum of the power from all the other frequencies. The value for SINAD is expressed in decibels. Total Harmonic Distortion THD THD is calculated by inputting a 50 Hz signal, and samples are acquired for over 2 sec. The amplitudes for each frequency up to the bandwidth given in as the ADC output bandwidth (−3 dB) are calculated. To determine the THD, the amplitudes of the 50 Hz harmonics up to the bandwidth are root sum squared. The value for THD is expressed in decibels. Spurious-Free Dynamic Range SFDR SFDR is calculated by inputting a 50 Hz signal, and samples are acquired for over 2 sec. The amplitudes for each frequency up to the bandwidth given in as the ADC output bandwidth (−3 dB) are calculated. To determine the SFDR, the amplitude of the largest signal that is not a harmonic of 50 Hz is recorded. The value for SFDR is expressed in decibels. ADC Output Pass Band The ADC output pass band is the bandwidth within 0.1 dB, resulting from the digital filtering in the sinc4 and sinc4 + IIR LPF. ADC Output Bandwidth The ADC output bandwidth is the bandwidth within −3 dB, resulting from the digital filtering in the sinc4 and sinc4 + IIR LPF.

transformer in some 3-wire delta configurations. is configured with the HPF_CRN bits in the CONFIG2 register. DICOEFF value to 0xFFFFE000. current that leads the voltage, as seen in a current transformer. where: fLINE is the line frequency. fDSP is 8 kHz. calibration. MTEN = 0 by default. MTTHR_Hx register values, as shown in Figure 59. Figure 59. Multipoint Phase and Gain Calibration xVGAIN registers have the same scaling as the xIGAIN registers.

For instance, if the signal is at ½ of full scale, x = 2. Figure 60. Voltage Channel Datapath

total apparent power for Phase A. Figure 64. Total Apparent Power, AVA, Calculation for Phase A and xFVA value is 20,694,066 decimals. threshold, zero energy is accumulated into the energy register. APP_NL_LVL registers contain the user defined no load threshold. IRQ1 interrupt, and the EVENT pin. of samples or half line cycles is set in the EGY_TIME register. during half line cycle accumulation. is set in the STATUS0 register and the energy register is updated. full-scale inputs, the user energy register overflows in 106.3 sec.

(ZXIA, ZXIB, and ZXIC) are active for all input signals levels. below which the voltage channel zero-crossing must be blocked. component in the combined zero-crossing circuit is set to zero. zero-crossing output on the CF3/ZX pin. generates an interrupt on the IRQ1 pin. COM_PERIOD registers, respectively. SELFREQ bit in the ACCMODE register. Figure 69. Line Period Selection for Resampling ANGL_VC_IC provide phase angle between voltage and currents. interrupt on IRQ1, set the SEQERR bit in the MASK1 register.

full-scale inputs is 52,702,092d. The signal chain is shown in Figure 70. Figure 70. RMS½, 10 Cycle RMS, and 12 Cycle RMS Measurements

10 Cycle RMS/12 Cycle RMS

10 cycles on a 50 Hz network or 12 cycles on a 60 Hz network. number of samples used in the calculation. ter reading with full-scale inputs is 52,702,092d. The signal chain is shown in Figure 70. ing SWELLA, SWELLB, and SWELLC registers. also generates an event on the CF4/EVENT/DREADY pin. register indicate which current channels exceeded the threshold.

IPPHASE bits. IPEAKVAL is equal to xI_PCF/25. CPF), is updated every 1.024 sec. xWATT value, as indicated in Figure 71. Figure 71. Active Power and VAR Sign for Capacitive and Inductive Loads CVTHD registers, respectively. THD updates once every second. THD value is 0x2000 0000, which corresponds to a THD of 400%. 16-bit signed integer in the waveform buffer. The temperature reading is available in the TEMP_RSLT register.

analog.com Rev. B | 40 of 79 The ADE9000 has a waveform buffer comprised of 2048, 32-bit memory locations. To configure the data into the waveform buffer, use the WF_SRC and WF_CAP_SEL bits in the WFB_CFG regis- ter. The data can come from the following four locations, as follows: ►Sinc4 outputs at 32 kSPS. The waveform buffer holds 8 ms of waveform data per channel. ►Sinc4 + IIR LPF output at 8 kSPS. The waveform buffer holds 32 ms of waveform data per channel. ►Current and voltage channel waveforms processed by the DSP at 8 kSPS. The waveform buffer holds 32 ms of waveform data per channel. ►Resampled waveforms with 128 points per line cycle processed by the DSP. The data rate varies with the line period. The waveform buffer holds 80 ms of waveform data per channel. The waveform buffer offers the following different filling modes for use with fixed data rate samples: ►Stop when buffer is full ►Continuous filling The ADE9000 allows a selection of events to trigger waveform buf- fer captures, and there is an option to store the current waveform buffer address during an event to allow the user to synchronize the event with the waveform samples. The following waveform buffer actions are associated with an event when the buffer is filling continuously: ►Stops filling on trigger ►Centers capture around trigger ►Saves the event address and keeps filling Use the SPI burst read mode to read the waveform buffer contents. The default value bursts out all the channels in the waveform buffer. The waveform buffer generates an interrupt on IRQ0 after the last address is filled. The DSP must be on to use the waveform buffer.

analog.com Rev. B | 41 of 79 The ADE9000 has three pins (IRQ0, IRQ1, and CF4/EVENT/ DREADY) that can be used as interrupts to the host processor. The IRQ0 and IRQ1 pins go low when an enabled interrupt oc- curs and stay low until the event is acknowledged by setting the corresponding status bit in the STATUS0 and STATUS1 registers, respectively. The bits in MASK0 and MASK1 configure respective interrupts. The EVENT function, which can multiplex with the CF4 and DREADY options, tracks the state of the enabled signals and goes low and high with these internal signals. The CF4_CFG bits in CONFIG1 register set the CF4/EVENT/DREADY pin functionality. The CF4/EVENT/ DREADY pin is useful for measuring the duration of events, such as dips or swells, externally.

mum serial clock frequency supported by this interface is 20 MHz. be read after sending one CMD_HDR. Figure 72. Command Header, CMD_HDR SPI read data as part of the SPI transaction. monitored registers change the value of the CRC_RSLT register. WR_LOCK register. To disable the feature, write 0x4AD1.

analog.com Rev. B | 43 of 79 There is a bug in read with reset when using energy accumulation. Using linecyc or sample base accumulation is suggested. Register affected by this is RD_RST_EN, keep this register at the default value of 0.

Table 6. Register Map

Table 6. Register Map (Continued)

hysteresis. See the Multipoint Phase and Gain Calibration section for more information. bit is set in the CONFIG0 register. equal to one in the CONFIG0 register, it is recommended to set this value to 0xFFFFE000. in STATUS0 if ISUMRMS exceeds this threshold.

register indicate which AIGAINx and APHCALx is currently being used. register indicate which BIGAINx and BPHCALx is currently being used.

these bits indicate which CIGAINx and CPHCALx is currently being used. EP_CFG and EGY_TIME registers.

EP_CFG and EGY_TIME registers. EP_CFG and EGY_TIME registers. EP_CFG and EGY_TIME registers. EP_CFG and EGY_TIME registers. EP_CFG and EGY_TIME registers. EP_CFG and EGY_TIME registers. EP_CFG and EGY_TIME registers. EP_CFG and EGY_TIME registers. EP_CFG and EGY_TIME registers. EP_CFG and EGY_TIME registers. EP_CFG and EGY_TIME registers.

EP_CFG and EGY_TIME registers. EP_CFG and EGY_TIME registers. after PWR_TIME 8 kSPS samples. updated after PWR_TIME 8 kSPS samples. updated after PWR_TIME 8 kSPS samples. updated after PWR_TIME 8 kSPS samples. after PWR_TIME 8 kSPS samples. after PWR_TIME 8 kSPS samples. after PWR_TIME 8 kSPS samples. after PWR_TIME 8 kSPS samples. register and AIRMSONE greater than the OILVL threshold, this value is updated. register and BIRMSONE greater than the OILVL threshold, this value is updated. register and CIRMSONE greater than the OILVL threshold, this value is updated. register and NIRMSONE greater than the OILVL threshold, this value is updated. when the UPERIOD_SEL bit in the CONFIG2 register is set. as well as the fundamental IRMS and VRMS values.

transaction on the SPI port. 0x4FE Version Version of ADE9000 IC. Use Logical AND 16-bit value with 0xFFC0 to obtain the current version. The current version is 0x00C0.

1 Not valid until run bit is set. 2 The default value is unique to every individual IC.

Table 7 details the registers of the ADE9000 that have bit fields. Additional registers listed in Table 6 do not have bit fields. Table 7. Register Details

13 DISRPLPF Set this bit to disable the low-pass filter in the total

12 DISAPLPF Set this bit to disable the low-pass filter in the total active

11 ININTEN Set this bit to enable the digital integrator in the neutral

10 VNOMC_EN Set this bit to use the nominal phase voltage rms, VNOM,

in the computation of Phase C total apparent power, CVA.

9 VNOMB_EN Set this bit to use the nominal phase voltage rms, VNOM,

in the computation of Phase B total apparent power, BVA.

8 VNOMA_EN Set this bit to use the nominal phase voltage rms, VNOM,

in the computation of Phase A total apparent power, AVA.

7 RMS_SRC_SEL This bit selects which samples are used for the rms½ and

10 cycle rms/12 cycle rms calculation. 1 ADC samples, before the high-pass filter and integrator.

6 ZX_SRC_SEL This bit selects whether data going into the zero-crossing

integrator, and phase compensation or afterwards.

0 After the high-pass filter, integrator, and phase

1 Before the high-pass filter, integrator, and phase

5 INTEN Set this bit to enable the integrators in the phase

is managed by the ININTEN bit in the CONFIG0 register.

4 MTEN Set this bit to enable multipoint phase and gain

the MTTHR_Lx and MTTHR_Hx register values.

3 HPFDIS Set this bit to disable high-pass filters in all the voltage

00 ISUM = AI_PCF + BI_PCF + CI_PCF (for approximated

neutral current rms calculation).

01 ISUM = AI_PCF + BI_PCF + CI_PCF + NI_PCF

10 ISUM = AI_PCF + BI_PCF + CI_PCF − NI_PCF

11 ISUM = AI_PCF + BI_PCF + CI_PCF (for approximated

neutral current rms calculation).

Table 7. Register Details (Continued) A current is generated by the IPEAKVAL, Bits[23:0] value. current. IPEAK is equal to xI_PCF/25.

voltage. VPEAK is equal to xV_PCF/25.

25 TEMP_RDY This bit goes high to indicate when a new temperature

24 MISMTCH This bit is set to indicate a change in the relationship

between ISUMRMS and ISUMLVL.

23 COH_WFB_FULL This bit is set when the waveform buffer is full with

22 WFB_TRIG This bit is set when one of the events configured in

21 THD_PF_RDY This bit goes high to indicate when the THD and power

factor measurements update, every 1.024 sec.

20 RMS1012RDY This bit is set when the 10 cycle rms/12 cycle rms values

18 PWRRDY This bit is set when the power values in the xWATT_ACC,

17 PAGE_FULL This bit is set when a page enabled in the

16 WFB_TRIG_IRQ This bit is set when the waveform buffer stops filling

after an event configured in WFB_TRG_CFG occurs. 15 DREADY This bit is set when new waveform samples are ready. WF_SRC bits in the WFB_CFG register.

14 CF4 This bit is set when a CF4 pulse is issued, when the CF4

pin goes from a high to low state.

13 CF3 This bit is set when a CF3 pulse is issued, when the CF3

pin goes from a high to low state.

12 CF2 This bit is set when a CF2 pulse is issued, when the CF2

pin goes from a high to low state.

11 CF1 This bit is set when a CF1 pulse is issued, when the CF1

pin goes from a high to low state. 10 REVPSUM4 This bit is set to indicate if the CF4 polarity changed sign. 9 REVPSUM3 This bit is set to indicate if the CF3 polarity changed sign. 8 REVPSUM2 This bit is set to indicate if the CF2 polarity changed sign.

7 REVPSUM1 This bit is set to indicate if the CF1 polarity changed sign.

6 REVRPC This bit indicates if the Phase C total or fundamental

5 REVRPB This bit indicates if the Phase B total or fundamental

reactive power has changed sign. See REVRPC.

4 REVRPA This bit indicates if the Phase A total or fundamental

reactive power has changed sign. See REVRPC.

3 REVAPC This bit indicates if the Phase C total or fundamental

2 REVAPB This bit indicates if the Phase B total or fundamental

active power has changed sign. See REVAPC.

1 REVAPA This bit indicates if the Phase A total or fundamental

active power has changed sign. See REVAPC.

0 EGYRDY This bit is set when the power values in the xWATTHR

30 ERROR2 This bit indicates that an error was detected and

corrected. No action is required.

29 ERROR1 This bit indicates an error and generates a non-maskable

28 ERROR0 This bit indicates an error and generates a non-maskable

27 CRC_DONE This bit is set to indicate when the configuration register

FORCE_CRC_UPDATE bit in the CRC_FORCE register.

26 CRC_CHG This bit is set if any of the registers monitored by

25 DIPC This bit is set to indicates Phase C voltage entered or

24 DIPB This bit is set to indicates Phase B voltage entered or

23 DIPA This bit is set to indicates Phase A voltage entered or

22 SWELLC This bit is set to indicates Phase C voltage entered or

21 SWELLB This bit is set to indicates Phase B voltage entered or

20 SWELLA This bit it set to indicates Phase A voltage entered or

18 SEQERR This bit is set to indicate a phase sequence error on the

Phase voltage zero crossings.

17 OI This bit is set to indicate that an overcurrent event

16 RSTDONE This bit is set to indicate that the IC finished its power-up

can configure the IC via the SPI port.

15 ZXIC When this bit is set to 1, it indicates a zero crossing is

detected on Phase C current.

14 ZXIB When this bit is set to 1, it indicates a zero crossing is

detected on Phase B current.

13 ZXIA When this bit is set to 1, it indicates a zero crossing is

detected on Phase A current.

12 ZXCOMB When this bit is set, it indicates a zero crossing is

detected on the combined signal from VA, VB, and VC.

11 ZXVC When this bit is set, it indicates a zero crossing is

detected on the Phase C voltage channel.

10 ZXVB When this bit is set, it indicates a zero crossing is

detected on the Phase B voltage channel.

9 ZXVA When this bit is set, it indicates a zero crossing is

detected on the Phase A voltage channel.

8 ZXTOVC This bit is set to indicate a zero-crossing timeout on

7 ZXTOVB This bit is set to indicate a zero-crossing timeout on

6 ZXTOVA This bit is set to indicate a zero-crossing timeout on

5 VAFNOLOAD This bit is set when one or more phase fundamental

phase is indicated in the PHNOLOAD register.

4 RFNOLOAD This bit is set when one or more phase fundamental

phase is indicated in the PHNOLOAD register.

3 AFNOLOAD This bit is set when one or more phase fundamental

phase is indicated in the PHNOLOAD register.

2 VANLOAD This bit is set when one or more phase total apparent

indicated in the PHNOLOAD register.

1 RNLOAD This bit is set when one or more phase total reactive

indicated in the PHNOLOAD register.

0 ANLOAD This bit is set when one or more phase total active

indicated in the PHNOLOAD register.

16 DREADY This bit changes from a zero to a one when new

15 VAFNOLOAD This bit is set when the fundamental apparent energy

energy accumulation goes into no load.

14 RFNOLOAD This bit is set when the fundamental reactive energy

reactive energy accumulation goes into no load.

13 AFNOLOAD This bit is set when the fundamental active energy

active energy accumulation goes into no load.

12 VANLOAD This bit is set when the total apparent energy

energy accumulation goes into no load.

11 RNLOAD This bit is set when the total reactive energy

energy accumulation goes into no load.

10 ANLOAD This bit is set when the total active energy accumulations

accumulation goes into no load.

5 SWELLC This bit is equal to one when the Phase C voltage is in

4 SWELLB This bit is equal to one when the Phase B voltage is in

3 SWELLA This bit is equal to one when the Phase A voltage is in

2 DIPC This bit is equal to one when the Phase C voltage is

1 DIPB This bit is equal to one when the Phase B voltage is in the

0 DIPA This bit is equal to one when the Phase A voltage is in the

dip condition and is zero when it is not in a dip condition.

25 TEMP_RDY_MASK Set this bit to enable an interrupt when a new

temperature measurement is available.

24 MISMTCH Set this bit to enable an interrupt when there is a change

in the relationship between ISUMRMS and ISUMLVL.

23 COH_WFB_FULL Set this bit to enable an interrupt when the waveform

WF_CAP_SEL = 0 in the WFB_CFG register.

22 WFB_TRIG Set this bit to enable an interrupt when one of the events

configured in WFB_TRG_CFG occurs.

21 THD_PF_RDY Set this bit to enable an interrupt when the THD and

20 RMS1012RDY Set this bit to enable an interrupt when the 10 cycle

rms/12 cycle rms values are updated.

19 RMSONERDY Set this bit to enable an interrupt when the fast rms½

18 PWRRDY Set this bit to enable an interrupt when the power

update, after PWR_TIME 8 kSPS samples.

17 PAGE_FULL Set this bit to enable an interrupt when a page enabled in

the WFB_PG_IRQEN register is filled.

16 WFB_TRIG_IRQ Set this bit to enable an interrupt when the waveform

15 DREADY Set this bit to enable an interrupt when new waveform

selected in the WF_SRC bits in the WFB_CFG register.

14 CF4 Set this bit to enable an interrupt when the CF4 pulse is

issued, when the CF4 pin goes from a high to low state.

13 CF3 Set this bit to enable an interrupt when the CF3 pulse is

issued, when the CF3 pin goes from a high to low state.

12 CF2 Set this bit to enable an interrupt when the CF2 pulse is

issued, when the CF2 pin goes from a high to low state.

11 CF1 Set this bit to enable an interrupt when the CF1 pulse is

issued, when the CF1 pin goes from a high to low state.

10 REVPSUM4 Set this bit to enable an interrupt when the CF4 polarity

9 REVPSUM3 Set this bit to enable an interrupt when the CF3 polarity

8 REVPSUM2 Set this bit to enable an interrupt when the CF2 polarity

7 REVPSUM1 Set this bit to enable an interrupt when the CF1 polarity

6 REVRPC Set this bit to enable an interrupt when the Phase C total

or fundamental reactive power has changed sign.

5 REVRPB Set this bit to enable an interrupt when the Phase C total

or fundamental reactive power has changed sign.

4 REVRPA Set this bit to enable an interrupt when the Phase A total

or fundamental reactive power has changed sign.

3 REVAPC Set this bit to enable an interrupt when the Phase C total

or fundamental active power has changed sign.

2 REVAPB Set this bit to enable an interrupt when the Phase B total

or fundamental active power has changed sign.

1 REVAPA Set this bit to enable an interrupt when the Phase A total

or fundamental active power has changed sign.

0 EGYRDY Set this bit to enable an interrupt when the power values

EGY_TMR_MODE bit in the EP_CFG register. 0x406 MASK1 31 ERROR3 Set this bit to enable an interrupt if ERROR3 occurs. hardware reset to clear this error. hardware reset to clear this error.

27 CRC_DONE Set this bit to enable an interrupt when the configuration

26 CRC_CHG Set this bit to enable an interrupt if any of the

configuration register CRC value.

25 DIPC Set this bit to enable an interrupt when the Phase C

24 DIPB Set this bit to enable an interrupt when the Phase B

voltage enters a dip condition.

23 DIPA Set this bit to enable an interrupt when the Phase A

voltage enters a dip condition.

22 SWELLC Set this bit to enable an interrupt when the Phase C

voltage enters a swell condition.

21 SWELLB Set this bit to enable an interrupt when the Phase B

voltage enters a swell condition.

20 SWELLA Set this bit to enable an interrupt when the Phase A

voltage enters a swell condition.

18 SEQERR Set this bit to enable an interrupt when on a phase

sequence error on the phase voltage zero crossings.

17 OI Set this bit to enable an interrupt when one of the

15 ZXIC Set this bit to enable an interrupt when a zero crossing is

detected on the Phase C current channel.

14 ZXIB Set this bit to enable an interrupt when a zero crossing is

detected on the Phase B current channel.

13 ZXIA Set this bit to enable an interrupt when a zero crossing is

detected on the Phase A current channel.

12 ZXCOMB Set this bit to enable an interrupt when a zero crossing is

detected on the combined signal from VA, VB, and VC.

11 ZXVC Set this bit to enable an interrupt when a zero crossing is

detected on the Phase C voltage channel.

10 ZXVB Set this bit to enable an interrupt when a zero crossing is

detected on the Phase B voltage channel.

9 ZXVA Set this bit to enable an interrupt when a zero crossing is

detected on the Phase A voltage channel.

8 ZXTOVC Set this bit to enable an interrupt when there is a zero-

crossing on the Phase C voltage is missing.

7 ZXTOVB Set this bit to enable an interrupt when there is a zero-

crossing on the Phase B voltage is missing.

6 ZXTOVA Set this bit to enable an interrupt when there is a zero-

crossing on the Phase A voltage is missing.

5 VAFNOLOAD Set this bit to enable an interrupt when one or more

4 RFNOLOAD Set this bit to enable an interrupt when one or more

3 AFNOLOAD Set this bit to enable an interrupt when one or more

2 VANLOAD Set this bit to enable an interrupt when one or more

1 RNLOAD Set this bit to enable an interrupt when one or more

0 ANLOAD Set this bit to enable an interrupt when one or more

16 DREADY Set this bit to enable the EVENT pin to go low when

15 VAFNOLOAD Set this bit to enable the EVENT pin to go low when

accumulation goes into no load.

14 RFNOLOAD Set this bit to enable the EVENT pin to go low when

accumulation goes into no load.

13 AFNOLOAD Set this bit to enable the EVENT pin to go low when

accumulation goes into no load.

12 VANLOAD Set this bit to enable the EVENT pin to go low when one

11 RNLOAD Set this bit to enable the EVENT pin to go low when

10 ANLOAD Set this bit to enable the EVENT pin to go low when one

9 REVPSUM4 Set this bit to enable the EVENT pin to go low to indicate

8 REVPSUM3 Set this bit to enable the EVENT pin to go low to indicate

7 REVPSUM2 Set this bit to enable the EVENT pin to go low to indicate

6 REVPSUM1 Set this bit to enable the EVENT pin to go low to indicate

5 SWELLCEN Set this bit to enable the EVENT pin to go low to indicate

that the Phase C voltage is in a swell condition.

4 SWELLBEN Set this bit to enable the EVENT pin to go low to indicate

that the Phase B voltage is in a swell condition.

3 SWELLAEN Set this bit to enable the EVENT pin to go low to indicate

that the Phase A voltage is in a swell condition.

2 DIPCEN Set this bit to enable the EVENT pin to go low to indicate

that the Phase C voltage is in a dip condition.

1 DIPBEN Set this bit to enable the EVENT pin to go low to indicate

that the Phase B voltage is in a dip condition.

0 DIPAEN Set this bit to enable the EVENT pin to go low to indicate

that the Phase A voltage is in a dip condition.

well as the fundamental IRMS and VRMS values.

17 CFVANL This bit is set if the Phase C fundamental apparent

16 CFVARNL This bit is set if the Phase C fundamental reactive energy

15 CFWATTNL This bit is set if the Phase C fundamental active energy is

14 CVANL This bit is set if the Phase C total apparent energy is in no

13 CVARNL This bit is set if the Phase B total reactive energy is in no

12 CWATTNL This bit is set if the Phase C total active energy is in no

11 BFVANL This bit is set if the Phase B fundamental apparent

10 BFVARNL This bit is set if the Phase B fundamental reactive energy

9 BFWATTNL This bit is set if the Phase B fundamental active energy is

8 BVANL This bit is set if the Phase B total apparent energy is in no

7 BVARNL This bit is set if the Phase B total reactive energy is in no

6 BWATTNL This bit is set if the Phase B total active energy is in no

5 AFVANL This bit is set if the Phase A fundamental apparent

4 AFVARNL This bit is set if the Phase A fundamental reactive energy

3 AFWATTNL This bit is set if the Phase A fundamental active energy is

2 AVANL This bit is set if the Phase A total apparent energy is in no

1 AVARNL This bit is set if the Phase A total reactive energy is in no

0 AWATTNL This bit is set if the Phase A total active energy is in no

bit descriptions for 000b through 110b match VC_DIN. bit descriptions for 000b through 110b match VC_DIN. bit descriptions for 000b through 110b match VC_DIN. bit descriptions for 000b through 110b match VC_DIN.

bit descriptions for 000b through 110b match VC_DIN. bit descriptions for 000b through 110b match VC_DIN. bit descriptions for 000b through 110b match VC_DIN.

22 CF4_LT If this bit is set, the CF4 pulse width is determined by the

21 CF3_LT If this bit is set, the CF3 pulse width is determined by

20 CF2_LT If this bit is set, the CF2 pulse width is determined by

19 CF1_LT If this bit is set, the CF1 pulse width is determined by

12 IRQ0_ON_IRQ1 Set this bit to combine all the interrupts onto a single

11 BURST_EN Set this bit to enable burst read functionality on the

disables the CRC being appended to SPI register reads.

0 Receive continuous interrupts after every DIP_CYC/

1 Receive one interrupt when entering dip/swell mode and

another interrupt when exiting dip/swell mode. power, energy, and CF accumulations.

5 CF_ACC_CLR Set this bit to clear the accumulation in the digital to

this bit automatically clears itself. 00 CF4, from digital to frequency converter. 01 CF4, from digital to frequency converter. 0 CF3, from digital to frequency converter.

1 Zero-crossing output selected by the ZX_SEL bits in the

OIPHASE, Bit 1 indicates Phase B is above OILVL. OIPHASE, Bit 2 indicates Phase C is above OILVL. OIPHASE, Bit 3 indicates Phase N is above OILVL. accumulated in the digital to frequency converter. 011 Fundamental active power. 100 Fundamental reactive power. 101 Fundamental apparent power.

Bit 2 to 1 to include Phase C in the CF4 pulse output. TERMSEL4, Bit 0 for Phase A.

8 SELFREQ Use this bit to configure the IC for a 50 Hz or 60 Hz

calculations if a zero crossing is not present.

7 ICONSEL Set this bit to calculate the current flowing through IB from

001 3-wire delta. VB' = VA − VC. 010 4-wire wye, nonBlondel compliant. VB' = −VA − VC. 011 4-wire delta, nonBlondel compliant. VB' = −VA. for energy registers and CFx pulses. 00 Signed accumulation mode. 10 Positive accumulation mode. 11 Negative accumulation mode. for energy registers and CFx pulses. See VARACC. all three phases and/or neutral simultaneously. selected for the overcurrent detection. for the overcurrent detection. for the overcurrent detection. for the overcurrent detection.

enables Phase C peak detection. 10 cycle rms/12 cycle rms, and resampling.

00 APERIOD, line period measurement from Phase A

01 BPERIOD, line period measurement from Phase B

10 CPERIOD, line period measurement from Phase C

11 COM_PERIOD, line period measurement on combined

00 ZXVA, Phase A voltage zero-crossing signal. 01 ZXVB, Phase B voltage zero-crossing signal. 10 ZXVC, Phase C voltage zero-crossing signal.

11 ZXCOMB, zero crossing on combined signal from VA, VB,

9 SUM4SIGN Sign of the sum of the powers included in the CF4

and negative if this bit is set.

8 SUM3SIGN Sign of the sum of the powers included in the CF3

and negative if this bit is set.

7 SUM2SIGN Sign of the sum of the powers included in the CF2

and negative if this bit is set.

6 SUM1SIGN Sign of the sum of the powers included in the CF1

and negative if this bit is set. total or fundamental reactive power. or fundamental active power. total or fundamental reactive power. or fundamental active power. total or fundamental reactive power.

or fundamental active power.

12 WF_IN_EN This setting determines whether the IN waveform

0 IN waveform samples are not read out of waveform buffer

1 IN waveform samples are read out of waveform buffer

10 Sinc4 + IIR LPF output at 8 kSPS.

11 Current and voltage channel waveform samples,

processed by the DSP (xI_PCF, xV_PCF) at 8 kSPS. 00 Stop when waveform buffer is full. 01 Continuous fill—stop only on enabled trigger events.

10 Continuous filling—center capture around enabled trigger

11 Continuous fill—save event address of enabled trigger

5 WF_CAP_SEL This bit selects whether the waveform buffer is filled with

1 The waveform capture is started, according to the type

this bit goes from a 0 to a 1. 1110IN if WF_IN_EN = 1 in the WFB_CFG register.

1111Single address read (SPI burst read mode is disabled).

10 TRIG_FORCE Set this bit to trigger an event to stop the waveform buffer

was filled last, when filling with fixed rate data samples.

12 UPERIOD_SEL Set this bit to use a user configured line period, in

bits in the ZX_LP_SEL register is used. bit in the CONFIG0 register is equal to zero. evaluate the no load condition over. 111 Disable no load threshold.

7 PWR_SIGN_SEL[1] Selects whether the REVRPx bit follows the sign of the

total or fundamental reactive power. 1 Fundamental reactive power.

6 PWR_SIGN_SEL[0] Selects whether the REVAPx bit follows the sign of the

total or fundamental active power.

5 RD_RST_EN3 Set this bit to enable the energy register read with reset

4 EGY_LD_ACCUM If this bit is equal to zero, the internal energy register

1 EGY_TMR_MODE This bit determines whether energy is accumulated based

events configured in the EGY_TIME register. 0 Accumulate energy based on 8 kSPS samples.

1 Accumulate energy based on the zero crossing selected

by the ZX_SEL bits in the ZX_LP_SEL register.

0 EGY_PWR_EN Set this bit to enable the energy and power accumulator,

when the run bit is also set.