ADE8052-DWDL1

ADE7566 AD | Alldatasheet

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Technical content

Single-Phase Energy Measurement IC with

8052 MCU, RTC, and LCD Driver

ADE7566/ADE7569/ADE7166/ADE7169 Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2007 Analog Devices, Inc. All rights reserved. GENERAL FEATURES Wide supply voltage operation: 2.4 V to 3.7 V Internal bipolar switch between regulated and battery inputs Ultralow power operation with power-saving modes (PSM) Full operation: 4 mA to 1.6 mA (PLL clock dependent) Battery mode: 3.2 mA to 400 μA (PLL clock dependent) Sleep mode Real-time clock (RTC) mode: 1.5 μA RTC and LCD mode: 27 μA (LCD charge pump enabled) Reference: 1.2 V ± 0.1% (10 ppm/°C drift) 64-lead RoHS package options Lead frame chip scale package (LFCSP) Low profile quad flat package (LQFP) Operating temperature range: −40°C to +85°C ENERGY MEASUREMENT FEATURES Proprietary analog-to-digital converters (ADCs) and digital signal processing (DSP) provide high accuracy active (Watt), reactive (VAR), and apparent energy (VA) measurement Less than 0.1% error on active energy over a dynamic range of 1000 to 1 @ 25°C Less than 0.5% error on reactive energy over a dynamic range of 1000 to 1 @ 25°C (ADE7569 and ADE7169 only) Less than 0.5% error on root mean square (rms) measurements over a dynamic range of 500 to 1 for current (Irms) and 100 to 1 for voltage (Vrms) @ 25°C Supports IEC 62053-21, IEC 62053-22, IEC 62053-23, EN 50470-3 Class A, Class B, and Class C, and ANSI C12-16 Differential input with programmable gain amplifiers (PGAs) supports shunts, current transformers, and di/dt current sensors (ADE7569 and ADE7169 only) Two current inputs for antitamper detection in the ADE7166/ADE7169 High frequency outputs proportional to Irms, active, reactive, or apparent power (AP) Table 1. Part No. Anti- Tamper Watt, VA, I rms, Vrms VAR di/dt Sensor ADE7566 No Yes No No ADE7569 No Yes Yes Yes ADE7166 Yes Yes No No ADE7169 Yes Yes Yes Yes MICROPROCESSOR FEATURES 8052-based core Single-cycle 4 MIPS 8052 core 8052-compatible instruction set 32.768 kHz external crystal with on-chip PLL Two external interrupt sources External reset pin Low power battery mode Wake-up from I/O, temperature change, alarm, and universal asynchronous receiver/transmitter (UART) LCD driver operation Temperature measurement Real-time clock Counter for seconds, minutes, and hours Automatic battery switchover for RTC backup Operation down to 2.4 V Ultralow battery supply current: 1.5 μA Selectable output frequency: 1 Hz to 16.384 kHz Embedded digital crystal frequency compensation for calibration and temperature variation 2 ppm resolution Integrated LCD driver 108-segment driver for the ADE7566/ADE7569 and 104-segment driver for the ADE7166/ADE7169 2×, 3×, or 4× multiplexing LCD voltages generated internally or with external resistors Internal adjustable drive voltages up to 5 V independent of power supply level On-chip peripherals UART, SPI or I2C, and watchdog timer Power supply monitoring with user-selectable levels Memory: 16 kB flash memory, 512 bytes RAM Development tools Single-pin emulation IDE-based assembly and C-source debugging

ADE7566/ADE7569/ADE7166/ADE7169 Rev. A | Page 2 of 144 TABLE OF CONTENTS di/dt Current Sensor and Digital Integrator for the Reactive Energy Calculation for the ADE7569/ADE7169 ... 64

ADE7566/ADE7569/ADE7166/ADE7169 Rev. A | Page 3 of 144

REVISION HISTORY

12/07—Revision A: Initial Combined Version 12/07—Rev. 0 to Rev. A 11/07—Revision 0: Initial Version

electronic energy meter with an LCD display in a single part. measurement DSP to simplify energy meter design. capable of driving LCDs up to 5 V .

256 BYTES

Figure 1. ADE7566/ADE7569 Functional Block Diagram

Figure 2. ADE7166/ADE7169 Functional Block Diagram

ADE7566/ADE7569/ADE7166/ADE7169 Rev. A | Page 6 of 144 SPECIFICATIONS VDD = 3.3 V ± 5%, AGND = DGND = 0 V , on-chip reference XTAL = 32.768 kHz, TMIN to TMAX = −40°C to +85°C, unless otherwise noted. ENERGY METERING Table 2. Parameter Min Typ Max Unit Test Conditions/Comments MEASUREMENT ACCURACY1 Phase Error Between Channels PF = 0.8 Capacitive ±0.05 Degrees Phase lead 37° PF = 0.5 Inductive ±0.05 Degrees Phase lag 60° Active Energy Measurement Error2 0.1 % of reading Over a dynamic range of 1000 to 1 @ 25°C AC Power Supply Rejection2 VDD = 3.3 V + 100 mV rms/120 Hz Output Frequency Variation 0.01 % IPx = VP = ±100 mV rms DC Power Supply Rejection2 VDD = 3.3 V ± 117 mV dc Output Frequency Variation 0.01 % Active Energy Measurement Bandwidth1 8 kHz Reactive Energy Measurement Error2, 3 0.5 % of reading Over a dynamic range of 1000 to 1 @ 25°C Vrms Measurement Error2 0.5 % of reading Over a dynamic range of 100 to 1 @ 25°C Vrms Measurement Bandwidth1 3.9 kHz Irms Measurement Error2 0.5 % of reading Over a dynamic range of 500 to 1 @ 25°C Irms Measurement Bandwidth1 3.9 kHz ANALOG INPUTS Maximum Signal Levels ±400 mV peak VP − VN differential input ADE7566/ADE7569 ±400 mV peak IP − IN differential input ADE7166/ADE7169 ±250 mV peak IPA − IN and IPB − IN differential inputs Input Impedance (DC) 770 kΩ ADC Offset Error2 ±10 mV PGA1 = PGA2 = 1 ±1 mV PGA1 = 16 Gain Error2 Current Channel −3 + 3 % IPA = IPB = 0.4 V dc or IP = 0.4 dc Voltage Channel −3 + 3 % Voltage channel = 0.4 V dc Gain Error Match ±0.2 % CF1 AND CF2 PULSE OUTPUT Maximum Output Frequency 13.5 kHz VP − VN = 400 mV peak; IPA − IN = 250 mV PGA1 = 2 sine wave Duty Cycle 50 % If CF1 or CF2 frequency, >5.55 Hz Active High Pulse Width 90 ms If CF1 or CF2 frequency, <5.55 Hz FAULT DETEC TION4 Fault Detection Threshold Inactive Input ≠ Active Input 6.25 %, of active IPA or IPB active Input Swap Threshold Inactive Input > Active Input 6.25 % of active IPA or IPB active Accuracy Fault Mode Operation IPA Active, IPB = AGND 0.1 % of reading Over a dynamic range of 500 to 1 IPB Active, IPA = AGND 0.1 % of reading Over a dynamic range of 500 to 1 Fault Detection Delay 3 Seconds Swap Delay 3 Seconds 1 These numbers are not production tested but are guaranteed by design and/or characterization data on production release. 2 See the Terminology section for definition. 3 This function is not available in the ADE7566 and the ADE7166. 4 This function is not available in the ADE7566 and the ADE7569.

ADE7566/ADE7569/ADE7166/ADE7169 Rev. A | Page 7 of 144 ANALOG PERIPHERALS Table 3. Parameter Min Typ Max Unit Test Conditions/Comments INTERNAL ADCs (BATTERY, TEMPERATURE, VDCIN) Power Supply Operating Range 2.4 3.7 V Measured on VSWOUT No Missing Codes1 8 Bits Conversion Delay2 38 μs ADC Gain VDCIN Measurement 15.3 mV/LSB VBAT Measurement 14.6 mV/LSB Temperature Measurement 0.78 °C/LSB ADC Offset VDCIN Measurement at 3 V 206 LSB VBAT Measurement at 3.7 V 205 LSB Temperature Measurement at 25°C 129 LSB VDCIN Analog Input Maximum Signal Levels 0 3.3 V Input Impedance (DC) 1 MΩ Low VDCIN Detection Threshold 1.09 1.2 1.27 V POWER-ON RESET (POR) VDD POR Detection Threshold 2.5 2.95 V POR Active Timeout Period 33 ms VSWOUT POR Detection Threshold 1.8 2.2 V POR Active Timeout Period 20 ms VINTD POR Detection Threshold 2.03 2.22 V POR Active Timeout Period 16 ms VINTA POR Detection Threshold 2.05 2.15 V POR Active Timeout Period 120 ms BATTERY SWITCH OVER Voltage Operating Range (VSWOUT) 2.4 3.7 V VDD to VBAT Switching Switching Threshold (VDD) 2.5 2.95 V Switching Delay 10 ns When VDD to VBAT switch activated by VDD 30 ms When VDD to VBAT switch activated by VDCIN VBAT to VDD Switching Switching Threshold (VDD) 2.5 2.95 V Switching Delay 30 ms Based on VDD > 2.75 V VSWOUT To VBAT Leakage Current 10 nA VBAT = 0 V, VSWOUT = 3.43 V, TA = 25°C LCD, CHARGE PUMP ACTIVE Charge Pump Capacitance Between LCDVP1 and LCDVP2 100 nF LCDVA, LCDVB, LCDVC Decoupling Capacitance 470 nF LCDVA 0 1.75 V LCDVB 0 3.5 V 1/3 bias mode LCDVC 0 5.3 V 1/3 bias mode V1 Segment Line Voltage LCDVA − 0.1 LCDVA V Current on segment line = −2 μA V2 Segment Line Voltage LCDVB − 0.1 LCDVB V Current on segment line = −2 μA V3 Segment Line Voltage LCDVC − 0.1 LCDVC V Current on segment line = −2 μA DC Voltage Across Segment and COM Pin 50 mV LCDVC − LCDVB, LCDVC − LCDVA, or LCDVB − LCDVA

ADE7566/ADE7569/ADE7166/ADE7169 Rev. A | Page 8 of 144 Parameter Min Typ Max Unit Test Conditions/Comments LCD, RESISTOR LADDER ACTIVE Leakage Current ±20 nA 1/2 and 1/3 bias modes, no load V1 Segment Line Voltage LCDVA − 0.1 LCDVA V Current on segment line = −2 μA V2 Segment Line Voltage LCDVB − 0.1 LCDVB V Current on segment line = −2 μA V3 Segment Line Voltage LCDVC − 0.1 LCDVC V Current on segment line = −2 μA ON-CHIP REFERENCE Reference Error ±0.9 mV TA = 25°C Power Supply Rejection 80 dB Temperature Coefficient1 10 50 ppm/°C 1 These numbers are not production tested but are guaranteed by design and/or characterization data on production release. 2 Delay between ADC conversion request and interrupt set. DIGITAL INTERFACE Table 4. Parameter Min Typ Max Unit Test Conditions/Comments LOGIC INPUTS All Inputs Except XTAL1, XTAL2, BCTRL, INT0, INT1, RESET Input High Voltage, VINH 2.0 V Input Low Voltage, VINL 0.4 V BCTRL, INT0, INT1, RESET Input High Voltage, VINH 1.3 V Input Low Voltage, VINL 0.4 V Input Currents RESET 100 nA RESET = VSWOUT = 3.3 V Port 0, Port 1, Port 2 ±100 nA Internal pull-up disabled, input = 0 V or VSWOUT −3.75 −8.5 μA Internal pull-up enabled, input = 0 V, VSWOUT = 3.3 V Input Capacitance 10 pF All digital inputs FLASH MEMORY Endurance1 10,000 Cycles Data Retention2 20 Years TJ = 85°C CRYSTAL OSCILLATOR Crystal Equivalent Series Resistance 30 50 kΩ Crystal Frequency 32 32.768 33.5 kHz XTAL1 Input Capacitance 12 pF XTAL2 Output Capacitance 12 pF MCU CLOCK RATE (fCORE) 4.096 MHz Crystal = 32.768 kHz and CD[2:0] = 0 32 kHz Crystal = 32.768 kHz and CD[2:0] = 0b111 LOGIC OUTPUTS Output High Voltage, VOH 2.4 V VDD = 3.3 V ± 5% ISOURCE 80 μA Output Low Voltage, VOL3 0.4 V VDD = 3.3 V ± 5% ISINK 2 m A START-UP TIME4 PSM0 Power-On Time 448 ms VDD at 2.75 V to PSM0 code execution From Power Saving Mode 1 (PSM1) PSM1 → PSM0 130 ms VDD at 2.75 V to PSM0 code execution From Power Saving Mode 2 (PSM2) PSM2 → PSM1 48 ms Wake-up event to PSM1 code execution PSM2 → PSM0 186 ms VDD at 2.75 V to PSM0 code execution

ADE7566/ADE7569/ADE7166/ADE7169 Rev. A | Page 9 of 144 Parameter Min Typ Max Unit Test Conditions/Comments POWER SUPPLY INPUTS VDD 3.13 3.3 3.46 V VBAT 2.4 3.3 3.7 V INTERNAL POWER SUPPLY SWITCH (VSWOUT) VBAT to VSWOUT On Resistance 22 Ω VBAT = 2.4 V VDD to VSWOUT On Resistance 10.2 Ω VDD = 3.13 V VBAT ←→ VDD Switching Open Time 40 ns BCTRL State Change and Switch Delay 18 μs VSWOUT Output Current Drive 1 6 mA POWER SUPPLY OUTPUTS VINTA 2.25 2.75 V VINTD 2.3 2.70 V VINTA Power Supply Rejection 60 dB VINTD Power Supply Rejection 50 dB POWER SUPPLY CURRENTS Current in Normal Mode (PSM0) 4 5.3 mA fCORE = 4.096 MHz, LCD and meter active 2.1 mA fCORE = 1.024 MHz, LCD and meter active 1.6 mA fCORE = 32.768 kHz, LCD and meter active 3.2 4.25 mA fCORE = 4.096 MHz, meter DSP active, metering ADC powered down 3 3.9 mA fCORE = 4.096 MHz, metering ADC and DSP powered down Current in PSM1 3.2 5.05 mA fCORE = 4.096 MHz, LCD active, VBAT = 3.7 V 880 μA fCORE = 1.024 MHz, LCD active Current in PSM2 38 μA LCD active with charge pump at 3.3 V + RTC 1.5 μA RTC only, TA = 25°C, VBAT = 3.3 V POWER SUPPLY CURRENTS Current in Normal Mode (PSM0) 4 5.3 mA fCORE = 4.096 MHz, LCD and meter active 1 Endurance is qualified as per JEDEC Standard 22 Method A117 and measured at −40°C, +25°C, +85°C, and +125°C. 2 Retention lifetime equivalent at junction temperature (TJ) = 85°C as per JEDEC Standard 22 Method A117. Retention lifetime derates with junction temperature. 3 Test carried out with all the I/Os set to a low output level. 4 Delay between power supply valid and execution of first instruction by 8052 core.

Table 7. SPI Master Mode Timing (SPICPHA = 1) Parameters 1 tCORE depends on the clock divider or CD bits of the POWCON SFR (see Table 25); tCORE = 2CD/4.096 MHz. Figure 5. SPI Master Mode Timing (SPICPHA = 1)

Table 8. SPI Master Mode Timing (SPICPHA = 0) Parameters 1 tCORE depends on the clock divider or CD bits of the POWCON SFR (see Table 25); tCORE = 2CD/4.096 MHz. Figure 6. SPI Master Mode Timing (SPICPHA = 0)

Table 9. SPI Slave Mode Timing (SPICPHA = 1) Parameters 1 tCORE depends on the clock divider or CD bits of the POWCON SFR (see Table 25); tCORE = 2CD/4.096 MHz. Figure 7. SPI Slave Mode Timing (SPICPHA = 1)

Table 10. SPI Slave Mode Timing (SPICPHA = 0) Parameters 1 tCORE depends on the clock divider or CD bits of the POWCON SFR (see Table 25); tCORE = 2CD/4.096 MHz. Figure 8. SPI Slave Mode Timing (SPICPHA = 0)

TA = 25°C, unless otherwise noted. soldered in a circuit board for surface-mount packages. Table 12. Thermal Resistance Digital Output Voltage to DGND −0.3 V to VSWOUT + 0.3 V 1 When used with external resistor divider.

47 XTAL1

46 XTAL2

48 INT0

35 FP0

34 FP1

33 FP2

Figure 9. Pin Configuration Table 13. Pin Function Descriptions 1 COM3/FP27 Common Output 3 or LCD Segment Output 27. COM3 is used for LCD backplane. 2 COM2/FP28 Common Output 2 or LCD Segment Output 28. COM2 is used for LCD backplane. 3 COM1 Common Output 1. COM1 is used for LCD backplane. 4 COM0 Common Output 0. COM0 is used for LCD backplane. 5 P1.2/FP25 General-Purpose Digital I/O Port 1.2 or LCD Segment Output 25. 6 P1.3/T2EX/FP24 General-Purpose Digital I/O Port 1.3, Timer 2 Control Input, or LCD Segment Output 24. 7 P1.4/T2/FP23 General-Purpose Digital I/O Port 1.4, Timer 2 Input, or LCD Segment Output 23. 8 P1.5/FP22 General-Purpose Digital I/O Port 1.5 or LCD Segment Output 22. 9 P1.6/FP21 General-Purpose Digital I/O Port 1.6 or LCD Segment Output 21. 10 P1.7/FP20 General-Purpose Digital I/O Port 1.7 or LCD Segment Output 20. 11 P0.1/FP19 General-Purpose Digital I/O Port 0.1 or LCD Segment Output 19. 12 P2.0/FP18 General-Purpose Digital I/O Port 2.0 or LCD Segment Output 18. 13 P2.1/FP17 General-Purpose Digital I/O Port 2.1 or LCD Segment Output 17. 14 P2.2/FP16 General-Purpose Digital I/O Port 2.2 or LCD Segment Output 16. 15 LCDVC Output Port for LCD Levels. This pin should be decoupled with a 470 nF capacitor. 17, 18 LCDVB, LCDVA Output Port for LCD Levels. These pins should be decoupled with a 470 nF capacitor. 35 to 20 FP0 to F15 LCD Segment Output 0 to LCD Segment Output 15. 36 P1.1/TxD General-Purpose Digital I/O Port 1.1 or Transmitter Data Output (Asynchronous). 37 P1.0/RxD General-Purpose Digital I/O Port 1.0 or Receiver Data Input (Asynchronous). 38 P0.7/SS/T1 General-Purpose Digital I/O Port 0.7, Slave Select when SPI is in Slave Mode or Timer 1 Input. 39 P0.6/SCLK/T0 General-Purpose Digital I/O Port 0.6, Clock Output for I2C or SPI Port, or Timer 0 Input. 40 P0.5/MISO General-Purpose Digital I/O Port 0.5 or Data Input for SPI Port. 41 P0.4/MOSI/SDATA General-Purpose Digital I/O Port 0.4, Data Line I2C-Compatible, or Data Output for SPI Port. instantaneous active, reactive, Irms, or apparent power information.

ADE7566/ADE7569/ADE7166/ADE7169 Rev. A | Page 17 of 144 Pin No. Mnemonic Description 43 P0.2/CF1/RTCCAL General-Purpose Digital I/O Port 0.2, Calibration Frequency Logic Output 1, or RTC Calibration Frequency Logic Output. The CF1 logic output gives instantaneous active, reactive, Irms, or apparent power information. The RTCCAL logic output gives access to the calibrated RTC output. 44 SDEN/P2.3 Serial Download Mode Enable or Digital Output Pin P2.3. This pin is used to enable serial download mode through a resistor when pulled low on power-up or reset. On reset, this pin momentarily becomes an input and the status of the pin is sampled. If there is no pull-down resistor in place, the pin momentarily goes high and then user code is executed. If the pin is pulled down on reset, the embedded serial download/debug kernel executes, and this pin remains low during the internal program execution. After reset, this pin can be used as a digital output port pin (P2.3). 45 BCTRL/INT1/P0.0 Digital Input for Battery Control, External Interrupt Input 1, or General-Purpose Digital I/O Port 0.0. This logic input connects VDD or VBAT to VSWOUT internally when set to logic high or logic low, respectively. When left open, the connection between VDD or VBAT and VSWOUT is selected internally. 46 XTAL2 A crystal can be connected across this pin and XTAL1 (see XTAL1 pin description) to provide a clock source for the ADE7566/ADE7569/ADE7166/ADE7169. The XTAL2 pin can drive one CMOS load when an external clock is supplied at XTAL1 or by the gate oscillator circuit. An internal 6 pF capacitor is connected to this pin. 47 XTAL1 An external clock can be provided at this logic input. Alternatively, a parallel resonant AT crystal can be connected across XTAL1 and XTAL2 to provide a clock source for the ADE7566/ADE7569/ADE7166/ADE7169. The clock frequency for specified operation is 32.768 kHz. An internal 6 pF capacitor is connected to this pin. 48 INT0 External Interrupt Input 0. 49, 50 VP, VN Analog Inputs for Voltage Channel. These inputs are fully differential voltage inputs with a maximum differential level of ±400 mV for specified operation. This channel also has an internal PGA. 51 EA This pin is used as an input for emulation. When held high, this input enables the device to fetch code from internal program memory locations. The ADE7566/ADE7569/ADE7166/ADE7169 do not support external code memory. This pin should not be left floating. 52, 53 IP or IPA, IN Analog Inputs for Current Channel. These inputs are fully differential voltage inputs with a maximum differential level of ±400 mV for specified operation. This channel also has an internal PGA. 54 AGND This pin provides the ground reference for the analog circuitry. 55 FP26 or IPB LCD Segment Output 26 (FP26) for ADE7566 and ADE7569 or Analog Inputs for Second Current Channel (IPB) for ADE7166 and ADE7169. This input is fully differential with a maximum differential level of ±400 mV referred to IN for specified operation. This channel also has an internal PGA. 56 RESET Reset Input, Active Low. 57 REFIN/OUT This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of 1.2 V ± 0.1% and a typical temperature coefficient of 50 ppm/°C maximum. This pin should be decoupled with a 1 μF capacitor in parallel with a ceramic 100 nF capacitor. 58 VBAT Power Supply Input from the Battery with a 2.4 V to 2.7 V Range. This pin is connected internally to VDD when the battery is selected as the power supply for the ADE7566/ADE7569/ADE7166/ADE7169. 59 VINTA This pin provides access to the on-chip 2.5 V analog LDO. No external active circuitry should be connected to this pin. This pin should be decoupled with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor. 60 VDD 3.3 V Power Supply Input from the Regulator. This pin is connected internally to VDD when the regulator is selected as the power supply for the ADE7566/ADE7569/ADE7166/ADE7169. This pin should be decoupled with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor. 61 VSWOUT 3.3 V Power Supply Output. This pin provides the supply voltage for the LDOs and internal circuitry of the ADE7566/ADE7569/ADE7166/ADE7169. This pin should be decoupled with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor. 62 VINTD This pin provides access to the on-chip 2.5 V digital LDO. No external active circuitry should be connected to this pin. This pin should be decoupled with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor. 63 DGND This pin provides the ground reference for the digital circuitry. 64 VDCIN Analog Input for DC Voltage Monitoring. The maximum input voltage on this pin is VSWOUT with respect to AGND. This pin is used to monitor the preregulated dc voltage.

ADE7566/ADE7569/ADE7166/ADE7169 Rev. A | Page 22 of 144 TERMINOLOGY For the dc PSR measurement, a reading at nominal supplies (3.3 V) is taken. A second reading is obtained with the same input signal levels when the supplies are varied ±5%. Any error introduced is again expressed as a percentage of the reading. Measurement Error The error associated with the energy measurement made by the ADE7566/ADE7569/ADE7166/ADE7169 is defined by the following formula: ADC Offset Error % 100×⎟⎟ ⎛ −= Energy True Energy TrueRegisterEnergyErrorPercentage ADC offset error is the dc offset associated with the analog inputs to the ADCs. It means that, with the analog inputs connected to AGND, the ADCs still see a dc analog input signal. The magnitude of the offset depends on the gain and input range selection (see the Phase Error Between Channels The digital integrator and the high-pass filter (HPF) in the current channel have a nonideal phase response. To offset this phase response and equalize the phase response between channels, two phase correction networks are placed in the current channel: one for the digital integrator and the other for the HPF. The phase correction networks correct the phase response of the corresponding component and ensure a phase match between current channel and voltage channel to within ±0.1° over a range of 45 Hz to 65 Hz with the digital integrator off. With the digital integrator on, the phase is corrected to within ±0.4° over a range of 45 Hz to 65 Hz. Typical Performance Characteristics section). However, when HPF1 is switched on, the offset is removed from the current channel, and the power calculation is not affected by this offset. The offsets can be removed by performing an offset calibration (see the Analog Inputs section). Gain Error Gain error is the difference between the measured ADC output code (minus the offset) and the ideal output code (see the Current Channel ADC section and the Voltage Channel ADC section). It is measured for each of the gain settings on the current channel (1, 2, 4, 8, and 16). The difference is expressed as a percentage of the ideal code. Power Supply Rejection (PSR) PSR quantifies the ADE7566/ADE7569/ADE7166/ADE7169 measurement error as a percentage of reading when the power supplies are varied. For the ac PSR measurement, a reading at nominal supplies (3.3 V) is taken. A second reading is obtained with the same input signal levels when an ac (100 mV rms/120 Hz) signal is introduced onto the supplies. Any error introduced by this ac signal is expressed as a percentage of reading (see the Measurement Error definition).

ADE7566/ADE7569/ADE7166/ADE7169 Rev. A | Page 23 of 144 SFR MAPPING Table 14. Mnemonic Address Details INTPR 0xFF Table 16 SCRATCH4 0xFE Table 24 SCRATCH3 0xFD Table 23 SCRATCH2 0xFC Table 22 SCRATCH1 0xFB Table 21 BATVTH 0xFA Table 51 STRBPER 0xF9 Table 48 IPSMF 0xF8 Table 17 TEMPCAL 0xF7 Table 127 RTCCOMP 0xF6 Table 126 BATPR 0xF5 Table 18 PERIPH 0xF4 Table 19 DIFFPROG 0xF3 Table 49 B 0xF0 Table 55 VDCINADC 0xEF Table 52 LCDSEGE2 0xED Table 88 IPSME 0xEC Table 20 SPISTAT 0xEA Table 142 SPI2CSTAT 0xEA Table 147 SPIMOD2 0xE9 Table 141 I2CADR 0xE9 Table 146 SPIMOD1 0xE8 Table 140 I2CMOD 0xE8 Table 145 WAV2H 0xE7 Table 30 WAV2M 0xE6 Table 30 WAV2L 0xE5 Table 30 WAV1H 0xE4 Table 30 WAV1M 0xE3 Table 30 WAV1L 0xE2 Table 30 ACC 0xE0 Table 55 BATADC 0xDF Table 53 MIRQSTH 0xDE Table 41 MIRQSTM 0xDD Table 40 MIRQSTL 0xDC Table 39 MIRQENH 0xDB Table 44 MIRQENM 0xDA Table 43 MIRQENL 0xD9 Table 42 ADCGO 0xD8 Table 50 TEMPADC 0xD7 Table 54 IRMSH 0xD6 Table 30 IRMSM 0xD5 Table 30 IRMSL 0xD4 Table 30 VRMSH 0xD3 Table 30 VRMSM 0xD2 Table 30 VRMSL 0xD1 Table 30 Mnemonic Address Details PSW 0xD0 Table 56 TH2 0xCD Table 110 TL2 0xCC Table 111 RCAP2H 0xCB Table 112 RCAP2L 0xCA Table 113 T2CON 0xC8 Table 105 EADRH 0xC7 Table 100 EADRL 0xC6 Table 99 POWCON 0xC5 Table 25 KYREG 0xC1 Table 116 WDCON 0xC0 Table 75 PROTR 0xBF Table 98 PROTB1 0xBE Table 97 PROTB0 0xBD Table 96 EDATA 0xBC Table 95 PROTKY 0xBB Table 94 FLSHKY 0xBA Table 93 ECON 0xB9 Table 92 IP 0xB8 Table 69 PINMAP2 0xB4 Table 152 PINMAP1 0xB3 Table 151 PINMAP0 0xB2 Table 150 LCDCONY 0xB1 Table 81 CFG 0xAF Table 62 LCDDAT 0xAE Table 87 LCDPTR 0xAC Table 86 IEIP2 0xA9 Table 70 IE 0xA8 Table 68 DPCON 0xA7 Table 66 INTVAL 0xA6 Table 125 HOUR 0xA5 Table 124 MIN 0xA4 Table 123 SEC 0xA3 Table 122 HTHSEC 0xA2 Table 121 TIMECON 0xA1 Table 120 P2 0xA0 Table 155 EPCFG 0x9F Table 149 SBAUDT 0x9E Table 134 SBAUDF 0x9D Table 135 LCDCONX 0x9C Table 79 SPI2CRx 0x9B Table 139 SPI2CTx 0x9A Table 138 SBUF 0x99 Table 133 SCON 0x98 Table 132 LCDSEGE 0x97 Table 85

ADE7566/ADE7569/ADE7166/ADE7169 Rev. A | Page 24 of 144 Mnemonic Address Details LCDCLK 0x96 Table 82 LCDCON 0x95 Table 78 MDATH 0x94 Table 30 MDATM 0x93 Table 30 MDATL 0x92 Table 30 MADDPT 0x91 Table 30 P1 0x90 Table 154 TH1 0x8D Table 108 TH0 0x8C Table 106 Mnemonic Address Details TL1 0x8B Table 109 TL0 0x8A Table 107 TMOD 0x89 Table 103 TCON 0x88 Table 104 PCON 0x87 Table 57 DPH 0x83 Table 59 DPL 0x82 Table 58 SP 0x81 Table 61 P0 0x80 Table 153

Table 15. Power Management SFRs 0xEC R/W IPSME Power Management Interrupt Enable. See Table 20. 0xF5 R/W BATPR Battery Switchover Configuration. See Table 18. 0xF8 R/W IPSMF Power Management Interrupt Flag. See Table 17. 0xFF R/W INTPR Interrupt Pins Configuration. See Table 16. 0xF4 R/W PERIPH Peripheral Configuration SFR. See Table 19. 0xC5 R/W POWCON Power Control. See Table 25. 0xFB R/W SCRATCH1 Scratch Pad 1. See Table 21. 0xFC R/W SCRATCH2 Scratch Pad 2. See Table 22. 0xFD R/W SCRATCH3 Scratch Pad 3. See Table 23. 0xFE R/W SCRATCH4 Scratch Pad 4. See Table 24. Table 16. Interrupt Pins Configuration SFR (INTPR, 0xFF) output on the P0.2/CF1/RTCCAL pin. Sets RTC calibration output frequency and calibration window.

4 Reserved

Controls the function of INT1. Controls the function of INT0.

0 INT0 input disabled

0 INT0PRG 0

1 INT0 input enabled

Table 17. Power Management Interrupt Flag SFR (IPSMF, 0xF8) 7 0xFF FPSR 0 Power Supply Restored Interrupt Flag. Set when the VDD power supply has been restored. This occurs when the source of VSWOUT changes from VBAT to VDD. 6 0xFE FPSM 0 PSM Interrupt Flag. Set when an enabled PSM interrupt condition occurs. 5 0xFD FSAG 0 Voltage SAG Interrupt Flag. Set when an ADE energy measurement SAG condition occurs. 4 0xFC RESERVED 0 This bit must be kept cleared for proper operation. 2 0xFA FBAT 0 VBAT Monitor Interrupt Flag. Set when VBAT falls below BATVTH or when VBAT measurement is ready. 1 0xF9 FBSO 0 Battery Switchover Interrupt Flag. Set when VSWOUT switches from VDD to VBAT. 0 0xF8 FVDCIN 0 VDCIN Monitor Interrupt Flag. Set when VDCIN falls below 1.2 V. Table 18. Battery Switchover Configuration SFR (BATPR, 0xF5) 7 to 2 Reserved 00 These bits must be kept to 0 for proper operation. Control Bits for Battery Switchover.

00 Battery switchover enabled on low VDD

01 Battery switchover enabled on low VDD and low VDCIN

Table 19. Peripheral Configuration SFR (PERIPH, 0xF4) 7 RXFLAG 0 If set, indicates that an Rx edge event triggered wake-up from PSM2. 6 VSWSOURCE 1 Indicates the power supply that is internally connected to VSWOUT (0 VSWOUT = VBAT, 1 VSWOUT = VDD). 5 VDD_OK 1 If set, indicates that VDD power supply is ready for operation. the Start ADC Measurement SFR (ADCGO, 0xD8) to acknowledge the fault and clear the PLL_FLT bit. 2 Reserved 0 This bit should be kept to zero. Controls the function of the P1.0/RxD pin.

00 GPIO

01 RxD with wake-up disabled

11 RxD with wake-up enabled

Table 20. Power Management Interrupt Enable SFR (IPSME, 0xEC) 7 EPSR 0 Enables a PSM interrupt when the power supply restored flag (FPSR) is set. 5 ESAG 0 Enables a PSM interrupt when the voltage SAG flag (FSAG) is set. 4 RESERVED 0 This bit must be kept cleared for proper operation. 3 EVADC 0 Enables a PSM interrupt when the VADC monitor flag (FVADC) is set. 2 EBAT 0 Enables a PSM interrupt when the VBAT monitor flag (FBAT) is set. 1 EBSO 0 Enables a PSM interrupt when the battery switchover flag (FBSO) is set. 0 EVDCIN 0 Enables a PSM interrupt when the VDCIN monitor flag (FVDCIN) is set. Table 21. Scratch Pad 1 SFR (SCRATCH1, 0xFB) 7 to 0 SCRATCH1 0 Value can be written/read in this register. This value is maintained in all the power saving modes.

Table 22. Scratch Pad 2 SFR (SCRATCH2, 0xFC) 7 to 0 SCRATCH2 0 Value can be written/read in this register. This value is maintained in all the power saving modes. Table 23. Scratch Pad 3 SFR (SCRATCH3, 0xFD) 7 to 0 SCRATCH3 0 Value can be written/read in this register. This value is maintained in all the power saving modes. Table 24. Scratch Pad 4 SFR (SCRATCH4, 0xFE) 7 to 0 SCRATCH4 0 Value can be written/read in this register. This value is maintained in all the power saving modes. PLL reset and, therefore, need to be set correctly in these situations. Table 25. Power Control SFR (POWCON, 0xC5) metering functions are not needed in PSM0. 5 RESERVED 0 This bit should be kept at 0 for proper operation. 4 COREOFF 0 Set this bit to shut down the core and enter PSM2 if in the PSM1 operating mode. Controls the core clock frequency, fCORE. fCORE = 4.096 MHz/2CD.

SWOUT changes from VDD to VBAT, indicating battery switchover. PSM interrupt (see Table 20). and cleared when VSWOUT is connected to VBAT. (IPSME, 0xEC) enables this event to generate a PSM interrupt. Table 50. The FVDCIN flag indicates when a VDCIN measurement details on how VDCIN is measured. Table 53. See the Battery 0xEC) enables this event to generate a PSM interrupt. (IPSME, 0xEC) enables this event to generate a PSM interrupt.

In PSM0, normal operating mode, VSWOUT is connected to VDD. reset or software reset, is 1.024 MHz. power-on reset or software reset, is 1.024 MHz.

2.5 V digital and analog circuitry powered through VINTA and VINTD

• The RAM in the MCU is no longer valid.
• The program counter for the 8052, also held in volatile memory, becomes invalid when the 2.5 V supply is shut down. Therefore, the program does not resume from where it left off but always starts from the power-on reset vector when the ADE7566/ADE7569/ADE7166/ADE7169 exit PSM2. The 3.3 V peripherals (temperature ADC, VDCIN ADC, RTC, and LCD) are active in PSM2. They can be enabled or disabled to reduce power consumption and are configured for PSM2 operation when the MCU core is active (see Table 28 for more information about the individual peripherals and their PSM2 configuration). The ADE7566/ADE7569/ADE7166/ADE7169 remain in PSM2 until an event occurs to wake them up. In PSM2, the ADE7566/ADE7569/ADE7166/ADE7169 provide four scratch pad RAM SFRs that are maintained during this mode. These SFRs can be used to save data from PSM0 or PSM1 when entering PSM2 (see Table 21 to Table 24). In PSM2, the ADE7566/ADE7569/ADE7166/ADE7169 maintain some SFRs (see Table 27). The SFRs that are not listed in this table should be restored when the part enters PSM0 or PSM1 from PSM2.

Table 27. SFR Maintained in PSM2

3.3 V PERIPHERALS AND WAKE-UP EVENTS

Table 28. The interrupt flag associated with Table 28. 3.3 V Peripherals and Wake-Up Events Table 20. The FVDCIN flag needs to be cleared prior to entering PSM2 mode. (PERIPH, 0xF4), is set to indicate that VSWOUT is connected to VDD. serviced and acknowledged prior to entering PSM2 mode. acknowledged prior to entering PSM2 mode. (PINMAP2, 0xB4) to decrease current consumption. The interrupts can be enabled/disabled. INT0 INT0PRG = 1 IE0 The edge of the interrupt is selected by Bit IT0 in the TCON register. IE1 The edge of the interrupt is selected by Bit IT1 in the TCON register. ADE7166/ADE7169 is in PSM2, it wakes up to PSM1. Scratch Pad The four SCRATCHx registers remain intact in PSM2.

ADE7566/ADE7569/ADE7166/ADE7169 Rev. A | Page 35 of 144 TRANSITIONING BETWEEN OPERATING MODES The operating mode of the ADE7566/ADE7569/ADE7166/ ADE7169 is determined by the power supply connected to VSWOUT. Therefore, changes in the power supply, such as when VSWOUT switches from VDD to VBAT or when VSWOUT switches to VDD, alter the operating mode. This section describes events that change the operating mode. Automatic Battery Switchover (PSM0 to PSM1) If any of the enabled battery switchover events occur (see the Battery Switchover section), VSWOUT switches to VBAT. This switchover results in a transition from the PSM0 to PSM1 operating mode. When battery switchover occurs, the analog circuitry used in the ADE energy measurement DSP is disabled. To reduce power consumption, the user code can initiate a transition to PSM2. Entering Sleep Mode (PSM1 to PSM2) To reduce power consumption when VSWOUT is connected to VBAT, user code can initiate sleep mode, PSM2, by setting Bit 4 in the Power Control SFR (POWCON, 0xC5) to shut down the MCU core. Events capable of waking the MCU can be enabled (see the 3.3 V Peripherals and Wake-Up Events section). Servicing Wake-Up Events (PSM2 to PSM1) The ADE7566/ADE7569/ADE7166/ADE7169 may need to wake up from PSM2 to service wake-up events (see the 3.3 V Peripherals and W ake-Up Events section). PSM1 code execution begins at the power-on reset vector. After servicing the wake-up event, the ADE7566/ADE7569/ADE7166/ ADE7169 can return to PSM2 by setting Bit 4 in the Power Control SFR (POWCON, 0xC5) to shut down the MCU core. Automatic Switch to VDD (PSM2 to PSM0) If the conditions to switch VSWOUT from VBAT to VDD occur (see the Battery Switchover section), the operating mode switches to PSM0. When this switch occurs, the MCU core and the analog circuitry used in the ADE energy measurement DSP automatically restart. PSM0 code execution begins at the power- on reset vector. Automatic Switch to VDD (PSM1 to PSM0) If the conditions to switch VSWOUT from VBAT to VDD occur (see the Battery Switchover section), the operating mode switches to PSM0. When this switch occurs, the analog circuitry used in the ADE energy measurement DSP automatically restarts. Note that code execution continues normally. A software reset can be performed to start PSM0 code execution at the power-on reset vector. USING THE POWER MANAGEMENT FEATURES Because program flow is different for each operating mode, the status of VSWOUT must be known at all times. The VSWSOURCE bit in the Peripheral Configuration SFR (PERIPH, 0xF4) indicates what VSWOUT is connected to (see Table 19). This bit can be used to control program flow on wake-up. Because code execution always starts at the power-on reset vector, Bit 6 of the PERIPH SRF can be tested to determine which power supply is being used and to branch to normal code execution or to wake up event code execution. Power supply events can also occur when the MCU core is active. To be aware of the events that change what V SWOUT is connected to, use the following guidelines:

• Enable the battery switchover interrupt (EBSO) if VSWOUT = VDD at power-up.
• Enable the power supply restored interrupt (EPSR) if VSWOUT = VBAT at power-up. An early warning that battery switchover is about to occur is provided by SAG detection and possibly low VDCIN detection (see the Battery Switchover section). For a user-controlled battery switchover, enable automatic battery switchover on low V DD only. Then, enable the low VDCIN event to generate the PSM interrupt. When a low VDCIN event occurs, start data backup. Upon completion of the data backup, enable battery switchover on low VDCIN. Battery switchover occurs 30 ms later.

Figure 37. Transitioning Between Operating Modes

and data SFR registers for the majority of energy measurements. as pointers to the energy measurement internal registers. the SFR when the SFR is read. byte results in reading the data from the previous latched sample. Table 29. Energy Measurement Pointer Address SFR MDATM SFR and MDATH SFR contents are ignored. or write to these registers can take place. SFRs are transferred to another SFR. register located at 0x16 into the data pointer is shown below.

Table 30. Energy Measurement SFRs 0x91 R/W MADDPT Energy Measurement Pointer Address. 0x92 R/W MDATL Energy Measurement Pointer Data Lowest Significant Byte. 0x93 R/W MDATM Energy Measurement Pointer Data Middle Byte. 0x94 R/W MDATH Energy Measurement Pointer Data Most Significant Byte. 0xD1 R VRMSL Vrms Measurement Lowest Significant Byte. 0xD2 R VRMSM Vrms Measurement Middle Byte. 0xD3 R VRMSH Vrms Measurement Most Significant Byte. 0xD4 R IRMSL Irms Measurement Lowest Significant Byte. 0xD5 R IRMSM Irms Measurement Middle Byte. 0xD6 R IRMSH Irms Measurement Most Significant Byte. 0xD9 R/W MIRQENL Energy Measurement Interrupt Enable Lowest Significant Byte. 0xDA R/W MIRQENM Energy Measurement Interrupt Enable Middle Byte. 0xDB R/W MIRQENH Energy Measurement Interrupt Enable Most Significant Byte. 0xDC R/W MIRQSTL Energy Measurement Interrupt Status Lowest Significant Byte. 0xDD R/W MIRQSTM Energy Measurement Interrupt Status Middle Byte. 0xDE R/W MIRQSTH Energy Measurement Interrupt Status Most Significant Byte. 0xE2 R WAV1L Selection 1 Sample Lowest Significant Byte. 0xE3 R WAV1M Selection 1 Sample Middle Byte. 0xE4 R WAV1H Selection 1 Sample Most Significant Byte. 0xE5 R WAV2L Selection 2 Sample Lowest Significant Byte. 0xE6 R WAV2M Selection 2 Sample Middle Byte. 0xE7 R WAV2H Selection 2 Sample Most Significant Byte. Figure 38. ADE7566 and ADE7569 Energy Metering Block Diagram

Figure 39. ADE7166 and ADE7169 Energy Metering Block Diagram

Table 31. Energy Measurement Register List 0x01 WATTHR R 24 S 0 Reads Wh accumulator without reset. 0x02 RWATTHR R 24 S 0 Reads Wh accumulator with reset. 0x03 LWATTHR R 24 S 0 Reads Wh accumulator synchronous to line cycle. 0x04 VARHR1 R 24 S 0 Reads VARh accumulator without reset. 0x05 RVARHR1 R 24 S 0 Reads VARh accumulator with reset. 0x06 LVARHR1 R 24 S 0 Reads VARh accumulator synchronous to line cycle. MODE2 register (0x0C) is set, this register accumulates Irms. 0x0A PER_FREQ R 16 U 0 Reads line period or frequency register depending on Mode2 register. 0x0B MODE1 R/W 8 U 0x06 Sets basic configuration of energy measurement (see Table 32). 0x0C MODE2 R/W 8 U 0x40 Sets basic configuration of energy measurement (see Table 33). 0x0E NLMODE R/W 8 U 0 Sets level of energy no-load thresholds (see Table 35). 0x10 PHCAL R/W 8 S 0x40 Sets phase calibration register (see the Phase Compensation section). Voltage SAG Detection section). 0x17 IPEAK R 24 U 0 Reads current peak level without reset (see the Peak Detection section). 0x18 RSTIPEAK R 24 U 0 Reads current peak level with reset (see the Peak Detection section). 0x1A RSTVPEAK R 24 U 0 Reads voltage peak level with reset (see the Peak Detection section). 0x1B GAIN R/W 8 U 0 Sets PGA gain of analog inputs (see Table 37). 0x1C IBGAIN2 R/W 12 S 0 Sets matching gain for IPB current input. 0x1D WGAIN R/W 12 S 0 Sets watt gain register. 0x1E VARGAIN1 R/W 12 S 0 Sets VAR gain register. 0x1F VAGAIN R/W 12 S 0 Sets VA gain register. 0x20 WATTOS R/W 16 S 0 Sets watt offset register. 0x21 VAROS1 R/W 16 S 0 Sets VAR offset register. 0x22 IRMSOS R/W 12 S 0 Sets current rms offset register. 0x23 VRMSOS R/W 12 S 0 Sets voltage rms offset register. 0x24 WDIV R/W 8 U 0 Sets watt energy scaling register. 0x25 VARDIV R/W 8 U 0 Sets VAR energy scaling register.

0x26 VADIV R/W 8 U 0 Sets VA energy scaling register. 0x27 CF1NUM R/W 16 U 0 Sets CF1 numerator register. 0x28 CF1DEN R/W 16 U 0x003F Sets CF1 denominator register. 0x29 CF2NUM R/W 16 U 0 Sets CF2 numerator register. 0x2A CF2DEN R/W 16 U 0x003F Sets CF2 denominator register. 0x3B Reserved 0 This register must be kept at its default value for proper operation. 0x3C Reserved 0x0300 This register must be kept at its default value for proper operation. 0x3D CALMODE2 R/W 8 U 0 For ADE7166/ADE7169 only. Set Calibration mode. 0x3E Reserved 0 This register must be kept at its default value for proper operation. 0x3F Reserved 0 This register must be kept at its default value for proper operation. 1 This function is not available in the ADE7566 and ADE7166. 2 This function is not available in the ADE7566 and ADE7569. Table 32. MODE1 Register (0x0B) 7 SWRST 0 Setting this bit resets all of the energy measurement registers to their default values. 6 DISZXLPF 0 Setting this bit disables the zero-crossing low-pass filter. 5 INTE 0 Setting this bit enables the digital integrator for use with a di/dt sensor. 4 SWAPBITS 0 Setting this bit swaps CH1 ADC and CH2 ADC. 3 PWRDN 0 Setting this bit powers down voltage and current ADCs. 2 DISCF2 1 Setting this bit disables Frequency Output CF2. 1 DISCF1 1 Setting this bit disables Frequency Output CF1. 0 DISHPF 0 Setting this bit disables the HPFs in voltage and current channels. Table 33. MODE2 Register (0x0C) Configuration Bits for CF2 Output. 00 CF2 frequency is proportional to active power. 1x CF2 frequency is proportional to apparent power or Irms. 5 to 4 CF1SEL[1:0] 00 Configuration Bits for CF1 Output. 00 CF1 frequency is proportional to active power. 1x CF1 frequency is proportional to apparent power or Irms.

3 VARMSCFCON 0 Configuration Bits for Apparent Power or Irms for CF1, CF2 Outputs, and VA Accumulation

proportional to Irms and vice versa. 0 If CF1SEL[1:0] = 1x, CF1 is proportional to VA. If CF2SEL[1:0] = 1x, CF2 is proportional to VA. 1 If CF1SEL[1:0] = 1x, CF1 is proportional to Irms. If CF2SEL[1:0] = 1x, CF2 is proportional to Irms. 2 ZXRMS 0 Logic 1 enables update of rms values synchronously to Voltage ZX.

1 FREQSEL Configuration Bits to Select Period or Frequency Measurement for PER_FREQ Register

0 PER_FREQ register holds a period measurement. 1 PER_FREQ register holds a frequency measurement. 0 WAVEN 0 When set, the waveform sampling mode is enabled. 1 This function is not available in the ADE7566 and ADE7166. Table 34. WAVMODE Register (0x0D) 7 to 5 WAV2SEL[2:0] 000 Waveform 2 Selection for Samples Mode.

000 Current

001 Voltage

010 Active power multiplier output

011 Reactive power multiplier output1

100 VA multiplier output

101 Irms LPF output

4 to 2 WAV1SEL[2:0] 000 Waveform 1 Selection for Samples Mode.

101 Irms LPF output (low 24-bit)

1 to 0 DTRT[1:0] 00 Waveform Samples Output Data Rate. 1 This function is not available in the ADE7566 and ADE7166. Table 35. NLMODE Register (0x0E) 7 DISVARCMP1 0 Setting this bit disables fundamental VAR gain compensation over line frequency. 5 to 4 VANOLOAD[1:0] 00 Apparent Power No-Load Threshold.

00 No-load detection disabled

3 to 2 VARNOLOAD[1:0]1 00 Reactive Power No-Load Threshold. 1 to 0 APNOLOAD[1:0] 00 Active Power No-Load Threshold. 1 This function is not available in the ADE7566 and ADE7166. Table 36. ACCMODE Register (0x0F) 7 ICHANNEL1 0 This bit indicates the current channel used to measure energy in antitampering mode. 6 FAULTSIGN1 0 Configuration bit to select the event that triggers a fault interrupt. interrupt occurs when reactive power changes from negative to positive. occurs when active power changes from negative to positive. 3 ABSVARM2 0 Logic 1 enables absolute value accumulation of reactive power in energy register and pulse output. 1 POAM 0 Logic 1 enables positive-only accumulation of active power in energy register and pulse output. 0 ABSAM 0 Logic 1 enables absolute value accumulation of active power in energy register and pulse output. 1 This function is not available in the ADE7566 and ADE7569. 2 This function is not available in the ADE7566 and ADE7166. Table 37. GAIN Register (0x1B) 7 to 5 PGA2[2:0] 000 These bits define the voltage channel input gain.

000 Gain = 1

001 Gain = 2

010 Gain = 4

011 Gain = 8

100 Gain = 16

3 CFSIGN_OPT 0 This bit defines where the CF change of sign detection (APSIGN or VARSIGN) is implemented.

0 Filtered power signal

1 On a per CF pulse basis

2 to 0 PGA1[2:0] 000 These bits defi ne the current channel input gain.

000 Gain = 1 1

1 This gain is not recommended in the ADE7166 and ADE7169 because it can create an overranging of the ADC when both current inputs are in opposite phase. Table 38. CALMODE Register (0x3D)1 7 to 6 Reserved 0 These bits should be kept cleared for proper operation. 5 to 4 SEL_I_CH[1:0] 0 These bits define the current channel used for energy measurements.

00 Current channel automatically selected by the tampering condition

01 Current channel connected to IPA

10 Current channel connected to IPB

11 Current channel automatically selected by the tampering condition

3 V_CH_SHORT 0 Logic one short voltage channel to ground. 2 I_CH_SHORT 0 Logic one short Current channels to ground. 1 This register is not available in the ADE7566 and ADE7569. Table 39. Interrupt Status 1 SFR (MIRQSTL, 0xDC) automatically cleared when all of the enabled ADE status flags are cleared. 5 FAULTSIGN 1 Logic 1 indicates that the fault mode has changed a ccording to the configuration of the ACCMODE register. 4 VARSIGN 2 Logic 1 indicates that the reactive power sign has changed according to the configuration of the ACCMODE register. 3 APSIGN Logic 1 indicates that the active power sign has changed according to the configuration of the ACCMODE register. used to reflect the part entering the Irms no-load mode. 1 RNOLOAD 2 Logic 1 indicates that an interrupt has been caused by reactive power no-load detected. 0 APNOLOAD Logic 1 indicates that an interrupt has been caused by active power no-load detected. 1 This function is not available in the ADE7566 and ADE7569. 2 This function is not available in the ADE7566 and ADE7166. Table 40. Interrupt Status 2 SFR (MIRQSTM, 0xDD) clearing Bit 2 of the MODE1 register. clearing Bit 1 of the MODE1 register. 5 VAEOF Logic 1 indicates that the VAHR register has overflowed. 4 REOF 1 Logic 1 indicates that the VARHR register has overflowed. 3 AEOF Logic 1 indicates that the WATTHR register has overflowed. 2 VAEHF Logic 1 indicates that the VAHR register is half full. 1 REHF 1 Logic 1 indicates that the VARHR register is half full. 0 AEHF Logic 1 indicates that the WATTHR register is half full. 1 This function is not available in the ADE7566 and ADE7166.

Table 41. Interrupt Status 3 SFR (MIRQSTH, 0xDE) 7 RESET Indicates the end of a reset (for both software and hardware reset). 5 WFSM Logic 1 indicates that new data is present in the waveform registers (Address 0xE2 to Address 0xE7).

4 PKI Logic 1 indicates that current channel has exceeded the IPKLVL value

3 PKV Logic 1 indicates that voltage channel has exceeded the VPKLVL value. 2 CYCEND Logic 1 indicates the end of the energy accumulation over an integer number of half-line cycles. 1 ZXTO Logic 1 indicates that no zero crossing on the line voltage happened for the last ZXTOUT half-line cycles. 0 ZX Logic 1 indicates detection of a zero crossing in the voltage channel. Table 42. Interrupt Enable 1 SFR (MIRQENL, 0xD9) 5 FAULTSIGN 1 When this bit is set, the FAULTSIGN bit set creates a pending ADE interrupt to the 8052 core. 4 VARSIGN 2 When this bit is set, the VARSIGN flag set creates a pending ADE interrupt to the 8052 core. 3 APSIGN When this bit is set, the APSIGN flag se t creates a pending ADE interrupt to the 8052 core. 2 VANOLOAD When this bit is set, the VANOLOAD flag set creates a pending ADE interrupt to the 8052 core. 1 RNOLOAD 2 When this bit is set, the RNOLOAD flag set creates a pending ADE interrupt to the 8052 core. 0 APNOLOAD When this bit is set, the APNOLOAD flag set creates a pending ADE interrupt to the 8052 core. 1 This function is not available in the ADE7566 and ADE7569. 2 This function is not available in the ADE7566 and ADE7166. Table 43. Interrupt Enable 2 SFR (MIRQENM, 0xDA) 7 CF2 When this bit is set, a CF2 pulse creates a pending ADE interrupt to the 8052 core. 6 CF1 When this bit is set, a CF1 pulse creates a pending ADE interrupt to the 8052 core. 5 VAEOF When this bit is set, the VAEOF flag se t creates a pending ADE interrupt to the 8052 core. 4 REOF 1 When this bit is set, the REOF flag set cr eates a pending ADE interrupt to the 8052 core. 3 AEOF When this bit is set, the AEOF flag set creates a pending ADE interrupt to the 8052 core. 2 VAEHF When this bit is set, the VAEHF flag se t creates a pending ADE interrupt to the 8052 core. 1 REHF 1 When this bit is set, the REHF flag set cr eates a pending ADE interrupt to the 8052 core. 0 AEHF When this bit is set, the AEHF flag set creates a pending ADE interrupt to the 8052 core. 1 This function is not available in the ADE7566 and ADE7166.

ADE7566/ADE7569/ADE7166/ADE7169 Rev. A | Page 50 of 144 Voltage Channel ADC Figure 47 shows the ADC and signal processing chain for the voltage channel. In waveform sampling mode, the ADC outputs a signed, twos complement, 24-bit data-word at a maximum of 25.6 kSPS (MCLK/160). The ADC produces an output code that is approximately between 0x28F5 (+10,485d) and 0xD70B (−10,485d). Channel Sampling The waveform samples of the current ADC and voltage ADC can also be routed to the waveform registers to be read by the MCU core. The active, reactive, apparent power, and energy calculation remain uninterrupted during waveform sampling. When in waveform sampling mode, one of four output sample rates can be chosen by using the DTRT[1:0] bits of the W AVMODE register (see Table 34). The output sample rate can be 25.6 kSPS, 12.8 kSPS, 6.4 kSPS, or 3.2 kSPS. If the WFSM enable bit is set in the Interrupt Enable 3 SFR (MIRQENH, 0xDB), the 8052 core has a pending ADE interrupt. The sampled signals selected in the W AVMODE register are latched into the Waveform SFRs when the waveform high byte (W AV1H or W AV2H) is read. The ADE interrupt stays active until the WFSM status bit is cleared (see the Energy Measurement Interrupts section). FAULT DETECTION1 The ADE7166/ADE7169 incorporate a fault detection scheme that warns of fault conditions and allows the ADE7166/ADE7169 to continue accurate measurement during a fault event. The ADE7166/ADE7169 do this by continuously monitoring both current inputs (I PA and IPB). For ease of understanding, these currents are referred to as phase and neutral (return) currents. In the ADE7166/ADE7169, a fault condition is defined when the difference between IPA and IPB is greater than 6.25% of the active channel. If a fault condition is detected and the inactive channel is larger than the active channel, the ADE7166/ADE7169 automatically switch current measurement to the inactive channel. During a fault, the active, reactive, current rms and apparent powers are generated using the larger of the two currents. On power-up, I PA is the current input selected for active, reactive, and apparent power and Irms calculations. To prevent false alarm, averaging is done for the fault detection, and a fault condition is detected approximately one second after the event. The fault detection is automatically disabled when the voltage signal is less than 0.3% of the full-scale input range. This eliminates false detection of a fault due to noise at light loads. Because the ADE7166/ADE7169 look for a difference between the voltage signals on IPA and IPB, it is important that both current transducers be closely matched. Channel Selection Indication The current channel selected for measurement is indicated by Bit 7 (ICHANNEL) in the ACCMODE Register (0x0F). When this bit is cleared, IPA is selected and, when it is set, IPB is selected. The ADE7166/ADE7169 automatically switch from one channel to the other and report the channel configuration in the 1 This function is not available in the ADE7566 and ADE7569. ACCMODE Register (0x0F). The current channel selected for measurement can also be forced. Setting the SEL_I_CH[1:0] bits in the CALMODE Register (0x3D) selects IPA and IPB, respectively. When both bits are cleared or set, the current channel used for measurement is selected automatically based on the fault detection. Fault Indication The ADE7166/ADE7169 provide an indication of the part going in or out of a fault condition. The new fault condition is indicated by the FAULTSIGN flag (Bit 5) in the Interrupt Status 1 SFR (MIRQSTL, 0xDC). When FAULTSIGN bit (Bit 6) of the ACCMODE Register (0x0F) is cleared, the FAULTSIGN flag in the Interrupt Status 1 SFR (MIRQSTL, 0xDC) is set when the part is a entering fault condition or a normal condition. When the FAULTSIGN bit is set in the Interrupt Enable 1 SFR (MIRQENL, 0xD9), and the FAULTSIGN flag in the Interrupt Status 1 SFR (MIRQSTL, 0xDC) is set, the 8052 core has a pending ADE interrupt. Fault with Active Input Greater Than Inactive Input If IPA is the active current input (that is, being used for billing), and the voltage signal on IPB (inactive input) falls below 93.75% of IPA, and the FAULTSIGN bit (Bit 6) of ACCMODE Register (0x0F) is cleared, the FAULTSIGN flag in the Interrupt Status 1 SFR (MIRQSTL, 0xDC) is set. Both analog inputs are filtered and averaged to prevent false triggering of this logic output. As a consequence of the filtering, there is a time delay of approximately three seconds on the logic output after the fault event. The FAULTSIGN flag is independent of any activity. Because IPA is the active input and it is still greater than IPB, billing is maintained on IPA; that is, no swap to the IPB input occurs. IPA remains the active input. Fault with Inactive Input Greater Than Active Input If the difference between IPB, the inactive input, and IPA, the active input (that is, being used for billing), becomes greater than 6.25% of I PB, and the FAULTSIGN bit (Bit 6) of ACCMODE Register (0x0F) is cleared, the FAULTSIGN flag in the Interrupt Status 1 SFR (MIRQSTL, 0xDC) is set. The analog input IPB becomes the active input. Again, a time constant of about three seconds is associated with this swap. IPA does not swap back to the active channel until IPA is greater than IPB and the difference between IPA and IPB—in this order—becomes greater than 6.25% of IPB. However, if FAULTSIGN bit (Bit 6) of ACCMODE Register (0x0F) is set, the FAULTSIGN flag in the Interrupt Status 1 SFR (MIRQSTL, 0xDC) is set as soon as IPA is within 6.25% of IPB. This threshold eliminates potential chatter between IPA and IPB.

of line cycles. This condition is illustrated in Figure 56.

3 LINE CYCLES

Figure 57. Peak Level Detection Figure 56. SAG Detection are compared to the absolute value of the output from LPF1.

1. The SAG level register is compared to the input of the ZX

processing chain for the rms calculation on the current channel. current channel waveform sample. setting the ZXRMS bit in the MODE2 register (0x0C). externally in the microprocessor using an amps/LSB constant. current channel rms offset compensation register (IRMSOS). 16,384 LSBs of the square of the current channel rms register. measurement error at −60 dB down of full scale. where Irms0 is the rms measurement without offset correction. Figure 60. ADE7566/ ADE7569 Current Channel RMS Signal Processing with PGA1 = 1, 2, 4, 8, or 16

ADE7566/ADE7569/ADE7166/ADE7169 Rev. A | Page 59 of 144 Active Power Gain Calibration Active Power Sign Detection Figure 65 shows the signal processing chain for the active power calculation in the ADE7566/ADE7569/ADE7166/ADE7169. As explained previously, the active power is calculated by filtering the output of the multiplier with a low-pass filter. Note that when reading the waveform samples from the output of LPF2, the gain of the active energy can be adjusted by using the multiplier and watt gain register (WGAIN[11:0]). The gain is adjusted by writing a twos complement 12-bit word to the watt gain register. Equation 12 shows how the gain adjustment is related to the contents of the watt gain register. The ADE7566/ADE7569/ADE7166/ADE7169 detect a change of sign in the active power. The APSIGN flag in the Interrupt Status 1 SFR (MIRQSTL, 0xDC) records when a change of sign has occurred according to Bit APSIGN in the ACCMODE register (0x0F). If the APSIGN flag is set in the Interrupt Enable

1 SFR (MIRQENL, 0xD9), the 8052 core has a pending ADE

interrupt. The ADE interrupt stays active until the APSIGN status bit is cleared (see the Energy Measurement Interrupts section). When APSIGN in the ACCMODE register (0x0F) is cleared (default), the APSIGN flag in the Interrupt Status 1 SFR (MIRQSTL, 0xDC) is set when a transition from positive–to- negative active power has occurred. ⎧ + ×= 122

1 WGAINPowerActiveWGAINOutput (12)

For example, when 0x7FF is written to the watt gain register, the power output is scaled up by 50% (0x7FF = 2047d, 2047/212 = 0.5). Similarly, 0x800 = −2048d (signed, twos complement) and power output is scaled by –50%. Each LSB scales the power output by 0.0244%. The minimum output range is given when the watt gain register contents are equal to 0x800 and the maximum range is given by writing 0x7FF to the watt gain register. This can be used to calibrate the active power (or energy) calculation in the ADE7566/ADE7569/ADE7166/ ADE7169. When APSIGN in the ACCMODE register (0x0F) is set, the APSIGN flag in the MIRQSTL SFR is set when a transition from negative to positive active power occurrs. Active Power No-Load Detection The ADE7566/ADE7569/ADE7166/ADE7169 include a no- load threshold feature on the active energy that eliminates any creep effects in the meter. The part accomplishes this by not accumulating energy if the multiplier output is below the no- load threshold. When the active power is below the no-load threshold, the APNOLOAD flag in the Interrupt Status 1 SFR (MIRQSTL, 0xDC) is set. If the APNOLOAD bit is set in the Interrupt Enable 1 SFR (MIRQENL, 0xD9), the 8052 core has a pending ADE interrupt. The ADE interrupt stays active until the APNOLOAD status bit is cleared (see the Active Power Offset Calibration The ADE7566/ADE7569/ADE7166/ADE7169 also incorporate an active power offset register (W ATTOS[15:0]). It is a signed, twos complement, 16-bit register that can be used to remove offsets in the active power calculation (see Energy Measurement InterruptsFigure 63). An offset can exist in the power calculation due to crosstalk between channels on the PCB or in the IC itself. The offset calibration allows the contents of the active power register to be maintained at 0 when no power is being consumed. section). The no-load threshold level is selectable by setting the APNOLOAD bits in the NLMODE register (0x0E). Setting these bits to 0b00 disables the no-load detection, and setting them to 0b01, 0b10, or 0b11 sets the no-load detection threshold to 0.015%, 0.0075%, or 0.0037% of the multiplier’s full-scale output frequency, respectively. The IEC 62053-21 specification states that the meter must start up with a load equal to or less than 0.4% I PB, which translates to .0167% of the full-scale output frequency of the multiplier. The 256 LSBs (W ATTOS = 0x0100) written to the active power offset register are equivalent to 1 LSB in the waveform sample register. Assuming the average value, output from LPF2 is 0xCCCCD (838,861d) when inputs on the voltage and current channels are both at full scale. At −60 dB down on the current channel (1/1000 of the current channel full-scale input), the average word value output from LPF2 is 838.861 (838,861/1,000). One LSB in the LPF2 output has a measurement error of 1/838.861 × 100% = 0.119% of the average value. The active power offset register has a resolution equal to 1/256 LSB of the waveform register. Therefore, the power offset correction resolution is 0.000464%/LSB (0.119%/256) at −60 dB.

accumulation. The LSB size of these two registers is equivalent. θ is the phase difference between the voltage and current channel. Figure 70. Energy Accumulation When LINCYC Changes q is referred to as the reactive power. the instantaneous reactive power signal q(t) in Equation 23.

60 Hz line frequency, it translates to a total duration of

Energy Register Scaling section). has some ripple due to the instantaneous reactive power signal. system when the phase of the current channel is shifted by 90°. WFSM bit in the Interrupt Enable 3 SFR (MIRQENH, 0xDB). kSPS, 6.4 kSPS, or 3.2 kSPS.

gain adjustment is related to the contents of the V AGAIN register. phase angle between the current and the voltage.

1221 VAGAINPowerApparent (32)

signal in an ac system with a phase shift. Figure 75. Apparent Power Signal Processing

Table 46. Energy Registers Scaling core, Vector Address 0x004B (see the Interrupt Vectors section). written to this register bit.

battery detection to be performed. be configured to continue functioning in PSM1 and PSM2. before using it for compensation. Table 47. Temperature, Battery, and Supply Voltage Measurement SFRs 0xF9 R/W STRBPER Peripheral ADC Strobe Period (see Table 48). 0xF3 R/W DIFFPROG Temperature and Supply Delta Configuration (see Table 49). 0xD8 R/W ADCGO Start ADC Measurement (see Table 50). 0xFA R/W BATVTH Battery Detection Threshold (see Table 51). 0xEF R/W VDCINADC VDCIN ADC Value (see Table 52). 0xDF R/W BATADC Battery ADC Value (see Table 53). 0xD7 R/W TEMPADC Temperature ADC Value (see Table 54). Table 48. Peripheral ADC Strobe Period SFR (STRBPER, 0xF9) 1 7 to 6 Reserved 00 These bits should be left clear for proper operation. Period for background external voltage measurements.

00 No VDCIN measurement

Period for background battery level measurements.

00 No battery measurement

Period for background temperature measurements.

00 No temperature measurements

1 The strobing option only works when the RTCEN bit in RTC Configuration SFR (TIMECON, 0xA1) is set.

Table 49. Temperature and Supply Delta SFR (DIFFPROG, 0xF3) temperature measurement that should interrupt 8052.

000 No interrupt

111 Every temperature measurement

external measurement that should interrupt 8052.

111 Every VDCIN measurement

Table 50. Start ADC Measurement SFR (ADCGO, 0xD8) generated if a reset is caused because the PLL lost lock. 6 to 3 0xDE to 0xDB Reserved 0 Reserved. the measurement request is received by the ADC. measurement request is received by the ADC. measurement request is received by the ADC. Table 51. Battery Detection Threshold SFR (BATVTH, 0xFA) lower than the threshold, an interrupt is generated. Table 52. VDCIN ADC Value SFR (VDCINADC, 0xEF) 7 to 0 VDCINADC 0 The VDCIN ADC value in this register is updated when an ADC interrupt occurs. Table 53. Battery ADC Value SFR (BATADC, 0xDF) 7 to 0 BATADC 0 The battery ADC value in this register is updated when an ADC interrupt occurs. Table 54. Temperature ADC Value SFR (TEMPADC, 0xD7) 7 to 0 TEMPADC 0 The temperature ADC value in this register is updated when an ADC interrupt occurs.

ADE7566/ADE7569/ADE7166/ADE7169 Rev. A | Page 75 of 144 TEMPERATURE MEASUREMENT To provide a digital temperature measurement, each ADE7566/ADE7569/ADE7166/ADE7169 includes a dedicated ADC. An 8-bit Temperature ADC Value SFR (TEMPADC, 0xD7) holds the results of the temperature conversion. The resolution of the temperature measurement is 0.78°C/LSB. There are two ways to initiate a temperature conversion: a single temperature measurement or background temperature measurements. Single Temperature Measurement Set the TEMP_ADC_GO bit in the Start ADC Measurement SFR (ADCGO, 0xD8) to obtain a temperature measurement (see Table 50). An interrupt is generated when the conversion is complete and when the temperature measurement is available in the Temperature ADC Value SFR (TEMPADC, 0xD7). Background Temperature Measurements Background temperature measurements are disabled by default. To configure the background temperature measurement mode, set a temperature measurement interval in the Peripheral ADC Strobe Period SFR (STRBPER, 0xF9). Temperature measurements are then performed periodically in the background (see Table 48). When a temperature conversion completes, the new temperature ADC value is compared to the last temperature ADC value that created an interrupt. If the absolute difference between the two values is greater than the setting in the TEMP_DIFF[2:0] bits in the Temperature and Supply Delta SFR (DIFFPROG, 0xF3), a TEMPADC interrupt is generated (see Table 49). This allows temperature measurements to take place completely in the background, only requiring MCU activity if the temperature changes more than a configurable delta. To set up background temperature measurements, follow these steps: 1. Initiate a single temperature measurement by setting the TEMP_ADC_GO bit in the Start ADC Measurement SFR (ADCGO, 0xD8). 2. Upon completion of this measurement, configure the TEMP_DIFF[2:0] bits to establish the change in temperature that triggers an interrupt. 3. Set up the interval for background temperature measurements by configuring the TEMP_PERIOD[1:0] bits in the Peripheral ADC Strobe Period SFR (STRBPER, 0xF9). Temperature ADC in PSM0, PSM1, and PSM2 Depending on the operating mode of the ADE7566/ADE7569/ ADE7166/ADE7169, a temperature conversion is initiated only by certain actions.

• In PSM0 operating mode, the 8052 is active. Temperature measurements are available in the background measurement mode and by initiating a single measurement.
• In PSM1 operating mode, the 8052 is active and the part is battery powered. Single temperature measurements can be initiated by setting the TEMP_ADC_GO bit in the Start ADC Measurement SFR (ADCGO, 0xD8). Background temperature measurements are not available.
• In PSM2 operating mode, the 8052 is not active. Temperature conversions are available through the background measurement mode only. The Temperature ADC Value SFR (TEMPADC, 0xD7) is updated with a new value only when a temperature ADC interrupt occurs. Temperature ADC Interrupt The temperature ADC can generate an ADC interrupt when at least one of the following conditions occurs:
• The difference between the new temperature ADC value and the last temperature ADC value generating an ADC interrupt is larger than the value set in the TEMP_DIFF[2:0] bits.
• The temperature ADC conversion, initiated by setting Start ADC Measurement SFR (ADCGO, 0xD8) finishes. When the ADC interrupt occurs, a new value is available in the Temperature ADC Value SFR (TEMPADC, 0xD7). Note that there is no flag associated with this interrupt. BATTERY MEASUREMENT To provide a digital battery measurement, each ADE7566/ ADE7569/ADE7166/ADE7169 includes a dedicated ADC. The battery measurement is available in an 8-bit SFR, the Battery ADC Value SFR (BATADC, 0xDF). The battery measurement has a resolution of 14.6 mV/LSB. A battery conversion can be initiated by two methods: a single battery measurement or background battery measurements. Single Battery Measurement Set the BATT_ADC_GO bit in the Start ADC Measurement SFR (ADCGO, 0xD8) to obtain a battery measurement. An interrupt is generated when the conversion is done and when the battery measurement is available in the Battery ADC Value SFR (BATADC, 0xDF). Background Battery Measurements To configure background measurements for the battery, establish a measurement interval in the Peripheral ADC Strobe Period SFR (STRBPER, 0xF9). Battery measurements are then performed periodically in the background (see Table 48). When a battery conversion completes, the battery ADC value is compared to the low battery threshold, established in the Battery Detection Threshold SFR (BATVTH, 0xFA). If the battery ADC value is below this threshold, a low battery flag is set. This low battery flag is the FBAT bit in the Power Management Interrupt Flag SFR (IPSMF, 0xF8), which is used for power supply moni- toring. This low battery flag can be enabled to generate the PSM interrupt by setting the EBAT bit in the Power Management Interrupt Enable SFR (IPSME, 0xEC). This method allows battery measurements to take place completely in the background, only requiring MCU activity if the battery drops below a user- specified threshold.

ADE7566/ADE7569/ADE7166/ADE7169 Rev. A | Page 76 of 144 To set up background battery measurements, follow these steps: 1. Configure the Battery Detection Threshold SFR (BATVTH, 0xFA) to establish a low battery threshold. If the BATADC measurement is below this threshold, the FBAT in the Power Management Interrupt Flag SFR (IPSMF, 0xF8) is set. 2. Set up the interval for background battery measurements by configuring the BATT_PERIOD[1:0] bits in the Peripheral ADC Strobe Period SFR (STRBPER, 0xF9). Battery ADC in PSM0, PSM1, and PSM2 Depending on the operating mode, a battery conversion is initiated only by certain actions.

• In PSM0 operating mode, the 8052 is active. Battery measurements are available in the background measurement mode and by initiating a single measurement.
• In PSM1 operating mode, the 8052 is active and the part is battery powered. Single battery measurements can be initiated by setting the BATT_ADC_GO bit in the Start ADC Measurement SFR (ADCGO, 0xD8). Background battery measurements are not available.
• In PSM2 operating mode, the 8052 is not active. Unlike temperature and VDCIN measurements, the battery conversions are not available in this mode. Battery ADC Interrupt The battery ADC can generate an ADC interrupt when at least one of the following conditions occurs:
• The new battery ADC value is smaller than the value set in the Battery Detection Threshold SFR (BATVTH, 0xFA), indicating a battery voltage loss.
• A single battery measurement initiated by setting the BATT_ADC_GO bit finishes. When the battery flag (FBAT) is set in the Power Management Interrupt Flag SFR (IPSMF, 0xF8), a new ADC value is available in the Battery ADC Value SFR (BATADC, 0xDF). This battery flag can be enabled as a source of the PSM interrupt to generate a PSM interrupt every time the battery drops below a set voltage threshold or after a single conversion initiated by setting the BATT_ADC_GO bit is ready. The Battery ADC Value SFR (BATADC, 0xDF) is updated with a new value only when the battery flag is set in the Power Management Interrupt Flag SFR (IPSMF, 0xF8). EXTERNAL VOLTAGE MEASUREMENT The ADE7566/ADE7569/ADE7166/ADE7169 include a dedicated ADC to provide a digital measurement of an external voltage on the VDCIN pin. An 8-bit SFR, the VDCIN ADC Value SFR (VDCINADC, 0xEF), holds the results of the conversion. The resolution of the external voltage measurement is 15.3 mV/LSB. There are two ways to initiate an external voltage conversion: a single external voltage measurement or background external voltage measurements. Single External Voltage Measurement To obtain an external voltage measurement, set the VDCIN_ADC_GO bit in the Start ADC Measurement SFR (ADCGO, 0xD8). An interrupt is generated when the conversion is done and when the external voltage measurement is available in the VDCIN ADC Value SFR (VDCINADC, 0xEF). Background External Voltage Measurements Background external voltage measurements are disabled by default. To configure the background external voltage measurement mode, set an external voltage measurement interval in the Peripheral ADC Strobe Period SFR (STRBPER, 0xF9). External voltage measurements are performed periodically in the background (see Table 48). When an external voltage conversion is complete, the new external voltage ADC value is compared to the last external voltage ADC value that created an interrupt. If the absolute difference between the two values is greater than the setting in the VDCIN_DIFF[2:0] bits in the Temperature and Supply Delta SFR (DIFFPROG, 0xF3), a V DCIN ADC flag is set. This VDCIN ADC flag is the FVDCIN in the Power Management Interrupt Flag SFR (IPSMF, 0xF8), which is used for power supply monitoring. This V DCIN ADC flag can be enabled to generate a PSM interrupt by setting the EVDCIN bit in the Power Management Interrupt Enable SFR (IPSME, 0xEC). This method allows external voltage measurements to take place completely in the background, only requiring MCU activity if the external voltage has changed more than a configurable delta. To set up background external voltage measurements, follow these steps: 1. Initiate a single external voltage measurement by setting the VDCIN_ADC_GO bit in the Start ADC Measurement SFR (ADCGO, 0xD8). 2. Upon completion of this measurement, configure the VDCIN_DIFF[2:0] bits to establish the change in voltage that sets the FVDCIN in the Power Management Interrupt Flag SFR (IPSMF, 0xF8). 3. Set up the interval for background external voltage measurements by configuring the VDCIN_PERIOD[1:0] bits in the Peripheral ADC Strobe Period SFR (STRBPER, 0xF9).

ADE7566/ADE7569/ADE7166/ADE7169 Rev. A | Page 77 of 144 External Voltage ADC in PSM1 and PSM2 An external voltage conversion is initiated only by certain actions that depend on the operating mode of the ADE7566/ADE7569/ ADE7166/ADE7169.

• In PSM0 operating mode, the 8052 is active. External voltage measurements are available in the background measurement mode and by initiating a single measurement.
• In PSM1 operating mode, the 8052 is active and the part is powered from battery. Single external voltage measurements can be initiated by setting the VDCIN_ADC_GO bit in the Start ADC Measurement SFR (ADCGO, 0xD8). Background external voltage measurements are not available.
• In PSM2 operating mode, the 8052 is not active. External voltage conversions are available through the background measurement mode only. The external voltage ADC in the VDCIN ADC Value SFR (VDCINADC, 0xEF) is updated with a new value only when an external voltage ADC interrupt occurs. External Voltage ADC Interrupt The external voltage ADC can generate an ADC interrupt when at least one of the following conditions occurs:
• The difference between the new external voltage ADC value and the last external voltage ADC value generating an ADC interrupt is larger than the value set in the VDCIN_DIFF[2:0] bits in the Temperature and Supply Delta SFR (DIFFPROG, 0xF3).
• The external voltage ADC conversion initiated by setting VDCIN_ADC_GO finishes. When the ADC interrupt occurs, a new value is available in the VDCIN ADC Value SFR (VDCINADC, 0xEF). Note that there is no flag associated with this interrupt.

8052 MCU CORE ARCHITECTURE

256 BYTES XRAM OTHER ON-CHIP

• SERIAL I/O
• WDT
• TIMERS BATTERY ADC LCD DRIVER TEMPERATURE ADC RTC POWER MANAGEMENT 128-BYTE SPECIAL FUNCTION REGISTER AREAIR STACK

Figure 80. ADE7566/ADE7569/ADE7166/ADE7169 Block Diagram All registers except the program counter (PC), instruction interface between the CPU and all on-chip peripherals. The registers used by the MCU are summarized in this section. Table 55. 8052 SFRs 0xF0 B Yes Auxiliary Math Register. 0xD0 PSW Yes Program Status Word (see Table 56). 0x87 PCON No Program Control Register (see Table 57). 0x82 DPL No Data Pointer Low (see Table 58). 0x83 DPH No Data Pointer High (see Table 59). 0x83 and 0x82 DPTR No Data Pointer (see Table 60). 0x81 SP No Stack Pointer (see Table 61). 0xAF CFG No Configuration (see Table 62). Table 56. Program Status Word SFR (PSW, 0xD0) 7 0xD7 CY Carry Flag. Modified by ADD, ADDC, SUBB, MUL, and DIV instructions. 6 0xD6 AC Auxiliary Carry Flag. Modified by ADD and ADDC instructions. 5 0xD5 F0 General-Purpose Flag Available to the User. 2 0xD2 OV Overflow Flag. Modified by ADD, ADDC, SUBB, MUL, and DIV instructions. 1 0xD1 F1 General-Purpose Flag Available to the User.

Table 57. Program Control SFR (PCON, 0x87) 7 0 SMOD bit. Double baud rate control. 6 to 0 0 Reserved. Should be left cleared. Table 58. Data Pointer Low SFR (DPL, 0x82) 7 to 0 0 Contain the low byte of the data pointer. Table 59. Data Pointer High SFR (DPH, 0x83) 7 to 0 0 Contain the high byte of the data pointer. Table 60. Data Pointer SFR (DPTR, 0x82 and 0x83) 15 to 0 0 Contain the 2-byte address of the data pointer. DPTR is a combination of DPH and DPL SFRs. Table 61. Stack Pointer SFR (SP, 0x81) 7 to 0 7 Contain the 8 LSBs of the pointer for the stack. Table 62. Configuration SFR (CFG, 0xAF) 7 Reserved This bit should be left set for proper operation. 0 Standard 8052 UART without enhanced error-checking features.

6 EXTEN

1 Enhanced UART with enhanced error checking (see the UART Additional Features section). Synchronous Communication Selection Bit. 0 I2C port is selected for control of the shared I2C/SPI pins and SFRs.

5 SCPS

1 SPI port is selected for control of the shared I2C/SPI pins and SFRs. 38 kHz Modulation Enable Bit. 0 38 kHz modulation is disabled.

4 MOD38EN

Extended Port Configuration SFR (EPCFG, 0x9F). XREN1 OR XREN0 = 1 Enables MOVX instruction to use 256 bytes of extended RAM. XREN1 AND XREN0 = 0 Disables MOVX instruction.

instructions that change which part of the program is active. where the main and shadow data pointers are distinguished. the data sheet, active DPTR is implied. not directly accessible to the user. for interrupts to keep track of the prior state of the PC. the Program Status Word SFR (PSW , 0xD0). stack pointer overflows in data RAM. Table 55). Data can still be stored in XRAM by using the MOVX command.

256 BYTES OF

as a scratch pad register such as those in the register banks. operations through carry, auxiliary carry, and overflow flags. Table 56. The Program Status Word SFR

Figure 83. General-Purpose RAM and SFR Memory Address Overlap space with the special function registers (SFRs). Figure 84. Bit Addressable Area of General-Purpose RAM accessible through direct addressing as shown in Figure 83. Configuration SFR (CFG, 0xAF) by writing 01 to CFG[1:0]. Figure 85. Extended Internal RAM (XRAM) Space memory, code indirect addressing is used. code. There are six addressing modes as shown in Table 63. Table 63. 8052 Addressing Modes because it refers only to a value and not to a memory location.

ADE7566/ADE7569/ADE7166/ADE7169 Rev. A | Page 83 of 144 Direct Addressing With direct addressing, the value at the source address is moved to the destination address. Direct addressing provides the fastest execution time of all the addressing modes when an instruction is performed between registers. Note that indirect or direct addressing modes can be used to access general-purpose RAM Address 0x00 through Address 0x7F. An instruction with direct addressing that uses an address between 0x80 and 0xFF is referring to a special function memory location. Indirect Addressing With indirect addressing, the value pointed to by the register is moved to the destination address. For example, to move the contents of internal RAM Address 0x82 to the accumulator, use the following instructions: MOV R0,#82h MOV A,@R0 These two instructions require a total of four clock cycles and three bytes of storage in the program memory. Indirect addressing allows addresses to be computed, which is useful for indexing into data arrays stored in RAM. Note that an instruction that refers to Address 0x00 through Address 0x7F is referring to internal RAM, and indirect or direct addressing modes can be used. An instruction with indirect addressing that uses an address between 0x80 and 0xFF is referring to internal RAM, not to an SFR. Extended Direct Addressing The DPTR register (see Table 60) is used to access internal extended RAM in extended indirect addressing mode. The ADE7566/ADE7569/ADE7166/ADE7169 have 256 bytes of XRAM, accessed through MOVX instructions. External memory spaces are not supported on this device. In extended direct addressing mode, the DPTR register points to the address of the byte of extended RAM. The following code moves the contents of extended RAM Address 0x100 to the accumulator: MOV DPTR,#100h MOVX A,@DPTR These two instructions require a total of seven clock cycles and four bytes of storage in the program memory. Extended Indirect Addressing The internal extended RAM is accessed through a pointer to the address in indirect addressing mode. The ADE7566/ADE7569/ ADE7166/ADE7169 have 256 bytes of internal extended RAM, accessed through MOVX instructions. External memory is not supported on the devices. In extended indirect addressing mode, a register holds the address of the byte of extended RAM. The following code moves the contents of extended RAM Address 0x80 to the accumulator: MOV R0,#80h MOVX A,@R0 These two instructions require six clock cycles and three bytes of storage. Note that there are 256 bytes of extended RAM; therefore, both extended direct and extended indirect addressing can cover the whole address range. There is a storage and speed advantage to using extended indirect addressing because the additional byte of addressing available through the DPTR register that is not needed is not stored. From the three examples demonstrating the access of internal RAM from 0x80 through 0xFF, and the access of extended internal RAM from 0x00 through 0xFF, it can be seen that it is most efficient to use the entire internal RAM accessible through indirect access before moving to extended RAM. Code Indirect Addressing The internal code memory can be accessed indirectly. This can be useful for implementing lookup tables and other arrays of constants that are stored in flash. For example, to move the data stored in flash memory at Address 0x8002 into the accumulator, use the following code: MOV DPTR,#8002h CLR A MOVX A,@A+DPTR The accumulator can be used as a variable index into the array of flash memory located at DPTR.

resulting in a 4-MIPS peak performance. Table 64. Instruction Set

ADE7566/ADE7569/ADE7166/ADE7169 Rev. A | Page 85 of 144 Mnemonic Description Bytes Cycles RLC A Rotate A Left Through Carry. 1 1 RR A Rotate A Right. 1 1 RRC A Rotate A Right Through Carry. 1 1 DATA TRANSFER MOV A,Rn Move Register to A. 1 1 MOV A,@Ri Move Indirect Memory to A. 1 2 MOV Rn,A Move A to Register. 1 1 MOV @Ri,A Move A to Indirect Memory. 1 2 MOV A,dir Move Direct Byte to A. 2 2 MOV A,#data Move Immediate to A. 2 2 MOV Rn,#data Move Register to Immediate. 2 2 MOV dir,A Move A to Direct Byte. 2 2 MOV Rn,dir Move Register to Direct Byte. 2 2 MOV dir,Rn Move Direct to Register. 2 2 MOV @Ri,#data Move Immediate to Indirect Memory. 2 2 MOV dir,@Ri Move Indirect to Direct Memory. 2 2 MOV @Ri,dir Move Direct to Indirect Memory. 2 2 MOV dir,dir Move Direct Byte to Direct Byte. 3 3 MOV dir,#data Move Immediate to Direct Byte. 3 3 MOV DPTR,#data Move Immediate to Data Pointer. 3 3 MOVC A,@A+DPTR Move Code Byte Relative DPTR to A. 1 4 MOVC A,@A+PC Move Code Byte Relative PC to A 1. 1 4 MOVX A,@Ri Move External (A8) Data to A. 1 4 MOVX A,@DPTR Move External (A16) Data to A. 1 4 MOVX @Ri,A Move A to External Data (A8). 1 4 MOVX @DPTR,A Move A to External Data (A16). 1 4 PUSH dir Push Direct Byte onto Stack. 2 2 POP dir Pop Direct Byte from Stack. 2 2 XCH A,Rn Exchange A and Register. 1 1 XCH A,@Ri Exchange A and Indirect Memory. 1 2 XCHD A,@Ri Exchange A and Indirect Memory Nibble. 1 2 XCH A,dir Exchange A and Direct Byte. 2 2 BOOLEAN CLR C Clear Carry. 1 1 CLR bit Clear Direct Bit. 2 2 SETB C Set Carry. 1 1 SETB bit Set Direct Bit. 2 2 CPL C Complement Carry. 1 1 CPL bit Complement Direct Bit. 2 2 ANL C,bit AND Direct Bit and Carry. 2 2 ANL C,/bit AND Direct Bit Inverse to Carry. 2 2 ORL C,bit OR Direct Bit And Carry. 2 2 ORL C,/bit OR Direct Bit Inverse to Carry. 2 2 MOV C,bit Move Direct Bit to Carry. 2 2 MOV bit,C Move Carry to Direct Bit. 2 2 BRANCHING JMP @A+DPTR Jump Indirect Relative to DPTR. 1 3 RET Return from Subroutine. 1 4 RETI Return from Interrupt. 1 4 ACALL addr11 Absolute Jump to Subroutine. 2 3 AJMP addr11 Absolute Jump Unconditional. 2 3 SJMP rel Short Jump (Relative Address). 2 3 JC rel Jump on Carry Equal to 1. 2 3

Some 8052 instructions read the latch and others read the pin. The state of the pin is read for instructions that input a port bit. that read a value, possibly change it, and rewrite it to the latch. rather than the pin returns the correct value of 1. called read-modify-write instructions and are listed in Table 65. instructions read the latch rather than the pin. Table 65. Read-Modify-Write Instructions JBC JBC P1.1,LABEL Jump if Bit = 1 and Clear Bit. CPL CPL P2.0 Complement Bit. DJNZ DJNZ P0,LABEL Decrement and Jump if Not Zero. MOV PX.Y ,C1 MOV P0.0,C Move Carry to Bit Y of Port X. CLR PX.Y1 CLR P0.0 Clear Bit Y of Port X. SETB PX.Y1 SETB P0.0 Set Bit Y of Port X.

1 These instructions read the port byte (all 8 bits), modify the addressed bit,

and write the new byte back to the latch. affect status flags are listed in this section. flags are referenced by the instruction. C Set if there is a carry out of Bit 7. Cleared otherwise. negative operands yield a positive result. AC Set if there is a carry out of Bit 3. Cleared otherwise. mulator. The carry status flag is referenced by the instruction. C Set if there is a carry out of Bit 7. Cleared otherwise. operands yield a positive result. AC Set if there is a carry out of Bit 3. Cleared otherwise.

ADE7566/ADE7569/ADE7166/ADE7169 Rev. A | Page 87 of 144 SUBB A, Source This instruction subtracts the source byte and the carry (borrow) flag from the accumulator. It references the carry (borrow) status flag. Affected Status Flags C Set if there is a borrow needed for Bit 7. Cleared otherwise. Used to indicate an overflow if the operands are unsigned. OV Set if there is a borrow needed for Bit 6 or Bit 7, but not for both. Used to indicate an overflow for signed subtraction. This flag is set if a negative number subtracted from a positive yields a negative result or if a positive number subtracted from a negative number yields a positive result. AC Set if a borrow is needed for Bit 3. Cleared otherwise. MUL AB This instruction multiplies the accumulator by the B register. This operation is unsigned. The lower byte of the 16-bit product is stored in the accumulator and the higher byte is left in the B register. No status flags are referenced by the instruction. Affected Status Flags C Cleared OV Set if the result is greater than 255. Cleared otherwise. DIV AB This instruction divides the accumulator by the B register. This operation is unsigned. The integer part of the quotient is stored in the accumulator and the remainder goes into the B register. No status flags are referenced by the instruction. Affected Status Flags C Cleared OV Cleared unless the B register is equal to 0, in which case the results of the division are undefined and the OV flag is set. DA A This instruction adjusts the accumulator to hold two 4-bit digits after the addition of two binary coded decimals (BCDs) with the ADD or ADDC instructions. If the AC bit is set or if the value of Bit 0 to Bit 3 exceeds nine, 0x06 is added to the accumulator to correct the lower four bits. If the carry bit is set when the instruction begins, or if 0x06 is added to the accumulator in the first step, 0x60 is added to the accumulator to correct the higher four bits. The carry and AC status flags are referenced by this instruction. Affected Status Flag C Set if the result is greater than 0x99. Cleared otherwise. RRC A This instruction rotates the accumulator to the right through the carry flag. The old LSB of the accumulator becomes the new carry flag, and the old carry flag is loaded into the new MSB of the accumulator. The carry status flag is referenced by this instruction. Affected Status Flag C Equal to the state of ACC.0 before execution of the instruction. RLC A This instruction rotates the accumulator to the left through the carry flag. The old MSB of the accumulator becomes the new carry flag, and the old carry flag is loaded into the new LSB of the accumulator. The carry status flag is referenced by this instruction. Affected Status Flag C Equal to the state of ACC.7 before execution of the instruction. CJNE Destination, Source, Relative Jump This instruction compares the source value to the destination value and branches to the location set by the relative jump if they are not equal. If the values are equal, program execution continues with the instruction after the CJNE instruction. No status flags are referenced by this instruction. Affected Status Flag C Set if the source value is greater than the destination value. Cleared otherwise.

postdecrement, as well as an automatic data pointer toggle. sheet, active DPTR is implied. automatically postincrement and postdecrement the DPTR. postincrement and postdecrement. Table 66. Data Pointer Control SFR (DPCON, 0xA7) 7 0 Not Implemented. Write Don’t Care. 6 DPT 0 Data Pointer Automatic Toggle Enable. Cleared by the user to disable autoswapping of the DPTR. Set in user software to enable automatic toggling of the DPTR after each MOVX or MOVC instruction. allowing more compact and more efficient code size and execution. 0 1 DPTR is postincremented after a MOVX or a MOVC instruction. 1 0 DPTR is postdecremented after a MOVX or MOVC instruction. useful for moving 8-bit blocks to/from 16-bit devices. more compact and more efficient code size and execution. 0 1 DPTR is postincremented after a MOVX or a MOVC instruction. 1 0 DPTR is postdecremented after a MOVX or MOVC instruction. for moving 8-bit blocks to/from 16-bit devices. 1 0 Not Implemented. Write Don’t Care. pointer, meaning that the contents of a separate 16-bit register appear in the DPL SRF and DPH SFR.

that can trigger an interrupt when the MCU core is active.

3.3 V Peripherals

can wake the 8052 core from PSM2. and others are assigned a low priority. Figure 86. Standard 8052 Interrupt Priority Levels occur at the same time, the Priority 1 interrupt is serviced first. Figure 87. Interrupt Architecture more information on the PSM interrupt. out through four interrupt-related SFRs discussed in this section. Table 67. Interrupt SFRs IE 0xA8 0x00 Yes Interrupt Enable (see Table 68). IP 0xB8 0x00 Yes Interrupt Priority (see Table 69). IEIP2 0xA9 0xA0 No Interrupt Enable and Priority 2 (see Table 70). Table 68. Interrupt Enable SFR (IE, 0xA8) 7 0xAF EA Enables All Interrupt Sources. Set by the user. Cleared by the user to disable all interrupt sources. 6 0xAE ETEMP Enables the Temperature ADC Interrupt. Set by the user. 5 0xAD ET2 Enables the Timer 2 Interrupt. Set by the user. 4 0xAC ES Enables the UART Serial Port Interrupt. Set by the user. 3 0xAB ET1 Enables the Timer 1 Interrupt. Set by the user. 2 0xAA EX1 Enables the External Interrupt 1 (INT1). Set by the user. 1 0xA9 ET0 Enables the Timer 0 Interrupt. Set by the user. 0 0xA8 EX0 Enables External Interrupt 0 (INT0). Set by the user.

Table 69. Interrupt Priority SFR (IP, 0xB8) 7 0xBF PADE ADE Energy Measurement Interrupt Priority (1 = high, 0 = low). 6 0xBE PTEMP Temperature ADC Interrupt Priority (1 = high, 0 = low). 5 0xBD PT2 Timer 2 Interrupt Priority (1 = high, 0 = low). 4 0xBC PS UART Serial Port Interrupt Priority (1 = high, 0 = low). 3 0xBB PT1 Timer 1 Interrupt Priority (1 = high, 0 = low). 2 0xBA PX1 INT1 (External Interrupt 1) Priority (1 = high, 0 = low). 1 0xB9 PT0 Timer 0 Interrupt Priority (1 = high, 0 = low). 0 0xB8 PX0 INT0 (External Interrupt 0) Priority (1 = high, 0 = low). Table 70. Interrupt Enable and Priority 2 SFR (IEIP2, 0xA9)

7 Reserved

6 PTI RTC Interrupt Priority (1 = high, 0 = low).

5 Reserved

4 PSI SPI/I2C Interrupt Priority (1 = high, 0 = low). 3 EADE Enables the Energy Metering Interrupt (ADE). Set by the user. 2 ETI Enables the RTC Interval Timer Interrupt. Set by the user. 1 EPSM Enables the PSM Power Supply Management Interrupt. Set by the user. 0 ESI Enables the SPI/I2C Interrupt. Set by the user. If two interrupts of the same priority level occur simultaneously, the polling sequence is observed (as shown in Table 71). Table 71. Priority Within Interrupt Level IPSM 0 (Highest) Power Supply Monitor Interrupt. IRTC 1 RTC Interval Timer Interrupt. IADE 2 ADE Energy Measurement Interrupt. WDT 3 Watchdog Timer Overflow Interrupt. ITEMP 4 Temperature ADC Interrupt. TF0 6 Timer/Counter 0 Interrupt. TF1 8 Timer/Counter 1 Interrupt. ISPI/I2CI 9 SPI/I2C Interrupt. RI/TI 10 UART Serial Port Interrupt. TF2/EXF2 11 (Lowest) Timer/Counter 2 Interrupt.

Figure 88. Interrupt System Functional Block Diagram

Table 74. Interrupt Vector Addresses access of the IP and IE registers. latency of 16.25 instruction cycles, 4 μs with a clock of 4.096 MHz.

Watchdog Timer SFR (WDCON, 0xC0). every write access to the WDCON SFR. predetermined amount of time (set by the PRE[3:0] bits). crystal connected between the CLKIN and CLKOUT pins. Protecting the Flash Memory section). Table 75. Watchdog Timer SFR (WDCON, 0xC0) interrupt when the watchdog time out period has expired. interrupt, depending on the WDIR bit.

Table 76. Watchdog and Flash Protection Byte in Flash (Flash Address = 0x3FFA) This bit holds the protection for the watchdog timer and the 7th bit of the flash protection key. timeout in PRE[3:0] can still be modified by user code.

7 WDPROT_PROTKY7 1

Protecting the Flash Memory section for more information on how to clear this bit). the Protecting the Flash Memory section for more information on how to configure these bits. instruction must be a write instruction to the WDCON SFR. the consecutive instruction cycles. be used as a long interval timer. disabled, the watchdog is kept active to watch over the program.

ladder for LCD waveform voltage generation is also supported. Table 77. LCD Driver SFRs 0x95 R/W LCDCON LCD Configuration SFR (see Table 78). 0x96 R/W LCDCLK LCD Clock (see Table 82). 0x97 R/W LCDSEGE LCD Segment Enable (see Table 85). 0x9C R/W LCDCONX LCD Configuration X (see Table 79). 0xAC R/W LCDPTR LCD Pointer (see Table 86). 0xAE R/W LCDDAT LCD Data (see Table 87). 0xB1 R/W LCDCONY LCD Configuration Y (see Table 81). 0xED R/W LCDSEGE2 LCD Segment Enable 2 (see Table 88). Table 78. LCD Configuration SFR (LCDCON, 0x95) 7 LCDEN 0 LCD Enable. If this bit is set, the LCD driver is enabled. 6 LCDRST 0 LCD Data Registers Reset. If this bit is set, the LCD data registers are reset to zero. BLKMOD[1:0] and BLKFREQ[1:0] bits in the LCD Clock SFR (LCDCLK, 0x96). the REF_BAT_EN bit in the Peripheral Configuration SFR (PERIPH, 0xF4) to allow LCD operation in PSM2. 0 The LCD is disabled or enabled in PSM2 by the LCDEN bit.

4 LCDPSM2 0

1 The LCD is disabled in PSM2 regardless of LCDEN setting.

3 CLKSEL 0

2 BIAS 0

01 2× Multiplexing. FP27/COM3 is used as FP27. FP28/COM2 is used as FP28. 10 3× Mulitplexing. FP27/COM3 is used as FP27. FP28/COM2 is used as COM2. 11 4× Multiplexing. FP27/COM3 is used as COM3. FP28/COM2 is used as COM2.

Table 79. LCD Configuration X SFR (LCDCONX, 0x9C) 0 External resistor ladder is disabled. Charge pump is enabled. 1 External resistor ladder is enabled. Charge pump is disabled. 5 to 0 BIASLVL[5:0] 0 Bias Level Selection Bits. See Table 80. Table 80. LCD Bias Voltage When Contrast Control Is Enabled

1 VC = 2 × VA VB = 2 × VA VC = 3 × VA VB = VA

Table 81. LCD Configuration Y SFR (LCDCONY, 0xB1) 7 Reserved 0 This bit should be kept cleared for proper operation. cleared, frames are not inverted. 5 to 2 Reserved 0 These bits should be kept cleared for proper operation. LCD memory has been updated and a new frame has begun. Table 82. LCD Clock SFR (LCDCLK, 0x96) 00 The blink rate is controlled by software. The display is off. 01 The blink rate is controlled by software. The display is on. 11 The blink rate is set by BLKFREQ[1:0]. 3 to 0 FD[3:0] 0 LCD Frame Rate Selection Bits. See Table 83 and Table 84.

Table 83. LCD Frame Rate Selection for fLCDCLK = 2048 Hz (LCDCON[3] = 0) 1 Not within the range of typical LCD frame rates. Table 84. LCD Frame Rate Selection for fLCDCLK = 128 Hz (LCDCON[3] = 1) 1 Not within the range of typical LCD frame rates. Table 85. LCD Segment Enable SFR (LCDSEGE, 0x97) 7 FP25EN 0 FP25 Function Select Bit. 0 = General-Purpose I/O, 1 = LCD Function. 6 FP24EN 0 FP24 Function Select Bit. 0 = General-Purpose I/O, 1 = LCD Function. 5 FP23EN 0 FP23 Function Select Bit. 0 = General-Purpose I/O, 1 = LCD Function. 4 FP22EN 0 FP22 Function Select Bit. 0 = General-Purpose I/O, 1 = LCD Function. 3 FP21EN 0 FP21 Function Select Bit. 0 = General-Purpose I/O, 1 = LCD Function. 2 FP20EN 0 FP20 Function Select Bit. 0 = General-Purpose I/O, 1 = LCD Function. 1 to 0 Reserved 0 These bits should be left at 0 for proper operation.

Table 86. LCD Pointer SFR (LCDPTR, 0xAC) 5 to 0 ADDRESS 0 LCD Memory Address (see Table 89). Table 87. LCD Data SFR (LCDDAT, 0xAE) 7 to 0 LCDDATA 0 Data to be written into or read out of the LCD Memory SFRs. Table 88. LCD Segment Enable 2 SFR (LCDSEGE2, 0xED) 3 FP19EN 0 FP19 Function Select Bit. 0 = General-Purpose I/O, 1 = LCD function. 2 FP18EN 0 FP18 Function Select Bit. 0 = General-Purpose I/O, 1 = LCD function. 1 FP17EN 0 FP17 Function Select Bit. 0 = General-Purpose I/O, 1 = LCD function. 0 FP16EN 0 FP16 Function Select Bit. 0 = General-Purpose I/O, 1 = LCD function. LCD module to drive the type of LCD in the user end system. and the FP27 pin functionality to COM3. LCD segments FP0 to FP15 and FP26 are enabled by default. other shared pins, FP16 to FP25, can be enabled instead. addition, a faster refresh rate consumes more power. waveform frequency depends heavily on the multiplex level. the LCD Clock SFR (LCDCLK, 0x96). LCD Clock SFR (LCDCLK, 0x96); see Table 83 and Table 84.

a software controlled blink mode and an automatic blink mode. maintained in PSM2 operating mode. LCDPTR is transferred to the LCD Data SFR (LCDDAT , 0xAE). attached to FP14 and FP15, is as follows. Table 89. LCD Data Memory Accessed Indirectly Through LCD Pointer SFR (LCDPTR, 0xAC) and LCD Data SFR (LCDDAT, 0xAE)1, 2 1 COMx designates the common lines. 2 FPx designates the segment lines.

Table 90. Bits Controlling LCD Functionality in PSM2 Mode 0 0 The display is off in PSM2. 0 1 The display is on in PSM2. 1 X The display is off in PSM2. is retained when the display is turned off.

• Type of LCD: 5 V , 4× multiplexed with 1/3 bias, 96 segment
• Voltage generation: internal charge pump
• Refresh rate: 64 Hz A 96-segment LCD with 4× multiplexing requires 96/4 = 24 segment lines. Sixteen pins, FP0 to FP15, are automatically dedicated for use as LCD segments. Eight more pins must be chosen for the LCD function. Because the LCD has 4× multi- plexing, all four common lines are used. As a result, COM2/FP28 and COM3/FP27 cannot be used as segment lines. Based on the alternate functions of the pins used for FP16 through FP25, FP16 to FP23 are chosen for the eight remaining segment lines. These pins are enabled for LCD functionality in the LCD Segment Enable SFR (LCDSEGE, 0x97) and LCD Segment Enable 2 SFR (LCDSEGE2, 0xED). To determine contrast setting for this 5 V LCD, Table 80 shows the BIASLVL[5:0] setting that corresponds to a VC of 5 V in 1/3 bias mode. The maximal bias level setting for this LCD is BIASLVL[5:0] = [101110]. The LCD is setup with the following 8052 code: ; setup LCD pins to have LCD functionality MOV LCDSEG,#FP20EN+FP21EN+FP22EN+FP23EN MOV LCDSEGX,#FP16EN+FP17EN+FP18EN+FP19EN ; setup LCDCON for fLCDCLK=2048Hz, 1/3 bias and 4x multiplexing MOV LCDCON,#BIAS+LMUX1+LMUX0 ; setup LCDCONX for charge pump and BIASLVL[110111] MOV LCDCONX,#BIASLVL5+BIASLVL4+BIASLVL3+BIASLVL2+BIASLVL1+BIASLVL0 ; set up refresh rate for 64Hz with fLCDCLK=2048Hz MOV LCDCLK,#FD3+FD2+FD1+FD0 ; set up LCD data registers with data to be displayed using ; LCDPTR and LCDDATA registers ; turn all segments on FP27 ON and FP26 OFF ORL LCDCONY,#01h ; start data memory refresh MOV LCDDAT,#F0H MOV LCDPTR, #80h OR 0DH ANL LCDCONY,#0FEh ; end of data memory refresh ORL LCDCON,#LCDEN ; enable LCD To setup the same 3.3 V LCD for use with an external resistor ladder: ; setup LCDCONX for external resistor ladder MOV LCDCONX,#EXTRES

inappropriately modified during its execution. increments to continue with the next instruction. to operate as configured throughout the flash memory access. Table 92. Flash Control SFR (ECON, 0xB9) EADRL. Note that the byte being addressed must be pre-erased. EADRH/EADRL. Any address in the page can be written to EADRH/EADRL to select it for erasure. parallel download modes but should not be executed by user code. 4 Read Byte. The byte in the flash memory addressed by EADRH/EADRL is read into EDATA. EDATA is then written to the byte of flash memory addressed by EADRH/EADRL. 8 Protect Code (see the Protecting the Flash Memory section). Table 93. Flash Key SFR (FLSHKY, 0xBA) operation is allowed (see the Protecting the Flash Memory section). Table 94. Flash Protection Key SFR (PROTKY, 0xBB) and by writing 0x08 in the ECON SFR. This operation can only be done once. Table 95. Flash Data SFR (EDATA, 0xBC) 7 to 0 EDATA 0 Flash Pointer Data. Table 96. Flash Write/Erase Protection 0 SFR (PROTB0, 0xBD) (see the Protecting the Flash Memory section). Clearing the bits enables the protection. Table 97. Flash Write/Erase Protection 1 SFR (PROTB1, 0xBE) (see the Protecting the Flash Memory section). Clearing the bits enables the protection.

Table 98. Flash Read Protection SFR (PROTR, 0xBF) (see the Protecting the Flash Memory section). Clearing the bits enables the protection. Table 99. Flash Low Byte Address SFR (EADRL, 0xC6) Table 100. Flash High Byte Address SFR (EADRH, 0xC7) flash memory 0x3C00 is accessed. Write 0xF3 into flash memory byte 0x3C00. Erase the page containing flash memory byte 0x3C00. Erase all of the 16 kB flash memory. Read flash memory byte 0x3C00.

reserved emulator commands available only in download mode. Download Protocol, available at www.analog.com.

• Command with ASCII Code I or 0x49 writes the data into R0.
• Command with ASCII Code F or 0x46 writes R0 into the SFR address defined in the data of this command. By omitting the protocol defined in the uC004: Understanding the Serial Download Protocol application note, the sequence to load protections is similar to the sequence presented in the Enabling Flash Protection by Code section, except that two emulator commands are necessary to replace one assembly command. For example, to write the protection value in EADRH, the two following commands need to be executed:
• Command I with data = value of Protection Byte 0x3FFF .
• Command F with data = 0xC7. Following this protocol, the protection can be written to the flash using the same sequence as mentioned in the Enabling Flash Protection by Code section. When the part is reset, the protection is effective. Notes on Flash Protection The flash protection scheme is disabled by default so that none of the pages of the flash are protected from reading or writing/ erasing. The last page must be read and write/erase protected for the protection scheme to work. To activate the protection settings, the ADE7566/ADE7569/ ADE7166/ADE7169 must be reset after configuring the protection. After configuring protection on the last page and resetting the part, protections that have been enabled can only be removed by mass erasing the flash memory. The protection bits are read and erase protected by enabling read and write/erase protection on the last page, but the protection bits are never truly write protected. Protection bits can be modified from a 1 to a 0, even after the last page has been protected. In this way, more protection can be added but none can be removed. The protection scheme is intended to protect the end system. Pro- tection should be disabled while developing and emulating code. Flash Memory Timing Typical program and erase times for the flash memory are shown in Table 101.

Table 101. Flash Memory Program and and Erase Times configured throughout this period. read. Write/erase protected pages cannot be written or erased.

timers can be configured to operate as timers or as event counters. transition, the maximum count rate is half the core clock frequency. Table 102. Timer SFRs TCON 0x88 Yes Timer/Counter 0 and Timer/Counter 1 Control (see Table 104). TMOD 0x89 No Timer/Counter 0 and Timer./Counter 1 Mode (see Table 103). TL0 0x8A No Timer 0 Low Byte (see Table 107). TL1 0x8B No Timer 1 Low Byte (see Table 109). TH0 0x8C No Timer 0 High Byte (see Table 106). TH1 0x8D No Timer 1 High Byte (see Table 108). T2CON 0xC8 Yes Timer/Counter 2 Control (see Table 105). RCAP2L 0xCA No Timer 2 Reload/Capture Low Byte (see Table 113). RCAP2H 0xCB No Timer 2 Reload/Capture High Byte (see Table 112). TL2 0xCC No Timer 2 Low Byte (Table 111). TH2 0xCD No Timer 2 High Byte (see Table 110). Table 103. Timer/Counter 0 and Timer/Counter 1 Mode SFR (TMOD, 0x89) TR1 control is set. Cleared by software to enable Timer 1 whenever the TR1control bit is set. 6 C/T1 0 Timer 1 Timer or Counter Select Bit. Set by software to select counter operation (input from T1 pin). Cleared by software to select the timer operation (input from internal system clock). 00 TH1 operates as an 8-bit timer/counter. TL1 serves as 5-bit prescaler. 01 16-Bit Timer/Counter. TH1 and TL1 are cascaded; there is no prescaler. 10 8-Bit Autoreload Timer/Counter. TH1 holds a value to reload into TL1 each time it overflows. control bit is set. Cleared by software to enable Timer 0 whenever the TR0 control bit is set. 2 C/T0 0 Timer 0 Timer or Counter Select Bit. Set by software to the select counter operation (input from T0 pin). Cleared by software to the select timer operation (input from internal system clock). 00 TH0 operates as an 8-bit timer/counter. TL0 serves as a 5-bit prescaler. 01 16-Bit Timer/Counter. TH0 and TL0 are cascaded; there is no prescaler. 10 8-Bit Autoreload Timer/Counter. TH0 holds a value to reload into TL0 each time it overflows. 8-bit timer only, controlled by Timer 1 control bits.

Table 104. Timer/Counter 0 and Timer/Counter 1 Control SFR (TCON, 0x88) when the program counter (PC) vectors to the interrupt service routine. when the PC vectors to the interrupt service routine. the PC vectors to the interrupt service routine only if the interrupt was transition activated. to-0 transition. Cleared by software to specify level sensitive detection, that is, zero level. 0 transition. Cleared by software to specify level sensitive detection, that is, zero level. 1 These bits are not used to control Timer/Counter 0 and Timer/Counter 1 but are instead used to control and monitor the external INT0 and INT1 interrupt pins. Table 105. Timer/Counter 2 Control SFR (T2CON, 0xC8) RCLK = 1 or TCLK = 1. Cleared by user software. transition on T2EX pin and EXEN2 = 1. Cleared by user software. Timer 1 overflow to be used for the receive clock. Timer 1 overflow to be used for the transmit clock. user for Timer 2 to ignore events at T2EX. 2 0xCA TR2 0 Timer 2 Start/Stop Control Bit. Set by the user to start Timer 2. Cleared by the user to stop Timer 2. timer is forced to autoreload on Timer 2 overflow.

present on the single cycle core. 7 to 0 TH0 0 Timer 0 Data High Byte. Table 107. Timer 0 Low Byte SFR (TL0, 0x8A) 7 to 0 TL0 0 Timer 0 Data Low Byte. Table 108. Timer 1 High Byte SFR (TH1, 0x8D) 7 to 0 TH1 0 Timer 1 Data High Byte. Table 109. Timer 1 Low Byte SFR (TL1, 0x8B) In this mode, the timer register is configured as a 13-bit register. overflow flag, TF0. TF0 can then be used to request an interrupt. Table 110. Timer 2 High Byte SFR (TH2, 0xCD) 7 to 0 TH2 0 Timer 2 Data High Byte. Table 111. Timer 2 Low Byte SFR (TL2, 0xCC) INT0 = 1. Setting Gate0 = 1 allows the timer to be Timer/Counter 0 and Timer/Counter 1 Mode SFR (TMOD, 0x89). 7 to 0 TL2 0 Timer 2 Data Low Byte. Table 112. Timer 2 Reload/Capture High Byte SFR Table 113. Timer 2 Reload/Capture Low Byte SFR Capture Low Byte. Figure 96. operation are the same for both Timer 0 and Timer 1.

which is preset by software. The reload leaves TH0 unchanged.

2 Low Byte SFR (TL2, 0xCC), Timer 2 Reload/Capture High

Figure 97. Timer/Counter 0, Mode 2 Table 114. T2CON Operating Modes

1 X 1 Baud rate

extra 8-bit timer or counter. Figure 100. The baud rate generator mode is selected by RCLK = 1 and/or TCLK = 1. Figure 98. Timer/Counter 0, Mode 3 UART Serial Interface section.

819.2 kHz across all CD settings. then a new value is written to the POWCON SFR. 0xD8) to acknowledge the PLL fault, clearing the PLL_FLT bit. Table 115. Power Control SFR (POWCON, 0xC5) functions are not needed in PSM0. 5 Reserved 0 This bit should be kept at 0 for proper operation. 4 COREOFF 0 Set this bit to shut down th e core if in the PSM1 operating mode. Controls the core clock frequency (fCORE). fCORE = 4.096 MHz/2CD. Table 116. Key SFR (KYREG, 0xC1) 7 to 0 KYREG 0 Write 0xA7 to the KYREG SFR before writing to the POWCON SFR to unlock it.

Table 117. Peripheral Configuration SFR (PERIPH, 0xF4) 7 RXFLAG 0 If set, indicates that a Rx edge event triggered wake-up from PSM2. 5 VDD_OK 1 If set, indicates that V DD power supply is ok for operation. 4 PLL_FLT 0 If set, indicates that PLL is not locked. 2 Reserved 0 This bit should be kept to zero. Controls the function of the P1.0/RxD pin.

01 Rx with wake-up disabled

11 Rx with wake-up enabled

Table 118. Start ADC Measurement SFR (ADCGO, 0xD8) is generated if a reset was caused because the PLL lost lock. 6 to 3 0xDE to 0xDB Reserved 0 Reserved. when the measurement request is received by the ADC. the measurement request is received by the ADC. measurement request is received by the ADC.

Table 120. RTC Configuration SFR (TIMECON, 0xA1) interrupt must be serviced and the flag cleared to be allowed to enter PSM2. 0 256-Hour Mode. The HOUR register rolls over from 255 to 0.

6 TFH 0

1 24-Hour Mode. The HOUR register rolls over from 23 to 0. Interval Timer Timebase Selection. 0 The ALARM flag is set after INTVAL counts and then another interval count starts.

3 SIT 0

1 The ALARM flag is set after one time interval. by the user to indicate that the alarm event has been serviced. This bit cannot be set to 1 by user code. 0 The interval timer is disabled. The 8-bit interval timer counter is reset.

1 ITEN 0

0 Reserved 1 This bit must be left set for proper operation. Table 121. Hundredths of a Second Counter SFR (HTHSEC, 0xA2) reset or an external reset. It is reset after a POR. Table 122. Seconds Counter SFR (SEC, 0xA3) external reset. It is reset after a POR. Table 123. Minutes Counter SFR (MIN, 0xA4) external reset. It is reset after a POR. Table 124. Hours Counter SFR (HOUR, 0xA5) a watchdog reset or an external reset. It is reset after a POR.

Table 125. Alarm Interval SFR (INTVAL, 0xA6) Table 126. RTC Nominal Compensation SFR (RTCCOMP, 0xF6) a watchdog reset or an external reset. It is reset after a POR. Table 127. RTC Temperature Compensation SFR (TEMPCAL, 0xF7) retained during a watchdog reset or an external reset. It is reset after a POR. Table 128. Interrupt Pins Configuration SFR (INTPR, 0xFF) output on the P0.2/CF1/RTCCAL pin. Sets RTC calibration output frequency and calibration window. Controls the function of INT1. Controls the function of INT0. Table 129. Key SFR (KYREG, 0xC1) 7 to 0 KYREG 0 Write 0xA7 to the this SFR before writing to the POWCON SFR, which unlocks KYREG.

ADE7566/ADE7569/ADE7166/ADE7169 Rev. A | Page 119 of 144 READ AND WRITE OPERATIONS Writing to the RTC Registers The RTC circuitry runs off a 32.768 kHz clock. The timekeeping registers, Hundredths of a Second Counter SFR (HTHSEC, 0xA2), Seconds Counter SFR (SEC, 0xA3), Minutes Counter SFR (MIN, 0xA4), and Hours Counter SFR (HOUR, 0xA5), are updated with a 32.768 kHz clock. However, the RTC Configuration SFR (TIMECON, 0xA1) and Alarm Interval SFR (INTV AL, 0xA6) are updated with a 128 Hz clock. It takes up to two 128 Hz clock cycles from when the MCU writes to the TIMECON SFR or INTV AL SFR until there is a successful update in the RTC. To protect the RTC timekeeping registers from runaway code, a key must be written to the Key SFR (KYREG, 0xC1), which is described in Table 116, to obtain write access to the HTHSEC, SEC, MIN and HOUR SFRs. KYREG should be set to 0xEA to unlock the timekeeping registers and reset to 0 after a timekeeping register is written to. The RTC registers can be written to using the following 8052 assembly code: MOV RTCKey,#0EAh CALL UpdateRTC UpdateRTC: MOV KYREG,RTCKey MOV SEC,#30 MOV KYREG,RTCKey MOV MIN,#05 MOV KYREG,RTCKey MOV HOUR,#04 MOV KYREG,#00h RET Reading the RTC Counter SFRs The RTC cannot be stopped to read the current time because stopping the RTC introduces an error in its timekeeping. Therefore, the RTC is read on the fly, and the counter registers must be checked for overflow. This can be accomplished through the following 8052 assembly code: ReadAgain: MOV R0,HTHSEC ; using Bank 0 MOV R1,SEC MOV R2,MIN MOV R3,HOUR MOV A,HTHSEC CJNE A, 00h, ReadAgain ; 00h is R0 in Bank 0 RTC MODES The RTC can be configured in a 24-hour mode or a 256-hour mode. A midnight event is generated when the RTC hour counter rolls over from 23 to 0 or 255 to 0, depending on whether the TFH bit is set in the RTC Configuration SFR (TIMECON, 0xA1). The midnight event sets the MIDNIGHT flag in the TIMECON SFR, and a pending RTC interrupt is created. The RTC midnight event wakes the 8052 MCU core if the MCU is asleep in PSM2 when the midnight event occurs. In the 24-hour mode, the midnight event is generated once a day at midnight. The 24-hour mode is useful for updating a software calendar to keep track of the current day. The 256-hour mode results in power savings during extended operation in PSM2 because the MCU core wakes up less frequently. RTC INTERRUPTS The RTC midnight interrupt and alarm interrupt are enabled by setting the ETI bit in the Interrupt Enable and Priority 2 SFR (IEIP2, 0xA9). When a midnight or alarm event occurs, a pending RTC interrupt is generated. If the RTC interrupt is enabled, the program vectors to the RTC interrupt address and the pending interrupt is cleared. If the RTC interrupt is disabled, the RTC interrupt remains pending until the RTC interrupt is enabled. The program then vectors to the RTC interrupt address. The MIDNIGHT flag and ALARM flag are set when the midnight event and alarm event occur, respectively. The user should manage these flags to keep track of which event caused an RTC interrupt by servicing the event and clearing the appropriate flag in the RTC interrupt servicing routine. Note that if the ADE7566/ADE7569/ADE7166/ADE7169 are awakened by an RTC event, either by the MIDNIGHT event or ALARM event, the pending RTC interrupt must be serviced before the device can go back to sleep again. The ADE7566/ ADE7569/ADE7166/ADE7169 keep waking up until this interrupt has been serviced. Interval Timer Alarm The RTC can be used as an interval timer. When the interval timer is enabled by setting the ITEN bit in the RTC Configuration SFR (TIMECON, 0xA1), the interval timer clock source selected by the ITS1 and ITS0 bits is passed through an 8-bit counter. This counter increments on every interval timer clock pulse until it is equal to the value in the Alarm Interval SFR (INTV AL, 0xA6). Then, an alarm event is generated, setting the ALARM flag and creating a pending RTC interrupt. If the SIT bit in the RTC Configuration SFR (TIMECON, 0xA1) is cleared, the 8-bit counter is also cleared and starts counting again. If the SIT bit is set, the 8-bit counter is held in reset after the alarm occurs.

1. If the Alarm Interval SFR (INTV AL, 0xA6) is going to

64,000 cycles at a 4.096 MHz instruction cycle clock.

1. Disable the interval timer by clearing the ITEN bit in the

64,000 cycles at a 4.096 MHz instruction cycle clock.

1. Read the TIMECON SFR to ensure that the ITEN bit is

clear. If it is not, wait for another 128 Hz clock cycle.

1. Set the time-base bits (ITS[1:0]) in the TIMECON SFR to

in PSM2 when the alarm event occurs. which adds or subtracts pulses from the external crystal signal. subtracting additional pulses based on temperature. the sum of these two registers is limited to ±248 ppm. bit in the Interrupt Pins Configuration SFR (INTPR, 0xFF). 01 in the Interrupt Pins Configuration SFR (INTPR, 0xFF). and hours/125 instead of seconds, minutes, and hours. Therefore, this mode should be used for calibration only. Table 130. RTC Calibration Options 1 second/day error is equal to 11.57 ppm.

1 Errorsec/dayRTCCOMP ××=

configured in one of four modes.

• Shift register with baud rate fixed at fCORE/12
• 8-bit UART with variable baud rate
• 9-bit UART with baud rate fixed at fCORE/64 or fCORE/32
• 9-bit UART with variable baud rate Variable baud rates are defined by using an internal timer to generate any rate between 300 baud/second and 115,200 baud/second. The UART serial interface provided in the ADE7566/ADE7569/ ADE7166/ADE7169 is a full-duplex serial interface. It is also receive buffered by storing the first received byte in a receive buffer until the reception of the second byte is complete. The physical interface to the UART is provided via the RxD (P1.0) and TxD (P1.1) pins, while the firmware interface is through the SFRs presented in Table 131. Both the serial port receive and transmit registers are accessed through the Serial Port Buffer SFR (SBUF, 0x99). Writing to SBUF loads the transmit register, and reading SBUF accesses a physically separate receive register. An enhanced UART mode is offered by using the UART timer and by providing enhanced frame error, break error, and overwrite error detection. This mode is enabled by setting the EXTEN bit in the Configuration SFR (CFG, 0xAF) (see the UART Additional Features section). The Enhanced Serial Baud Rate Control SFR (SBAUDT, 0x9E) and UART Timer Fractional Divider SFR (SBAUDF, 0x9D) are used to configure the UART timer and to indicate the enhanced UART errors. UART REGISTERS

Table 131. Serial Port SFRs SCON 0x98 Yes Serial Communications Control Register (see Table 132). SBUF 0x99 No Serial Port Buffer (see Table 133). SBAUDT 0x9E No Enhanced Serial Baud Rate Control (see Table 134). SBAUDF 0x9D No UART Timer Fractional Divider (see Table 135). Table 132. Serial Communications Control Register Bit Description SFR (SCON, 0x98) UART Serial Mode Select Bits. These bits select the serial port operating mode. 00 Mode 0, shift register, fixed baud rate (fCORE/12). 01 Mode 1, 8-bit UART, variable baud rate. 10 Mode 2, 9-bit UART, fixed baud rate (fCORE/32) or (fCORE/16). 11 Mode 3, 9-bit UART, variable baud rate. Mode 2 and Mode 3, and framing error detection in Mode 1. In Mode 0, SM2 should be cleared. In Mode 1, if SM2 is set, RI is not activated if a valid stop bit was not received. If SM2 is cleared, RI is set as soon as the byte of data is received. In Mode 2 or Mode 3, if SM2 is set, RI is not activated if the received ninth data bit in RB8 is 0. If SM2 is cleared, RI is set as soon as the byte of data is received. 4 0x9C REN 0 Serial Port Receive Enable Bit. Set by user software to enable serial port reception. Cleared by user software to disable serial port reception. into RB8. For Mode 1, the stop bit is latched into RB8. at the beginning of the stop bit in Mode 1, Mode 2, and Mode 3. TI must be cleared by user software. halfway through the stop bit in Mode 1, Mode 2, and Mode 3. RI must be cleared by user software.

Table 133. Serial Port Buffer SFR (SBUF, 0x99) 7 to 0 SBUF 0 Serial Port Data Buffer. Table 134. Enhanced Serial Baud Rate Control SFR (SBAUDT, 0x9E) and updated every time a frame is received. updated every time a frame is received. 4, 3 SBTH1, SBTH0 0 Extended divider ratio for baud rate setting as shown in Table 136. 2, 1, 0 DIV2, DIV1, DIV0 0 Binary Divider. See Table 136. Table 135. UART Timer Fractional Divider SFR (SBAUDF, 0x9D) 7 UARTBAUDEN 0 UART Baud Rate Enable. Set to enable UART timer to generate the baud rate. When set, PCON.7 (SMOD), T2CON.4 (TCLK), and T2CON.5 (RCLK) are ignored. Cleared to let the baud rate be generated as per a standard 8052. 6 Not Implemented, Write Don’t Care. 5 SBAUDF.5 0 UART Timer Fractional Divider Bit 5. 4 SBAUDF.4 0 UART Timer Fractional Divider Bit 4. 3 SBAUDF.3 0 UART Timer Fractional Divider Bit 3. 2 SBAUDF.2 0 UART Timer Fractional Divider Bit 2. 1 SBAUDF.1 0 UART Timer Fractional Divider Bit 1. 0 SBAUDF.0 0 UART Timer Fractional Divider Bit 0.

Table 136. Common Baud Rates Using UART Timer with a 4.096 MHz PLL Clock

ADE7566/ADE7569/ADE7166/ADE7169 Rev. A | Page 125 of 144 T o transmit, the eight data bits must be written into the Serial Port Buffer SFR (SBUF, 0x99). The ninth bit must be written to TB8 in the Serial Communications Control Register Bit Description SFR (SCON, 0x98). When transmission is initiated, the eight data bits from SBUF are loaded into the transmit shift register (LSB first). The ninth data bit, held in TB8, is loaded into the ninth bit position of the transmit shift register. The transmission starts at the next valid baud rate clock. The transmit interrupt flag (TI) is set as soon as the transmission completes, when the stop bit appears on TxD. All of the following conditions must be met at the time the final shift pulse is generated to receive a character:

• If the extended UART is disabled (EXTEN = 0 in the CFG SFR), RI must be 0 to receive a character. This ensures that the data in SBUF is not overwritten if the last received character has not been read.
• If multiprocessor communication is enabled by setting SM2, the received ninth bit must be set to receive a character. This ensures that only frames with the ninth bit set, frames that contain addresses, generate a receive interrupt. If any of these conditions are not met, the received frame is irretrievably lost, and the receive interrupt flag (RI) is not set. Reception for Mode 2 is similar to that of Mode 1. The eight data bytes are input at RxD (LSB first) and loaded onto the receive shift register. If the received frame has met the previous criteria, the following events occur:
• The eight bits in the receive shift register are latched into the SBUF SFR.
• The ninth data bit is latched into RB8 in the SCON SFR.
• The receiver interrupt flag (RI) is set. Mode 3 (9-Bit UART with Variable Baud Rate) Mode 3 is selected by setting both SM0 and SM1. In this mode, the 8052 UART serial port operates in 9-bit mode with a variable baud rate. The baud rate is set by a timer overflow rate. Timer 1 or Timer 2 can be used to generate baud rates, or both timers can be used simultaneously where one generates the transmit rate and the other generates the receive rate. There is also a dedicated timer for baud rate generation, the UART timer, which has a fractional divisor to precisely generate any baud rate (see the UART Timer Generated Baud Rates section). The operation of the 9-bit UART is the same as for Mode 2, but the baud rate can be varied. In all four modes, transmission is initiated by any instruction that uses SBUF as a destination register. Reception is initiated in Mode 0 when RI = 0 and REN = 1. Reception is initiated in the other modes by the incoming start bit if REN = 1. UART BAUD RATE GENERATION Mode 0 Baud Rate Generation The baud rate in Mode 0 is fixed. ⎛= 12 COREfd RateMode 0 Bau Mode 2 Baud Rate Generation The baud rate in Mode 2 depends on the value of the PCON.7 (SMOD) bit in the Program Control SFR (PCON, 0x87). If SMOD = 0, the baud rate is 1/32 of the core clock. If SMOD = 1, the baud rate is 1/16 of the core clock. Mode 2 Baud Rate = 32 2SMOD × fCORE Mode 1 and Mode 3 Baud Rate Generation The baud rates in Mode 1 and Mode 3 are determined by the overflow rate of the timer generating the baud rate, that is, either Timer 1, Timer 2, or the dedicated baud rate generator, UART timer, which has an integer and fractional divisor. Timer 1 Generated Baud Rates When Timer 1 is used as the baud rate generator, the baud rates in Mode 1 and Mode 3 are determined by the Timer 1 overflow rate. The value of SMOD is as follows: Mode 1 or Mode 3 Baud Rate = ×32 2SMOD Timer 1 Overflow Rate The Timer 1 interrupt should be disabled in this application. The timer itself can be configured for either timer or counter operation, and in any of its three running modes. In the most typical application, it is configured for timer operation in autoreload mode (high nibble of TMOD = 0010 binary). In that case, the baud rate is given by the following formula: Mode 1 or Mode 3 Baud Rate = )256(32 TH1 fCORE SMOD Timer 2 Generated Baud Rates Baud rates can also be generated by using Timer 2. Using Timer 2 is similar to using Timer 1 in that the timer must overflow 16 times before a bit is transmitted or received. Because Timer 2 has a 16-bit autoreload mode, a wider range of baud rates is possible. Mode 1 or Mode 3 Baud Rate = 16 1 × Timer 2 Overflow Rate Therefore, when Timer 2 is used to generate baud rates, the timer increments every two clock cycles rather than every core machine cycle as before. It increments six times faster than Timer 1, and, therefore, baud rates six times faster are possible. Because Timer 2 has 16-bit autoreload capability, very low baud rates are still possible. Timer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in Timer/Counter 2 Control SFR (T2CON, 0xC8).

The SPI port can be configured for master or slave operation. Receive Buffer SFR (SPI2CRx, 0x9B). Configuration SFR (CFG, 0xAF) selects which peripheral is active. Table 137. SPI SFR List 0x9A SPI2CTx W 8 SPI/I2C Transmit Buffer (see Table 138). 0x9B SPI2CRx R 8 0 SPI/I2C Receive Buffer (see Table 139). 0xE8 SPIMOD1 R/W 8 0x10 SPI Configuration SFR 1 (see Table 140). 0xE9 SPIMOD2 R/W 8 0 SPI Configuration SFR 2 (see Table 141). 0xEA SPISTAT R/W 8 0 SPI/I2C Interrupt Status (see Table 142). Table 138. SPI/I2C Transmit Buffer SFR (SPI2CTx, 0x9A) input. When a write is requested, the FIFO output is sent on the SPI or I2C bus. Table 139. SPI/I2C Receive Buffer SFR (SPI2CRx, 0x9B) to SPI2CRx SFR. A new data byte from the SPI or I2C bus is written to the FIFO input.

Table 140. SPI Configuration SFR 1 (SPIMOD1, 0xE8) 5 0xED INTMOD 0 SPI Interrupt Mode. 0 SPI interrupt is set when SPI Rx buffer is full. 1 SPI interrupt is set when SPI Tx buffer is empty. 4 0xEC AUTO_SS 1 Master Mode, SS Output Control (see Figure 108). transmission and then returns high. continuous transfer and then returns high. 3 0xEB SS_EN 0 Slave Mode, SS Input Enable. 2 0xEA RxOFW 0 Receive Buffer Overflow Write Enable.

0 If the SPI2CRx SFR has not been read when a new data byte is received,

1 If the SPI2CRx SFR has not been read when a new data byte is received,

the new byte overwrites the old data. SPIR[1:0] 0 Master Mode, SPI SCLK Frequency.

Table 141. SPI Configuration SFR 2 (SPIMOD2, 0xE9) Master Mode, SPI Continuous Transfer Mode Enable Bit. be initiated after a stalled period.

7 SPICONT 0

remains asserted until the SPI2CTx SFR and the transmit shift registers are empty. 0 The SPI interface is disabled.

6 SPIEN 0

1 The SPI interface is enabled. SPI Open-Drain Output Configuration Bit. 0 Internal pull-up resistors are connected to the SPI outputs.

5 SPIODO 0

not exceed the specified operating voltage. 0 The SPI interface is defined as a slave.

4 SPIMS_b 0

1 The SPI interface is defined as a master. SPI Clock Polarity Configuration Bit (see Figure 110). sampled on the rising or falling edge of SCLK.

3 SPICPOL 0

input is sampled on the falling or rising edge of SCLK. SPI Clock Phase Configuration Bit (see Figure 110).

0 The SPI data output changes state when SS goes low at the second edge of SCLK and then every

2 SPICPHA 0

1 The SPI data output changes state at the first edge of SCLK and then every two subsequent

Master Mode, LSB First Configuration Bit. 0 The MSB of the SPI outputs is transmitted first.

1 SPILSBF 0

1 The LSB of the SPI outputs is transmitted first. Transfer and Interrupt Mode of the SPI Interface.

0 TIMODE 1

1 This bit must be left set for proper operation.

Table 142. SPI Interrupt Status SFR (SPISTAT, 0xEA) 0 The SPI peripheral is idle.

7 BUSY 0

1 The SPI peripheral is busy transferring data in slave or master mode. 0 A multiple master error has not occurred.

6 MMERR 0

1 If the SS_EN bit is set, enabling the slave select input and asserting the SS pin while the SPI

peripheral is transferring data as a master, this flag is raised to indicate the error. Write a 0 to this bit to clear it. SPI Receive Overflow Error Flag. Reading the SPI2CRx SFR clears this bit. 0 X The SPI2CRx register contains valid data.

5 SPIRxOF 0

transfer. If the RxOFW bit is set and this condition occurs, SPI2CRx is overwritten. SPI Receive Mode Interrupt Flag. Reading the SPI2CRx SFR clears this bit. 0 X The SPI2CRx register does not contain new data. and the SS pin is deasserted.

4 SPIRxIRQ 0

1 1 The SPI2CRx register contains new data. 3 SPIRxBF 0 Status Bit for SPI Rx Buffer. When set, the Rx FIFO is full. A read of the SPI2CRx clears this flag. 2 SPITxUF 0 Status Bit for SPI Tx Buffer. When set, the Tx FIFO is underflowing and data can be written into SPI2CTx. Write a 0 to this bit to clear it. SPI Transmit Mode Interrupt Flag. Writing new data to the SPI2CTx SFR clears this bit. 0 X The SPI2CTx register is full. 1 0 The SPI2CTx register is empty.

1 SPITxIRQ 0

stops, and the SS pin is deasserted. Write a 0 to this bit to clear it. 0 SPITxBF 0 Status Bit for SPI Tx Buffer. When set, the SPI Tx buffer is full. Write a 0 to this bit to clear it. (8-bit) serial data, MSB first. mode and as an input in slave mode. SPI Configuration SFR 2 (SPIMOD2, 0xE9). the same for the master and slave devices.

Configuration SFR (CFG, 0xAF) selects which peripheral is active. device ID. The LSB of this register contains a read/write request.

• I2CMOD
• SPI2CSTAT The transfer sequence of an I2C system consists of a master device initiating a transfer by generating a start condition while the bus is idle. The master transmits the address of the slave device and the direction of the data transfer in the initial address transfer. If the slave acknowledges, the data transfer is initiated. This continues until the master issues a stop condition and the bus becomes idle.
• I2CADR
• SPI2CTx
• SPI2CRx Because the SPI and I2C serial interfaces share the same pins, they also share the same SFRs, such as the SPI2CTx and SPIXCRx SFRs. In addition, the I2CMOD, I2CADR, SPI2CSTAT, and SPI2CTx SFRs are shared with the SPIMOD1, SPIMOD2, and SPISTAT SFRs, respectively. SERIAL CLOCK GENERATION The I2C master in the system generates the serial clock for a transfer. The master channel can be configured to operate in fast mode (256 kHz) or standard mode (32 kHz).

Table 144. I2C SFR List 0x9A SPI2CTx W 8 SPI/I2C Transmit Buffer (see Table 138). 0x9B SPI2CRx R 8 0 SPI/I2C Receive Buffer (see Table 139). 0xE8 I2CMOD R/W 8 0 I2C Mode (see Table 145). 0xE9 I2CADR R/W 8 0 I2C Slave Address (see Table 146). 0xEA SPI2CSTAT R/W 8 0 I2C Interrupt Status Register (see Table 147). Table 145. I2C Mode SFR (I2CMOD, 0xE8) I2CADR SFR starts a communication. 6 to 5 0xEE to 0xED I2CR[1:0] 0 I2C SCLK Frequency. I2CRCT, Bit[4:0] + 1 byte have been read or if an error occurs. Table 146. I2C Slave Address SFR (I2CADR, 0xE9) 7 to 1 I2CSLVADR 0 Address of the I2C Slave Being Addressed. Writing to this register starts the I2C transmission (read or write). to Logic 0, a write command is transmitted on the I2C bus. Data to slave is expected in the SPI2CTx SFR.

Table 147. I2C Interrupt Status Register SFR (SPI2CSTAT, 0xEA) 7 I2CBUSY 0 This bit is set to Logic 1 when the I2C interface is used. When set, the Tx FIFO is emptied. does not send an acknowledgement. The I2C communication is stopped after this event. Write a 0 to this bit to clear it. 5 I2CRxIRQ 0 I2C Receive Interrupt. This bit is set to Logic 1 when the receive FIFO is not empty. Write a 0 to this bit to clear it. 4 I2CTxIRQ 0 I2C Transmit Interrupt. This bit is set to Logic 1 when the transmit FIFO is empty. Write a 0 to this bit to clear it. used in I2C communication (receive or transmit) because only one FIFO is active at a time.

00 FIFO empty

01 Reserved

10 FIFO half full

11 FIFO full

1 I2CACC_ERR 0 Set when trying to write and read at the same time. Write a 0 to this bit to clear it. 0 I2CTxWR_ERR 0 Set when write was attempted when I2C transmit FIFO was full. Write a 0 to this bit to clear it. Figure 111. I2C Read Operation Figure 112. I2C Write Operation start condition and continues with the next communication. Mov a, spi2crx or Mov R0, spi2crx. does not transfer the right data into RAM Address 0x3d.

I2C receive and transmit FIFOs. needed in the transmit shift register, the communication stops. operation, the Tx FIFO is flushed.

4 BYTE FIFO

Figure 113. I2C FIFO Operation

Table 149. Extended Port Configuration SFR (EPCFG, 0x9F) 7 MOD38_FP21 0 Enable 38 kHz modulation on P1.6/FP21 pin. 6 MOD38_FP22 0 Enable 38 kHz modulation on P1.5/FP22 pin. 5 MOD38_FP23 0 Enable 38 kHz modulation on P1.4/T2/FP23 pin. 4 MOD38_TxD 0 Enable 38 kHz modulation on P1.1/TxD pin. 3 MOD38_CF1 0 Enable 38 kHz modulation on P0.2/CF1/RTCCAL pin. 2 MOD38_SSb 0 Enable 38 kHz modulation on P0.7/SS/T1pin. 1 MOD38_MISO 0 Enable 38 kHz modulation on P0.5/MISO pin. 0 MOD38_CF2 0 Enable 38 kHz modulation on P0.3/CF2 pin. Table 150. Port 0 Weak Pull-Up Enable SFR (PINMAP0, 0xB2) 7 PINMAP0.7 0 The weak pull-up on P0.7 is disabled when this bit is set. 6 PINMAP0.6 0 The weak pull-up on P0.6 is disabled when this bit is set. 5 PINMAP0.5 0 The weak pull-up on P0.5 is disabled when this bit is set. 4 PINMAP0.4 0 The weak pull-up on P0.4 is disabled when this bit is set. 3 PINMAP0.3 0 The weak pull-up on P0.3 is disabled when this bit is set. 2 PINMAP0.2 0 The weak pull-up on P0.2 is disabled when this bit is set. 1 PINMAP0.1 0 The weak pull-up on P0.1 is disabled when this bit is set. 0 PINMAP0.0 0 The weak pull-up on P0.0 is disabled when this bit is set. Table 151. Port 1 Weak Pull-Up Enable SFR (PINMAP1, 0xB3) 7 PINMAP1.7 0 The weak pull-up on P1.7 is disabled when this bit is set. 6 PINMAP1.6 0 The weak pull-up on P1.6 is disabled when this bit is set. 5 PINMAP1.5 0 The weak pull-up on P1.5 is disabled when this bit is set. 4 PINMAP1.4 0 The weak pull-up on P1.4 is disabled when this bit is set. 3 PINMAP1.3 0 The weak pull-up on P1.3 is disabled when this bit is set. 2 PINMAP1.2 0 The weak pull-up on P1.2 is disabled when this bit is set. 1 PINMAP1.1 0 The weak pull-up on P1.1 is disabled when this bit is set. 0 PINMAP1.0 0 The weak pull-up on P1.0 is disabled when this bit is set. Table 152. Port 2 Weak Pull-Up Enable SFR (PINMAP2, 0xB4) 7 to 6 Reserved 0 Reserved. Should be left cleared. 5 PINMAP2.5 0 The weak pull-up on RESET is disabled when this bit is set. 4 Reserved 0 Reserved. Should be left cleared. 3 PINMAP2.3 0 Reserved. Should be left cleared. 2 PINMAP2.2 0 The weak pull-up on P2.2 is disabled when this bit is set. 1 PINMAP2.1 0 The weak pull-up on P2.1 is disabled when this bit is set. 0 PINMAP2.0 0 The weak pull-up on P2.0 is disabled when this bit is set.

Table 153. Port 0 SFR (P0, 0x80) 7 0x87 T1 1 This bit reflects the state of P0.7/SS/T1 pin. It can be written or read. 6 0x86 T0 1 This bit reflects the state of P0.6/SCLK/T0 pin. It can be written or read. 5 0x85 1 This bit reflects the state of P0.5/MISO pin. It can be written or read. 4 0x84 1 This bit reflects the state of P0.4/MOSI/SDATA pin. It can be written or read. 3 0x83 CF2 1 This bit reflects the state of P0.3/CF2 pin. It can be written or read. 2 0x82 CF1 1 This bit reflects the state of P0.2/CF1 pin. It can be written or read. 1 0x81 1 This bit reflects the state of P0.1/FP19 pin. It can be written or read. 0 0x80 INT1 1 This bit reflects the state of BCTRL/INT1/P0.0 pin. It can be written or read. 1 When an alternate function is chosen for a pin of this port, the bit controlling this pin should always be set. Table 154. Port 1 SFR (P1, 0x90) 7 0x97 1 This bit reflects the state of P1.7/FP20 pin. It can be written or read. 6 0x96 1 This bit reflects the state of P1.6/FP2 pin. It can be written or read. 5 0x95 1 This bit reflects the state of P1.5/FP22 pin. It can be written or read. 4 0x94 T2 1 This bit reflects the state of P1.4/T2/FP23 pin. It can be written or read. 3 0x93 T2EX 1 This bit reflects the state of P1.3/T2EX/FP24 pin. It can be written or read. 2 0x92 1 This bit reflects the state of P1.2/FP25 pin. It can be written or read. 1 0x91 TxD 1 This bit reflects the state of P1.1/TxD pin. It can be written or read. 0 0x90 RxD 1 This bit reflects the state of P1.0/RxD pin. It can be written or read. 1 When an alternate function is chosen for a pin of this port, the bit controlling this pin should always be set. Table 155. Port 2 SFR (P2, 0xA0) 7 to 4 0x97 to 0x94 0x1F These bits are unused and should remain set. 3 0x93 P2.3 1 This bit reflects the state of P2.3/SDEN pin. It can be written only. 2 0x92 P2.2 1 This bit reflects the state of P2.2/FP16 pin. It can be written or read. 1 0x91 P2.1 1 This bit reflects the state of P2.1/FP17 pin. It can be written or read. 0 0x90 P2.0 1 This bit reflects the state of P2.0/FP18 pin. It can be written or read. 1 When an alternate function is chosen for a pin of this port, the bit controlling this pin should always be set.

Table 156. Port 0 Alternate Functions INT1 External Interrupt Set EX1 in the Interrupt Enable SFR (IE, 0xA8). P0.1 FP19 LCD Segment Pin Set FP19EN in the LCD Segment Enable 2 SFR (LCDSEGE2, 0xED). the SPI Configuration SFR 2 (SPIMOD2, 0xE9). the SPI Configuration SFR 2 (SPIMOD2, 0xE9). SPI Configuration SFR 2 (SPIMOD2, 0xE9) to enable the I2C or SPI interface. 0x89) to enable T0 as an external event counter. SS SPI Slave Select Input for SPI in Slave Mode Set the SS_EN bit in the SPI Configuration SFR 1 (SPIMOD1, 0xE8). SS SPI Slave Select Output for SPI in Master Mode Set the SPIMS_b bit in the SPI Configuration SFR 2 (SPIMOD2, 0xE9). 0x89) to enable T1 as an external event counter. Table 157. Port 1 Alternate Functions Rx Edge Wake-up from PSM2 Operating Mode Set RXPROG[1:0] = 11 in the Peripheral Configuration SFR (PERIPH, 0xF4). P1.1 TxD Transmitter Data Output for UART This pin becomes TxD as soon as data is written into SBUF. P1.2 FP25 LCD Segment Pin Set FP25EN in the LCD Segment Enable SFR (LCDSEGE, 0x97). T2EX Timer 2 Control Input Set EXEN2 in the Timer/Counter 2 Control SFR (T2CON, 0xC8). as an external event counter. P1.5 FP22 LCD Segment Pin Set FP22EN in the LCD Segment Enable SFR (LCDSEGE, 0x97). P1.6 FP21 LCD Segment Pin Set FP21EN in the LCD Segment Enable SFR (LCDSEGE, 0x97). P1.7 FP20 LCD Segment Pin Set FP20EN in the LCD Segment Enable SFR (LCDSEGE, 0x97). Table 158. Port 2 Alternate Functions P2.0 FP18 LCD Segment Pin Set FP18EN in the LCD Segment Enable 2 SFR (LCDSEGE2, 0xED). P2.1 FP17 LCD Segment Pin Set FP17EN in the LCD Segment Enable 2 SFR (LCDSEGE2, 0xED). P2.2 FP16 LCD Segment Pin Set FP16EN in the LCD Segment Enable 2 SFR (LCDSEGE2, 0xED).

ADE7566/ADE7569/ADE7166/ADE7169 Rev. A | Page 141 of 144 PORT 0 Port 0 is controlled directly through the bit-addressable Port 0 SFR (P0, 0x80). The weak internal pull-ups for Port 0 are configured through the Port 0 Weak Pull-Up Enable SFR (PINMAP0, 0xB2); they are enabled by default. The weak internal pull-up is disabled by writing a 1 to PINMAP0.x. Port 0 pins also have various secondary functions as described in Table 156. The alternate functions of Port 0 pins can be activated only if the corresponding bit latch in the Port 0 SFR contains a 1. Otherwise, the port pin remains at 0. PORT 1 Port 1 is an 8-bit bidirectional port controlled directly through the bit-addressable Port 1 SFR (P1, 0x90). The weak internal pull-ups for Port 1 are configured through the Port 1 Weak Pull-Up Enable SFR (PINMAP1, 0xB3); they are enabled by default. The weak internal pull-up is disabled by writing a 1 to PINMAP1.x. Port 1 pins also have various secondary functions as described in Table 157. The alternate functions of Port 1 pins can be activated only if the corresponding bit latch in the Port 1 SFR contains a 1. Otherwise, the port pin remains at 0. PORT 2 Port 2 is a 4-bit bidirectional port controlled directly through the bit-addressable Port 2 SFR (P2, 0xA0). Note that P2.3 can be used as an output only. Consequently, any read operation, such as a CPL P2.3, cannot be executed on this I/O. The weak internal pull-ups for Port 2 are configured through the Port 2 Weak Pull-Up Enable SFR (PINMAP2, 0xB4); they are enabled by default. The weak internal pull-up is disabled by writing a 1 to PINMAP2.x. Port 2 pins also have various secondary functions as described in Table 158. The alternate functions of Port 2 pins can be activated only if the corresponding bit latch in the Port 2 SFR contains a 1. Otherwise, the port pin remains at 0.

ADE7566/ADE7569/ADE7166/ADE7169 Rev. A | Page 142 of 144 DETERMINING THE VERSION OF THE ADE7566/ADE7569 Each ADE7566/ADE7569 holds in its internal flash registers a value that defines its version. This value helps to determine if users have the latest version of the part. The ADE7566/ADE756 version corresponding to this datasheet is ADE7566/ADE7569V3.4. To access this value, the following procedure can be followed: 1. Launch HyperTerminal with a 9600 baud rate. 2. Put the part in serial download mode by first holding SDEN to logic low then resetting the part 3. Hold the SDEN pin. 4. Press and release the RESET pin. 5. The following string should appear on the HyperTerminal screen: ADE7566V3.4 or ADE7569V3.4

Figure 116. 64-Lead Low Profile Quad Flat Package [LQFP]

0.65 TYP

0.05 MAX

0.02 NOM

0.60 MAX

Figure 117. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

ADE7566/ADE7569/ADE7166/ADE7169 Rev. A | Page 144 of 144 ORDERING GUIDE Model1 Anti- Tamper di/dt Sensor Interface VAR Flash (kB) Temperature Range Package Description Package Option ADE7566ACPZF82 No No No 8 −40°C to +85°C 64-Lead LFCSP_VQ CP-64-1 ADE7566ACPZF8-RL2 No No No 8 −40°C to +85°C 64-Lead LFCSP_VQ, Reel CP-64-1 ADE7566ACPZF162 No No No 16 −40°C to +85°C 64-Lead LFCSP_VQ CP-64-1 ADE7566ACPZF16-RL2 No No No 16 −40°C to +85°C 64-Lead LFCSP_VQ, Reel CP-64-1 ADE7566ASTZF82 No No No 8 −40°C to +85°C 64-Lead LQFP ST-64-2 ADE7566ASTZF8-RL2 No No No 8 −40°C to +85°C 64-Lead LQFP , Reel ST-64-2 ADE7566ASTZF162 No No No 16 −40°C to +85°C 64-Lead LQFP ST-64-2 ADE7566ASTZF16-RL2 No No No 16 −40°C to +85°C 64-Lead LQFP , Reel ST-64-2 ADE7569ACPZF162 No Yes Yes 16 −40°C to +85°C 64-Lead LFCSP_VQ CP-64-1 ADE7569ACPZF16-RL2 No Yes Yes 16 −40°C to +85°C 64-Lead LFCSP_VQ, Reel CP-64-1 ADE7569ASTZF162 No Yes Yes 16 −40°C to +85°C 64-Lead LQFP ST-64-2 ADE7569ASTZF16-RL2 No Yes Yes 16 −40°C to +85°C 64-Lead LQFP , Reel ST-64-2 ADE7166ACPZF82 Yes No No 8 −40°C to +85°C 64-Lead LFCSP_VQ CP-64-1 ADE7166ACPZF8-RL2 Yes No No 8 −40°C to +85°C 64-Lead LFCSP_VQ, Reel CP-64-1 ADE7166ACPZF162 Yes No No 16 −40°C to +85°C 64-Lead LFCSP_VQ CP-64-1 ADE7166ACPZF16-RL2 Yes No No 16 −40°C to +85°C 64-Lead LFCSP_VQ, Reel CP-64-1 ADE7166ASTZF82 Yes No No 8 −40°C to +85°C 64-Lead LQFP ST-64-2 ADE7166ASTZF8-RL2 Yes No No 8 −40°C to +85°C 64-Lead LQFP , Reel ST-64-2 ADE7166ASTZF162 Yes No No 16 −40°C to +85°C 64-Lead LQFP ST-64-2 ADE7166ASTZF16-RL2 Yes No No 16 −40°C to +85°C 64-Lead LQFP , Reel ST-64-2 ADE7169ACPZF162 Yes Yes Yes 16 −40°C to +85°C 64-Lead LFCSP_VQ CP-64-1 ADE7169ACPZF16-RL2 Yes Yes Yes 16 −40°C to +85°C 64-Lead LFCSP_VQ, Reel CP-64-1 ADE7169ASTZF162 Yes Yes Yes 16 −40°C to +85°C 64-Lead LQFP ST-64-2 ADE7169ASTZF16-RL2 Yes Yes Yes 16 −40°C to +85°C 64-Lead LQFP , Reel ST-64-2 ADE8052-PRG1 ADE Programmer ADE8052Z-PRG1 ADE Programmer ADE8052-DWDL1 ADE Downloader ADE8052Z- DWDL 1 ADE Downloader ADE8052-EMUL1 ADE Emulator ADE8052Z-EMUL1 ADE Emulator EVAL- ADE7169F16EBZ2 ADE7169 Evaluation Board EVAL- ADE7569F16EBZ2 ADE7569 Evaluation Board 1 All models have W + VA + rms, 5 V LCD, and RTC. 2 Z = RoHS Compliant Part. Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06353-0-12/07(A)