ADE7756BRS

ADE7756 AD | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 32

Technical content

REV.0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a ADE7756* Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001 Active Energy Metering IC with Serial Interface FUNCTIONAL BLOCK DIAGRAM MULTIPLIER DVDD HPF1 LPF2 DGND CLKOUT V1P V1N V2P V2N 2.4V REFERENCE ADC AVDD PGA CLKINREFIN/OUT CF RESET AGND 4k/H9024 /H9021 PHCAL[5:0] MULTIPLIER APOS[11:0] DFC DIN DOUT SCLK CS SAG ZX IRQ ADE7756 REGISTERS AND SERIAL INTERFACE ADE7756 TEMP SENSOR APGAIN[11:0] CFDIV[11:0]LPF1 ADC

FEATURES

High Accuracy, Supports IEC 687/1036 Less than 0.1% Error over a Dynamic Range of 1000 to 1 An On-Chip User Programmable Threshold for Line Voltage SAG Detection and PSU Supervisory The ADE7756 Supplies Sampled Waveform Data (20 Bits) and Active Energy (40 Bits) Digital Power, Phase and Input Offset Calibration An On-Chip Temperature Sensor ( /H115503/H11543C Typical after Calibration) An SPI-Compatible Serial Interface A Pulse Output with Programmable Frequency An Interrupt Request Pin (IRQ) and Status Register Provide Early Warning of Register Overflow and Other Conditions Proprietary ADCs and DSP Provide High Accuracy over Large Variations in Environmental Conditions and Time Reference 2.4 V /H11550 8% (20 ppm//H11543C Typical) with External Overdrive Capability Single 5 V Supply, Low Power (25 mW Typical) *U.S. Patents 5,745,323; 5,760,617; 5,862,069; 5,872,469; other pending. GENERAL DESCRIPTION The ADE7756 is a high-accuracy electrical power measurement IC with a serial interface and a pulse output. The ADE7756 incorporates two second-order sigma-delta ADCs, reference circuitry, temperature sensor, and all the signal processing required to perform active power and energy measurement. The ADE7756 contains a sampled Waveform register and an Active Energy register capable of holding at least five seconds of accumulated power at full load. Data is read from the ADE7756 via the serial interface. The ADE7756 also provides a pulse output (CF) with a frequency that is proportional to the active power. In addition to real power information, the ADE7756 also provides system calibration features, i.e., channel offset correction, phase calibration, and power calibration. The part also incorporates a detection circuit for short duration low voltage variations or sags. The voltage threshold level and the duration (in number of half- line cycles) of the variation are user programmable. An open drain logic output (SAG) goes active low when a sag event occurs. A zero crossing output (ZX) produces an output that is synchro- nized to the zero crossing point of the line voltage. This output can be used to extract timing or frequency inform ation from the line. The signal is also used intern ally to the chip in the calibration mode. This permits faster and more accurate calibration of the real power calculation. This signal is also useful for synchronization of relay switching with a voltage zero crossing, thus improving the relay life by reducing the risk of arcing. The interrupt request output is an open drain, active low logic output. The IRQ output will become active when the accumu- lated real power register is half-full and also when the register overflows. A status register indicates the nature of the interrupt. The ADE7756 is available in 20-lead DIP and 20-lead SSOP packages.

REV. 0 ADE7756 –2– SUSPENDING THE ADE7756 FUNCTIONALITY . . . . 26 Interrupt Status Register (04H)/Reset Interrupt TABLE OF CONTENTS

REV. 0 –3– ADE7756 SPECIFICATIONS1 Parameter A Version B Version Unit Test Conditions/Comments ENERGY MEASUREMENT ACCURACY Measurement Bandwidth 14 14 kHz CLKIN = 3.579545 MHz Measurement Error 1 on Channel 1 Channel 2 = 300 mV rms/60 Hz, Gain = 2 Channel 1 Range = 1 V Full Scale Gain = 1 0.1 0.1 % typ Over a Dynamic Range 1000 to 1 Gain = 2 0.1 0.1 % typ Over a Dynamic Range 1000 to 1 Gain = 4 0.1 0.1 % typ Over a Dynamic Range 1000 to 1 Gain = 8 0.1 0.1 % typ Over a Dynamic Range 1000 to 1 Gain = 16 0.1 0.1 % typ Over a Dynamic Range 1000 to 1 Channel 1 Range = 0.5 V Full Scale Gain = 1 0.1 0.1 % typ Over a Dynamic Range 1000 to 1 Gain = 2 0.1 0.1 % typ Over a Dynamic Range 1000 to 1 Gain = 4 0.1 0.1 % typ Over a Dynamic Range 1000 to 1 Gain = 8 0.1 0.1 % typ Over a Dynamic Range 1000 to 1 Gain = 16 0.2 0.2 % typ Over a Dynamic Range 1000 to 1 Channel 1 Range = 0.25 V Full Scale Gain = 1 0.1 0.1 % typ Over a Dynamic Range 1000 to 1 Gain = 2 0.1 0.1 % typ Over a Dynamic Range 1000 to 1 Gain = 4 0.1 0.1 % typ Over a Dynamic Range 1000 to 1 Gain = 8 0.2 0.2 % typ Over a Dynamic Range 1000 to 1 Gain = 16 0.2 0.2 % typ Over a Dynamic Range 1000 to 1 Phase Error1 Between Channels ±0.05 ±0.05 ° max Line Frequency = 45 Hz to 65 Hz, HPF On AC Power Supply Rejection 1 AVDD = DVDD = 5 V + 175 mV rms/120 Hz Output Frequency Variation (CF) 0.2 0.2 % typ Channel 1 = 20 mV rms/60 Hz, Gain = 16, Range = 0.5 V Channel 2 = 175 mV rms/60 Hz, Gain = 4 DC Power Supply Rejection 1 AVDD = DVDD = 5 V ± 250 mV dc Output Frequency Variation (CF) ±0.3 ±0.3 % typ Channel 1 = 20 mV rms/60 Hz, Gain = 16, Range = 0.5 V Channel 2 = 175 mV rms/60 Hz, Gain = 4 ANALOG INPUTS See Analog Inputs Section Maximum Signal Levels ± 1 ± 1 V max V1P, V1N, V2N and V2P to AGND Input Impedance (dc) 390 390 k Ω min Bandwidth 14 14 kHz CLKIN/256, CLKIN = 3.579545 MHz Gain Error1, 2 External 2.5 V Reference, Gain = 1 on Channel 1 and 2 Channel 1 Range = 1 V Full Scale ± 4 ± 4 % typ V1 = 1 V dc Range = 0.5 V Full Scale ± 4 ± 4 % typ V1 = 0.5 V dc Range = 0.25 V Full Scale ± 4 ± 4 % typ V1 = 0.25 V dc Channel 2 ± 4 ± 4 % typ V2 = 1 V dc Gain Error Match 1 External 2.5 V Reference Channel 1 Range = 1 V Full Scale ±0.3 ±0.3 % typ Gain = 1, 2, 4, 8, 16 Range = 0.5 V Full Scale ±0.3 ±0.3 % typ Gain = 1, 2, 4, 8, 16 Range = 0.25 V Full Scale ±0.3 ±0.3 % typ Gain = 1, 2, 4, 8, 16 Channel 2 ±0.3 ±0.3 % typ Gain = 1, 2, 4, 8, 16 Offset Error1 Channel 1 ±20 ±20 mV max Range = 1 V, Gain = 1 Channel 2 ±20 ±20 mV max Gain = 1 WAVEFORM SAMPLING Sampling CLKIN/128, 3.579545 MHz/128 = 27.9 kSPS Channel 1 See Channel 1 Sampling Signal-to-Noise Plus Distortion 62 62 dB typ 700 mV rms/60 Hz, Range = 1 V, Gain = 1 Bandwidth (–3 dB) 14 14 kHz CLKIN = 3.579545 MHz Channel 2 See Channel 2 Sampling Signal-to-Noise Plus Distortion 52 52 dB typ 300 mV rms/60 Hz, Gain = 2 Bandwidth (–3 dB) 156 156 Hz CLKIN = 3.579545 MHz (AVDD = DVDD = 5 V /H11550 5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN = 3.579545 MHz XTAL, TMIN to TMAX = –40 /H11543C to +85/H11543C, unless otherwise noted.)

REV. 0–4– ADE7756–SPECIFICATIONS Parameter A Version B Version Unit Test Conditions/Comments REFERENCE INPUT REFIN/OUT Input Voltage Range 2.6 2.6 V max 2.4 V + 8% 2.2 2.2 V min 2.4 V – 8% Input Capacitance 10 10 pF max ON-CHIP REFERENCE Nominal 2.4 V at REF IN/OUT Pin Reference Error ±200 ±200 mV max Load Current 10 10 µA max Output Impedance 4 4 k Ω min Temperature Coefficient ±20 ±20 ppm/ °C typ ±80 ppm/ °C max CLKIN Note All Specifications CLKIN of 3.579545 MHz Input Clock Frequency 10 10 MHz max 1 1 MHz min LOGIC INPUTS RESET, DIN, SCLK, CLKIN and CS Input High Voltage, V INH 2.4 2.4 V min DV DD = 5 V ± 5% Input Low Voltage, V INL 0.8 0.8 V max DV DD = 5 V ± 5% Input Current, I IN ± 3 ± 3 µA max Typically 10 nA, V IN = 0 V to DVDD Input Capacitance, C IN 10 10 pF max LOGIC OUTPUTS SAG and IRQ Open Drain Outputs, 10 k Ω Pull-Up Resistor Output High Voltage, V OH 4 4 V min I SOURCE = 5 mA Output Low Voltage, V OL 0.4 0.4 V max I SINK = 0.8 mA ZX and DOUT Output High Voltage, V OH 4 4 V min I SOURCE = 5 mA Output Low Voltage, V OL 0.4 0.4 V max I SINK = 0.8 mA CF Output High Voltage, V OH 4 4 V min I SOURCE = 5 mA Output Low Voltage, V OL 0.4 0.4 V max I SINK = 7 mA POWER SUPPLY For Specified Performance AVDD 4.75 4.75 V min 5 V – 5% 5.25 5.25 V max 5 V + 5% DVDD 4.75 4.75 V min 5 V – 5% 5.25 5.25 V max 5 V + 5% AIDD 3 3 mA max Typically 2.0 mA DIDD 4 4 mA max Typically 3.0 mA NOTES 1See Terminology section for explanation of specifications. 2See plots in Typical Performance Characteristic curves. 3See Analog Inputs section. Specifications subject to change without notice

t1 20 ns (min) CS falling edge to first SCLK falling edge. t2 150 ns (min) SCLK logic high pulsewidth. t3 150 ns (min) SCLK logic low pulsewidth. t4 10 ns (min) Valid Data Setup time before falling edge of SCLK. t5 5 ns (min) Data Hold time after SCLK falling edge. t6 6.4 µs (min) Minimum time between the end of data byte transfers. t7 4 µs (min) Minimum time between byte transfers during a serial write. t8 100 ns (min) CS Hold time after SCLK falling edge. t10 4 µs (min) Minimum time between data byte transfers during a multibyte read. 4 100 ns (max) Bus relinquish time after falling edge of SCLK. 4 100 ns (max) Bus relinquish time after rising edge of CS. 90%) and timed from a voltage level of 1.6 V. 2See timing diagram below and Serial Interface section of this data sheet. 3Measured with the load circuit in Load Circuit for Timing Specifications and defined as the time required for the output to cross 0.8 V or 2.4 V. is the true bus relinquish time of the part and is independent of the bus loading. Specifications subject to change without notice. Figure 1. Load Circuit for Timing Specifications

1 DB0 DB7 DB0

Figure 2. Serial Write Timing Figure 3. Serial Read Timing

REV. 0 ADE7756 –6– CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADE7756 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE ABSOLUTE MAXIMUM RATINGS * (TA = 25°C unless otherwise noted) Analog Input Voltage to AGND Operating Temperature Range Lead Temperature, Soldering *Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ORDERING GUIDE Model Package Description Package Option ADE7756AN Plastic DIP N-20 ADE7756BN Plastic DIP N-20 ADE7756ARS Shrink Small Outline Package in Tubes RS-20 ADE7756ARSRL Shrink Small Outline Package in Tubes RS-20 ADE7756BRS Shrink Small Outline Package in Tubes RS-20 ADE7756BRSRL Shrink Small Outline Package in Reel RS-20 EVAL-ADE7756EB ADE7756 Evaluation Board ADE7756AN-REF ADE7756 Reference Design PIN CONFIGURATION DIP and SSOP Packages TOP VIEW (Not to Scale) ADE7756 DGND REFIN/OUT AGND DVDD AVDD V1P V2P V2N V1N CF ZX SAG DOUT SCLK CS IRQ CLKIN CLKOUT RESET DIN

REV. 0 ADE7756 –7– PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Description 1 RESET Reset Pin for the ADE7756. A logic low on this pin will hold the ADCs and digital circuitry (including the Serial Interface) in a reset condition. 2D V DD Digital Power Supply. This pin provides the supply voltage for the digital circuitry in the ADE7756. The supply voltage should be maintained at 5 V ± 5% for specified operation. This pin should be decoupled to DGND with a 10 µF capacitor in parallel with a ceramic 100 nF capacitor. 3A V DD Analog Power Supply. This pin provides the supply voltage for the analog circuitry in the ADE7756. The supply should be maintained at 5 V ± 5% for specified operation. Every effort should be made to minimize power supply ripple and noise at this pin by the use of proper decoupling. The typical per- formance graphs in this data sheet show the power supply rejection performance. This pin should be decoupled to AGND with a 10 µF capacitor in parallel with a ceramic 100 nF capacitor. 4, 5 V1P, V1N Analog Inputs for Channel 1. This channel is intended for use with the current transducer. These inputs are fully differential voltage inputs with maximum differential input signal levels of ±1 V, ±0.5 V and ±0.25 V, depending on the full-scale selection. See Analog Inputs section. Channel 1 also has a PGA with gain selections of 1, 2, 4, 8, or 16. The maximum signal level at these pins with respect to AGND is ±1 V. Both inputs have internal ESD protection circuitry and in addition an overvoltage of ±6 V can be sustained on these inputs without risk of permanent damage. 6, 7 V2N, V2P Analog Inputs for Channel 2. This channel is intended for use with the voltage transducer. These inputs are fully differential voltage inputs with a maximum differential signal level of ±1 V. Channel 2 also has a PGA with gain selections of 1, 2, 4, 8, or 16. The maximum signal level at these pins with respect to AGND is ±1 V. Both inputs have internal ESD protection circuitry, and an overvoltage of ±6 V can be sustained on these inputs without risk of permanent damage. 8 AGND This pin provides the ground reference for the analog circuitry in the ADE7756, i.e., ADCs and refer- ence. This pin should be tied to the analog ground plane or the quietest ground r eference in the system. This quiet ground reference should be used for all analog circuitry, e.g., antialiasing filters, current and voltage transducers, etc. In order to keep ground noise around the ADE7756 to a minimum, the quiet ground plane should only be connected to the digital ground plane at one point. It is acceptable to place the entire device on the analog ground plane—see Applications Information section.

9 REF

IN/OUT This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of 2.4 V ± 8% and a typical temperature coefficient of 20 ppm/ °C. An external reference source may also be connected at this pin. In either case this pin should be decoupled to AGND with a 1 µF ceramic capacitor. 10 DGND This provides the ground reference for the digital circuitry in the ADE7756, i.e., multiplier, filters, and digital-to-frequency converter. Because the digital return currents in the ADE7756 are small, it is acceptable to connect this pin to the analog ground plane of the system—see Applications Information section. However, high bus capacitance on the DOUT pin may result in noisy digital current which could affect performance. 11 CF Calibration Frequency Logic Output. The CF logic output gives Active Power information. This out- put is intended to be used for operational and calibration purposes. The full-scale output frequency can be adjusted by writing to the CFDIV Register—see Energy To Frequency Conversion section . 12 ZX Voltage Waveform (Channel 2) Zero Crossing Output. This output toggles logic high and low at the zero crossing of the differential signal on Channel 2—see Zero Crossing Detection section. 13 SAG This open drain logic output goes active low when either no zero crossings are detected or a low volt- age threshold (Channel 2) is crossed for a specified duration. See Line Voltage Sag Detection section. 14 IRQ Interrupt Request Output. This is an active low open drain logic output. Maskable interrupts include: Active Energy Register roll-over, Active Energy Register at half level, and arrivals of new waveform samples—see Interrupts section. 15 CLKIN Master clock for ADCs and digital signal processing. An external clock can be provided at this logic input. Alternatively, a parallel resonant AT crystal can be connected across CLKIN and CLKOUT to provide a clock source for the ADE7756. The clock frequency for specified operation is 3.579545 MHz. Ceramic load capacitors of between 22 pF and 33 pF should be used with the gate oscillator circuit. Refer to crystal manufacturers data sheet for load capacitance requirements. 16 CLKOUT A crystal can be connected across this pin and CLKIN as described above to provide a clock source for the ADE7756. The CLKOUT pin can drive one CMOS load when either an external clock is supplied at CLKIN or a crystal is being used.

REV. 0 ADE7756 –8– Pin No. Mnemonic Description 17 CS Chip Select. Part of the 4-Wire SPI Serial Interface. This active low logic input allows the ADE7756 to share the serial bus with several other devices—see Serial Interface section. 18 SCLK Serial Clock Input for the Synchronous Serial Interface. All Serial data transfers are synchronized to this clock. See Serial Interface section. The SCLK has a Schmitt-trigger input for use with a clock source that has a slow edge transition time, e.g., opto-isolator outputs. 19 DOUT Data Output for the Serial Interface. Data is shifted out at this pin on the rising edge of SCLK. This logic output is normally in a high impedance state unless it is driving data onto the serial data bus— see Serial Interface section. 20 DIN Data Input for the Serial Interface. Data is shifted in at this pin on the falling edge of SCLK—see Serial Interface section. TERMINOLOGY MEASUREMENT ERROR The error associated with the energy measurement made by the ADE7756 is defined by the following formula: Percentage Error = Energy by ADE True Energy True Energy Registered 7756 100– %  × PHASE ERROR BETWEEN CHANNELS The HPF (High-Pass Filter) in Channel 1 has a phase lead response. To offset this phase response and equalize the phase response between channels, a phase correction network is also placed in Channel 1. The phase correction network ensures a phase match between Channel 1 (current) and Channel 2 (volt- age) to within ±0.1° over a range of 45 Hz to 65 Hz and ±0.2° over a range 40 Hz to 1 kHz. POWER SUPPLY REJECTION This quantifies the ADE7756 measurement error as a percent- age of reading when the power supplies are varied. For the ac PSR measurement, a reading at nominal supplies (5 V) is taken. A second reading is obtained with the same input signal levels when an ac (175 mV rms/120 Hz) signal is introduced onto the supplies. Any error introduced by this ac signal is expressed as a percentage of reading—see Measurement Error definition above. For the dc PSR measurement, a reading at nominal supplies (5 V) is taken. A second reading is obtained with the same input signal levels when the supplies are varied ±5%. Any error intro- duced is again expressed as a percentage of reading. ADC OFFSET ERROR This refers to the dc offset associated with the analog inputs to the ADCs. It means that with the analog inputs connected to AGND the ADCs still see a dc analog input signal. The magni- tude of the offset depends on the gain and input range selection —see Typical Performance Characteristics. However, when HPF1 is switched on the offset is removed from Channel 1 (current) and the power calculation is not affected by this offset. The offsets may be removed by performing an offset calibration—see Analog Inputs section. GAIN ERROR The gain error in the ADE7756 ADCs is defined as the differ- ence between the measured ADC output code (minus the offset) and the ideal output code—see Channel 1 ADC and Channel 2 ADC section. It is measured for each of the input ranges on Channel 1 (1 V, 0.5 V and 0.25 V ). The difference is expressed as a percentage of the ideal code. GAIN ERROR MATCH The Gain Error Match is defined as the gain error (minus the offset) obtained when switching between a gain of 1 (for each of the input ranges) and a gain of 2, 4, 8, or 16. It is expressed as a percentage of the output ADC code obtained under a gain of 1. This gives the gain error observed when the gain selection is changed from 1 to 2, 4, 8, or 16.

REV. 0 –9– Typical Performance Characteristics– ADE7756 AMPS 0.01 % ERROR –0.50 –0.40 –0.30 –0.20 –0.10 0.10 0.20 0.30 0.40 0.50 0.10 1.0 10.0 100.0 PF = 1 GAIN = 1 ON-CHIP REFERENCE –40/H11543C +25/H11543C +85/H11543C TPC 1. Error as a % of Reading (Power Factor = 1, Internal Reference, Gain = 1) AMPS 0.01 % ERROR –0.50 –0.40 –0.30 –0.20 –0.10 0.10 0.20 0.30 0.40 0.50 0.10 1.0 10.0 100.0 PF = 1 GAIN = 2 ON-CHIP REFERENCE –40/H11543C +25/H11543C +85/H11543C TPC 2. Error as a % of Reading (Power Factor = 1, Internal Reference, Gain = 2) AMPS 0.01 % ERROR –0.50 –0.40 –0.30 –0.20 –0.10 0.10 0.20 0.30 0.40 0.50 0.10 1.0 10.0 100.0 PF = 1 GAIN = 4 ON-CHIP REFERENCE –40/H11543C +25/H11543C +85/H11543C TPC 3. Error as a % of Reading (Power Factor = 1, Internal Reference, Gain = 4) AMPS 0.01 % ERROR –0.50 –0.40 –0.30 –0.20 –0.10 0.10 0.20 0.30 0.40 0.50 0.10 1.0 10.0 100.0 PF = 0.5 GAIN = 1 ON-CHIP REFERENCE –40/H11543C, PF = 0.5 +25/H11543C, PF = 0.5 +85/H11543C, PF = 0.5 +25/H11543C, PF = 1.0 TPC 4. Error as a % of Reading (Power Factor = 0.5, Internal Reference, Gain = 1) AMPS 0.01 % ERROR –0.50 –0.40 –0.30 –0.20 –0.10 0.10 0.20 0.30 0.40 0.50 0.10 1.0 10.0 100.0 PF = 0.5 GAIN = 2 ON-CHIP REFERENCE –40/H11543C, PF = 0.5 +25/H11543C, PF = 0.5 +85/H11543C, PF = 0.5 +25/H11543C, PF = 1.0 TPC 5. Error as a % of Reading (Power Factor = 0.5, Internal Reference, Gain = 2) AMPS 0.01 % ERROR –0.50 –0.40 –0.30 –0.20 –0.10 0.10 0.20 0.30 0.40 0.50 0.10 1.0 10.0 100.0 PF = 0.5 GAIN = 4 ON-CHIP REFERENCE –40/H11543C, PF = 0.5 +25/H11543C, PF = 0.5 +85/H11543C, PF = 0.5 +25/H11543C, PF = 1.0 TPC 6. Error as a % of Reading (Power Factor = 0.5, Internal Reference, Gain = 4)

REV. 0 ADE7756 –10– AMPS 0.01 % ERROR –0.50 –0.40 –0.30 –0.20 –0.10 0.10 0.20 0.30 0.40 0.50 0.10 1.0 10.0 100.0 PF = 1 GAIN = 8 ON-CHIP REFERENCE –40/H11543C +25/H11543C +85/H11543C TPC 7. Error as a % of Reading (Power Factor = 1, Internal Reference, Gain = 8) AMPS 0.01 % ERROR –0.50 –0.40 –0.30 –0.20 –0.10 0.10 0.20 0.30 0.40 0.50 0.10 1.0 10.0 100.0 PF = 1 GAIN = 16 ON-CHIP REFERENCE –40/H11543C +25/H11543C +85/H11543C TPC 8. Error as a % of Reading (Power Factor = 1, Internal Reference, Gain = 16) AMPS 0.01 % ERROR –0.50 –0.40 –0.30 –0.20 –0.10 0.10 0.20 0.30 0.40 0.50 0.10 1.0 10.0 100.0 PF = 1 GAIN = 1 EXTERNAL REFERENCE –40/H11543C +25/H11543C +85/H11543C TPC 9. Error as a % of Reading (Power Factor = 1, External Reference, Gain = 1) AMPS 0.01 % ERROR –0.50 –0.40 –0.30 –0.20 –0.10 0.10 0.20 0.30 0.40 0.50 0.10 1.0 10.0 100.0 PF = 0.5 GAIN = 8 ON-CHIP REFERENCE –40/H11543C, PF = 0.5 +25/H11543C, PF = 0.5 +85/H11543C, PF = 0.5 +25/H11543C, PF = 1.0 TPC 10. Error as a % of Reading (Power Factor = 0.5, Internal Reference, Gain = 8) AMPS 0.01 % ERROR –0.50 –0.40 –0.30 –0.20 –0.10 0.10 0.20 0.30 0.40 0.50 0.10 1.0 10.0 100.0 PF = 0.5 GAIN = 16 ON-CHIP REFERENCE –40/H11543C, PF = 0.5 +25/H11543C, PF = 0.5 +85/H11543C, PF = 0.5 +25/H11543C, PF = 1.0 TPC 11. Error as a % of Reading (Power Factor = 0.5, Internal Reference, Gain = 16) AMPS 0.01 % ERROR –0.50 –0.40 –0.30 –0.20 –0.10 0.10 0.20 0.30 0.40 0.50 0.10 1.0 10.0 100.0 PF = 1 GAIN = 2 EXTERNAL REFERENCE –40/H11543C +85/H11543C +25/H11543C TPC 12. Error as a % of Reading (Power Factor = 1, External Reference, Gain = 2)

REV. 0 ADE7756 –11– 33nF 1k/H9024 RB RB 1k/H9024 33nF 33nF1k/H9024 33nF1k/H9024 1M/H9024 100nF10/H9262F AVDD DVDD RESET 10/H9262F 40A TO 40mA VDD 100nF 10/H9262F V1P V1N V2N V2P REFIN/OUT DOUT SCLK CS CLKOUT CLKIN IRQ DIN SAG ZX CF AGND DGND 22pF TO FREQUENCY COUNTER NOT CONNECTED TO SPI BUS (USED ONLY FOR CALIBRATION) 110V 15.8/H9024 7.5/H9024 4.0/H9024 2.0/H9024 1.0/H9024 GAIN(CH1) CT TURN RATIO = 1800:1 CHANNEL 2 GAIN = 4 RB ADE7756 100nF 3.58MHz 22pF PS2501-1 TPC 13. Test Circuit for Performance Curves AMPS 0.01 % ERROR –0.50 –0.40 –0.30 –0.20 –0.10 0.10 0.20 0.30 0.40 0.50 0.10 1.0 10.0 100.0 5.25V 4.75V 5.0V TPC 14. PSR with Internal Reference FREQUENCY – Hz % ERROR –0.6 50 55 60 PF = 1 –0.4 –0.2 0.2 0.4 0.6 0.8 65 70 75 PF = 0.5 TPC 15. Error as a % of Reading over Frequency AMPS 0.01 % ERROR –0.50 –0.40 –0.30 –0.20 –0.10 0.10 0.20 0.30 0.40 0.50 0.10 1.0 10.0 100.0 5.25V 4.75V 5.0V TPC 16. PSR with External Reference

The ADE7756 has two fully differential voltage input channels. also ±1 V with respect to AGND. Amplifier) with possible gain selections of 1, 2, 4, 8, and 16. Channel 1 is made using the Gain register. Figure 4. PGA in Channel 1 maximum ADC input voltage can be set to 1 V, 0.5 V, or 0.25 V.

1 V Gain = 1

0.5 V Gain = 2 Gain = 1

0.25 V Gain = 4 Gain = 2 Gain = 1

0.125 V Gain = 8 Gain = 4 Gain = 2

0.0625 V Gain = 16 Gain = 8 Gain = 4

0.0313 V Gain = 16 Gain = 8

0.0156 V Gain = 16

Figure 5. Analog Gain Register Power signal in the Active Energy register (AENERGY[39:0]). See Energy Calculation section. Figure 6. Effect of Channel Offsets on the Real Power

6 HALF-CYCLES

Figure 9. ADE7756 Sag Detection in the Sag Level register (SAGLVL[7:0]) for nine half-cycles. active low—see ADE7756 Interrupts section. on Channel 2 first dropped below the threshold level. the contents of the sag level register are greater. The ADE7756 also contains an on-chip power supply monitor. correct device operation at power-up and during power-down. The power supply monitor has built-in hysteresis and filtering. Figure 10. On-Chip Power Supply Monitor specified for normal operation.

Figure 32. Energy-to-Frequency Conversion ditions the output frequency is proportional to the Active Power. with the CFDIV register = 0.

1. The output frequency is given in Equation 9.

CFDIV register. The power-up default value in CFDIV is 3Fh. is shown by the dashed straight line and is equal to V × I × t.

REV. 0 ADE7756 –25– Assuming the meter is set up with a test current (basic current) of 20 A and a line voltage of 220 V for calibration, the load is calculated as 220 V × 20 A = 4.4 kW. Therefore the expected output frequency on CF under this steady load condition would be 4.4 × 0.8888 Hz = 3.9111 Hz. Under these load conditions the transducers on Channel 1 and Channel 2 should be selected such that the signal on the voltage channel should see approximately half scale and the signal on the current channel about 1/8 of full scale (assuming a maximum current of 80A). The average value from LPF2 is calculated as 3,276.81 decimal using the calibration mode as described above. Then, using Equation 8 (Energy to Frequency Conver- sion), the frequency under this load is calculated as: Frequency CF MHz Hz() .. .= × =3276 81 3 579545 2 349 56625 However, this is the frequency with the contents of the CFDIV and APGAIN registers equal to 000h. The desired frequency out is 3.9111 Hz. Therefore the CF frequency must be divided by 349.566/3.9111 Hz or 89.378 decimal. This is achieved by loading the CF Divide register with 88 (or 58h)—Note the CF frequency is divided by the contents of CFDIV + 1. The fine adjustment of the output frequency can be made using the Active Power Gain register. This register has a fine gain adjustment of 0.0244%/LSB. With the CF Divide register con- tents equal to 58h, the output frequency is given as 349.556 Hz/ 89 = 3.9276 Hz. This setting has an error of 0.42%. This error can be further reduced by writing –(0.21/0.0244) or –17 to APGAIN[11:0] i.e., FEFh. Calibrating CF is made easy by using the Calibration mode on the ADE7756. The only critical part of the setup is that the line frequency be exactly known. If this is not possible, it could be measured by using the ZX output of the ADE7756. Energy Meter Display Besides the pulse output which is used to verify calibration, a solid state energy meter will very often require some form of display. The display should display the amount of energy con- sumed in kWh (Kilowatt Hours). One convenient and simple way to interface the ADE7756 to a display or energy register (e.g., MCU with nonvolatile memory) is to use CF. For example the CF frequency could be calibrated to 1,000 imp/kWh. The MCU would count pulses from CF. Every pulse would be equivalent to 1 watt-hour. If more resolution is required the CF frequency could be set to, say, 10,000 imp/kWh. If more flexibility is required when monitoring energy usage, the Active Energy register (AENERGY) can be used to calculate energy. A full description of this register can be found in the Energy Calculation section. The AENERGY register gives the user both sign and magnitude information regarding energy consumption. On completion of the CF frequency output cali- bration, i.e., after the Active Power Gain (APGAIN) register has been adjusted, a second calibration sequence can be initiated. The purpose of this second calibration routine is to determine a kWh/LSB coefficient for the AENERGY register. Once the coefficient has been calculated the MCU can determine the energy consumption at any time by reading the AENERGY contents and multiplying by the coefficient to calculate kWh. CLKIN FREQUENCY In this data sheet, the characteristics of the ADE7756 are shown with CLKIN frequency equal to 3.579545 MHz. However, the ADE7756 is designed to have the same accuracy at any CLKIN frequency within the specified range. If the CLKIN frequency is not 3.579545 MHz, various timing and filter characteristics will need to be redefined with the new CLKIN frequency. For example, the cut-off frequencies of all digital filters (LPF1, LPF2, HPF1, etc.) will shift in proportion to the change in CLKIN frequency according to the following equation: New Frequency Original Frequency CLKIN Frequency MHz=× 3 579545. (17) The change of CLKIN frequency does not affect the timing characteristics of the serial interface because the data transfer is synchronized with serial clock signal (SCLK). But one needs to observe the read/write timing of the serial data transfer-see Timing Characteristics. Table III lists various timing changes that are affected by CLKIN frequency.

APPLICATION INFORMATION

Application note AN-564 contains detail information on how to design a ANSI Class 100 Watt-Hour meter based on the ADE7756. It is available from the ADE7756 product home page under the Application Note link. Figure 35 shows the block dia- gram of the ADE7756 reference meter implemented in AN-564. RS-232 220V LOAD L1 L2N ADE7756 16/H115472 LCD DISPLAY EEPROM SPI BUS PIC16C62B CF Figure 35. Block Diagram of the ADE7756 Reference

The analog and the digital circuit can be suspended separately. circuitry can be halted by holding the CLKIN input to 0 or 1. and setting the ASUSPEND bit to logic low. must begin with a write to the Communications register. Figure 36. Addressing ADE7756 Registers via the and write operation respectively. once again enters Communications Mode.

00 ADDRESS

1 MULTIBYTE WRITE DATA

low), a write to the Communications register first takes place. shifting in the register data on the next falling edge of SCLK. edge of subsequent SCLK pulses—see Figure 38. to the destination register.

the 12-bit word. Figure 39 illustrates this example. preceded with a write to the Communications register. leaves its high impedance state and starts driving the data bus. impedance state on the rising edge of CS. without the risk of corrupting data during a multibyte transfer. Figure 38. Serial Interface Write Timing Diagram Figure 39. 12-Bit Serial Write Operation Figure 40. Serial Interface Read Timing Diagram

REV. 0 ADE7756 –28– Table IV. Register List No. of Address Name R/W Bits Default Description 00h Not Used No Operation. 01h WAVEFORM R 24 0h The W aveform register is a 24 bit read-only register. This r egister contains the sampled waveform data from either Channel 1, Channel 2 or the Active Power signal. The data source is selected by data bits 14 and 13 in the Mode Register—see Channel 1 and 2 Sampling sections. 02h AENERGY R 40 0h The Active Energy Register. Active Power is accumulated (Integrated) over time in this 40-bit, read-only register. The energy register can hold a minimum of 6 seconds of Active Energy information with full-scale analog inputs before it overflows—see Energy Calculation section. 03h RSTENERGY R 40 0h Same as the Active Energy register except that the register is reset to zero following a read operation 04h STATUS R 8 0h The Interrupt Status Register. This is an 8-bit read-only register. The Status Register contains information regarding the source of ADE7756 interrupts—see Interrupts section. 05h RSTSTATUS R 8 0h Same as the Interrupt Status register except that the register contents are reset to zero (all flags cleared) after a read operation. 06h MODE R/W 16 000Ch The Mode Register. This is a 16-bit register through which most of the ADE7756 functionality is accessed. Signal sample rates, filter enabling and calibration modes are selected by writing to this register. The contents may be read at any time—see Mode Register section. 07h CFDIV R/W 12 3Fh The Frequency Divider Register. This is a 12-bit read/write register. The output frequency on the CF pin is adjusted by writing to this register—see Energy to Frequency Conversion section . 08h CH1OS R/W 6 0h Channel 1 Offset Adjust. Writing to this 6-bit register allows any off- sets on Channel 1 to be removed—see Analog Inputs section. 09h CH2OS R/W 6 0h Channel 2 Offset Adjust. Writing to this 6-bit register allows any off- sets on Channel 2 to be removed—see Analog Inputs section. 0Ah GAIN R/W 8 0h PGA Gain Adjust. This 8-bit register is used to adjust the gain selec- tion for the PGA in Channel 1 and Channel 2—Analog Inputs section. 0Bh APGAIN R/W 12 0h Active Power Gain Adjust. This is a 12-bit register. The Active Power calculation can be calibrated by writing to this register. The calibration range is ± 50% of the nominal full scale active power. The resolution of the gain adjust is 0.0244%/LSB—see Channel 1 ADC Gain Adjust section. 0Ch PHCAL R/W 6 0h Phase Calibration Register. The phase relationship between Channel 1 and Channel 2 can be adjusted by writing to this 6-bit re gister. The adjustment range is approximately ±3.1° at 60 Hz in 0.097 ° steps—see Phase Compensation section. 0Dh APOS R/W 12 8h Active Power Offset Correction. This 12-bit register allows small off- sets in the Active Power Calculation to be removed—see Active Power Calculation section. 0Eh ZXTOUT R/W 12 FFFFh Zero-Cross Time Out. If no zero crossings are detected on Channel 2 within a time period specified by this 12-bit register, the interrupt request line (IRQ) will be activated. The maximum time-out period is 0.15 second—see Zero Crossing Detection section. 0Fh SAGCYC R/W 8 FFh Sag Line Cycle Register. This 8-bit register specifies the number of consecutive half line cycles the signal on Channel 2 must be b elow SAGLVL before the SAG output is activated—see Voltage Sag Detec- tion section. It is also used during calibration mode to set the number of line cycles Active power is accumulated for Energy calibration—see Energy Calibration section.

REV. 0 ADE7756 –29– Table IV. Register List (continued) No. of Address Name R/W Bits Default Description 10H IRQEN R/W 8 0h Interrupt Enable Register. ADE7756 interrupts may be deactivated at any time by setting the corresponding bit in this 8-bit Enable register Logic 0. The Status register will continue to register an interrupt event even if disabled. However, the IRQ output will not be activated —see Interrupts section. 11H SAGLVL R/W 8 0h Sag Voltage Level. An 8-bit write to this register determines at what peak signal level on Channel 2 the SAG pin will become active. The signal must remain low for the number of cycles specified in the SAGCYC register before the SAG pin is activated—see Line Voltage Sag Detec- tion section. 12H TEMP R 8 0h Temperature Register. This is an 8-bit register which contains the result of the latest temperature conversion. A full description of this register’s contents can be found in the Temperature Measurement section of this data sheet. REGISTER DESCRIPTIONS All ADE7756 functionality is accessed via the on-chip registers. Each register is accessed by first writing to the communicatio ns register and then transferring the register data. A full description of the serial interface protocol is given in the Serial In terface section of this data sheet. Communications Register The Communications register is an 8-bit, write-only register that controls the serial data transfer between the ADE7756 and the host processor. All data transfer operations must begin with a write to the communications register. The data written to the communi ca- tions register determines whether the next operation is a read or a write and which register is being accessed. Table V outline s the bit designations for the Communications register. Table V. Communications Register DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 W/R 0 0 A4 A3 A2 A1 A0 Bit Bit Location Mnemonic Description 0 to 4 A0 to A4 The five LSBs of the Communications register specify the register for the data transfer opera- tion. Table IV lists the address of each ADE7756 on-chip register. 5 to 6 RESERVED These bits are unused and should be set to zero. 7W / R When this bit is a Logic 1, the data transfer operation immediately following the write to the Communications register will be interpreted as a write to the ADE7756. When this bit is a Logic 0, the data transfer operation immediately following the write to the Communications register will be interpreted as a read operation.

REV. 0 ADE7756 –30– Mode Register (06H) The ADE7756 functionality is configured by writing to the MODE register. Table VI summarizes the functionality of each bit in t he MODE register. Table VI. Mode Register Bit Bit Location Mnemonic Description 0 DISHPF The HFP (High-Pass Filter) in Channel 1 is disabled when this bit is set. 1 DISLPF2 The LPF (Low-Pass Filter) after the multiplier (LPF2) is disabled when this bit is set. 2 DISCF The frequency output CF is disabled when this bit is set. 3 DISSAG The line voltage Sag detection is disabled when this bit is set. 4 ASUSPEND By setting this bit to Logic 1, both ADE7756’s A/D converters can be turned off. In normal operation, this bit should be left at Logic 0. All digital functionality can be stopped by sus- pending the clock signal at CLKIN pin. 5 TEMPSEL The temperature conversion starts when this bit is set to one. This bit is automatically reset to zero when the temperature conversion is finished. 6 SWRST Software Chip Reset. A data transfer should not take place to the ADE7756 for at least 18 µs after a software reset. 7 CMODE Setting this bit to a Logic 1 places the chip in calibration mode. 8 DISCH1 ADC 1 (Channel 1) inputs are internally shorted together. 9 DISCH2 ADC 2 (Channel 2) inputs are internally shorted together.

10 SWAP By setting this bit to Logic 1 the analog inputs V2P and V2N are connected to ADC 1 and the

analog inputs V1P and V1N are connected to ADC 2. 12, 11 DTRT1, 0 These bits are used to select the Waveform Register update rate. DTRT 1 DTRT0 Update Rate 0 0 27.9 kSPS (CLKIN/128) 0 1 14 kSPS (CLKIN/256) 1 0 7 kSPS (CLKIN/512) 1 1 3.5 kSPS (CLKIN/1024) 14, 13 WAVSEL1, 0 These bits are used to select the source of the sampled data for the Waveform Register WAVSEL1 WAVSEL0 Source 0 0 Active Power signal (output of LPF2) 0 1 RESERVED 1 0 Channel 1 1 1 Channel 2 15 TEST1 Writing a Logic 1 to this bit position places the ADE7756 in test mode. This is intended for factory testing only and should be left at zero. MODE REGISTER* ADDR: 06H TEST 1 (TEST MODE SELECTION SHOULD BE SET TO 0) WAVSEL (WAVE FORM SELECTION FOR SAMPLE MODE) 00 = LPF2 01 = RESERVED 10 = CH1 11 = CH2 DTRT (WAVE FORM SAMPLES OUTPUT DATA RATE) 00 = 27.9kSPS (CLKIN/128) 01 = 14.4kSPS (CLKIN/256) 10 = 7.2kSPS (CLKIN/512) 11 = 3.6kSPS (CLKIN/1024) SWAP (SWAP CH1 AND CH2 ADCs) DISCH2 (SHORT THE ANALOG INPUTS ON CHANNEL 2) DISCH1 (SHORT THE ANALOG INPUTS ON CHANNEL 1) *REGISTER CONTENTS SHOW POWER-ON DEFAULTS 00000000 76543210 00001100 89101112131415 DISHPF (DISABLE HPF IN CHANNEL 1) DISLPF2 (DISABLE LPF2 AFTER MULTIPLIER) DISCF (DISABLE FREQUENCY OUTPUT CF) DISSAG (DISABLE SAG OUTPUT) ASUSPEND (SUSPEND CH1 AND CH2 ADCs) TEMPSEL (START TEMPERATURE SENSING) SWRST (SOFTWARE CHIP RESET) CMODE (CALIBRATION MODE) Figure 41.

REV. 0–32– C02438–2.5–4/01(0) PRINTED IN U.S.A. ADE7756 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 20-Lead Plastic DIP (N-20) 11 0 PIN 1 1.060 (26.90) 0.925 (23.50) 0.280 (7.11) 0.240 (6.10) 0.195 (4.95) 0.115 (2.93) 0.015 (0.381) 0.008 (0.204) 0.325 (8.25) 0.300 (7.62)SEATING PLANE 0.060 (1.52) MAX 0.022 (0.558) 0.014 (0.356) 0.160 (4.06) 0.115 (2.93) 0.100 (2.54) BSC 0.070 (1.77) 0.045 (1.15) 0.130 (3.30) MIN 20-Lead Shrink Small Outline Package (RS-20) 20 11 101 0.295 (7.50) 0.271 (6.90) 0.311 (7.9) 0.301 (7.64) 0.212 (5.38) 0.205 (5.21) PIN 1 SEATING PLANE 0.008 (0.203) 0.002 (0.050) 0.07 (1.78) 0.066 (1.67) 0.0256 (0.65) BSC 0.078 (1.98) 0.068 (1.73) 0.009 (0.229) 0.005 (0.127) 0.037 (0.94) 0.022 (0.559) 8/H11543 0/H11543