ADE7755

ADE7755ARSZRL AD | Alldatasheet

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Energy Metering IC with Pulse Output ADE7755 Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2002–2009 Analog Devices, Inc. All rights reserved.

FEATURES

High accuracy, surpasses 50 Hz/60 Hz IEC 687/IEC 1036 Less than 0.1% error over a dynamic range of 500 to 1 Supplies active power on the frequency outputs, F1 and F2 High frequency output CF is intended for calibration and supplies instantaneous active power Synchronous CF and F1/F2 outputs Logic output REVP provides information regarding the sign of the active power Direct drive for electromechanical counters and 2-phase stepper motors (F1 and F2) Programmable gain amplifier (PGA) in the current channel facilitates usage of small shunts and burden resistors Proprietary ADCs and DSPs provide high accuracy over large variations in environmental conditions and time On-chip power supply monitoring On-chip creep protection (no load threshold) On-chip reference 2.5 V ± 8% (30 ppm/°C typical) with external overdrive capability Single 5 V supply, low power (15 mW typical) Low cost CMOS process GENERAL DESCRIPTION The ADE7755 is a high accuracy electrical energy measurement IC. The part specifications surpass the accuracy requirements as quoted in the IEC 1036 standard. The only analog circuitry used in the ADE7755 is in the ADCs and reference circuit. All other signal processing (for example, multiplication and filtering) is carried out in the digital domain. This approach provides superior stability and accuracy over extremes in environmental conditions and over time. The ADE7755 supplies average active power information on the low frequency outputs, F1 and F2. These logic outputs can be used to directly drive an electromechanical counter or interface to an MCU. The CF logic output gives instantaneous active power information. This output is intended to be used for calibration purposes or for interfacing to an MCU. The ADE7755 includes a power supply monitoring circuit on the AV DD supply pin. The ADE7755 remains in a reset condition until the supply voltage on AVDD reaches 4 V . If the supply falls below 4 V , the ADE7755 resets and no pulse is issued on F1, F2, and CF. Internal phase matching circuitry ensures that the voltage and current channels are phase matched whether the HPF in Channel 1 is on or off. An internal no load threshold ensures that the ADE7755 does not exhibit any creep when there is no load. The ADE7755 is available in a 24-lead SSOP package. FUNCTIONAL BLOCK DIAGRAM POWER SUPPLY MONITOR G0 G1 AVDD AGND DVDD DGND RESET F2F1CFREVPS1 S0SCFCLKOUTCLKINREFIN/OUT ADE7755 4kΩ2.5V REFERENCE ADC PGA ×1, ×2, ×8, ×16 V1P V1N V2P V2N DIGITAL-TO-FREQUENCY CONVERTER ADC 242220131412181710 21121131516 DCAC/ 02896-001 PHASE CORRECTION LPFHPF SIGNAL PROCESSING BLOCK MULTIPLIER Figure 1. 1U.S. Patents 5,745,323; 5,760,617; 5,862,069; and 5,872,469.

Rev. A | Page 2 of 20 TABLE OF CONTENTS Interfacing the ADE7755 to a Microcontroller for Energy

REVISION HISTORY

8/09—Rev. 0 to Rev. A Changes to Features Section and General Description Section . 1 Changes to Theory of Operation Section, Figure 22, Power Changes to Nonsinusoidal Voltage and Current Section and Changes to HPF and Offset Effects Section, Figure 29, and Changes to Selecting a Frequency for an Energy Meter 5/02—Revision 0: Initial Version

Rev. A | Page 3 of 20 SPECIFICATIONS AVDD = DVDD = 5 V ± 5%, AGND = DGND = 0 V , on-chip reference, CLKIN = 3.58 MHz, TMIN to TMAX = −40°C to +85°C. Table 1. Parameter Min Typ Max Unit Test Conditions/Comments ACCURACY1, 2 Measurement Error1 on Channel 1 Channel 2 with full-scale signal (±660 mV), 25°C Gain = 1 0.1 % reading Over a dynamic range of 500 to 1 Gain = 2 0.1 % reading Over a dynamic range of 500 to 1 Gain = 8 0.1 % reading Over a dynamic range of 500 to 1 Gain = 16 0.1 % reading Over a dynamic range of 500 to 1 Phase Error1 Between Channels Line frequency = 45 Hz to 65 Hz V1 Phase Lead 37° (PF = 0.8 Capacitive) ±0.1 Degrees AC/DC = 0 and AC/DC = 1 V1 Phase Lag 60° (PF = 0.5 Inductive) ±0.1 Degrees AC/DC = 0 and AC/DC = 1 AC Power Supply Rejection1 AC/DC = 1, S0 = S1 = 1, G0 = G1 = 0 Output Frequency Variation (CF) 0.2 % reading V1 = 100 mV rms, V2 = 100 mV rms @ 50 Hz, ripple on AVDD of 200 mV rms @ 100 Hz DC Power Supply Rejection1 AC/DC = 1, S0 = S1 = 1, G0 = G1 = 0 Output Frequency Variation (CF) ±0.3 % reading V1 = 100 mV rms, V2 = 100 mV rms, AVDD = DVDD = 5 V ± 250 mV ANALOG INPUTS See the Analog Inputs section Maximum Signal Levels ±1 V V1P , V1N, V2N, and V2P to AGND Input Impedance (DC) 390 kΩ CLKIN = 3.58 MHz −3 dB Bandwidth 14 kHz CLKIN/256, CLKIN = 3.58 MHz ADC Offset Error1, 2 ±25 mV Gain = 11, 2 Gain Error1 ±7 % ideal External 2.5 V reference, gain = 1 V1 = 470 mV dc, V2 = 660 mV dc Gain Error Match1 ±0.2 % ideal External 2.5 V reference REFERENCE INPUT REFIN/OUT Input Voltage Range 2.7 V 2.5 V + 8% 2.3 V 2.5 V − 8% Input Impedance 3.2 kΩ Input Capacitance 10 pF ON-CHIP REFERENCE Nominal 2.5 V Reference Error ±200 mV Temperature Coefficient ±30 ppm/°C CLKIN Note all specifications for CLKIN of 3.58 MHz Input Clock Frequency 4 MHz

1 MHz

SCF , S0, S1, AC/DC, RESET, G0, and G1 Input High Voltage, VINH 2.4 V DVDD = 5 V ± 5% Input Low Voltage, VINL 0.8 V DVDD = 5 V ± 5% Input Current, IIN ±3 μA Typically 10 nA, VIN = 0 V to DVDD Input Capacitance, CIN 10 pF LOGIC OUTPUTS3 F1 and F2 Output High Voltage, VOH 4.5 V ISOURCE = 10 mA, DVDD = 5 V Output Low Voltage, VOL 0.5 V ISINK = 10 mA, DVDD = 5 V CF and REVP Output High Voltage, VOH 4 V ISOURCE = 5 mA, DVDD = 5 V Output Low Voltage, VOL 0.5 V ISINK = 5 mA, DVDD = 5 V

5.25 V 5 V + 5%

1 See the Terminology section. 2 See the Typical Performance Characteristics section for the plots. 3 Sample tested during initial release and after any redesign or process change that may affect this parameter. AVDD = DVDD = 5 V ± 5%, AGND = DGND = 0 V , on-chip reference, CLKIN = 3.58 MHz, TMIN to TMAX = −40°C to +85°C. 1 Sample tested during initial release and after any redesign or process change that may affect this parameter. 3 The pulse widths of F1, F2, and CF are not fixed for higher output frequencies. See the Frequency Outputs section. 4 The CF pulse is always 18 μs in the high frequency mode. See the Frequency Outputs section and Table 8. Figure 2. Timing Diagram for Frequency Outputs

Rev. A | Page 5 of 20 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter Rating AVDD to AGND −0.3 V to +7 V DVDD to DGND −0.3 V to +7 V DVDD to AVDD −0.3 V to +0.3 V Analog Input Voltage to AGND V1P , V1N, V2P , and V2N −6 V to +6 V Reference Input Voltage to AGND −0.3 V to AVDD + 0.3 V Digital Input Voltage to DGND −0.3 V to DVDD + 0.3 V Digital Output Voltage to DGND −0.3 V to DVDD + 0.3 V Operating Temperature Range Industrial −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C 24-Lead SSOP , Power Dissipation 450 mW θJA Thermal Impedance 112°C/W Lead Temperature, Soldering Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION

Figure 3. Pin Configuration Table 4. Pin Function Descriptions capacitor in parallel with a ceramic 100 nF capacitor. frequency range of 45 Hz to 1 kHz. The HPF should be enabled in power metering applications. with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor. of ±6 V can be sustained on these inputs without risk of permanent damage. 9 RESET Reset Pin. A logic low on this pin holds the ADCs and digital circuitry in a reset condition. Bringing this pin logic low clears the ADE7755 internal registers. 11 AGND This pin provides the ground reference for the analog circuitry in the ADE7755, that is, the ADCs and reference. star ground configuration helps to keep noisy digital currents away from the analog circuits. 12 SCF Select Calibration Frequency. This logic input is used to select the frequency on the calibration output, CF. Table 8 shows how the calibration frequencies are selected. 13, 14 S1, S0 These logic inputs are used to select one of four possible frequencies for the digital-to-frequency conversion. an Energy Meter Application section. are 1, 2, 8, and 16. See the Analog Inputs section.

Rev. A | Page 7 of 20 Pin No. Mnemonic Description 17 CLKIN An external clock can be provided at this logic input. Alternatively, a parallel resonant AT crystal can be connected across CLKIN and CLKOUT to provide a clock source for the ADE7755. The clock frequency for specified operation is 3.579545 MHz. Crystal load capacitance of between 22 pF and 33 pF (ceramic) should be used with the gate oscillator circuit. 18 CLKOUT A crystal can be connected across this pin and CLKIN to provide a clock source for the ADE7755. The CLKOUT pin can drive one CMOS load when an external clock is supplied at CLKIN or by the gate oscillator circuit. 20 REVP This logic output goes logic high when negative power is detected, that is, when the phase angle between the voltage and current signals is greater than 90°. This output is not latched and is reset when positive power is detected again. The output goes high or low at the same time that a pulse is issued on CF. 21 DGND This pin provides the ground reference for digital circuitry in the ADE7755, that is, the multiplier, filters, and digital-to-frequency converter. This pin should be tied to the digital ground plane of the PCB. The digital ground plane is the ground reference for all digital circuitry, for example, counters (mechanical and digital), MCUs, and indicator LEDs. For good noise suppression, the analog ground plane should be connected to the digital ground plane at one point only, for example, a star ground. 22 CF Calibration Frequency Logic Output. The CF logic output gives instantaneous active power information. This output is intended to be used for calibration purposes. Also, see the SCF pin description. 23, 24 F2, F1 Low Frequency Logic Outputs. F1 and F2 supply average active power information. The logic outputs can be used to directly drive electromechanical counters and 2-phase stepper motors. See the Transfer Function section.

Rev. A | Page 11 of 20 TERMINOLOGY Measurement Error The error associated with the energy measurement made by the ADE7755 is defined by the following formula: % 1007755 ×− Energy True Energy TrueADE the byRegisteredEnergy ErrorPercentage Phase Error Between Channels The high-pass filter (HPF) in Channel 1 has a phase lead response. To offset this phase response and equalize the phase response between channels, a phase compensation network is also placed in Channel 1. The phase compensation network matches the phase to within ±0.1° over a range of 45 Hz to 65 Hz and ±0.2° over a range of 40 Hz to 1 kHz. See Figure 30 and Figure 31. Power Supply Rejection (PSR) The PSR quantifies the ADE7755 measurement error as a percentage of the reading when the power supplies are varied. For the ac PSR measurement, a reading at nominal supplies (5 V) is taken. A 200 mV rms/100 Hz signal is then introduced onto the supplies and a second reading is obtained under the same input signal levels. Any error introduced is expressed as a percentage of the reading (see the Measurement Error definition). For the dc PSR measurement, a reading at nominal supplies (5 V) is taken. The supplies are then varied ±5% and a second reading is obtained with the same input signal levels. Any error introduced is again expressed as a percentage of the reading. ADC Offset Error The ADC offset error refers to the dc offset associated with the analog inputs to the ADCs. It means that with the analog inputs connected to AGND, the ADCs still see a small dc signal (offset). The offset decreases with increasing gain in Channel 1. This specification is measured at a gain of 1. At a gain of 16, the dc offset is typically less than 1 mV . However, when the HPF is switched on, the offset is removed from the current channel, and the power calculation is not affected by this offset. Gain Error The gain error of the ADE7755 is defined as the difference between the measured output frequency (minus the offset) and the ideal output frequency. It is measured with a gain of 1 in Channel 1. The difference is expressed as a percentage of the ideal frequency. The ideal frequency is obtained from the ADE7755 transfer function (see the Transfer Function section). Gain Error Match The gain error match is defined as the gain error (minus the offset) obtained when switching between a gain of 1 and a gain of 2, 8, or 16. It is expressed as a percentage of the output frequency obtained under a gain of 1. This gives the gain error observed when the gain selection is changed from 1 to 2, 8, or 16.

vary from device to device due to a reference tolerance of ±8%. VREF = 2.5 V (nominal reference value). vary from device to device due to a reference tolerance of ±8%. Freq = output frequency on F1 and F2 (Hz). V1 = differential rms voltage signal on Channel 1 (volts). V2 = differential rms voltage signal on Channel 2 (volts). made using logic inputs G0 and G1. VREF = the reference voltage (2.5 V ± 8%) (volts). by using the logic inputs S0 and S1, see Table 6. Table 7. Maximum Output Frequency on F1 and F2 block diagram in Figure 22). the specified CLKIN frequency is altered. VREF = 2.5 V (nominal reference value).

Table 8. Maximum Output Frequency on CF As shown in Table 6, the user can select one of four frequencies. 100 imp/kWh with a maximum current between 10 A and 120 A. Table 9. F1 and F2 Frequency at 100 imp/kWh signals and signals with high crest factors to be accommodated. align well with those listed in Table 9 for maximum load. Table 10. F1 and F2 Frequency with Half-Scale AC Inputs of 100 imp/kWh is 0.153 Hz at 25 A and 220 V (from Table 9). Table 10, the closest frequency to 0.153 Hz in Column 4, is 0.17 Hz. 2 (3.4 Hz, see Table 6) is selected for this design. for F1 and F2 are shown in Table 7. to active power. The CF output frequencies are listed in Table 8. if the CF frequency is 20 Hz, the CF pulse width is 25 ms. is always 18 μs, regardless of the output frequency on CF.

Rev. A | Page 19 of 20 NO LOAD THRESHOLD The ADE7755 also includes a no load threshold and start-up current feature that eliminates any creep effects in the meter. The ADE7755 is designed to issue a minimum output frequency in all modes except when SCF = 0 and S1 = S0 = 1. The no load detection threshold is disabled in this output mode to accommodate specialized application of the ADE7755. Any load generating a frequency lower than this minimum frequency will not cause a pulse to be issued on F1, F2, or CF. The minimum output frequency is given as 0.0014% of the full-scale output frequency for each of the f i frequencies (i = 1, 2, 3, or 4), see Table 6. For example, in an energy meter with a meter constant of 100 imp/kWh on F1 and F2 using f 2 (3.4 Hz), the maximum output frequency at F1 or F2 is 0.0014% of 3.4 Hz or 4.76 × 10−5 Hz. This is 3.05 × 10−3 Hz at CF (64 × F1 Hz). In this example, the no load threshold is equivalent to 1.7 W of the load or a start-up current of 8 mA at 220 V . IEC 1036 states that the meter must start up with a load current equal to or less than 0.4% Ib. For a 5 A (Ib) meter, 0.4% Ib is equivalent to 20 mA. The start-up current of this design therefore satisfies the IEC requirement. As illustrated in this example, the choice of f i frequency (i = 1, 2, 3, or 4) and the ratio of the stepper motor display determine the start-up current.

0.05 MIN

0.65 BSC

2.00 MAX

Figure 34. 24-Lead Shrink Small Outline Package [SSOP] registered trademarks are the prop erty of their respective owners.