ADE7752BARWZ-RL

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Polyphase Energy Metering IC with Pulsed Output Preliminary Technical Data ADE7752B Rev. PrA Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2006 Analog Devices, Inc. All rights reserved.

FEATURES

High accuracy supports 50 Hz/60 Hz IEC62053-21 Less than 0.1% error over a dynamic range of 500 to 1 Compatible with 3-phase 3-wire delta and 3-phase 4-wire Wye configurations Supplies average active power on the frequency outputs F1 and F2 High frequency output (CF) is intended for calibration and supplies instantaneous active power Logic output REVP indicates a potential miswiring or negative power on the sum of all phases Direct drive for electromechanical counters and 2-phase stepper motors (F1 and F2) Proprietary ADCs and DSP provide high accuracy over large variations in environmental conditions and time On-chip power supply monitoring On-chip creep protection (no load threshold) based on the sum of the three phases On-chip reference 2.4 V ± 8% (25 ppm/°C typical) with external overdrive capability Single 5 V supply, low power (TBD mW typical) Low cost CMOS process GENERAL DESCRIPTION The ADE7752B1 is an accurate active energy measurement IC intended for use in any 3-phase distribution system and has enhanced features that make it better suited for 3-phase 3-wire applications compared to the ADE7752/52A. The no-load threshold and reverse polarity indication are based on the sum of the three phase energies in the ADE7752B. The ADE7752B specifications surpass the accuracy requirements as quoted in the IEC62053-21 standard. The only analog circuitry used in the ADE7752B is in the analog-to-digital converters (ADCs) and reference circuit. All other signal processing (for example, multiplication, filtering, and summation) is carried out in the digital domain. This approach provides superior stability and accuracy over extremes in environmental conditions and over time. The ADE7752B supplies average active power information on the low frequency outputs, F1 and F2. These logic outputs can be used to directly drive an electromechanical counter or to interface with an MCU. The CF logic output gives instantaneous active power information. This output is intended to be used for calibration purposes. The ADE7752B includes a power supply monitoring circuit on the V DD pin. The ADE7752B remains inactive until the supply voltage on VDD reaches 4 V . If the supply falls below 4 V , the ADE7752B also resets and no pulses are issued on F1, F2, and CF. Internal phase matching circuitry ensures that the voltage and current channels are phase matched. An internal no load threshold ensures the ADE7752B does not exhibit any creep when there is no load. The ADE7752B is available in a 24-lead SOIC package. 1 Patent pending. FUNCTIONAL BLOCK DIAGRAM LPFHPF Φ CLKOUT CLKIN DGND CFS1 F1 F2S0SCFREVP DIGITAL-TO-FREQUENCY CONVERTER 2.4V REF REFIN/OUTAGND 4kΩ IBP IBN VBP VN ICP ICN VCP IAP IAN VA P ADC ADC ADC ADC VDD ADE7752B POWER SUPPL Y MONITOR ADC ADC PHASE CORRECTION PHASE CORRECTION PHASE CORRECTION 11 12 4 18 21 22 23 24 1 HPF Φ HPF Φ LPF LPF ABS Σ X X X 05905-001 Figure 1.

ADE7752B Preliminary Technical Data Rev. PrA | Page 2 of 27 TABLE OF CONTENTS

Preliminary Technical Data ADE7752B Rev. PrA | Page 3 of 27 SPECIFICATIONS VDD = 5 V ± 5%, AGND = DGND = 0 V , on-chip reference, CLKIN = 10 MHz, TMIN to TMAX = −40°C to +85°C, unless otherwise noted. Table 1. Parameter Conditions Min Typ Max Unit ACCURACY1, 2 Measurement Error on Current Channel Voltage channel with full-scale signal (±500 mV), 25°C, over a dynamic range of 500 to 1 0.1 % Reading Phase Error Between Channels PF = 0.8 Capacitive ±0.1 Degrees PF = 0.5 Capacitive ±0.1 Degrees AC Power Supply Rejection SCF = 0, S0 = S1 = 1 Output Frequency Variation (CF) IA = IB = IC = 100 mV rms, VA = VB = VC = 100 mV rms @ 50 Hz, Ripple on VDD of 200 mV rms @ 100 Hz 0.01 % Reading DC Power Supply Rejection S1 = 1; S0 = SCF = 0 Output Frequency Variation (CF) V1 = 100 mV rms, V2 = 100 mV rms, VDD = 5 V ± 250 mV 0.1 % Reading ANALOG INPUTS See Analog Inputs section Maximum Signal Levels V AP – VN, VBP – VN, VCP – VN, IAP – IAN, IBP – IBN, ICP – ICN ±0.5 V peak difference Input Impedance (DC) CLKIN = 10 MHz 370 410 kΩ Bandwidth (−3 dB) CLKIN/256, CLKIN = 10 MHz 14 kHz ADC Offset Error1, 2 ±25 mV Gain Error External 2.5 V reference, IA = IB = IC = 500 mV dc ±9 % Ideal REFERENCE INPUT REFIN/OUT Input Voltage Range 2.4 V + 8% 2.6 V 2.4 V − 8% 2.2 V Input Impedance 3.3 kΩ Input Capacitance 10 pF ON-CHIP REFERENCE Nominal 2.4 V Reference Error ±200 mV Temperature Coefficient 25 ppm/°C CLKIN All specifications for CLKIN of 10 MHz Input Clock Frequency 10 MHz LOGIC INPUTS3 ACF , S0, S1, and ABS Input High Voltage, VINH V DD = 5 V ± 5% 2.4 V Input Low Voltage, VINL V DD = 5 V ± 5% 0.8 V Input Current, IIN Typically 10 nA, V IN = 0 V to VDD ±3 μA Input Capacitance, CIN 10 pF LOGIC OUTPUTS3 F1 and F2 Output High Voltage, VOH I SOURCE = 10 mA, VDD = 5 V 4.5 V Output Low Voltage, VOL I SINK = 10 mA, VDD = 5 V 0.5 V CF and NEGP Output High Voltage, VOH V DD = 5 V, ISOURCE = 5 mA 4.5 V Output Low Voltage, VOL V DD = 5 V, ISINK = 5 mA 0.5 V LED_CTRL V DD = 5 V, CLKIN = 10 MHz Output Frequency 17.39 kHz Output High Voltage V DD = 5 V, ISOURCE = 10 mA 4.5 V Output Low Voltage V DD = 5 V, ISINK = 10 mA TBD V

ADE7752B Preliminary Technical Data Rev. PrA | Page 4 of 27 Parameter Conditions Min Typ Max Unit LED_A, LED_B, LED_C Output Low ISINK V DD = 4.75 V TBD mA Output High Source V DD = 4.75 V TBD mA POWER SUPPLY For specified performance VDD 5 V ± 5% 4.75 5.25 V IDD TBD TBD mA 1 See the Terminology section for explanation of specifications. 2 See the plots in the Typical Performance Characteristics section. 3 Sample tested during initial release and after any redesign or process changes that might affect this parameter.

VDD = 5 V ± 5%, AGND = DGND = 0 V , on-chip reference, CLKIN = 10 MHz, TMIN to TMAX = −40°C to +85°C, unless otherwise noted. 1 Sample tested during initial release and after any redesign or process changes that might affect this parameter. 3 The pulse widths of F1, F2, and CF are not fixed for higher output frequencies (see the Frequency Outputs section). 4 CF is not synchronous to F1 or F2 frequency outputs. 5 The CF pulse is always 1 μs in the high frequency mode (see the Frequency Outputs section). Figure 2. Timing Diagram for Frequency Outputs

ADE7752B Preliminary Technical Data Rev. PrA | Page 6 of 27 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter Rating VDD to AGND −0.3 V to +7 V VDD to DGND −0.3 V to +7 V Analog Input Voltage to AGND VA P, V B P, V C P, V N , I A P, I A N , I B P, I B N , I C P, and ICN −6 V to +6 V Reference Input Voltage to AGND −0.3 V to V DD + 0.3 V Digital Input Voltage to DGND −0.3 V to V DD + 0.3 V Digital Output Voltage to DGND −0.3 V to V DD + 0.3 V Operating Temperature Range Industrial −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C 28-Lead SOIC, Power Dissipation 63 mW θJA Thermal Impedance 55°C/W Lead Temperature, Soldering Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electros tatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge wi thout detection. Although this product features proprietary ESD protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Figure 3. Pin Configuration Table 4. Pin Function Descriptions 1 CF Calibration Frequency Logic Output. The CF logic output gives instantaneous active power information. This output is intended to be used for calibration purposes. acceptable to connect this pin to the analog ground plane of the whole system. DGND with a 10 μF capacitor in parallel with a 100 nF ceramic capacitor.

4 REVP This logic output goes logic high when negative power is detected on the sum of the three phase

Negative Power Information section). inputs without risk of permanent damage. 11 AGND This pin provides the ground reference for the analog circuitry in the ADE7752B (ADCs and reference). device on the analog ground plane. without risk of permanent damage. CF. Table 7 shows how the calibration frequencies are selected. provide a clock source for the ADE7752B. The clock frequency for the specified operation is 10 MHz. to the crystal manufacturer’s data sheet for the load capacitance requirements.

ADE7752B Preliminary Technical Data Rev. PrA | Page 8 of 27 Pin No. Mnemonic Description CLKOUT A crystal can be connected across this pin and CLKIN as described previously to provide a clock source for the ADE7752B. The CLKOUT pin can drive one CMOS load when an external clock is supplied at CLKIN or when a crystal is being used. 21, 22 S0, S1 These logic inputs are used to select one of four possible frequencies for the digital-to-frequency conversion for design flexibility. 23, 24 F2, F1 Low Frequency Logic Outputs. F1 and F2 supply average active power information. The logic outputs can be used to drive electromechanical counters and 2-phase stepper motors directly (see the Transfer Function section).

Preliminary Technical Data ADE7752B Rev. PrA | Page 11 of 27 TERMINOLOGY Measurement Error The error associated with the energy measurement made by the ADE7752B is defined by the following formula: %– 100Energy True Energy True 7762ADEby RegisteredEnergy Error Percentage × Error between Channels The high-pass filter (HPF) in the current channel has a phase lead response. To offset this phase response and equalize the phase response between channels, a phase correction network is placed in the current channel. The phase correction network ensures a phase match between the current channels and voltage channels to within ±0.1° over a range of 45 Hz to 65 Hz and ±0.2° over a range of 40 Hz to 1 kHz (see Figure 25 and Figure 26). Power Supply Rejection (PSR) This quantifies the ADE7752B measurement error as a percentage of reading when the power supplies are varied. For the ac PSR measurement, a reading at a nominal supply (5 V) is taken. A 200 mV rms/100 Hz signal is then introduced onto the supply and a second reading is obtained under the same input signal levels. Any error introduced is expressed as a percentage of reading. See definition for Measurement Error. For the dc PSR measurement, a reading at nominal supplies (5 V) is taken. The supply is then varied ±5% and a second reading is obtained with the same input signal levels. Any error introduced is again expressed as a percentage of reading. ADC Offset Error This refers to the dc offset associated with the analog inputs to the ADCs. It means that with the analog inputs connected to AGND, the ADCs still see an analog input signal offset. However, because the HPF is always present, the offset is removed from the current channel and the power calculation is not affected by this offset. Gain Error The gain error of the ADE7752B is defined as the difference between the measured output frequency (minus the offset) and the ideal output frequency. The difference is expressed as a percentage of the ideal frequency. The ideal frequency is obtained from the ADE7752B transfer function (see the Transfer Function section).

Figure 14. Test Circuit for Performance Curves

digital domain for superior stability over temperature and time. under steady load conditions. Figure 15. Signal Processing Block Diagram

This is the correct active power calculation. Figure 16. DC Component of Instantaneous Power Signal v(t) is the instantaneous voltage. Vn is the rms value of voltage harmonic n. and α n is the phase angle of the voltage harmonic. i(t) is the instantaneous current. In is the rms value of current harmonic n. βn is the phase angle of the current harmonic. harmonic is present in both the voltage and current waveforms. a master clock frequency of 10 MHz.

power supply (VDD) is monitored continuously by the ADE7752B. or VREF falls below 1.9 V (typ), the data path is again held in reset. false triggering due to noisy supplies. Figure 23. On-Chip Power Supply Monitor

frequency and its harmonics, that is, cos(hωt), where h = 1, 2, 3 …. where the −3 dB cutoff frequency of the low-pass filter is 8 Hz. passes through the digital-to-frequency conversion. in a stepper-motor based meter. Figure 27. Active Power-to-Frequency Conversion

Preliminary Technical Data ADE7752B Rev. PrA | Page 21 of 27 POWER MEASUREMENT CONSIDERATIONS Calculating and displaying power information always have some associated ripple that depends on the integration period used in the MCU to determine average power as well as the load. For example, at light loads, the output frequency can be 10 Hz. With an integra- tion period of two seconds, only about 20 pulses are counted. The possibility of missing one pulse always exists since the ADE7752B output frequency is running asynchronously to the MCU timer. This would result in a 1-in-20 or 5% error in the power measure- ment. To remedy this, an appropriate integration time should be considered to achieve the desired accuracy. MODE SELECTION OF THE SUM OF THE THREE ACTIVE ENERGIES The ADE7752B can be configured to execute the arithmetic sum of the three active energies, Wh = WhΦA + WhΦB + WhΦC, or the sum of the absolute value of these energies, Wh = |WhΦA| + |WhΦB| + |WhΦC|. The selection between the two modes can be made by setting the ABS pin. Logic high and logic low applied on the ABS pin correspond to the arithmetic sum and the sum of absolute values, respectively. When the sum of the absolute values is selected, the active energy from each phase is always counted positive in the total active energy. It is particularly useful in 3-phase 4-wire instillation where the sign of the active power should always be the same. If the meter is misconnected to the power lines, that is, CT connected in the wrong direction then the total active energy recorded without this solution can be reduced by two- thirds. The sum of the absolute values assures that the active energy recorded represents the actual active energy delivered. Regardless of the mode selected using this pin, the reverse power pin still detects when negative power is present on the sum of the three phase inputs.

Freq = output frequency on F1 and F2 (Hz). VREF = the reference voltage (2.4 V ±8%) (V). logic inputs SCF, S0, and S1 (see Table 5). Table 5. F1–7 Frequency Selection1

1 F1–7 is a fraction of the master clock and therefore varies if the specified

frequencies when using all three channel inputs. power signal (see Figure 15). Table 7. Maximum Output Frequency on CF

Table 8. F1 and F2 Frequency at 100 imp/kWhr F2 when all six analog inputs are half scale. Table 9. F1 and F2 Frequency with Half-Scale AC Inputs

25 A maximum current is being designed, the output frequency on

output frequencies for F1 and F2 are shown in Table 6. frequency is 20 Hz, the CF pulse width is 25 ms. circuitry features that eliminate any creep effects in the meter. The circuit is designed to issue a minimum output frequency. CF. The no-load threshold is determined by the sum of all phases.

Table 10. CF, F1, and F2 Minimum Frequency at No Load negative power is detected on the sum of the three phase inputs. then REVP pin output is low. phases measures positive power.

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 28. 24-Lead Standard Small Outline Package [SOIC_W] 2 RW = small outline wide body package in tubes.

Preliminary Technical Data ADE7752B Rev. PrA | Page 27 of 27 NOTES © 2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. PR05905-0-1/06(PrA)