ADE7752AR

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Polyphase Energy Metering IC with Pulse Output ADE7752/ADE7752A

FEATURES

High accuracy, supports 50 Hz/60 Hz IEC62053-2x Less than 0.1% error over a dynamic range of 500 to 1 Compatible with 3-phase/3-wire delta and 3-phase/4-wire W ye configurations The ADE7752 supplies average real power on frequency outputs F1 an d F2 High frequency output CF is intended for calibration and sup plies instantaneous real power Logic output REVP indicates a potential miswiring or nega tive power for each phase Direct drive for electromechanical counters and 2-phase st epper motors (F1 and F2) Proprietary ADCs and DSP provide high accuracy over large v ariations in environmental conditions and time On-chip power supply monitoring On-chip creep protection (no load threshold) On-chip reference 2.4 V ±8% (20 ppm/°C typical) with e xternal overdrive capability Single 5 V supply, low power 60 mW t ypical: ADE7752 30 mW typical: ADE7752A Low cost CMOS process GENERAL DESCRIPTION The ADE7752 is a high accuracy polyphase electrical energy measurement IC. The ADE7752A is a pin-to-pin compatible low power version of ADE7752. The functions of ADE7752 and ADE7752A are the same. Both products are referred to in the text of this data sheet as ADE7752. The part specifications surpass the accuracy requirements as q uoted in the IEC62053-2x standard. The only analog circuitry used in the ADE7752 is in the analog-to-digital converters (ADCs) and reference circuit. All other signal processing (such as multi- plication, filtering, and summation) is carried out in the digital domain. This approach provides superior stability and accuracy over extremes in environmental conditions and over time. The ADE7752 supplies average real power information on the lo w frequency outputs, F1 and F2. These logic outputs may be used to directly drive an electromechanical counter or to interface with an MCU. The CF logic output gives instanta- neous real power information. This output is intended to be used for calibration purposes. The ADE7752 includes a power supply monitoring circuit on th e VDD pin. The ADE7752 remains inactive until the supply voltage on VDD reaches 4 V . If the supply falls below 4 V , no pulses are issued on F1, F2, and CF. Internal phase matching circuitry ensures that the voltage and current channels are phase matched. An internal no load threshold ensures the part does not exhibit any creep when there is no load. The ADE7752 is available in a 24-lead SOIC package. FUNCTIONAL BLOCK DIAGRAM LPFHPF Φ CLKOUT CLKIN DGND CFS1 F1 F2S0SCFREVP DIGITAL-TO-FREQUENCY CONVERTER 2.4V REF REFIN/OUTAGND 4kΩ IBP IBN VBP VN ICP ICN VCP IAP IAN VA P ADC ADC ADC ADC VDD ADE7752/ ADE7752A POWER SUPPL Y MONITOR ADC ADC PHASE CORRECTION PHASE CORRECTION PHASE CORRECTION 11 12 4 18 21 22 23 24 1 HPF Φ HPF Φ LPF LPF ABS Σ X X X 02676-A-001 Figure 1. 24-Lead Standard Small Outline Package [SOIC] rights of third parties that may result from its use. Specifications subject to change without notice. Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.

Rev. C | Page 2 of 24 TABLE OF CONTENTS

REVISION HISTORY

7/05—Rev. B to Rev. C 9/03—Rev. A to Rev. B 5/03—Rev. 0 to Rev. A Changes to SELECTING A FREQUENCY FOR AN ENERGY

Rev. C | Page 3 of 24 SPECIFICATIONS VDD = 5 V ± 5%, AGND = DGND = 0 V , on-chip reference, CLKIN = 10 MHz, TMIN to TMAX = –40°C to +85°C, unless otherwise noted. Table 1. ADE7752 ADE7752A Parameter Min Typ Max Min Typ Max Unit Conditions ACCURACY1, 2 Measurement Error on Current Channel 0.1 0.1 % Reading Voltage channel with full-scale signal (±500 mV), 25°C, over a dynamic range of 500 to 1 Phase Error Between Channels PF = 0.8 Capacitive ±0.1 ±0.1 Degrees PF = 0.5 Inductive ±0.1 ±0.1 Degrees AC Power Supply Rejection SCF = 0; S0 = S1 = 1 Output Frequency Variation (CF) 0.01 0.01 % Reading IA = IB = IC = 100 mV rms, VA = VB = VC = 100 mV rms, @ 50 Hz, ripple on V DD of 175 mV rms @ 100 Hz DC Power Supply Rejection S1 = 1; S0 = SCF = 0 Output Frequency Variation (CF) 0.1 0.1 % Reading IA = IB = IC = 100 mV rms, VA = VB = VC = 100 mV rms, V DD = 5 V ±250 mV ANALOG INPUTS See the Analog Inputs section. Maximum Signal Levels ±0.5 ±0.5 Vpeak differential VAP to VN, VBP to VN, VCP to VN, IAP to IAN, IBP to IBN, ICP to ICN Input Impedance (DC) 370 410 370 450 kΩ CLKIN = 10 MHz Bandwidth (–3 dB) 14 14 kHz CLKIN/256, CLKIN = 10 MHz ADC Offset Error1, 2 ±25 ±25 mV Gain Error ±9 ±9 % Ideal External 2.5 V reference, IA = IB = IC = 500 mV dc REFERENCE INPUT REFIN/OUT Input Voltage Range 2.6 2.6 V 2.4 V + 8% 2.2 2.2 V 2.4 V – 8% Input Impedance 3.3 3.3 kΩ Input Capacitance 10 10 pF ON-CHIP REFERENCE Nominal 2.4 V Reference Error ±200 ±200 mV Temperature Coefficient 25 25 ppm/°C CLKIN All specifications for CLKIN of 10 MHz Input Clock Frequency 10 10 MHz LOGIC INPUTS3 ACF, S0, S1, and ABS Input High Voltage, VINH 2.4 2.4 V VDD = 5 V ±5% Input Low Voltage, VINL 0.8 0.8 V VDD = 5 V ±5% Input Current, IIN ±3 ±3 μA Typically 10 nA, VIN = 0 V to VDD Input Capacitance, CIN 10 10 pF LOGIC OUTPUTS3 F1 and F2 Output High Voltage, VOH 4.5 4.5 V ISOURCE = 10 mA, VDD = 5 V Output Low Voltage, VOL 0.5 0.5 V ISINK = 10 mA, VDD = 5 V CF and REVP Output High Voltage, VOH 4 4 V VDD = 5 V, ISOURCE = 5 mA Output Low Voltage, VOL 0.5 0.5 V VDD = 5 V, ISINK = 5 mA POWER SUPPLY For specified performance VDD 4.75 5.25 4.75 5.25 V 5 V ±5% IDD 12 16 6 9 mA 1 See the Terminology section for explanation of specifications. 2 See the plots in the Typical Performance Characteristics section. 3 Sample tested during initial release and after any redesign or process change that may affect this parameter.

1 Sample tested during initial release and after any redesign or process change that may affect this parameter. 3 The pulse widths of F1, F2, and CF are not fixed for higher output frequencies. See the Frequency Outputs section. 4 CF is not synchronous to F1 or F2 frequency outputs. 5 The CF pulse is always 1 μs in the high frequency mode. Figure 2. Timing Diagram for Frequency Outputs

Rev. C | Page 5 of 24 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 3. Parameter Rating Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. V to AGND −0.3 V to +7 V DD V to DGND −0.3 V to +7 V DD Analog Input Voltage to AGND VAP, VBP, VCP, VN, IAP, IAN, IBP, IBN, ICP, and ICN −6 V to +6 V Reference Input Voltage to AGND −0.3 V to V + 0.3 V DD Digital Input Voltage to DGND −0.3 V to V + 0.3 V DD Digital Output Voltage to DGND −0.3 V to V + 0.3 V DD Operating Temperature Range −40°C to +85°C Industrial Storage Temperature Range −65°C to +150°C Junction Temperature 150°C 24-Lead SOIC, Power Dissipation 88 mW θJA Thermal Impedance 250°C/W Lead Temperature, Soldering Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as hi gh as 4000 V readily accumulate on the human body and test equipment and can discharge wi thout detection. Although this product features proprietary ESD protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Figure 3. Pin Configuration Table 4. Pin Function Descriptions 1 CF Calibration Frequency Logic Output. The CF logic output gives instantaneous real power information. This output is intended to be used for calibration purposes. See the SCF pin description. acceptable to connect this pin to the analog ground plane of the whole system. DGND with a 10 μF capacitor in parallel with a 100 nF ceramic capacitor. without risk of permanent damage. one point. It is acceptable to place the entire device on the analog ground plane. connected at this pin. In either case, this pin should be decoupled to AGND with a 1 μF ceramic capacitor. 17 ABS This logic input is used to select the way the three active energies from the three phases are summed. CF. Table 7 shows how the calibration frequencies are selected.

Rev. C | Page 7 of 24 Pin No. Mnemonic Description 19 CLKIN Master Clock for ADCs and Digital Signal Processing. An external clock can be provided at this logic input. Alternatively, a parallel resonant AT crystal can be connected across CLKIN and CLKOUT to provide a clock source for the ADE7752. The clock frequency for specified operation is 10 MHz. Ceramic load capacitors between 22 pF and 33 pF should be used with the gate oscillator circuit. Refer to the crystal manufacturer’s data sheet for load capacitance requirements. 20 CLKOUT A crystal can be connected across this pin and CLKIN as described previously to provide a clock source for the ADE7752. The CLKOUT pin can drive one CMOS load when an external clock is supplied at CLKIN or when a crystal is being used. 21, 22 S0, S1 These logic inputs are used to select one of four possible frequencies for the digital-to-frequency conver- sion. This offers the designer greater flexibility when designing the energy meter. See the Selecting a Frequency for an Energy Meter Application section. 24, 23 F1, F2 Low Frequency Logic Outputs. F1 and F2 supply average real power information. The logic outputs can be used to drive electromechanical counters and two-phase stepper motors directly. See the Transfer Function section.

Figure 14. Test Circuit for Performance Curves

Rev. C | Page 11 of 24 TERMINOLOGY Measurement Error The error associated with the energy measurement made by the ADE7752 is defined by the following formula: ADC Offset Error This refers to the dc offset associated with the analog inputs to the ADCs. It means that with the analog inputs connected to AGND, the ADCs still see an analog input signal offset. However, because the HPF is always present, the offset is removed from the current channel, and the power calculation is not affected by this offset. % Energy True Energy True – ADE by Registered Energy ErrorPercentage 1007752 × Error Between Channels The high-pass filter (HPF) in the current channel has a phase lead response. To offset this phase response and equalize the phase response between channels, a phase correction network is also placed in the current channel. The phase correction net- work ensures a phase match between the current channels and voltage channels to within ±0.1° over a range of 45 Hz to 65 Hz and ±0.2° over a range of 40 Hz to 1 kHz. See Gain Error The gain error of the ADE7752 is defined as the difference between the measured output frequency (minus the offset) and the ideal output frequency. The difference is expressed as a percentage of the ideal frequency. The ideal frequency is obtained from the ADE7752 transfer function. See the Transfer FunctionFigure 24 and section. Figure 26. Power Supply Rejection (PSR) This quantifies the ADE7752 measurement error as a percentage of reading when the power supplies are varied. For the ac PSR measurement, a reading at a nominal supply (5 V) is taken. A 200 mV rms/100 Hz signal is then introduced onto the supply and a second reading is obtained under the same input signal levels. Any error introduced is expressed as a percentage of reading. See definition for Measurement Error. For the dc PSR measurement, a reading at nominal supplies (5 V) is taken. The supply is then varied ±5% and a second reading is obtained with the same input signal levels. Any error introduced is again expressed as a percentage of reading.

This is the correct real power calculation. i(t) is the instantaneous current. In is the rms value of current harmonic n. Figure 16. DC Component of Instantaneous Power Signal v(t) is the instantaneous voltage. Vn is the rms value of voltage harmonic n. α n is the phase angle of the voltage harmonic.

Rev. C | Page 19 of 24 MODE SELECTION OF THE SUM OF THE THREE ACTIVE ENERGIES The ADE7752 can be configured to execute the arithmetic sum of the three active energies, Wh = WhϕA + WhϕB + WhϕC, or the sum of the absolute value of these energies, Wh = |WhϕA| + |WhϕB| + |WhϕC|. The selection between the two modes can be made by setting the ABS pin. Logic high and logic low applied on the ABS pin correspond to the arithmetic sum and the sum of absolute values, respectively. When the sum of the absolute values is selected, the active energy from each phase is always counted positive in the total active energy. It is particularly useful in 3-phase 4-wire installa- tion where the sign of the active power should always be the same. If the meter is misconnected to the power lines, (for instance, if CT is connected in the wrong direction), the total active energy recorded without this solution can be reduced by two-thirds. The sum of the absolute values assures that the active energy recorded represents the actual active energy delivered. In this mode, the reverse power pin still detects when negative power is present on any of the three phase inputs. POWER MEASUREMENT CONSIDERATIONS Calculating and displaying power information always has some associated ripple that depends on the integration period used in the MCU to determine average power as well as the load. For example, at light loads, the output frequency may be 10 Hz. With an integration period of 2 seconds, only about 20 pulses are counted. The possibility of missing one pulse always exists since the ADE7752 output frequency is running asynchro- nously to the MCU timer. This would result in a 1-in-20 or 5% error in the power measurement.

29.32 Hz maximum for ac signals with SCF = 1; S0 = S1 = 1 (see

Freq = the output frequency on F1 and F2 (Hz). REF = the reference voltage (2.4 V ± 8%) (V). logic inputs SCF, S0, and S1 (see Table 5). Table 5. F1–7 Frequency Selection1

1 F1–7 is a fraction of the master clock and therefore varies if the specified

0.5 V(rms of dc = dc)

phase are not in phase in normal operation.

frequencies when using all three channel inputs. where VAN = V × sin(2π/3) and VBN = V × sin(π/3). power information is accumulated over a much shorter time. the CF output is much more responsive to power fluctuations. Table 7. Maximum Output Frequency on CF

used to drive the energy register (electromechanical or other). and a maximum current between 10 A and 100 A. the meter constant is 100 imp/kWhr. Table 8. V. F1 and F2 Frequency at 100 imp/kWhr F2 when all six analog inputs are half scale. Table 9. F1 and F2 Frequency with Half-Scale AC Inputs meter constant should be compared with column 5 of Table 9.

0.15 Hz at 25 A and 220 V (from

the closest frequency to 0.15 Hz in column 5 is 0.12 Hz. 1–7 = 0.6 Hz is selected for this design. output frequencies for F1 and F2 are shown in Table 6. SCF = S1 = 0. In this case, the CF pulse width is 66% of the period. ADE7752 is designed to issue a minimum output frequency. approximately 0.00204% of the F1–7 frequency (see Table 10). Table 10. CF, F1, and F2 Minimum Frequency at No Load

Rev. C | Page 23 of 24 NEGATIVE POWER INFORMATION The ADE7752 detects when the current and voltage channels of any of the three phase inputs have a phase difference greater than 90°: ϕA or ϕB or ϕB C > 90°. This mechanism can detect wrong connection of the meter or generation of active energy. The REVP pin output goes active high when negative power is detected on any of the three phase inputs. If positive active energy is detected on all the three phases, REVP pin output is low. The REVP pin output changes state at the same time a pulse is issued on CF. If several phases measure negative power, the REVP pin output stays high until all the phases measure positive power. If a phase has gone below the no load threshold, REVP detection on this phase is disabled. REVP detection on this phase resumes when the power returns out of no load condition. See the No Load Threshold section.

Figure 28. 24-Lead Standard Small Outline Package [SOIC] registered trademarks are the proper ty of their respective companies.