ADE7566ASTZF16-RL

ADE75 AD | Alldatasheet

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Technical content

Single-Phase Energy Measurement IC with

8052 MCU, RTC and LCD driver

Preliminary Technical Data ADE75xx/ADE71xx Rev. PrE 01/07 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent ri ghts of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2007 Analog Devices, Inc. All rights reserved. GENERAL FEATURES Wide supply voltage operation 2.4 to 3.7V Battery supply input with Automatic switch-over Reference 1.2 V ± 1% (drift 50 ppm/°C Maximum) 64-Lead Quad Flat (LQFP) or Chip Scale (LCSP) Lead Free Packages1 Operating Temperature -40°C to 85°C ENERGY MEASUREMENT FEATURES High accuracy active, reactive energy measurement IC, supports IEC 62053-21, 62053-22, 62053-23 Two differential inputs with PGAs to support Shunt, Current Transformer and di/dt current sensors Selectable Digital integrator to support di/dt current sensor Digital parameters for Gain, offset and phase compensation Selectable No-load threshold level for Watt, VA, and VAR anti-creep Less than 0.1% error on active energy over a dynamic range of 1000 to 1 @ 25C Less than 0.5% error on reactive energy over a dynamic range of 1000 to 1 @ 25C Less than 0.5% error on rms measurements over a dynamic range of 1000 to 1 for current and 100:1 for voltage @ 25C Auto-calibration of offsets High frequency outputs supply proportional to Irms, active, reactive or apparent power Proprietary ADCs and DSP provide high accuracy over large variations in environmental conditions and time Temperature monitoring

1 Please contact your Analog Devices representative to check availability of

Single-cycle 4MIPS 8052 core 8052 compatible instruction set 32.768 kHz external crystal with on-chip PLL Two external interrupt sources External reset pin Real Time Clock Counter for seconds, minutes and hours Automatic battery switchover for RTC back up Ultra-Low Battery Supply Current < 1μA Software clock calibration with temperature and offset compensation Integrated LCD driver 104-segment with 2, 3 or 4 Multiplexer 3V/5V driving capability Internally generated LCD drive voltages Temperature and Supply compensated drive voltages Low power battery mode Wake-up from I/O and UART LCD driver capability On-chip peripherals UART, SPI or I Watch-Dog timer Power Supply Monitoring with User Selectable Levels Memory: 16kBytes Flash Memory, 512 Bytes RAM Development tools Single pin emulation IDE based assembly and C source debugging GENERAL DESCRIPTION The ADE75xx/ADE71xx integrates Analog Devices Energy (ADE) Metering IC analog front end and fixed function DSP solution with an enhanced 8052 MCU core, a RTC, an LCD driver and all the peripherals to make an electronic energy meter with LCD display with a single part. The ADE Energy Measurement core includes Active, Reactive, Apparent Energy calculations, as well as voltage and current rms measurements. This information is ready to use for energy billing by using built-in energy scalars. Many power line supervisory features like SAG, Peak, Zero-crossing are also included in the energy measurement DSP to simplify energy meter design. The microprocessor functionality includes a single cycle 8052 core, a Real Time Clock with a power supply back-up pin, a UART, and a SPI or I2C interface. The ready to use information from the ADE core reduces the program memory size requirement thus making it easy to integrate complicated design in 16k Bytes of Flash memory. The ADE75xx/ADE71xx also includes a 108/104-segment LCD driver respectively. This driver generates voltages capable of driving 5V LCDs.

Figure 1. ADE75xx/ADE71xx Functional Block Diagram

Preliminary Technical Data ADE75xx/ADE71xx Rev. PrE | Page 3 of 148 TABLE OF CONTENT Battery Switchover and Power Supply Restored PSM

ADE75xx/ADE71xx Preliminary Technical Data Rev. PrE | Page 4 of 148

Preliminary Technical Data ADE75xx/ADE71xx Rev. PrE | Page 5 of 148

ADE75xx/ADE71xx Preliminary Technical Data Rev. PrE | Page 6 of 148 Mode 0 (Shift Register with baud rate fixed at Fcore /12) Mode 2 (9- bit UART with baud fixed at Fcore/64 or Fcore/32)

Table 1. (VDD = 3.3 V ± 5%, AGND = DGND = 0 V , On-Chip Reference, XTAL = 32.768kHz, TMIN to TMAX = –40°C to +85°C)

ADE75xx/ADE71xx Preliminary Technical Data Rev. PrE | Page 8 of 148 Parameter Min Typ Max Unit Test Conditions/Comments Internal ADCs (Battery, Temperature, VDD) Power supply operating range 2.2 3.7 V Measured on V SWOUT No missing codes1 8 bits AC Power Supply Rejection TBD dB DC Power Supply Rejection TBD dB Integral Linearity Error -1 1 LSB 3 Differential Linearity Error -1 1 LSB Conversion Delay4 1 ms Temperature sensor accuracy -1 1 °C at 25°C -4 4 °C between -40°C and 85°C VDCIN ANALOG INPUT Maximum Signal Levels 0 V SWOUT V Input Impedance (DC) 1 MΩ Low V DCIN detection threshold 1.08 1.2 1.32 V Power-On Reset (POR) VDD POR Voltage operating range 1 3.7 V Detection threshold 1.6 2.9 V POR active Time-out period TBD ms Strobe period in Battery operation TBD Ms VSWOUT POR Voltage operating range (VSWOUT) 1 3.7 V Detection threshold 1.8 2.2 V POR active Time-out period TBD ms VINTA and VINTD POR Voltage operating range (VSWOUT) 1 3.7 V Detection threshold 2.25 2.4 V POR active Time-out period TBD ms BATTERY SWITCH OVER Voltage operating range (VSWOUT) 2.4 3.7 V VDD Î VBAT switching threshold (VSWOUT) 2.75 TBD V VDD Î VBAT switching delay TBD ms VBAT Î VDD switching threshold (VDD) 2.75 TBD V VBAT Î VDD switching delay VSWOUT to VBAT leakage current TBD ms nA LCD – Charge pump active LCDVP1 – LCDVP2 charge pump capacitance 200 nF LCDVA, LCDVB, LCDVC decoupling capacitance 470 nF LCDVA 0 1.7 V LCDVB 0 4.0 V 1/2 bias modes LCDVB 0 3.4 V 1/3 bias modes LCDVC 0 5.1 V 1/3 bias mode LCD stand-by current 100 nA 1/2 and 1/3 bias modes V1 Segment line voltage LCDVA-0.1 LCDVA V Current on segment line = -2μA V2 Segment line voltage LCDVB-0.1 LCDVB V Current on segment line = -2μA V3 Segment line voltage LCDVC-0.1 LCDVC V Current on segment line = -2μA DC voltage across Segment and COM pin 50 mV LCDVC-LCDVB, LCDVC-LCDVA or LCDVB- LCDVA LCD – Resistor ladder active

Preliminary Technical Data ADE75xx/ADE71xx Rev. PrE | Page 9 of 148 Parameter Min Typ Max Unit Test Conditions/Comments Leakage current ±20 nA 1/2 and 1/3 bias modes – No load V1 Segment line voltage LCDVA-0.1V LCDVA V Current on segment line = -2μA V2 Segment line voltage LCDVB-0.1V LCDVB V Current on segment line = -2μA V3 Segment line voltage LCDVC-0.1V LCDVC V Current on segment line = -2μA ON-CHIP REFERENCE Reference Error ±12 mV Power supply rejection 80 dB Temperature Coefficient 50 ppm/°C DIGITAL INTERFACE LOGIC INPUTS All inputs except XTAL1, XTAL2, BCTRL, INT0, INT1, RESET Input High Voltage, VINH 2.0 V Input Low Voltage, VINL 0.4 V BCTRL, INT0, INT1, RESET Input High Voltage, VINH 1.3 V Input Low Voltage, VINL 0.4 V Input currents RESET ±10 μA RESET = 0V 100 μA RESET = VSWOUT = 3.3V Port 0, 1 , 2 ±10 μA Internal pull-up disabled, input – 0V or VOUT -250 μA Internal pull-up enabled, input = 2V, VSWOUT=3.3V -50 μA Internal pull-up enabled, input = 0.4V, VSWOUT=3.3V Input capacitance 10 pF All digital input CRYSTAL OSCILLATOR Crystal Equivalent Series Resistance 30 50 kΩ Crystal frequency 32 32.768 33.5 kHz XTAL1 Input Capacitance 12 pF XTAL2 Output Capacitance 12 pF MCU CLOCK RATE - Fcore 4.096 MHz Crystal = 32.768kHz and CD[2:0]=0 32 kHz Crystal = 32.768kHz and CD[2:0]=0b111 LOGIC OUTPUTS Output High Voltage, VOH 2.4 V V DD = 3.3 V ± 5% I SOURCE 80 μA Output Low Voltage, VOL 0.4 V V DD = 3.3 V ± 5% I SINK 2 mA Floating state Leakage current ±10 μA Floating state Output Capacitance TBD pF STARTUP TIME5 At Power-On TBD ms From Power Saving Mode 2 (PSM2) TBD μs From Power Saving Mode 1 (PSM1) TBD μs POWER SUPPLY INPUTS VDD 3.0 3.3 3.6 V VBAT 2.4 3.3 3.7 V POWER SUPPLY OUTPUTS VBAT to VSWOUT ON-Resistance 25 Ω VBAT = 2.4V VDD to VSWOUT ON-Resistance 6.1 Ω VDD = 3V VSWOUT output current drive 1 mA VINTA, VINTD 2.25 2.75 V

ADE75xx/ADE71xx Preliminary Technical Data Rev. PrE | Page 10 of 148 Parameter Min Typ Max Unit Test Conditions/Comments VINTA power supply rejection 80 dB VINTD power supply rejection 60 dB POWER SUPPLY CURRENTS Current in Normal Mode (PSM0) 3.5 mA F core = 4.096 MHz Current in Normal Mode (PSM0) 2.1 mA F core = 1.024 MHz Current in PSM1 with VINTA disabled 880 μA Fcore = 1.024 MHz Current in PSM2 1.5 μA 1 These numbers are not production tested but are guaranteed by design and/or characterization data on production release 2 See Terminology section for explanation of specifications.

3 LSB means Least Significant Bit

4 Delay between ADC conversion request and interrupt set

5 Delay between power supply valid and execution of first instruction by 8052 core

Logic 1 and VIL max for Logic 0 as shown in Figure 2. 100 mV change from the loaded VOH/VOL level occurs as shown in Figure 2. CLOAD for all outputs = 80 pF, unless otherwise noted. VDD = 2.7 V to 3.6 V; all specifications TMIN to TMAX, unless otherwise noted. Table 2. CLOCK INPUT (External Clock Driven XTAL1) Parameter system. The core can operate at this frequency or at a binary submultiple called Core_Clk, selected via the PLLCON SFR. Figure 2. Timing Waveform Characteristics

Table 3. I2C COMP ATIBLE INTERFACE TIMING Parameter 1 Input filtering on both the SCLOCK and SDATA inputs suppresses noise spikes less than 50 ns. Figure 3. I2C Compatible Interface Timing

Table 4. SPI MASTER MODE TIMING (CPHA = 1) Parameter

1 Characterized under the following conditions:

a. Core clock divider bits CD2, CD1, and CD0 in POWCON SFR set to 0, 0, and 0, respectively, that is, core clock frequency = 4.096/8 MHz. b. SPI bit-rate selection bits SPIR1 and SPR0 in SPI2CMOD SFR set to 0 and 0, respectively. Figure 4. SPI Master Mode Timing (CPHA = 1)

Table 5. SPI MASTER MODE TIMING (CPHA = 0) Parameter a. Core clock divider bits CD2, CD1, and CD0 in POWCON SFR set to 0, 0, and 0, respectively, that is, core clock frequency = 4.096/8 MHz. b. SPI bit-rate selection bits SPIR1 and SPR0 in SPI2CMOD SFR set to 0 and 0, respectively. Figure 5. SPI Master Mode Timing (CPHA = 0)

Table 6. SPI SLAVE MODE TIMING (CPHA = 1) Parameter Figure 6. SPI Slave Mode Timing (CPHA = 1)

Table 7. SPI SLAVE MODE TIMING (CPHA = 0) Parameter Figure 7. SPI Slave Mode Timing (CPHA = 0)

Table 8. UART Timing (Shift Register Mode) Parameter

4.09612.58 MHz Core_Clk Variable Core_Clk

Figure 8. UART Timing in Shift Register Mode

TA = 25°C, unless otherwise noted. Table 9. Absolute Maximum Rating

2 When used with external resistor divider

degradation or loss of functionality.

Preliminary Technical Data ADE75xx/ADE71xx Rev. PrE | Page 19 of 148 TERMINOLOGY MEASUREMENT ERROR The error associated with the energy measurement made by the ADE75xx/ADE71xx is defined by the following formula: %100Re ×⎟⎟ ⎛ −= EnergyTrue EnergyTruegisterEnergyErrorPercentage PHASE ERROR BETWEEN CHANNELS The digital integrator and the high-pass filter (HPF) in the current channel have a non-ideal phase response. To offset this phase response and equalize the phase response between channels, two phase-correction networks are placed in the current channel: one for the digital integrator and the other for the HPF. The phase correction networks correct the phase response of the corresponding component and ensure a phase match between current channel and voltage channel to within ±0.1° over a range of 45 Hz to 65 Hz with the digital integrator off. With the digital integrator on, the phase is corrected to within ±0.4° over a range of 45 Hz to 65 Hz. POWER SUPPLY REJECTION This quantifies the ADE75xx/ADE71xx measurement error as a percentage of reading when the power supplies are varied. For the ac PSR measurement, a reading at nominal supplies (3.3 V) is taken. A second reading is obtained with the same input signal levels when an ac (100 mV rms/120 Hz) signal is introduced onto the supplies. Any error introduced by this ac signal is expressed as a percentage of reading—see the Measurement Error definition. For the dc PSR measurement, a reading at nominal supplies (3.3 V) is taken. A second reading is obtained with the same input signal levels when the supplies are varied ±5%. Any error introduced is again expressed as a percentage of the reading. ADC OFFSET ERROR The dc offset associated with the analog inputs to the ADCs. It means that with the analog inputs connected to AGND, the ADCs still see a dc analog input signal. The magnitude of the offset depends on the gain and input range selection—see the Typical Performance Characteristics section. However, when HPF1 is switched on, the offset is removed from the current channel and the power calculation is not affected by this offset. The offsets can be removed by performing an offset calibration—see the Analog Inputs section. GAIN ERROR The difference between the measured ADC output code (minus the offset) and the ideal output code—see the Current Channel ADC and difference is expressed as a percentage of the ideal code.

Table 10. Pin Function Descriptions

1 COM3/ FP27 Common output, COM3 is used fo r LCD backplane / LCD segment outputs 27

2 COM2/ FP28 Common output, COM2 is used fo r LCD backplane / LCD segment outputs 28

3 COM1 Common output, COM1 is used for LCD backplanes

4 COM0 Common output, COM0 is used for LCD backplanes

15 LCDVC Output port for LCD levels. This pin should be decoupled with a 470nF capacitor. for internal LCD charge pump device. 17, 18 LCDVB, LCDVA Output ports for LCD levels. Thes e pins should be decoupled with a 470nF capacitor. internal LCD charge pump device. 42 P0.3/CF2 General-purpose digital I/O / Calibration Frequency Logic Output. The CF2 logic output gives instantaneous active, reactive or apparent power information. 43 P0.2/CF1/RTCCAL General-purpose digital I/O / Calibrat ion Frequency Logic Output/ RTC calibration output.. The CF1 logic output gives instantaneous active, reactive or apparent power information. remains low during internal program execution. This pin can also be used as a general purpose output. XTAL1 or by the gate oscillator circuit. frequency for specified operation is 32.768 kHz.

48 INT0 General-purpose digital I/O / Interrupt input

Preliminary Technical Data ADE75xx/ADE71xx Rev. PrE | Page 21 of 148 Pin No. Mnemonic Description 49, 50 V P, VN Analog Inputs for Voltage Channel. These inputs are fully differential voltage inputs with a maximum differential level of ±500mV for specified operation. This channel also has an internal PGA. 51 EA This pin is used as an input for emulation. When held high, this input enables the device to fetch code from internal program memory locations.The ADE75xx/ADE71xx does not support external code memory. This pin should not be left floating. 52, 53 I P, IN Analog Inputs for Current Channel. These inputs are fully differential voltage inputs with a maximum differential level of ±500mV for specified operation. This channel also has an internal PGA.

54 AGND This pin provides the ground reference for the analog circuitry

55 I PB Analog Inputs for second Current Channel. This input is fully differential with a maximum differential level of ±500mVrefered to IN for specified operation. This channel also has an internal PGA.

56 RESET Reset input, Active low

57 REF IN/OUT This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of

1.2 V ± 8% and a typical temperature coefficient of 50 ppm/°C maximum

58 V BAT 3.3V Power supply input from Battery. This pin is connected internally to VDD when the Battery is selected as the power supply for the ADE75xx/ADE71xx. 59 V INTA This pin provides access to the on-chip 2.5V analog LDO. No external active circuitry should be connected to this pin. This pin should be decoupled with a 10μF capacitor in parallel with a ceramic 100nF capacitor. 60 V DD 3.3V Power supply input from regulator. This pin is connected internally to VDD when the regulator is selected as the power supply for the ADE75xx/ADE71xx. This pin should be decoupled with a 10μF capacitor in parallel with a ceramic 100nF capacitor. 61 V SWOUT 3.3V Power supply output from ADE75xx/ADE71xx. This pin provides the supply voltage for the LDOs and internal cicuitry of the ADE75xx/ADE71xx. This pin should be decoupled with a 10μF capacitor in parallel with a ceramic 100nF capacitor. 62 V INTD This pin provides access to the on-chip 2.5V digital LDO. No external active circuitry should be connected to this pin. This pin should be decoupled with a 10μF capacitor in parallel with a ceramic 100nF capacitor.

63 DGND This pin provides the ground reference for the digital circuitry

VDCIN Analog input for dc voltage monitoring. The maximum input voltage on this pin is xxxmV with respect to AGND. This pin is used to monitor the pre-regulated dc voltage. A dedicated ADC measures the voltage on this pin—see the External Voltage Measurement section.

ADE75xx/ADE71xx Preliminary Technical Data Rev. PrE | Page 22 of 148 SFR MAPPING IPSMF STRBPER BATVTH SCRATCH1 SCRATCH2 SCRATCH3 SCRATCH4 INTPR xF8 Table 13 xF9 Table 46 xFA Table 49 xFB Table 17 xFC Table 18 xFD Table 19 xFE Table 20 xFF Table 12 B DIFFPROG PERIPH BATPR RTCCOMP TEMPCAL xF0 x F 3 Table 47 xF4 Table 15 xF5 Table 14 xF6 Table 116 xF7 Table 117 SPIMOD1 I2CMOD SPIMOD2 I2CADR SPISTAT I2CSTAT IPSME LCDSEGE2 VDCINADC xE8 Table 130 Table 135 xE9 Table 131 Table 136 xEA Table 132 Table 137 xEC Table 16 xED Table 84 xEF Table 50 xE8 Table 130 Table 135 xE9 Table 131 Table 136 xEA Table 132 xEC Table 16 xED Table 84 xEF Table 50 ACC WAV 1 L WAV 1 M WAV 1 H WAV 2 L WAV 2 M WAV 2 H xE0 xE2 Table 27 xE3 Table 27 xE4 Table 27 xE5 Table 27 xE6 Table 27 xE7 Table 27 ADCGO MIRQENL MIRQENM MIRQENH MIRQSTL MIRQSTM MIRQSTH BATADC xD8 48 xD9 Table 39 xDA Table 40 xDB Table 41 xDC Table 36 xDD Table 37 xDE Table 38 xDF Table 51 PSW VRMSL VRMSM VRMSH IRMSL IRMSM IRMSH TEMPADC xD0 Table 54 xD1 Table 27 xD2 Table 27 xD3 Table 27 xD4 Table 27 xD5 Table 27 xD6 Table 27 xD7 Table 52 T2CON RCAP2L RCAP2H TL2 TH2 xC8 Table 99 xCA Table 107 xCB Table 106 xCC Table 105 xCD Table 104 WDCON KYREG POWCON EADRL EADRH xC0 Table 71 xC1 Table 109 xC5 Table 22 xC6 Table 94 xC7 Table 95 IP ECON FLSHKY PROTKY EDATA PROTB0 PROTB1 PROTR xB8 Table 64 xB9 Table 87 xBA Table 88 xBB Table 89 xBC Table 90 xBD Table 91 xBE Table 92 xBF Table 93 LCDCONY PINMAP0 PINMAP1 PINMAP2 xB1 Table 77 xB2 Table 141 xB3 Table 142 xB4 Table 143 IE IEIP2 LCDPTR LCDDAT CFG xA8 Table 63 xA9 Table 65 xAC Table 82 xAE Table 83 xAF Table 59 P2 TIMECON HTHSEC SEC MIN HOUR INTV AL DPCON xA0 Table 146 xA1 Table 110 xA2 Table 111 xA3 Table 112 xA4 Table 113 xA5 Table 114 xA6 Table 115 xA7 Table 138 SCON SBUF SPI2CTx SPI2CRx LCDCON X SBAUDF SBAUDT EPCFG x98 Table 122 x99 Table 123 x9A Table 128 x9B Table 129 x9C Table 75 x9D Table 125 x9E Table 124 x9F Table 140 P1 MADDPT MDATL MDATM MDATH LCDCON LCDCLK LCDSEGE x90 Table 145 x91 Table 27 x92 Table 27 x93 Table 27 x94 Table 27 x95 Table 74 x96 Table 78 x97 Table 81 TCON TMOD TL0 TL1 TH0 TH1 x88 Table 98 x89 Table 97 x8A Table 101 x8B Table 103 x8C Table 100 x8D Table 102 P0 SP DPL DPH PCON x80 Table 144 x81 Table 58 x82 Table 56 x83 Table 57 x87 Table 55 Mnemonic WDCON xC0 Table 71 MAPKEY Address Link to detailed table

Preliminary Technical Data ADE75xx/ADE71xx Rev. PrE | Page 23 of 148 POWER MANAGEMENT The ADE75XX/ADE71XX has an elaborate power management circuitry that manages the regular power supply to Battery switch over and power supply failures. The power management functionalities can be accessed directly through the 8052 SFR – see Table 11. Table 11. Power Management SFRs Table 12. Interrupt pins configuration SFR (INTPR, 0xFF)

Description

7 RTCCAL 0 Control RTC calibration output

When set, the RTC calibration frequency selected by FSEL[1:0] is output on the P0.2/CF1/RTCCAL pin. Sets RTC calibration output frequency and calibration window FSEL[1:0] Calibration window, frequency 0 0 30.5 seconds, 1Hz 0 1 30.5 seconds, 512 Hz 1 0 0.244 seconds, 500Hz 6-5 FSEL[1:0] 1 1 0.244 seconds, 16.384 kHz

4 Reserved

Controls the function of INT1 T INT1PRG[2:0] Function x 0 0 GPIO x 0 1 BCTRL 0 1 x INT1 input disabled 3-1 INT1PRG[2:0] 000 1 1 x INT1 input enabled

ADE75xx/ADE71xx Preliminary Technical Data Rev. PrE | Page 24 of 148 Controls the function of INT0 INT0PRG Function

0 INT0 input disabled

0 INT0PRG 0

1 INT0 input enabled

Table 13. Power Management Interrupt Flag SFR (IPSMF, 0xF8) 7 0xFF FPSR 0 Power Supply Restored Interrupt flag. Set when the VDD power supply has been restored. This occurs when the source of VSW changes from VBAT to VDD. 6 0xFE FPSM 0 PSM Interrupt flag. Set when an enabled PSM interrupt condition occurs. 5 0xFD FSAG 0 Voltage SAG Interrupt flag. Set when an ADE energy measurement SAG condition occurs. 4 0xFC RESERVED 0 This bit must be kept cleared for proper operation 3 0xFB FVADC 0 V DCIN ADC interrupt flag. Set when VDCIN changes by VDCINDIF or when a VDCIN measurement is ready. 2 0xFA FBAT 0 V BAT Monitor interrupt flag. Set when VBAT falls below BATVTH or when the VBAT measurement is ready. 1 0xF9 FBSO 0 Battery Sw itchover interrupt flag. Set when VSW switches from VDD to VBAT. 0 0xF8 FVDC 0 V DCIN Monitor interrupt flag. Set when VDCIN falls below 1.2V. Table 14. Battery Switchover Configuration SFR (BATPR, 0xF5) 7-2 Reserved 00 These bits must be kept to 0 for proper operation Control bits for Battery Switchover. BATPRG [1:0] Function 0 0 Battery Swichover Enabled on Low V DD 0 1 Battery Swichover Enabled on Low V DD and Low VDCIN 1-0 BATPRG [1:0] 00

1 X Battery Switchover Disabled

Table 15. Peripheral Configuration SFR (PERIPH, 0xF4)

7 RXFLAG 0 If set, indicates that a RX Edge event triggered wakeup from PSM2

Indicates the power supply that is connected internally to V SW.

0 V SW=VBAT

6 VSWSOURCE 1

1 V SW=VDD

5 VDD_OK 1 If set, indicates that VDD power supply is ok for operation

4 PLL_FLT 0 If set, indicates that a PLL fault occurred where the PLL lost lock. Set the PLL_FLT_ACK bit in the Start ADC Measurement SFR (ADCGO, 0xD8) SFR to acknowledge the fault and clear the PLL_FLT bit 3 REF_BAT_EN 0 If set, Internal voltage reference enabled in PSM2 mode. This bit should be set to maintain the LCD in PSM2 mode.

2 Reserved 0 This bit should be kept to zero

Controls the function of the P1.0/RX pin. RXPROG [1:0] Function 1-0 RXPROG[1:0] 00 0 0 GPIO

Preliminary Technical Data ADE75xx/ADE71xx Rev. PrE | Page 25 of 148 0 1 RX with wakeup disabled 1 1 RX with wakeup enabled Table 16. Power Management Interrupt Enable SFR (IPSME, 0xEC) 7 EPSR 0 Enables a PSM interrupt when th e Power Supply Restored flag is set.

6 RESERVED 0 Reserved

5 ESAG 0 Enables a PSM interrupt when the voltage sag flag (FSAG) is set.

4 RESERVED 0 This bit must be kept cleared for proper operation

3 EVADC 0 Enables a PSM interrupt when the V DCIN ADC flag (FVADC) is set. 2 EBAT 0 Enables a PSM interrupt when the V BAT monitor flag (FBAT) is set. 1 EBSO 0 Enables a PSM interrupt when the Battery Switchover flag (FBSO) is set. 0 EVDCIN 0 Enables a PSM interrupt when the V DCIN monitor flag (FVDCIN) is set. Table 17. Scratch Pad 1 SFR (SCRATCH1, 0xFB) 7-0 SCRATCH1 0 Value can be written/read in this register. This value will be maintained in all the power saving modes of the ADE75xx/ADE71xx Table 18. Scratch Pad 2 SFR (SCRATCH2, 0xFC) 7-0 SCRATCH2 0 Value can be written/read in this register. This value will be maintained in all the power saving modes of the ADE75xx/ADE71xx Table 19. Scratch Pad 3 SFR (SCRATCH3, 0xFD) 7-0 SCRATCH3 0 Value can be written/read in this register. This value will be maintained in all the power saving modes of the ADE75xx/ADE71xx Table 20. Scratch Pad 4 SFR (SCRATCH4, 0xFE) 7-0 SCRATCH4 0 Value can be written/read in this register. This value will be maintained in all the power saving modes of the ADE75xx/ADE71xx Table 21. Key SFR (KYREG, 0xC1) 7-0 KYREG 0 Write 0xA7 to the KYREG SFR befo re writing the POWCON SFR, to unlock it Write 0xEA to the KYREG SFR before writing to the HTHSEC, SEC, MIN, or HOUR timekeeping register to unlock it.. Table 22. Power Control SFR (POWCON, 0xC5)

7 RESERVED X

ADE75xx/ADE71xx Preliminary Technical Data Rev. PrE | Page 26 of 148 6 METER_OFF 0 Set this bit to turn off the modulators and energy metering DSP circuitry to reduce power if metering functions are not needed in PSM0

5 RESERVED 0

4 COREOFF 0 Set this bit to shut down the core if in the PSM1 operating mode.

3 RESERVED

Controls the core clock frequency, Fcore. Fcore=4.096MHz/2CD CD[2:0] F core (MHz) 0 0 0 4.096 0 0 1 2.048 0 1 0 1.024 0 1 1 0.512 1 0 0 0.256 1 0 1 0.128 1 1 0 0.064 2-0 CD[2:0] 010 1 1 1 0.032 Note: The POWCON register must be unlocked by first writing to the KYREG key register. The KYREG SFR is set to 0xA7 to unlock the POWCON SFR and then the POWCON SFR can be modified. For example: MOV KYREG,#0A7h ;Write KYREG to 0xA7 to get write access to the POWCON SFR MOV POWCON, #10H ;Shutdown the core POWER SUPPLY ARCHITECTURE ADE75XX/ADE71XX has two power supply inputs, VDD and VBAT, and requires only a single 3.3V power supply at VDD for full operation. A battery backup, or secondary power supply, with a maximum of 3.6V can be connected to the VBAT input. Internally, the ADE75XX/ADE71XX connects VDD or VBAT to VSW, which is used to derive the power for the ADE75XX/ADE71XX circuitry. The VSWOUT output pin reflects the voltage at VSW, and has a maximum output current of TBD mA. This pin may also be used to power a limited number of peripheral components. The 2.5V analog supply, V INTA and the 2.5V supply for the core logic, VINTD, are derived by on-chip linear regulators from VSW. Figure 9 shows the power supply architecture of ADE75XX/ADE71XX. The ADE75XX/ADE71XX provides automatic battery switchover between VDD and VBAT based on the voltage level detected at VDD or VDCIN. Additionally, the BCTRL input can also be used to trigger a battery switchover. The conditions for switching VSW from VDD to VBAT and back to VDD are described in the Battery Switchover section. VDCIN is an input pin that can be connected to a 0V to 3.3V DC signal. This input is intended for power supply supervisory purposes and does not provide power to the ADE75XX/ADE71XX circuitry - see Battery Switchover section. MCU SCRATCHPAD LCD RTC TEMPERATURE ADC DCINV DDV INTDV INTAV 3.3V 2.5V LDO BATV SWOUTV BCTRL SWV ADE SPI/I2C UART LDO POWER SUPPLY MANAGEMENT ADC ADC Figure 9: Power Supply Architecture BATTERY SWITCHOVER ADE75XX/ADE71XX monitors VDD, VBAT, and VDCIN. Automatic battery switchover from VDD to VBAT can be configured based on the status of VDD, VDCIN, or the BCTRL pin. Battery switchover is enabled by default. Setting bit 1 in the Battery Switchover Configuration SFR (BATPR, 0xF5), disables battery switchover so that VDD is always connected to VSW. The source of VSW is indicated by bit 6 in the Peripheral Configuration SFR (PERIPH, 0xF4), which is set when VSW is connected to VDD and cleared when VSW is connected to VBAT. The battery switchover functionality provided by the ADE75XX/ADE71XX allows a seamless transition from VDD to VBAT. An automatic battery switchover option ensures a stable power supply to the ADE75XX/ADE71XX, as long as the external battery voltage is above TBD V . It allows continuous code execution even while the internal power supply is switching from V DD to VBAT and back. Note that the energy metering ADCs are not available when VBAT is being used for

Preliminary Technical Data ADE75xx/ADE71xx Rev. PrE | Page 27 of 148 VSW. Power supply monitor (PSM) interrupts can be enabled to indicate when battery switchover occurs and when the VDD power supply is restored - see the Power Supply Monitor Interrupt (PSM) section. Switching from VDD to VBAT There are three events that can be enabled to switch the internal power supply, VSW, from VDD to VBAT: 1. (VDCIN < 1.2 V): When VDCIN falls below 1.2V VSW switches from VDD to VBAT. This event is enabled when the BATTPROG[1:0] bits in the Battery Switchover Configuration SFR (BATPR, 0xF5) are clear. Setting this bit will disable switchover based on VDCIN. Battery switchover on low VDCIN is disabled by default. 2. (VDD < TBD V): When VDD falls below TBD V VSW switches from VDD to VBAT. This event is enabled when BATTPROG[1] in the Battery Switchover Configuration SFR (BATPR, 0xF5) is cleared. 3. Rising edge on BCTRL: When the battery control pin, BCTRL, goes high, VSW switches from VDD to VBAT. This external switchover signal can trigger a switchover to VBAT at any time. Setting bits INT1PRG[4:2] to 0bx01 in the Interrupt pins configuration SFR (INTPR, 0xFF) enables the battery control pin. Switching from VBAT to VDD To s witch VSW back from VBAT to VDD all of the events that are enabled to force battery switchover must be false: 1. (VDCIN < 1.2 V) and (VDD < TBD V) Enabled: If the low VDCIN condition is enabled, VSW switches to VDD after VDCIN remains above TBD V for TBD seconds and VDD remains above TBD V for TBD seconds. 2. (VDD < TBD V) Enabled: VSW switches back to VDD after VDD has been above TBD V for TBD seconds. 3. BCTRL Enabled: VSW switches back to VDD after BCTRL is low and number 1 or number 2 are satisfied. POWER SUPPLY MONITOR INTERRUPT (PSM) The Power Supply Monitor Interrupt (PSM) alerts the 8052 core of power supply events. The PSM interrupt is disabled by default. Setting the EPSM bit in the Interrupt Enable and Priority 2 SFR (IEIP2, 0xA9) enables the PSM interrupt. The Power Management Interrupt Enable SFR (IPSME, 0xEC) controls the events that result in a PSM interrupt. Figure 10 is a diagram illustrating how the PSM interrupt vector is shared among the PSM interrupt sources. The PSM interrupt flags are latched and must be cleared by writing to the flag register. EPSR ESAG EBAT EBSO EVDCIN FPSR FSAG FBAT FBSO FVDCINFPSM IPSME Addr. 0ECh IPSMF Addr. 0F8h ETI EPSM ESIPTI PSIIEIP2 Addr. 0A9h ADEAUTOCLR EPSR ESAG EBAT EVSW EBSO FPSR FSAG FBAT FVSW FBSO FPSM Pending PSM interruptEPSM TRUE? EVSWreserved reserved reserved reserved EADE : Not involved in PSM Interrupt signal chain FVSW EVDCIN FVDCIN Figure 10: PSM Interrupt Sources

Preliminary Technical Data ADE75xx/ADE71xx Rev. PrE | Page 28 of 148 Battery Switchover and Power Supply Restored PSM Interrupt The ADE75XX/ADE71XX can be configured to generate a PSM interrupt when the source of VSW changes from VDD to VBAT, indicating battery switchover. Setting the EBSO bit in the Power Management Interrupt Enable SFR (IPSME, 0xEC) enables this event to generate a PSM interrupt. The ADE75XX/ADE71XX can also be configured to generate an interrupt when the source of VSW changes from VBAT to VDD, indicating that the VDD power supply has been restored. This event is enabled to generate a PSM interrupt by setting the EPSR bit in the Power Management Interrupt Enable SFR (IPSME, 0xEC). The flags in the Power Management Interrupt Flag SFR (IPSMF, 0xF8) for these interrupts, BSOF and PSRF are set regardless of whether the respective enable bits have been set. The battery switchover and power supply restore event flags, BSOF and PSRF , are latched. These events must be cleared by writing a zero to these bits. Bit 6 in the Peripheral Configuration SFR (PERIPH, 0xF4), VSWSOURCE, tracks the source of VSW. The bit is set when VSW is connected to VDD and cleared when VSW is connected to VBAT. VDCIN ADC PSM Interrupt The ADE75XX/ADE71XX can be configured to generate a PSM interrupt when VDCIN changes magnitude by more than a configurable threshold. This threshold is set in the Temperature and Voltage ADC Delta SFR (DIFFPROG, 0xF3) –see External Voltage Measurement section. Setting the EV ADC bit in the Power Management Interrupt Enable SFR (IPSME, 0xEC) enables this event to generate a PSM interrupt. The VDCIN voltage is measured using a dedicated ADC. These measurements take place in the background at intervals to check the change in VDCIN. Conversions can also be initiated by writing to the Start ADC Measurement SFR (ADCGO, 0xD8). The FV ADC flag will indicate that a VDCIN measurement is ready. See the External Voltage Measurement section for details on how VDCIN is measured. VBAT Monitor PSM Interrupt The VBAT voltage is measured using a dedicated ADC. These measurements take place in the background at intervals to check the change in V BAT. The BATTF bit is set when the battery level is lower than the threshold set in the Battery detection threshold SFR (BATVTH, 0xFA) or when a new measurement is ready in the Battery ADC value SFR (BATADC, 0xDF) - see Battery measurement section. Setting the EBATT bit in the Power Management Interrupt Enable SFR (IPSME, 0xEC) enables this event to generate a PSM interrupt. VDCIN Monitor PSM Interrupt The VDCIN voltage is monitored by a comparator. The FVDC bit in the Power Management Interrupt Flag SFR (IPSMF, 0xF8) is set when the VDCIN input level is lower than 1.2 V . Setting the EVDCIN bit in the Power Management Interrupt Enable SFR (IPSME, 0xEC) enables this event to generate a PSM interrupt. This event associated with the SAG monitoring can be used to detect a power supply - V DD - being compromised and trigger further actions prior to decide a switch of VDD to VBAT . SAG Monitor PSM Interrupt The ADE75XX/ADE71XX energy measurement DSP monitors the ac voltage input at the VP and VN input pins. The SAGLVL register is used to set the threshold for a line voltage sag event. The SAGF bit in the Power Management Interrupt Flag SFR (IPSMF, 0xF8) is set if the line voltage stays below the level set in the SAGLVL register for the number of line cycles set in the SAGCYC register, - see Line Voltage Sag Detection section. Setting the ESAG bit in the Power Management Interrupt Enable SFR (IPSME, 0xEC) enables this event to generate a PSM interrupt. USING THE POWER SUPPLY FEATURES In an energy meter application, VDD, the 3.3V power supply, is typically generated from the ac line voltage and regulated to 3.3V by a voltage regulator IC. The pre-regulated DC voltage, typically 5V to 12V , can be connected to VDCIN through a resistor divider. A 3.6V battery can be connected to VBAT. Figure 11 shows how the ADE75XX/ADE71XX power supply inputs would be set up in this application.

ADE75xx/ADE71xx Preliminary Technical Data Rev. PrE | Page 30 of 148 BSO Event (FBSO=1) V -VPN VDCIN VDD SAG LEVEL trip point 2.75V SAG Event (FSAG=1) V Event 1.2V DCIN SAGCYC=1 Automatic Battery switchover V connected to VSW BAT If switchover on low V is enabled,DCIN (FVDC=1) t1 t3 Figure 13: Power Supply Management Interrupts and Battery Switchover with VDD or VDCIN enabled for battery switchover Time Comment t1 TBD Time between when V DCIN goes below 1.2 V and when FVDCIN is raised. t2 TBD Time between when V DD falls below TBD V and when battery switchover occurs. t3 TBD Time between when V DCIN falls below 1.2 V and when battery switchover occurs, if VDCIN is enabled to cause battery switchover. VDCIN_OPT[1:0] in the Battery Switchover Configuration SFR (BATPR, 0xF5) sets this timeout Table 23: Power Supply Event Timings Operating Modes Finally, the transition between VDD and VBAT and the different Power Supply Modes (see Operating modessection) is represented in Figure 15.

Preliminary Technical Data ADE75xx/ADE71xx Rev. PrE | Page 31 of 148 V -VPN VDCIN 1.2V SAG LEVEL Trip point VDD VBAT 2.75V SAG EVENT VDCIN EVENT 30ms min. VSW Battery switch enabled on low VDCIN VSW Battery switch enabled on low VDD VDCIN EVENT 30ms min. PSM0 PSM0 PSM0 PSM0 PSM1 or PSM2 PSM1 or PSM2 Figure 14: Power Supply Management transitions between modes

8052 core and all of the digital circuitry are enabled by default. V if the PWRDN bit in the MODE1 register (0x0B) is cleared. or software reset, is 1.024 MHz.

1. The RAM in the MCU is no longer valid.
2. The program counter for the 8052, also held in volatile

vector when the ADE75XX/ADE71XX comes out of PSM2. until an event occurs to wake it up. Table 24. The SFRs that are not listed in this table should be restored when the part enters PSM0 or PSM1 frm PSM2 mode. Table 24. SFR maintained in PSM2

Wa keup Eve nts column i n Table 25. Table 25. 3.3V Peripherals and Wakeup Events SW switches to be connected to VDD). This is a nonmaskable wakeup event. every day to update its calendar. This event is a nonmaskable wakeup event. the RTC Configuration SFR (TIMECON, 0xA1). pull-up through the I2C port for example. The interrupts can be enabled/disabled. The IE0 flag bit in the TCON register will not be affected. The IE1 flag bit in the TCON register will not be affected. is in PSM2, it will wake up to PSM1. Scratchpad - - - - The 4 SCRATCHx registers will remain intact in PSM2. section describes events that change the operating mode.

ADE75xx/ADE71xx Preliminary Technical Data Rev. PrE | Page 34 of 148 operating mode. When battery switchover occurs, the analog circuitry used in the ADE energy measurement DSP is disabled. To reduce power consumption, the user code can initiate a transition to PSM2. Entering Sleep Mode (PSM1 to PSM2) To re duce p ower consumpt ion w hen VSW is connected to VBAT, user code can initiate sleep mode, PSM2, by setting bit 4 in the Power Control SFR (POWCON, 0xC5) to shut down the MCU core. Events capable of waking the MCU can be enabled—see the 3.3V Peripherals and Wakeup Events section. Servicing Wakeup Events (PSM2 to PSM1) The ADE75XX/ADE71XX may need to wake up from PSM2 to service wakeup events – see the 3.3V Peripherals and Wakeup Events section. PSM1 code execution will begin at the power on reset vector. After servicing the wakeup event, the ADE75XX/ADE71XX can return to PSM2 by setting bit 4 in the Power Control SFR (POWCON, 0xC5) to shut down the MCU core. Automatic Switch to VDD (PSM2 to PSM0) If the conditions to switch VSW from VBAT to VDD occur (see the Battery Switchover section), the operating mode will switch to PSM0. When this switch occurs, the MCU core and the analog circuitry used in the ADE energy measurement DSP will start up again automatically. PSM0 code execution will begin at the power on reset vector. Automatic Switch to VDD (PSM1 to PSM0) If the conditions to switch VSW from VBAT to VDD occur (see the Battery Switchover section), the operating mode will switch to PSM0. When this switch occurs, the analog circuitry used in the ADE energy measurement DSP will start up automatically. Note that code execution will continue normally. A software reset can be performed to start PSM0 code execution at the power on reset vector. USING THE POWER MANAGEMENT FEATURES Since program flow is different for each operating mode, the status of VSW must be known at all times. The VSWSOURCE bit in the Power Management Interrupt Flag SFR (IPSMF, 0xF8) indicates what VSW is connected to. This bit can be used to control program flow on wakeup. Since code execution always starts at the power on reset vector, bit 6 of the Peripheral Configuration SFR (PERIPH, 0xF4) can be tested to determine which power supply is being used and to branch to normal code execution or to wakeup event code execution. Power supply events can also occur when the MCU core is active. T o be aware of events that change what V SW is connected to: ¾ Enable the battery switchover interrupt (EBSO) if VSW=VDD at power up. ¾ Enable the power supply restored interrupt (EPSR) if VSW=VBAT at power up. An early warning that battery switchover is about to occur is provided by SAG detection and possibly low VDCIN detection— see the Battery Switchover section. For a user controlled battery switchover, enable automatic battery switchover on low V DD only. Then enable the low VDCIN event to generate the PSM interrupt. When a low VDCIN event occurs, start data backup. Upon completion of the data backup, enable battery switchover on low VDCIN. Then battery switchover will occur TBDms later. PSM0 Normal Mode VSW connected to VDD PSM1 Battery Mode VSW connected to VBAT PSM2 Sleep Mode VSW connected to VBAT User code directs MCU to shutdown core after servicing wakeup event Automatic Battery Switchover Power Supply Restored Wakeup Event Power Supply Restored Figure 15: Transitioning between Operating Modes

data SFR registers for the majority of the energy measurements. Table 26. Other energy act as pointers to the energy measurement internal registers. the SFR when the SFR is read. Table 26. Energy Measurement pointer address SFR MDATM and MDATH SFR contents are ignored. these registers is implemented. MDATM and MDATH SFR content are reset to 00h.

Preliminary Technical Data ADE75xx/ADE71xx Rev. PrE | Page 36 of 148 Table 27. Energy measurement SFRs Table 28. Energy Measurement Register List 0x01 WATTHR R 24 S 0 Read Watt-ho ur accumulator without reset 0x02 RWATTHR R 24 S 0 Read Watt- hour accumulator with reset 0x03 LWATTHR R 24 S 0 Read Watt-hour accumulator synchronous to line cycle

Preliminary Technical Data ADE75xx/ADE71xx Rev. PrE | Page 37 of 148 Address MADDPT[6:0] Name R/W Length Signed /Unsigned Default Value 0x04 VARHR R 24 S 0 Read VAR-ho ur accumulator without reset3 0x05 RVARHR R 24 S 0 Read VAR-hour accumulator with reset 1 0x06 LVARHR R 24 S 0 Read VAR-hour accumulator synchronous to line cycle1 0x07 VAHR R 24 S 0 Read VA-hour accumulator without reset 0x08 RVAHR R 24 S 0 Read VA-hour accumulator with reset 0x09 LVAHR R 24 S 0 Read VA-hour accu mulator synchronous to line cycle 0x0A PER_FREQ R 16 U 0 Read Line Period or Frequency register depending on Mode2 register 0x0B MODE1 R/W 8 U 0x06 Set basic configuration of energy measurement – see Table 29 0x0C MODE2 R/W 8 U 0x40 Set basic configuration of energy measurement – see Table 30 0x0D WAVMODE R/W 8 U 0 Set configuration of waveform sample 1 and waveform sample 2 – see Table 31 0x0E NLMODE R/W 8 U 0 Set level of energy no-load thresholds - Table 32 0x0F ACCMODE R/W 8 U 0 Set configuration of Watt, VAR accumulation and various tamper alarms – see Table 33 0x10 PHCAL R/W 8 S 0x40 Set phase calibration register – see Phase Compensation section 0x11 ZXTOUT R/W 12 0x0FFF Set time out for Zero-crossing time out detection – see Zero-Crossing Timeout 0x12 LINCYC R/W 16 U 0xFFFF Set number of half line cycles for LWATTHR, LVARHR and LVAHR accumulators 0x13 SAGCYC R/W 8 U 0xFF Set number of half line cycles for SAG detection – see Line Voltage Sag Detection 0x14 SAGLVL R/W 16 U 0 Set detection level for SAG detection - see Line Voltage Sag Detection 0x15 IPKLVL R/W 16 U 0xFFFF Set peak detection level for current peak detection – see Peak Detection 0x16 VPKLVL R/W 16 U 0xFFFF Set peak detection level for voltage peak detection– see Peak Detection 0x17 IPEAK R 24 U 0 Read current peak level without reset – see Peak Detection 0x18 RSTIPEAK R 24 U 0 Read current peak level with reset – see Peak Detection 0x19 VPEAK R 16 U 0 Read voltage peak level without reset – see Peak Detection 0x1A RSTVPEAK R 16 U 0 Read voltage peak level with reset – see Peak Detection 0x1B GAIN R/W 8 U 0 Set PGA ga in of analog inputs – see Table 34 0x1C IBGAIN 4 R/W 12 S 0 Set Matching Ga in for IB current input 0x1D WGAIN R/W 12 S 0 Set Watt gain register 0x1E VARGAIN R/W 12 S 0 Set VAR gain register 0x1F VAGAIN R/W 12 S 0 Set VA gain register 0x20 WATTOS R/W 16 S 0 Set Watt offset register 0x21 VAROS R/W 16 S 0 Set VAR offset register 0x22 IRMSOS R/W 12 S 0 Set current rms offset register 0x23 VRMSOS R/W 12 S 0 Set voltage rms offset register 0x24 WDIV R/W 8 U 0 Set Watt energy scaling register 3 This function is not available in ADE7566 and ADE7166 products. 4 This function is not available in ADE7566 and ADE7569 products.

ADE75xx/ADE71xx Preliminary Technical Data Rev. PrE | Page 38 of 148 Address MADDPT[6:0] Name R/W Length Signed /Unsigned Default Value 0x25 VARDIV R/W 8 U 0 Set VA R energy scaling register 0x26 VADIV R/W 8 U 0 Set VA energy scaling register 0x27 CF1NUM R/W 16 U 0 Set CF1 numerator register 0x28 CF1DEN R/W 16 U 0x003F Set CF1 denominator register 0x29 CF2NUM R/W 16 U 0 Set CF2 numerator register 0x2A CF2DEN R/W 16 U 0x003F Set CF2 denominator register 0x3D CALMODE R/W 8 U 0 Set Calibration Mode ENERGY MEASUREMENT INTERNAL REGISTERS DETAILS Table 29. MODE1 register (0x0B)

7 SWRST 0 Setting this bit will reset all of the energy measurement registers to their

6 DISZXLPF 0 Setting this bit disables the zero-crossing lowpass filter

5 INTE 1 0 Setting this bit enables the digital integrator for use with a di/dt sensor

4 SWAPBITS 0 Setting this bit swaps CH1 & CH2 ADCs

3 PWRDN 0 Setting this bit powers down voltage and current ADC’s

2 DISCF2 1 Setting this bit disables Frequency output CF2

1 DISCF1 1 Setting this bit disables Frequency output CF1

0 DISHPF 0 Setting this bit disables the HPFs in voltage and current channels

Table 30. MODE2 register (0x0C) 7-6 CF2SEL[1:0] 01 Configuration bits for CF2 output CF2SEL[1:0] Source

00 CF2 frequency is proportional to active power

01 CF2 fr equency is proportional to reactive power5

1x CF2 freq uency is proportional to apparent power or IRMS 5-4 CF1SEL[1:0] 00 Configuration bits for CF1 output CF1SEL[1:0] Source

00 CF1 frequency is proportional to active power

01 CF1 fr equency is proportional to reactive power

1x CF1 freq uency is proportional to apparent power or IRMS

3 VARMSCFCON 0 Configuration bits for appare nt power or IRMS for CF1 and CF2 outputs

0 If CF1SEL[1:0]=1x, CF1 is proportional to VA

If CF2SEL[1:0]=1x, CF2 is proportional to VA

1 If CF1SEL[1:0]=1x, CF1 is proportional to IRMS

If CF2SEL[1:0]=1x, CF2 is proportional to IRMS Note that CF1 cannot be proportional to VA if CF2 is proportional to IRMS and vice versa

2 ZXRMS 0 Logic one enables update of RM S values synchronously to voltage ZX

1 FREQSEL 0 Configuration bits to select PERIOD or FREQUENCY measurement for

PER_FREQ register (0Ah)

0 PER_FREQ register holds a period measurement

5 This function is not available in ADE7566 and ADE7166 products.

Preliminary Technical Data ADE75xx/ADE71xx Rev. PrE | Page 39 of 148

1 PER_FREQ register holds a frequency measurement

0 Reserved 1 This bit should be kept to one

Table 31. W AVMODE register (0x0D) 7-5 WAV2SEL[2:0] 0 Waveform 2 selection for samples mode WAV2SEL[2:0] Source

000 Current

001 Voltage

010 Active Power multiplier output

011 Reactive Power multiplier output

100 VA multiplier output

101 IRMS LPF output

4-2 WAV1SEL[2:] 0 Waveform 1 selection for samples mode WAV1SEL[2:0] Source

101 IRMS LPF output (low 24-bit)

1-0 DTRT[1:0] 0 Waveform sa mples output data rate DTRT[1:0] Update rate (clock=MCLK/5=819.2kHz) 00 25.6Ksps(clock/32) 01 12.8Ksps(clock/64) 10 6.4Ksps(clock/128) 11 3.2Ksps(clock/256) Table 32. NLMODE register (0x0E)

7 DISVARCMP 1 0 Setting this bit disables fundamental VAR gain compensation over line

6 IRMSNOLOAD 0 Logic one enables IRMS no-load thresold detection. The level is defined by the setting of the VANOLOADbits. 5-4 VANOLOAD[1:0] 0 Apparent Power No-load threshold [1:0]

00 No-load detection disabled

01 No-load enabled with threshold = 0.030% of Full scale 10 No-load enabled with threshold = 0.015% of Full scale 11 No-load enabled with threshold = 0.0075% of Full scale 3-2 VARNOLOAD[1:0] 1 0 Reactive Power No-load threshold [1:0] 01 No-load enabled with threshold = 0.015% of Full scale 10 No-load enabled with threshold = 0.0075% of Full scale 11 No-load enabled with threshold = 0.0037% of Full scale 1-0 APNOLOAD[1:0] 0 Active Power No-load threshold 6 This function is not available in ADE7566 and ADE7166 products.

ADE75xx/ADE71xx Preliminary Technical Data Rev. PrE | Page 40 of 148 [1:0] 01 No-load enabled with threshold = 0.015% of Full scale 10 No-load enabled with threshold = 0.0075% of Full scale 11 No-load enabled with threshold = 0.0037% of Full scale Table 33. ACCMODE register (0x0F)

7 ICHANNEL 7 0 This bit indicate the current channel used to measure energy in anti-

tampering mode. 0 – Channel A 1 – Channel B

6 FAULTSIGN 1 0 Configuration bit to select event that will trigger a Fault interrupt

0 – FAULT interrupt occurs when part enters Fault Mode 1 – FAULT interrupt occurs when part enters Normal Mode

5 VARSIGN 8 0 Configuration bit to select event that will trigger an reactive power sign

0 – VARSIGN interrupt occurs when reactive power changes from positive to negative 1 - VARSIGN interrupt occurs when reactive power changes from negative to positive

4 APSIGN 0 Configuration bit to select event that will trigger an active power sign

0 – APSIGN interrupt occurs when active power changes from positive to negative 1 - APSIGN interrupt occurs when active power changes from negative to positive

3 ABSVARM 2 0 Logic one enables absolute value accumulation of Reactive power in

energy register and pulse output

2 SAVARM 2 0 Logic one enables reactive power accumulation depending on the sign of

the active power: If Active Power is positive, VAR is accumulated as it is; If Active Power is negative, the sign of the VAR is reversed for the accumulation. This accumulation mode affects both the VAR registers and the VARCF output.

1 POAM 0 Logic one enables positive only accumulation of Active power in energy

0 ABSAM 0 Logic one enables absolute value accumulation of Active power in energy

Table 34. GAIN register (0x1B) 7 - 5 PGA2[2:0] 0 These bits define the voltage channel input gain [2:0]

000 Gain = 1

001 Gain = 2

010 Gain = 4

011 Gain = 8

7 This function is not available in ADE7566 and ADE7569 products. 8This function is not available in ADE7566 and ADE7166 products.

Preliminary Technical Data ADE75xx/ADE71xx Rev. PrE | Page 41 of 148

100 Gain = 16

4 Reserved 0 Reserved

3 CFSIGN_OPT 0 This bit defines where the CF change of sign, APSIGN or VARSIGN,

detection is implemented.

0 Filtered power signal

1 On a per CF pulse basis

2 - 0 PGA1[2:0] 0 These bits define the current channel input gain [2:0] Table 35. CALMODE register (0x3D) 7 – 6 Reserved 0 These bits should be kept cleared for proper operation 5 - 4 SEL_I_CH[1:0] 9 0 These bits define the current ch annel used for energy measurements [1:0]

00 Current channel automatically selected by the tampering condition

01 Current channel connected to IA

10 Current channel connected to IB

11 Current channel automatically selected by the tampering condition

3 V_CH_SHORT 0 Logic one short voltage channel to ground

2 I_CH_SHORT 0 Logic one short Current channels to ground

Table 36. Interrupt Status Register 1 SFR (MIRQSTL, 0xDC)

5 FAULTSIGN 1 Logic one indicates that the Fault mode has changed according to the configuration of

4 VARSIGN 10 Logic one indicates that the reactive power sign changed according to the configuration

3 APSIGN Logic one indicates that the active power sign changed according to the configuration of

2 VANOLOAD Logic one indicates that an interrupt was caused by apparent power no-load detected. This interrupt is also used to reflect the part entering the IRMS No load mode. 1 RNOLOAD 2 Logic one indicates that an interrupt was caused by reactive power no-load detected. 0 APNOLOAD Logic one indicates that an interrupt was caused by active power no-load detected. Table 37. Interrupt Status Register 2 SFR (MIRQSTM, 0xDD) 9 This function is not available in ADE7566 and ADE7569 products. 10 This function is not available in ADE7566 and ADE7166 products.

output is not enabled by clearing bit 2 of MODE1 register. output is not enabled by clearing bit 1 of MODE1 register.

5 VAEOF Logic one indicates that th e VAHR register has overflowded

4 REOF 11 Logic one indicates that the VARHR register has overflowded

3 AEOF Logic one indicates that th e WATTHR register has overflowded

2 VAEHF Logic one indicates that the VAHR register is half full

1 REHF 1 Logic one indicates that the VARHR register is half full

0 AEHF Logic one indicates that the WATTHR register is half full

Table 38. Interrupt Status Register 3 SFR (MIRQSTH, 0xDE) 7 RESET Indicates the end of a reset (for both sofware or hardware reset).

5 WFSM Logic one indicates that new data is present in the Waveform Registers

4 PKI Logic one indicates that current channel has exceeded the IPKLVL value

3 PKV Logic one indicates that voltage ch annel has exceeded the VPKLVL value.

2 CYCEND Logic one indicates the end of the energy accumulation over an integer number of half

1 ZXTO Logic one indicates that no zero crossing on the line voltage happened for the last

0 ZX Logic one indicates detection of a zero crossing in the voltage channel. Table 39. Interrupt Enable Register 1 SFR (MIRQENL, 0xD9)

5 FAULTSIGN 12 When this bit is set, the FAULTSIGN bit set creates a pending ADE interrupt to the 8052

4 VARSIGN 1 When this bit is set, the VARSIGN bit set creates a pending ADE interrupt to the 8052 core. 3 APSIGN When this bit is set, the APSIGN bit set creates a pending ADE interrupt to the 8052 core.

2 VANOLOAD When this bit is set, the VANOLOAD bit set creates a pending ADE interrupt to the 8052

1 RNOLOAD 1 When this bit is set, the RNOLOAD bit set creates a pending ADE interrupt to the 8052

0 APNOLOAD When this bit is set, the APNOLOAD bit set creates a pending ADE interrupt to the 8052

Table 40. Interrupt Enable Register 2 SFR (MIRQENM, 0xDA) 7 CF2 When this bit is set, a CF2 pulse issued creates a pending ADE interrupt to the 8052 core. 6 CF1 When this bit is set, a CF1 pulse issued creates a pending ADE interrupt to the 8052 core. 5 VAEOF When this bit is set, the VAEOF flag se t creates a pending ADE interrupt to the 8052 core. 4 REOF 1 When this bit is set, the REOF flag set cr eates a pending ADE interrupt to the 8052 core. 3 AEOF When this bit is set, the AEOF flag set creates a pending ADE interrupt to the 8052 core. 2 VAEHF When this bit is set, the VAEHF flag se t creates a pending ADE interrupt to the 8052 core. 1 REHF 1 When this bit is set, the REHF flag set cr eates a pending ADE interrupt to the 8052 core. 11 This function is not available in ADE7566 and ADE7166 products. 12 This function is not available in ADE7566 and ADE7569 products.

0 AEHF When this bit is set, the AEHF flag set creates a pending ADE interrupt to the 8052 core. Table 41. Interrupt Enable Register 3 SFR (MIRQENH, 0xDB) 5 WFSM When this bit is set, the WFSM flag se t creates a pending ADE interrupt to the 8052 core. 4 PKI When this bit is set, th e PKI flag set creates a pending ADE interrupt to the 8052 core. 3 PKV When this bit is set, th e PKV flag set creates a pending ADE interrupt to the 8052 core.. 2 CYCEND When this bit is set, the CYCEND flag set creates a pending ADE interrupt to the 8052 core. 1 ZXTO When this bit is set, th e ZXTO flag set creates a pending ADE interrupt to the 8052 core. 0 ZX When this bit is set, the ZX flag set creates a pending ADE interrupt to the 8052 core. is ±0.5 V with respect to AGND.

0 ADDR:

Figure 17. Bits 0 to 2 select the gain for the PGA in the current the current channel is made using the gain register. Figure 16. PGA in current channel Figure 17. As mentioned previously, the maximum differential

Figure 17. ADE75XX/ADE71XX Analog Gain Register modulator and the digital low-pass filter. Figure 18. First-Order Σ-∆ ADC resolution from what is essentially a 1-bit conversion technique. Figure 19. However, oversampling alone is not Figure 19. Noise Reduction Due to Oversampling and to the modulator. This filter is present to prevent aliasing.

Figure 22. ADC and Signal Processing in Voltage Channel calculation remain uninterrupted during waveform sampling. waveform high byte (W AV1H or W AV2H) is read. Energy measurement interrupts section. 13 This function is not available in ADE7566 and ADE7569 products. eliminates false detection of a fault due to noise at light loads. transducers be closely matched. this bit is cleared, IA is selected and when it is set, IB is selected.

which represents 0.014% when the line frequency is 60 Hz. enables the measurement of line frequencies as low as 12.5 Hz. established and the measurement does not change. which represents 0.104% when the line frequency is 60Hz. cycles. This condition is illustrated in Figure 31.

3 LINE CYCLES

Figure 31. ADE75XX/ADE71XX Sag Detection set in the sag level register (SAGLVL[15:0]) for three line cycles. dropped below the threshold level. Figure 22. Writing 0x00 made when the contents of the sag level register are greater. Current Channels are monitored at the same time. Figure 32. ADE75XX/ADE71XX Peak Level Detection measurement interrupts section.

1. The detection is done by comparing the contents of the

Figure 37. Active Power Calculation sinusoidal and has a frequency equal to twice the line frequency. Active Energy Calculation section. Figure 38. Frequency Response of LPF2

1 WGAINPowerActiveWGAINOutput (11)

energy) calculation in the ADE75XX/ADE71XX. (MIRQENL, 0xD9), the 8052 core has a pending ADE interrupt. cleared—see Energy measurement interrupts section. to negative active power has occurred.

Energy measurement interrupts section. Figure 39. ADE75XX/ADE71XX Active Energy Calculation As stated earlier, power is defined as the rate of energy flow. This relationship can be expressed mathematically in Equation 12. Conversely, energy is given as the integral of power. summation is equivalent to integration in continuous time. Equation 14 expresses the relationship. n is the discrete time sample number.

Preliminary Technical Data ADE75xx/ADE71xx Rev. PrE | Page 59 of 148 REACTIVE POWER CALCULATION15 Reactive power is defined as the product of the voltage and current waveforms when one of these signals is phase-shifted by 90°. The resulting waveform is called the instantaneous reactive power signal. Equation 25 gives an expression for the instanta- neous reactive power signal in an ac system when the phase of the current channel is shifted by +90°. v(t) = )sin(2 θ+ωtV (23) i(t) = )sin(2 tI ω ⎛ π+ω=′ 2sin2)( tIti (24) where: θ is the phase difference between the voltage and current channel. V is the rms voltage. I is the rms current. q(t) = v(t) × i’(t) (25) q(t) = VI sin (θ) + VI sin )2( θ+ωt The average reactive power over an integral number of lines (n) is given in Equation 26. ∫ == nT VIdttqnTQ )sin()(1 θ (26) where: T is the line cycle period. q is referred to as the reactive power. Note that the reactive power is equal to the dc component of the instantaneous reactive power signal q(t) in Equation 25. This is the relationship used to calculate reactive power in the ADE75XX/ADE71XX. The instantaneous reactive power signal q(t) is generated by multiplying Voltage and Current channels. In this case, the phase of Current channel is shifted by +90°. The dc component of the instantaneous reactive power signal is then extracted by a low-pass filter in order to obtain the reactive power information – see Figure 45. In addition, the phase shifting filter has a non-unity magnitude response. Because the phase-shift filter has a large attenuation at high frequency, the reactive power is primarily for the calculation at line frequency. The effect of harmonics is largely ignored in the reactive power calculation. Note that because of the magnitude characteristic of the phase shifting filter, the weight of the reactive power is slightly different from the active power calculation – see Energy register scaling.

15 This function is not available in ADE7566 and ADE7166products

The frequency response of the LPF in the reactive signal path is identical to that of the LPF2 used in the average active power calculation. Since LPF2 does not have an ideal “brick wall” frequency response—see Figure 38, the reactive power signal has some ripple due to the instantaneous reactive power signal. This ripple is sinusoidal and has a frequency equal to twice the line frequency. Because the ripple is sinusoidal in nature, it is removed when the reactive power signal is integrated to calculate energy—see the Reactive Power Calculation section. The reactive power signal can be read from the waveform register by setting the W AVMODE register (0x0D) and setting the WFSM bit in the Interrupt Enable Register 3 SFR (MIRQENH, 0xDB). Like the current and voltage channels waveform sampling modes, the waveform date is available at sample rates of 27.9 kSPS, 14 kSPS, 7 kSPS, or 3.5 kSPS. Reactive gain automatic compenstation The ADE75XX/ADE71XX reactive power calculation has a 20dB/decade attenuation over frequency. In order to attenuate this effect for the line frequency, the ADE75XX/ADE71XX has a dynamic compensation of the line frequency to maintain a constant gain over the fundamental line frequency between 45 and 65Hz. However, this automatic compensation can be disabled by setting bit 7 of the NLMODE register (0x0E). Reactive power gain calibration Figure 45 shows the signal processing chain for the reactive power calculation in the ADE75XX/ADE71XX. As explained, the reactive power is calculated by low-pass filtering the instantaneous reactive power signal. Note that when reading the waveform samples from the output of LPF2, the gain of the reactive energy can be adjusted by using the multiplier and var gain register (V ARGAIN[11:0]). The gain is adjusted by writing a twos complement 12-bit word to the var gain register. Equation 11 shows how the gain adjustment is related to the contents of the watt gain register: ⎧ +×= 1221Re VARGAINPoweractiveVARGAINOutput (11) The resolution of the V ARGAIN register is the same as the WGAIN register – see Active power gain calibration section. V ARGAIN can be used to calibrate the reactive power (or energy) calculation in the ADE75XX/ADE71XX. Reactive power offset calibration The ADE75XX/ADE71XX also incorporates a reactive power offset register (V AROS[15:0]). This is a signed twos complement 16-bit register that can be used to remove offsets in the reactive power calculation—see Figure 45. An offset could exist in the reactive power calculation due to crosstalk between channels on the PCB or in the IC itself. The offset calibration allows the contents of the reactive power register to be

maintained at 0 when no power is being consumed. enabled, and +90° phase shift when the integrator is disabled. Table 42. Sign of Reactive Power Calculation positive to negative reactive power has occurred. to positive reactive power has occurred. Energy measurement interrupts section. Figure 45. ADE75XX/ADE71XX Reactive Energy Calculation

instantaneous power signal in an ac system with a phase shift. calculation of the apparent power in the ADE75XX/ADE71XX. Figure 49. Apparent Power Signal Processing sample rates of 27.9 kSPS, 14 kSPS, 7 kSPS, or 3.5 kSPS. is related to the contents of the V AGAIN register.

1 VAGAINPowerApparentINOutputVAGA (29)

is proportional to Irms and vice-versa. smaller than 180ms, the duty cycle of the pulse output is 50%. connected to an LED as shown on Figure 53. Figure 53. CF Pulse output used to adjust the CFx frequency to a wide range of values. scale the output frequency by 1/216 to 1 with a step of 1/216. writing 0xFF to the CFxDEN register. Table 43. In Table calibration and simplify the adjustment of V AR and V A gains. no need to do reactive or apparent gai adjustment. Table 43. Energy Registers scaling Table 44. Gain compensation adjustments

16 This function is not available in ADE7166 and ADE7566 products

Preliminary Technical Data ADE75xx/ADE71xx Rev. PrE | Page 67 of 148 WGAIN/0.9997 WGAIN/0.9999 V AGAIN = 9.44 + WGAIN/0.9977 V AGAIN = -60.53 + WGAIN/1.0015 ENERGY MEASUREMENT INTERRUPTS The Energy Measurement part of the ADE75XX/ADE71XX has its own interrupt vector for the 8052 core – Vector address 0x004B – see Interrupt Vectors section. The bits set in the Interrupt Enable Register 1 SFR (MIRQENL, 0xD9), Interrupt Enable Register 2 SFR (MIRQENM, 0xDA), and Interrupt Enable Register 3 SFR (MIRQENH, 0xDB) enables the energy measurement interrupts that are allowed to interrupt the 8052 core. If an event is not enabled, it cannot create a system interrupt. The ADE interrupt stays active until the status bit that has created the interrupt is cleared. A status bit of the ADE irq status register (1, 2 or 3) is cleared when a zero is written the bit to clear and acknowledge the event.

ADE75xx/ADE71xx Preliminary Technical Data Rev. PrE | Page 68 of 148 TEMPERATURE, BATTERY AND EXTERNAL VOLTAGE MEASUREMENTS The ADE75XX/ADE71XX includes temperature measurements as well as battery and an external voltage measurements. These measurements enable many forms of compensation. The temperature measurements can be used to compensate external circuitry. The RTC can be calibrated over temperature to ensure that it doesn’t drift. External voltage measurements allow the VDCIN voltage to be monitored, which is especially useful if the VDCIN voltage tracks the bulk voltage. Battery measurements allow low battery detection to be performed. All ADC measurements are configured through the SFR detailed in Table 45. The temperature, battery and external voltage measurements can be configured to still be functional in PSM1 and PSM2. This is done bit setting bit RTCEN in the RTC Configuration SFR (TIMECON, 0xA1). Maintaining the temperature measurement active ensures that it is not necessary to wait for the temperature measurement to settle before using it for compensation. Table 45. Temperature, Battery and External voltage measurement SFRs Table 46. Peripheral ADC Strobe Period SFR (STRBPER, 0xF9) Note: The strobing option only work when the RTCEN bit in RTC Configuration SFR (TIMECON, 0xA1) is set. Period for background external voltage measurements VDCIN_PERIOD[1:0] 0 0 No VDCIN measurement 0 1 8 minutes 1 0 2 minutes 5-4 VDCIN_PERIOD[1:0] 0 1 1 1 minute Period for background battery level measurements BATT_PERIOD[1:0] 0 0 No Battery measurement 0 1 16 minutes 1 0 4 minutes 3-2 BATT_PERIOD[1:0] 0 1 1 1 minute Period for background temperature measurements TEMP_PERIOD[1:0] 0 0 No Temperature measurements 1-0 TEMP_PERIOD[1:0] 0 0 1 8 minutes

Preliminary Technical Data ADE75xx/ADE71xx Rev. PrE | Page 69 of 148 1 0 2 minutes 1 1 1 minute Table 47. T emperature and Voltage ADC Delta SFR (DIFFPROG, 0xF3) Difference threshold between last temperature measurement interrupting 8052 and new temperature measurement that should interrupt 8052 TEMP_DIFF[2:0] 0 0 0 No Interrupt 0 0 1 1 LSB (≈ 0.8°C) 0 1 0 2 LSB (≈ 1.6°C) 0 1 1 3 LSB (≈ 2.4°C) 1 0 0 4 LSB (≈ 3.2°C) 1 0 1 5 LSB (≈ 4.0°C) 1 1 0 6 LSB (≈ 4.8°C) 5-3 TEMP_DIFF[2:0] 0 1 1 1 Every Temperature measurement Difference threshold between last external voltage measurement interrupting 8052 and new external voltage measurement that should interrupt 8052 VDCIN_DIFF[2:0] 0 0 0 No Interrupt 0 0 1 1 LSB (≈ 120 mV) 0 1 0 2 LSB (≈ 240 mV) 0 1 1 3 LSB (≈ 360 mV) 1 0 0 4 LSB (≈ 480 mV) 1 0 1 5 LSB (≈ 600 mV) 1 1 0 6 LSB (≈ 720 mV) 2-0 VDCIN_DIFF[2:0] 0 1 1 1 Every VDCIN measurement 48. Start ADC Measurement SFR (ADCGO, 0xD8) Bit Location Bit Addr. Bit Name Default Value 7 0xDF PLLACK 0 Set this bit to clear the PLL fault bit, PLL_FLT in the PERIPH register. A PLL fault is generated if a reset was caused because the PLL lost lock. 6-3 0xDE – 0xDB Reserved 0 Reserved 2 0xDA VADC 0 Set this bit to initiate an externalvoltage measurement. This bit will be cleared when the measurement request is received by the ADC. 1 0xD9 TADC 0 Set this bit to initiate a temperature measurement. This bit will be cleared when the measurement request is received by the ADC. 0 0xD8 BTADC 0 Set this bit to initiate a battery measurement. This bit will be cleared when the measurement request is received by the ADC. Table 49. Battery detection threshold SFR (BATVTH, 0xFA)

ADE75xx/ADE71xx Preliminary Technical Data Rev. PrE | Page 70 of 148 Location Mnemonic 7-0 BATVTH 0 The battery ADC value is compared to this register, the battery threshold register. If BATADC is lower than the threshold, an interrupt is generated. Table 50. VDCIN ADC value SFR (VDCINADC, 0xEF) 7-0 VDCINADC 0 The external voltage ADC value in this register is updated when a VDCINADC interrupt occurs. Table 51. Battery ADC value SFR (BATADC, 0xDF) 7-0 BATADC 0 The battery ADC value in this register is updated when a BATADC interrupt occurs. Table 52. Temperature ADC value SFR (TEMP ADC, 0xD7) 7-0 TEMPADC 0 The temperature ADC value in this register is updated when a TEMPADC interrupt occurs. TEMPERATURE MEASUREMENT To provide a digital temperature measurement, the ADE75XX/ADE71XX includes a dedicated ADC. An 8-bit Temperature ADC value SFR (TEMPADC, 0xD7) holds the results of the temperature conversion. The resolution of the temperature measurement is TBD˚C/LSB. There are two ways to initiate a temperature conversion: - Single Temperature Measurement - Background Temperature Measurements Single Temperature Measurement Set the TADC bit in the Start ADC Measurement SFR (ADCGO, 0xD8) to get a temperature measurement. An interrupt will be generated when the conversion is done and the temperature measurement is available in the Temperature ADC value SFR (TEMPADC, 0xD7). Background Temperature Measurements Background temperature measurements are disabled by default. To configure the background temperature measurement mode, set a temperature measurement interval in the Peripheral ADC Strobe Period SFR (STRBPER, 0xF9). Then temperature measurements will be performed periodically in the background – see Table 46. When a temperature conversion the temperature has changed more than a configurable delta.

1. Initiate a single temperature measurement by setting
2. Upon completion of this measurement, configure the

temperature that will trigger an interrupt.

1. Set up the interval for background temperature

mode and by initiating a single measurement.

Preliminary Technical Data ADE75xx/ADE71xx Rev. PrE | Page 71 of 148 initiated by setting the TADC bit in the Start ADC Measurement SFR (ADCGO, 0xD8). Background temperature measurements are not available. PSM2: In this operating mode, the 8052 is not active. Temperature conversions are available through the background measurement mode only. The Temperature ADC value SFR (TEMPADC, 0xD7) is updated with a new value only when a temperature ADC interrupt occurs. Temperature ADC interrupt The temperature ADC can generate an ADC interrupt when at least one of the following conditions occurs: - The difference between the new temperature ADC value and the last temperature ADC value generating an ADC interrupt is larger than the value set in the TEMP_DIFF bits. - The Temperature ADC conversion, initiated by setting TADC in the Start ADC Measurement SFR (ADCGO, 0xD8), is finished. When the ADC interrupt occurs, a new value is available in the Temperature ADC value SFR (TEMPADC, 0xD7). Note that there is no flag associated with this interrupt. BATTERY MEASUREMENT To provide a digital battery measurement, the ADE75XX/ADE71XX includes a dedicated ADC. The battery measurement is available in an 8-bit SFR (Battery ADC value SFR (BATADC, 0xDF). The battery measurement has a resolution of 15 mV/LSB. A battery conversion can be initiated by two methods: - Single Battery Measurement - Background Battery Measurements Single Battery Measurement Set the BTADC bit in the Start ADC Measurement SFR (ADCGO, 0xD8) to get a battery measurement. An interrupt will be generated when the conversion is done and the battery measurement is available in the Battery ADC value SFR (BATADC, 0xDF). Background Battery measurements To configure background measurements for the battery, establish a measurement interval in the Peripheral ADC Strobe Period SFR (STRBPER, 0xF9). Then battery measurements will be performed periodically in the background – see Table 46. When a battery conversion completes, the battery ADC value is compared to the low battery threshold, established in the Battery detection threshold SFR (BATVTH, 0xFA). If it is below this threshold, a low battery flag is set. This low battery flag is the BATTFLAG bit in the Power Management Interrupt Flag SFR (IPSMF, 0xF8), used for power supply monitoring. This low battery flag can be enabled to generate the PSM interrupt by setting the EBATT bit in the Power Management Interrupt Enable SFR (IPSME, 0xEC). This method allows battery measurements to take place completely in the background, only requiring MCU activity if the battery drops below a user specified threshold. To set up background battery measurements: 1. Configure the Battery detection threshold SFR (BATVTH, 0xFA) to establish a low battery threshold. If the BATADC measurement is below this threshold, the BATTFLAG in the Power Management Interrupt Flag SFR (IPSMF, 0xF8) will be set. 2. Set up the interval for background battery measurements by configuring the BATT_PERIOD[1:0] bits. Battery ADC in PSM1 and PSM2 Depending on the operating mode, a battery conversion is initiated only by certain actions: PSM0: In this operating mode, the 8052 is active. Battery measurements are available in the background measurement mode and by initiating a single measurement. PSM1: In this operating mode, the 8052 is active and the part is powered from battery. Single battery measurements can be initiated by setting the BTADC bit in the Start ADC Measurement SFR (ADCGO, 0xD8). Background battery measurements are not available. PSM2: In this operating mode, the 8052 is not active. Battery conversions are available through the background measurement mode only. Battery ADC interrupt The battery ADC can generate an ADC interrupt when at least one of the following conditions occurs: - The new battery ADC value is smaller than the value set in the Battery detection threshold SFR (BATVTH, 0xFA), indicating a battery voltage loss. - A single battery measurement, initiated by setting the BATT_ADC_GO bit, is finished. When the battery flag is set in the Power Management Interrupt Flag SFR (IPSMF, 0xF8), a new ADC value is available in the Battery ADC value SFR (BATADC, 0xDF). This battery flag can be enabled as a source of the PSM interrupt to generate a PSM interrupt every time the battery drops below a set voltage threshold or after a single conversion initiated by setting the BATT_ADC_GO bit is ready. The Battery ADC value SFR (BATADC, 0xDF) is updated with a

Management Interrupt Flag SFR (IPSMF, 0xF8). a digital measurement of an external voltage, on the VDCIN pin. external voltage measurement is available in the Table 50. VDCIN ADC value SFR (VDCINADC, 0xEF). Table 46. When an external

1. Initiate a single external voltage measurement by
2. Upon completion of this measurement, configure the

Management Interrupt Flag SFR (IPSMF, 0xF8).

1. Set up the interval for background external voltage

measurement mode and by initiating a single measurement. voltage measurements are not available. external voltage ADC interrupt occurs. interrupt is larger than the value set in the VDCIN_DIFF bits. is no flag associated with this interrupt.

8052 MCU CORE ARCHITECTURE

to it in the ADE75XX/ADE71XX. between the CPU and all on-chip peripherals.

256 BYTES XRAM

256 BYTES

The registers used by the MCU are summarized hereafter. Table 53. 8051 SFRs Table 54. Program Status Word SFR (PSW , 0xD0) 7 0xD7 CY Carry Flag. Modified by ADD, ADDC, SUBB, MUL, and DIV instructions. 6 0xD6 AC Auxiliary Carry Flag. Modifi ed by ADD, and ADDC instructions. 2 0xD2 OV Overflow Flag. Modified by AD D, ADDC, SUBB, MUL and DIV instructions. 1 0xD1 F1 General-Purpose Flag availble to the user. will always be an even number.

Table 55. Program Control SFR (PCON, 0x87) Table 56. Data Pointer Low SFR (DPL, 0x82) Table 57. Data Pointer High SFR (DPH, 0x83) Table 58. Stack Pointer SFR (SP , 0x81) Table 59. Configuration SFR (CFG, 0xAF) 7 Reserved.. This bit should be left set for proper operation.

0 Standard 8052 UART without enha nced error checking features

6 EXTEN

1 Enhanced UART with enhanced error checking—see the UART additional features

0 I2C port is selected for control of the shared I2C/SPI pins and SFRs

5 SCPS

1 SPI port is selected for control of the shared I2C/SPI pins and SFRs

0 38kHz modulation is disabled.

4 MOD38EN

part of the program is active. register is not directly accessible to the user. are convenient for temporary storage of mathematical operands. located in the first 32 bytes of RAM.

the Program Status Word SFR (PSW , 0xD0). instructions, MUL AB and DIV AB to hold one of the operands. register is stored in the SFR space - see Table 53. Table 54. The Program Status Word SFR (PSW , 0xD0) is bit addition to the stack is the first to come off it. for interrupts, to keep track of the prior state of the PC. register holds the address of the stack into the externded RAM. pointer overflowing in data RAM.

256 BYTES OF

Figure 55. Extended Stack Pointer Operation

Flash memory so that an external code space is unnecessary. access to external code and data spaces.

8052 Ports 1, 2 and 3 can be disabled to make open drain

0x87) is not bit addressable. See the Power Management section.

• ADE Energy Measurement DSP
• RTC
• LCD driver
• Battery Switchover/Power Management
• Te mp er ature A D C
• Battery ADC
• SPI/I2C communication
• Flash Memory controller
• Watchdog Ti me r MEMORY OVERVIEW The ADE75XX/ADE71XX contains three memory blocks:
• 16 kbytes of on-chip Flash/EE program and data memory
• 256 bytes of general-purpose RAM
• 256 bytes of internal extended RAM (XRAM) The 256 bytes of general-purpose RAM shares the upper 128 bytes of its address space with Special Function Registers. All of the memory spaces are shown in Figure 54. The addressing mode specifies which memory space to access. General Purpose RAM: General purpose RAM resides in memory locations 0x00 through 0xFF. It contains the register banks. 07H 0FH 17H 1FH 2FH 7FH 00H 08H 10H 18H 20H RESET VALUE OF STACK POINTER 30H FOUR BANKS OF EIGHT REGISTERS R0 TO R7 BIT-ADDRESSABLE (BIT ADDRESSES) GENERAL-PURPOSE AREA BANKS SELECTED VIA BITS IN PSW 04741-0-008

Figure 56. Lower 128 Bytes of Internal Data Memory

addressing as shown in Figure 57 . Configuration SFR (CFG, 0xAF) by writing 01 to CFG[1:0]. Table 60. 8052 Addressing Modes

by the assembler and stored in the memory address specified. referring to a special function memory location. pointed to by the register is moved to the destination address. and three bytes of storage in the program memory. useful for indexing into data arrays stored in RAM. extended RAM (XRAM), accessed through MOVX instructions. External memory spaces are not supported on this device. and four bytes of storage in the program memory. memory is not supported on this device. before moving to extended RAM. of Flash memory located at DPTR. clock cycles,resulting in a 4 MIPS peak performance. Table 61. Instruction Set

Preliminary Technical Data ADE75xx/ADE71xx Rev. PrE | Page 79 of 148 Mnemonic Description Bytes Cycles ADD A,dir Add direct byte to A 2 2 ADD A,#data Add immediate to A 2 2 ADDC A,Rn 1 1 Add register to A with carry 1 1 ADDC A,@Ri Add indirect memory to A with carry 1 2 ADDC A,dir Add direct byte to A with carry 2 2 ADD A,#data Add immediate to A with carry 2 2 SUBB A,Rn Subtract register from A with borrow 1 1 SUBB A,@Ri Subtract indirect memory from A with borrow 1 2 SUBB A,dir Subtract direct from A with borrow 2 2 SUBB A,#data Subtract immediate from A with borrow 2 2 INC A Increment A 1 1 INC Rn Increment register 1 1 INC @ Ri Increment indirect memory 1 2 INC dir Increment direct byte 2 2 INC DPTR Increment data pointer 1 3 DEC A Decrement A 1 1 DEC Rn Decrement register 1 1 DEC @Ri Decrement indirect memory 1 2 DEC dir Decrement direct byte 2 2 MUL AB Multiply A by B 1 9 DIV AB Divide A by B 1 9 DA A A Decimal adjust A 1 2 Logic ANL A,Rn AND register to A 1 1 ANL A,@Ri AND indirect memory to A 1 2 ANL A,dir AND direct byte to A 2 2 ANL A,#data AND immediate to A 2 2 ANL dir,A AND A to direct byte 2 2 ANL dir,#data AND immediate data to direct byte 3 3 ORL A,Rn OR register to A 1 1 ORL A,@Ri OR indirect memory to A 1 2 ORL A,dir OR direct byte to A 2 2 ORL A,#data OR immediate to A 2 2 ORL dir,A OR A to direct byte 2 2 ORL dir,#data OR immediate data to direct byte 3 3 XRL A,Rn Exclusive-OR register to A 1 1 XRL A,@Ri Exclusive-OR indirect memory to A 2 2 XRL A,#data Exclusive-OR immediate to A 2 2 XRL dir,A Exclusive-OR A to direct byte 2 2 XRL A, dir Exclusive-OR indirect memory to A 2 2 XRL dir,#data Exclusive-OR immediate data to direct 3 3 CLR A Clear A 1 1 CPL A Complement A 1 1 SWAP A Swap nibbles of A 1 1 RL A Rotate A left 1 1 RLC A Rotate A left through carry 1 1 RR A Rotate A right 1 1 RRC A Rotate A right through carry 1 1

ADE75xx/ADE71xx Preliminary Technical Data Rev. PrE | Page 80 of 148 Mnemonic Description Bytes Cycles Data Transfer MOV A,Rn Move register to A 1 1 MOV A,@Ri Move indirect memory to A 1 2 MOV Rn,A Move A to register 1 1 MOV @Ri,A Move A to indirect memory 1 2 MOV A,dir Move direct byte to A 2 2 MOV A,#data Move immediate to A 2 2 MOV Rn,#data Move register to immediate 2 2 MOV dir,A Move A to direct byte 2 2 MOV Rn,dir Move register to direct byte 2 2 MOV dir,Rn Move direct to register 2 2 MOV @Ri,#data Move immediate to indirect memory 2 2 MOV dir,@Ri Move indirect to direct memory 2 2 MOV @Ri,dir Move direct to indirect memory 2 2 MOV dir,dir Move direct byte to direct byte 3 3 MOV dir,#data Move immediat e to direct byte 3 3 MOV DPTR,#data Move immediate to data pointer 3 3 MOVC A,@A+DPTR Move code byte relative DPTR to A 1 4 MOVC A,@A+PC Move code b yte relative PC to A 1 1 4 MOVX A,@Ri Move extern al (A8) data to A 1 4 MOVX A,@DPTR Move exte rnal (A16)data to A 1 4 MOVX @Ri,A Move A to ex ternal data (A8) 1 4 MOVX @DPTR,A Move A to external data (A16) 1 4 PUSH dir Push direct byte onto stack 2 2 POP dir Pop direct byte from stack 2 2 XCH A,Rn Exchange A and register 1 1 XCH A,@Ri Exchange A and indirect memory 1 2 XCHD A,@Ri Exchange A and indirect memory nibble 1 2 XCH A,dir Exchange A and direct byte 2 2 Boolean CLR C Clear carry 1 1 CLR bit Clear direct bit 2 2 SETB C Set carry 1 1 SETB bit Set direct bit 2 2 CPL C Complement carry 1 1 CPL bit Complement direct bit 2 2 ANL C,bit AND direct bit and carry 2 2 ANL C,/bit AND direct bit inverse to carry 2 2 ORL C,bit OR direct bit and carry 2 2 ORL C,/bit OR direct bit inverse to carry 2 2 MOV C,bit Move direct bit to carry 2 2 MOV bit,C Move carry to direct bit 2 2 Branching

Some 8051 instructions read the latch while others read the pin. The state of the pin is read for instructions that input a port bit. that read a value, possibly change it, and rewrite it to the latch. rather than the pin returns the correct value of 1. instructions read the latch rather than the pin. Table 62. Read-Modify-Write Instructions

1 These instructions read the port byte (all 8 bits), modify the addressed bit,

and write the new byte back to the latch. affect status flags are listed in this section.

ADE75xx/ADE71xx Preliminary Technical Data Rev. PrE | Page 82 of 148 ADD A, source Function: Adds the source to the Accumulator. Status Flags Referenced by Instruction: None Status Flags Affected: Status Flag C Set if there is a carry out of bit 7. Cleared otherwise. Used to indicate an overflow if the operands are unsigned. OV Set if there is a carry out of bit 6 or a carry out of bit 7 but not if both are set. Used to indicate an overflow for signed addition. This flag will be set if two positive operands yield a negative result or two negative operands yield a positive result. AC Set if there is a carry out of bit 3. Cleared otherwise. ADDC A, source Function: Adds the source and the Carry bit to the Accumulator Status Flags Referenced by Instruction: Carry Status Flags Affected: Status Flag C Set if there is a carry out of bit 7. Cleared otherwise. Used to indicate an overflow if the operands are unsigned. OV Set if there is a carry out of bit 6 or a carry out of bit 7 but not if both are set. Used to indicate an overflow for signed addition. This flag will be set if two positive operands yield a negative result or two negative operands yield a positive result. AC Set if there is a carry out of bit 3. Cleared otherwise. SUBB A, source Function: Subtract the source byte and the carry (borrow) flag from the Accumulator. Status Flags Referenced by Instruction: Carry (Borrow) Status Flags Affected: Status Flag C Set if there is a borrow needed for of bit 7. Cleared otherwise. Used to indicate an overflow if the operands are unsigned. OV Set if there is a borrow is needed for bit 6 or bit 7 but not for both. Used to indicate an overflow for signed subtraction. This flag will be set if a negative number subtracted from a positive yields a negative result or it a positive number subtracted from a negative number yields a positive result. AC Set if a borrow is needed for bit 3. Cleared otherwise. MUL AB Function: Multiplies the Accumulator by the B register. This operation is unsigned. The lower byte of the 16-bit product is stored in the Accumulator and the higher byte is left in the B register. Status Flags Referenced by Instruction: None Status Flags Affected: None Status Flag OV Set if the result is greater than 255. Cleared otherwise. DIV AB Function: Divides the Accumulator by the B register. This operation is unsigned. The integer part of the quotient is stored in the Accumulator and the remainder goes into the B register. Status Flags Referenced by Instruction: None Status Flags Affected: Status Flag OV Cleared unless the B register was equal to 0, in which case the results of the division are undefined and the OV flag is set. DA A Function: Adjusts the Accumulator to hold two four bit digits after the addition of two binary coded decimals (BCDs) with the ADD or ADDC instructions. If the AC bit is set or if the value of bits 0-3 exceed 9, 0x06 is added to the accumulator to correct the lower four bits. If the carry bit was set when the instruction began, or if 0x06 was added to the accumulator in the first step, 0x60 is added to the accumulator to correct the higher four bits.

Preliminary Technical Data ADE75xx/ADE71xx Rev. PrE | Page 83 of 148 Status Flags Referenced by Instruction: Carry, AC Status Flags Affected: Status Flag C Set if the result is greater than 99h. Cleared otherwise. RRC A Function: Rotates the accumulator to the right through the carry flag. The old LSB of the Accumulator becomes the new carry flag and the old carry flag is loaded into the new MSB of the Accumulator. Status Flags Referenced by Instruction: Carry Status Flags Affected: Status Flag C Equal to the state of ACC.0 before execution of the instruction RLC A Function: Rotates the accumulator to the left through the carry flag. The old MSB of the Accumulator becomes the new carry flag and the old carry flag is loaded into the new LSB of the Accumulator. Status Flags Referenced by Instruction: Carry Status Flags Affected: Status Flag C Equal to the state of ACC.7 before execution of the instruction CJNE destination, source, relative jump Function: Compares the value of the source to the value of the destination and branches to the location set by the relative jump if they are not equal. If the values are equal, program execution continues with the instruction after the CJNE instruction. Status Flags Referenced by Instruction: None Status Flags Affected: Status Flag C Set if the source value is greater than the destination value. Cleared otherwise.

Preliminary Technical Data ADE75xx/ADE71xx Rev. PrE | Page 85 of 148 0 0xA8 EX0 Set by the user to enable External Interrupt 0 (INT0). Table 64. Interrupt priority SFR (IP , 0xB8) 6 0xBE PTEMP Temperature ADC Interrupt Priority (1 = High; 0 = Low). 5 0xBD PT2 Timer 2 Interrupt Priority (1 = High; 0 = Low). 4 0xBC PS UART Serial Port Interrupt Priority (1 = High; 0 = Low). 3 0xBB PT1 Timer 1 Interrupt Priority (1 = High; 0 = Low). 2 0xBA PX1 INT1 (External Interrupt 1) priority (1 = High; 0 = Low). 1 0xB9 PT0 Timer 0 Interrupt Priority (1 = High; 0 = Low). 0 0xB8 PX0 INT0 (External Interrupt 0) Priority (1 = High; 0 = Low). Table 65. Interrupt Enable and Priority 2 SFR (IEIP2, 0xA9) 6 PTI RTC Interrupt Priority (1 = High; 0 = Low). 4 PSI SPI/I2C Interrupt Priority (1 = High; 0 = Low).

3 EADE Set by the user to enable th e Energy Metering Interrupt (ADE)

2 ETI Set by the user to enable the RTC interrupt. 1 EPSM Set by the user to enable the PSM Power Supply Management interrupt. 0 ESI Set by the user to enable the SPI/I2C interrupt. Interrupt pins configuration SFR (INTPR, 0xFF) Bit Location Bit Mnemonic Default Value When set, the RTC calibration frequency selected by FSEL[1:0] is output on the P0.2/CF1/RTCCAL pin. Sets RTC calibration output frequency and calibration window FSEL[1:0] Calibration window, f RTCCAL calibration frequency 0 0 30.5 seconds, 1Hz 0 1 30.5 seconds, 512 Hz 1 0 0.244 seconds, 500Hz 6-5 FSEL[1:0] 1 1 0.244 seconds, 16.384 kHz Controls the function of INT1 INT1PRG[2:0] Function x 0 0 GPIO x 0 1 BCTRL 0 1 x INT1 input disabled 3-1 INT1PRG[2:0] 000 1 1 x INT1 input enabled Controls the function of INT0 INT0PRG Function

ADE75xx/ADE71xx Preliminary Technical Data Rev. PrE | Page 86 of 148 Table 66. WatchDog Timer SFR (WDCON, 0xC0) 7-4 0xC7 – 0xC4 PRE[3:0] 7 Watchdog pre-scaler. In normal mode, the 16-bit watchdog timer is clocked by the input clock (32.768kHz). The PRE bits set which of the upper bits of the counter are used as the watchdog output following: CLKIN t PRE watchdog 922 ×= [3:0] Watchdog Timeout 0000 15.6ms 0001 31.2ms 0010 62.5ms 0011 125ms 0100 250ms 0101 500ms 0110 1s 0111 2s 1000 0 Automatic Reset 1001 0 Serial download reset 1010 to 1111 Not a valid selection 3 0xC3 WDIR 0 Watchdog interrupt response bit. When clear, watchdog will generate a system reset when the watchdog time out period has expired When set, the watchdog will generate a interrupt when the watchdog time out period has expired. 2 0xC2 WDS 0 WDS Watchdog status bit. This bit is set to indicate that a watchdog timeout has occurred. WDS is cleared by writing a zero or by an external hardware reset. A watchdog reset will not clear WDS. The bit can therefore be used to distinguish between a watchdog reset and a hardware reset from the RESET pin. 1 0xC1 WDE 1 WDE Watchdog enable bit. When set, enables the watchdog and clears its counter (e.g. 2 above). The watchdog counter is subsequently cleared again whenever the WDE bit is set. If the watchdog is not cleared within its selected timeout period it will generate a system reset or watchdog interrupt, depending on the WDIR bit. The watchdog is disabled (and WDE cleared) by any of the following: Write zero to WDE Watchdog reset (WDIR = 0) Hardware reset PSM interrupt LOCK interrupt. 0 0xC0 WDWR 0 WDWR Watchdog write enable bit. To write data into the WDCON SFR involves a double instruction sequence. The WDWR bit must be set and the following instruction must be a write instruction to the WDCON SFR. This sequence is necessary so that the WDCON SFR is protected from code execution upsets that might unintentionally modify this SFR. Interrupts should be disabled during this operation due to the consecutive instruction cycles. e.g. Disable Watch dog 1 write to WDCON e.g. 2 Clear WDE bit CLR EA SETB WDWR CLR WDE SETB EA

Table 67. Priority within Interrupt Level Table 68. Interrupt Flags Table 69. Status Flags ITEMP (Temperature ADC) - The Temperature ADC interrupt does not have an status flag associated with it.

Preliminary Technical Data ADE75xx/ADE71xx Rev. PrE | Page 89 of 148 IPSMF FPSM (IPSMF.6)IPSME INDIVIDUAL INTERRUPT ENABLES GLOBAL INTERRUPT ENABLE (EA) IE/IEIP2 REGISTERS IP/IEIP2 REGISTERS WATCHDOG TIMEOUT WDIR LOW HIGH HIGHEST MIDNIGHT ALARM IN OUT LATCH RESET MIRQSTH MIRQSTM MIRQSTL MIRQENHMIRQENM MIRQENL MIRQSTL.7 TEMPADC INTERRUPT IN OUT LATCH RESET INT0 IT0 IE0 TF0 INT1 IT1 TF1 IN OUT LATCH RESET CFG.5 I2C INTERRUPT SPI INTERRUPT RI TI TF2 EXF2 PRIORITY LEVEL INTERRUPT POLLING SEQUENCE PSM RTC ADE WATCHDOG TEMP ADC EXTERNAL INTERRUPT 0 TIMER 0 EXTERNAL INTERRUPT 1 TIMER 1 I2C/SPI UART TIMER 2 AUTOMATIC CLEAR SIGNAL LEGEND IT0 IE1 IT1 PSM2 PSM2

Table 70. Interrupt Vector Addresses the main program are restored to their pre-interrupt state.

Preliminary Technical Data ADE75xx/ADE71xx Rev. PrE | Page 91 of 148 WATCHDOG TIMER The watchdog timer generates a device reset or interrupt within a reasonable amount of time if the ADE75XX/ADE71XX enters an erroneous state, possibly due to a programming error or electrical noise. The watchdog is enabled by default with a time out of 2 seconds and will create a system reset if not cleared within 2 seconds. The watchdog function can be disabled by clearing the WDE (watchdog enable) bit in the watchdog control ( WatchDog Timer SFR (WDCON, 0xC0). The watchdog circuit generates a system reset or interrupt (WDS) if the user program fails to set the WDE bit within a predetermined amount of time (see the PRE3…0 bits in WatchDog Timer SFR (WDCON, 0xC0)). The watchdog timer is clocked from the 32.768 kHz external crystal connected between the CLKIN and CLKOUT pins. The WDCON SFR can be written only by user software if the double write sequence described in Table 71 is initiated on every write access to the WDCON SFR. In order to prevent any code from inadverdently disabling the watchdog, a watchdog protection can be activated. This watchdog protection locks in the watchdog enable and event settings so that they cannot be changed by user code. The protection is activated by clearing a watchdog protection bit in the Flash memory. The watchdog protection bit is the most significant bit at the address 0x3FFA of the Flash memory. When this bit is cleared, the WDIR bit is forced to 0 and the WDE bit is forced to 1. Note that the sequence for configuring the flash protection bits must be followed to modify the watchdog protection bit at 0x3FFA—see the Protecting the Flash section. Table 71. WatchDog Timer SFR (WDCON, 0xC0) 7-4 0xC7 – 0xC4 PRE[3:0] 7 Watchdog pre-scaler. In normal mode, the 16-bit watchdog timer is clocked by the input clock (32.768kHz). The PRE bits set which of the upper bits of the counter are used as the watchdog output following: CLKIN t PRE watchdog 922 ×= [3:0] Watchdog Timeout 0000 15.6ms 0001 31.2ms 0010 62.5ms 0011 125ms 0100 250ms 0101 500ms 0110 1s 0111 2s 1000 0 Automatic Reset 1001 0 Serial download reset 1010 to 1111 Not a valid selection 3 0xC3 WDIR 0 Watchdog interrupt response bit. When clear, watchdog will generate a system reset when the watchdog time out period has expired When set, the watchdog will generate a interrupt when the watchdog time out period has expired. 2 0xC2 WDS 0 WDS Watchdog status bit. This bit is set to indicate that a watchdog timeout has occurred. WDS is cleared by writing a zero or by an external hardware reset. A watchdog reset will not clear WDS. The bit can therefore be used to distinguish between a watchdog reset and a hardware reset from the RESET pin. 1 0xC1 WDE 1 WDE Watchdog enable bit. When set, enables the watchdog and clears its counter (e.g. 2 above). The watchdog counter is subsequently cleared again whenever the WDE bit is set. If the watchdog is not cleared within its selected timeout period it will generate a system reset or watchdog interrupt, depending on the WDIR bit. 0 0xC0 WDWR 0 WDWR Watchdog write enable bit. To write data into the WDCON SFR involves a double instruction sequence. The WDWR bit must be set and the following instruction must be a write instruction to the WDCON SFR. This sequence is

operation due to the consecutive instruction cycles. Table 72. WatchDog and Flash protection byte in Flash (Flash Address = 0x3FFA)

7 WDPROT_PROTKY7 1 This bit holds the protection for the Watchdog timer and the 7th bit of

timeout in PRE[3:0] can still be modified by user code. Flash section for more information on how to clear this bit. the new protection is written to the Flash addresses 0x3FFF to 0x3FFB. bit is located in the Watch D og Ti mer SFR ( W D C ON, 0xC0). watchdog to be used as a long interval timer.

Preliminary Technical Data ADE75xx/ADE71xx Rev. PrE | Page 93 of 148 LCD DRIVER The LCD module is capable of directly driving an LCD panel of 24 x 4 segments without compromising any ADE75XX/ADE71XX functionalities. Using shared pins, the driver can accommodate an LCD with up to 26 x 4 segments. It is capable of driving LCDs with 2x, 3x and 4x multiplexing. LCD waveform voltages generated through internal charge pump circuitry support up to 5V LCDs. An external resistor ladder for LCD waveform voltage generation is also supported. The ADE75XX/ADE71XX has an embedded LCD control circuit, LCD driver and power supply circuit. The LCD module is functional in all Operating modes. LCD SFR REGISTER LIST There are six LCD control registers that configure the driver for the specific type of LCD in the end system and set up the user display preferences. The LCD Configuration SFR (LCDCON, 0x95), LCD Configuration X SFR (LCDCONX, 0x9C) and LCD Configuration Y SFR (LCDCONY , 0xB1) SFRs contains general LCD driver configuration information including the LCD enable and reset, as well as method of LCD voltage generation and the multiplex level. The LCD Clock SFR (LCDCLK, 0x96) configures timing settings for LCD frame rate and blink rate. LCD pins are configured for LCD functionality in the LCD Segment Enable SFR (LCDSEGE, 0x97) and LCD Segment Enable 2 SFR (LCDSEGE2, 0xED). Table 73. LCD Driver SFRs Table 74. LCD Configuration SFR (LCDCON, 0x95) 7 LCDEN 0 LCD enable. If this bit is set, the LCD driver is enabled. 6 LCDRST 0 LCD data registers are reset to zero. If this bit is set, the LCD data registers will be reset to zero. 5 BLINKEN 0 Blink Mode enable bit. If this bit is set, blink mode is enabled. The blink mode is configured by the BLKMOD[1:0] and BLKFREQ[1:0] bits in the LCD Clock SFR (LCDCLK, 0x96) Force LCD off when in PSM2 (Sleep mode). 0 The LCD is disabled or enabled in PSM2 by LCDEN bit.

4 LCDPSM2 0

1 The LCD is disabled in PSM2 regarless of LCDEN setting. LCD clock selection f LCDCLK 0 2048Hz

3 CLKSEL 0

ADE75xx/ADE71xx Preliminary Technical Data Rev. PrE | Page 94 of 148 1 1/3 LCD Multiplex level LMUX[1:0] 0 0 Reserved 0 1 2x FP27/COM3 is used as FP27 FP28/COM2 is used as FP28 1 0 3x FP27/COM3 is used as FP27 FP28/COM2 is used as COM2 1-0 LMUX[1:0] 0 1 1 4x FP27/COM3 is used as COM3 FP28/COM2 is used as COM2 Table 75. LCD Configuration X SFR (LCDCONX, 0x9C)

7 Reserved 0 Reserved

External Resistor Ladder selection bit. 0 External resistor ladder is disabled. Charge pump is enabled.

6 EXTRES 0

1 External resistor ladder is enab led. Charge pump is disabled. 5-0 BIASLVL[5:0] 0 Bias Level Selection bits. See Table 76. Table 76. LCD bias voltage when contrast control is enabled Table 77. LCD Configuration Y SFR (LCDCONY , 0xB1)

7 Reserved 0 This bit should be kept cleared for proper operation

6 INV_LVL 0 Frame Inversion Mode Enable bit

If this bit is set, frames are inverted every other frame If this bit is cleared, frames are not inverted 5-2 Reserved 0 These bits should be kept cleared for proper operation 1 UPDATEOVER 0 Update finished flag bi t. This bit is updated by LCD driver. When set, indicates that the LCD memory has been updated and a new frame has begun. 0 REFRESH 0 Refresh LCD data memory bi t, this bit should be set by user. When set, the LCD driver does not use the data in the LCD data registers to update display. The LCD data registers can be updated by the 8052. When clear, the LCD driver will use the data in the LCD data registers to update display at the next frame.

Preliminary Technical Data ADE75xx/ADE71xx Rev. PrE | Page 95 of 148 Table 78. LCD Clock SFR (LCDCLK, 0x96) Blink Mode Clock Source Configuration bits BLKMOD[1:0] 0 0 The blink rate is controlled by software. The display is OFF. 0 1 The blink rate is controlled by software. The display is ON. 1 0 The blink rate is 2 Hz 7-6 BLKMOD[1:0] 0 1 1 The blink rate is set by BLKFREQ[1:0] Blink Rate Configuration bits These bits control LCD blink rate if BLKMOD[1:0]=11 BLKFREQ[1: Blink rate (Hz) 0 0 1 0 1 1/2 1 0 1/3 5-4 BLKFREQ[1:0] 0 1 1 1/4 3-0 FD[3:0] 0 LCD Frame Rate Selection bits. See Table 79 and Table 80. Table 79. LCD frame rate selection for fLCDCLK=2048Hz (LCDCON[3]=0)

ADE75xx/ADE71xx Preliminary Technical Data Rev. PrE | Page 96 of 148 Table 80. LCD frame rate selection for fLCDCLK=128Hz (LCDCON[3]=1) Table 81. LCD Segment Enable SFR (LCDSEGE, 0x97)

0 General Purpose I/O

7 FP25EN 0

1 LCD Function

6 FP24EN 0

5 FP23EN 0

4 FP22EN 0

3 FP21EN 0

2 FP20EN 0

Delay before powerdown? FDELAY[1:0] 0 0 No timeout 0 1 2 cycles 1 0 4 cycles 1-0 FDELAY 0 1 1 8 cycles Table 82. LCD Pointer SFR (LCDPTR, 0xAC)

Preliminary Technical Data ADE75xx/ADE71xx Rev. PrE | Page 97 of 148

7 W/R 0 Read or Write LCD bit

If this bit is set, the data in LCDDAT will be written to the address indicated by the bits LCDPTR[5 :0] 5-0 ADDRESS 0 LCD Memory Address - See Table 85. Table 83. LCD Data SFR (LCDDAT, 0xAE) 7-0 LCDDATA 0 Data to be written into or read out of the LCD Memory SFRs. Table 84. LCD Segment Enable 2 SFR (LCDSEGE2, 0xED)

3 FP19EN 0

2 FP18EN 0

1 FP17EN 0

0 FP16EN 0

Peripheral Configuration SFR (PERIPH, 0xF4) Bit Location Bit Mnemonic Default Value Indicates the power supply that is connected internally to V SW.

4 PLL_FLT 0 If set, indica tes that PLL is not locked

3 REF_BAT_EN 0 If set, Internal voltage reference enabled in PSM2 mode. This bit should be set if LCD On in PSM2 mode.

2 Reserved 0

Controls the function of the P1.0/RX pin. RXPROG [1:0] Function 0 0 GPIO 0 1 RX with wakeup disabled 1-0 RXPROG[1:0] 00 1 1 RX with wakeup enabled

LCD module to drive the type of LCD in the user end system. according to the LCD specifications. to COM2 and the FP27 pin to COM3. FP16-25, could be enabled instead. independent of the multiplex level. waveform frequency depends heavily on the multiplex level. the LCD Clock SFR (LCDCLK, 0x96). (LCDCLK, 0x96)—see Table 79 and Table 80. controlled blink mode and an automatic blink mode. LCD Clock SFR (LCDCLK, 0x96) – see Table 78. Table 85. Note that Table 85. LCD Data Memory accessed indirectly through

Preliminary Technical Data ADE75xx/ADE71xx Rev. PrE | Page 99 of 148 09h FP19 FP19 FP19 FP19 FP18 FP18 FP18 FP18 08h FP17 FP17 FP17 FP17 FP16 FP16 FP16 FP16 07h FP15 FP15 FP15 FP15 FP14 FP14 FP14 FP14 06h FP13 FP13 FP13 FP13 FP12 FP12 FP12 FP12 05h FP11 FP11 FP11 FP11 FP10 FP10 FP10 FP10 04h FP9 FP9 FP9 FP9 FP8 FP8 FP8 FP8 03h FP7 FP7 FP7 FP7 FP6 FP6 FP6 FP6 02h FP5 FP5 FP5 FP5 FP4 FP4 FP4 FP4 01h FP3 FP3 FP3 FP3 FP2 FP2 FP2 FP2 00h FP1 FP1 FP1 FP1 FP0 FP0 FP0 FP0 COM# designates the common lines FP# designates the segment lines The LCD data memory is accessed indirectly through the LCD Pointer SFR (LCDPTR, 0xAC)and Table 83. LCD Data SFR (LCDDAT, 0xAE). Moving a value to the LCD Pointer SFR (LCDPTR, 0xAC) selects the LCD data byte to be accessed and initiates a read or write operation—see Table 82. Writing to LCD Data registers To update the LCD data memory, first set the LSB of the LCD Configuration Y SFR (LCDCONY , 0xB1) to freeze the data being displayed on the LCD while updating it. Then, move the data to the LCD Data SFR (LCDDAT, 0xAE) prior to accessing the LCD Pointer SFR (LCDPTR, 0xAC). When the MSB of the LCD Pointer SFR (LCDPTR, 0xAC) is set, the content of the LCD Data SFR (LCDDAT, 0xAE) is transferred to the internal LCD data memory designated by the address in the LCD Pointer SFR (LCDPTR, 0xAC). Clear the LSB of the LCD Configuration Y SFR (LCDCONY , 0xB1) when all of the data memory has been updated to allow to use the new LCD set up for display. Sample 8052 code to update the segments attached to pins FP10 and FP11 on is shown below: ORL LCDCONY ,#01h ; start updating the data MOV LCDDATA,#FFh MOV LCDPTR,#80h OR 05h ANL LCDCONY ,#0FEh ; update finished Reading LCD Data registers When the MSB of the LCD Pointer SFR (LCDPTR, 0xAC) is cleared, the content of the LCD Data memory address designated by LCDPTR are transferred to the LCD Data SFR (LCDDAT, 0xAE). Sample 8052 code to read the contents of LCD data memory address 07h, which holds the on and off state of the segments attached to FP14 and FP15, is shown below: MOV LCDPTR,#NOT 80h AND 07h MOV R1, LCDDATA VOLTAGE GENERATION The ADE75XX/ADE71XX provides two ways to generate the LCD waveform voltage levels. The on-chip charge pump option can generate 5V . This makes it possible to use 5V LCDs with the 3.3V ADE75XX/ADE71XX. There is also an option to use an external resistor ladder with a 3.3V LCD. The EXTRES bit in the LCD Configuration X SFR (LCDCONX, 0x9C) selects the resistor ladder or charge pump option. When selecting how to generate the LCD waveform voltages, the following should be considered:

• Power Consumption
• Contrast Control
• Lifetime Performance Power Consumption In most LCDs, a high amount of current is required when the LCD waveforms change state. The external resistor ladder option draws a constant amount of current whereas the charge pump circuitry allows dynamic current consumption. If the LCD module is used with the internal charge pump option, when the display is disabled, the voltage generation is disabled, so that no power is consumed by the LCD function. This feature will result in significant power savings if the display is turned off in battery operation. Contrast control The electrical characteristics of the liquid in the LCD change over temperature, requiring adjustments in the LCD waveform voltages to ensure a readable display. An added benefit of the internal charge pump voltage generation is a configurable bias voltage that can be compensated over temperature to maintain contrast on the LCD. These compensations can be performed based on the ADE75XX/ADE71XX temperature measurements—see the Temperature, Battery and External Voltage Measurements section. This dynamic contrast control is not easily implemented with external resistor ladder voltage generation. The LCD bias voltage sets the contrast of the display when the charge-pump provides the LCD waveform voltages. The ADE75XX/ADE71XX provides 64 bias levels selectable using the BLVL bits in the LCD Configuration X SFR (LCDCONX, 0x9C). The voltage level on LCDV A, LCDVB and LCDVC depend on the the Interntal voltage reference value (Vref), BLVL[5:0] selection and the biasing selected as described in Table 76. Lifetime Performance DC offset on a segment will degrade its performance over time. The voltages generated through the internal charge pump

Preliminary Technical Data ADE75xx/ADE71xx Rev. PrE | Page 101 of 148 ; turn all segments on FP25 ON and FP26 OFF ORL LCDCONY ,#01h ; start data memory refresh MOV LCDDAT, #F0H MOV LCDPTR, #80h OR 0DH ANL LCDCONY,#0FEh ; end of data memory refresh ORL LCDCON,#080h ; enable LCD T o setup the same 3.3V LCD for use with an external resistor ladder: ; setup LCD pins to have LCD functionality MOV LCDSEGE, # 00111100b MOV LCDSEGE2, #00001111b ; setup LCDCON for f LCDCLK=2048Hz, 1/3 bias and 4x multiplexing MOV LCDCON, #00000111b ; setup LCDCONX for external resistor ladder MOV LCDCONX, #01000000b ; set up refresh rate for 64Hz with f LCDCLK=2048Hz, from Table 79 MOV LCDCLK, #00000011b ; set up LCD data registers with data to be displayed using ; LCDPTR and LCDDATA registers ; turn all segments on FP25 ON and FP26 OFF ORL LCDCONY ,#01h ; start data memory refresh MOV LCDDAT, #F0H MOV LCDPTR, #80h OR 0DH ANL LCDCONY,#0FEh ; end of data memory refresh ORL LCDCON,#080h ; enable LCD

flash memory must be erased to turn the zeros back to ones. However, a byte of flash memory cannot be erased individually. memory can be erased by page or all at once in a mass erase. conventional third party memory programmers.

1. Initial page erase sequence
2. Second read/verify sequence

endurance figure of 20,000 cycles of operation at 25°C. Figure 65. Flash/EE Memory Data Retention update a byte of data memory.

ADE75xx/ADE71xx Preliminary Technical Data Rev. PrE | Page 104 of 148 flash memory. Upon completion of the flash memory operation, the FLSHKY register is reset such that it must be written prior to another flash memory operation. Requiring the key to be set before an access to the flash memory decreases the likelihood of user code or data being overwritten by a program that has run amuck. The program counter, PC, is held on the instruction where the ECON register is written to until the flash memory controller is done performing the requested operation. Then the PC increments to continue with the next instruction. Any interrupts requests that occur while the flash controller is performing an operation are not handled until the flash operation is complete. All peripherals, such as timers and counters, will continue to operate as configured throughout the flash memory access. Table 87. Flash Control SFR (ECON, 0xB9) 7-0 ECON 0 1 Write byte: The value in EDATA is written to the Flash memory, at the page address given by EADRH and EARDL. Note that the byte being addressed must be pre-erased 2 Erase page: A 512-byte page of Flash memory address is erased. The page is selected by the address in EADRH/L. Any address in the page can be written to EADRH/L to select it for erasure. 3 Erase all: All 16 or 32kbytes of the Flash memory are erased. Note: This command is used during serial and parallel download modes but should not be executed by user code.

4 Read byte: The byte in th e Flash memory, addressed by

EADRH/L, is read into EDATA.

5 Erase page and write byte: The page that holds the byte

addressed by EADRH/L is erased. Then, data in EDATA is written to the byte of flash memory addressed by EADRH/L. 8 Protect code: See Protecting the Flash. Table 88. Flash Key SFR (FLSHKY , 0xBA) 7-0 FLSHKY 0xFF The content of this SFR is compared to the Flash key – 0x3B. If the two values match the next ECON operation is allowed - see Protecting the Flash. Table 89. Flash Protection Key SFR (PROTKY , 0xBB) 7-0 PROTKY 0xFF The content of this SFR is compared to the Flash memory location at address 0x3FFA. If the two values match, the update of the Write/Erase and Read protection set up is allowed - see Protecting the Flash. If the protection Key in the flash is 0xFF, PROTKY SFR value is not used for comparison. The PROTKY SFR is also used to write the protection key in the flash. This is done by writing the desired value in PROTKY and write 0x08 in the ECON SFR. This operation can only be done once. Table 90. Flash Data SFR (EDATA, 0xBC) 7-0 EDATA 0 Flash pointer data Table 91. Flash Write/Erase Protection 0 SFR (PROTB0, 0xBD)

Preliminary Technical Data ADE75xx/ADE71xx Rev. PrE | Page 105 of 148 Location Mnemonic Value 7-0 PROTB0 0xFF This SFR is used to write the write/erase protection bits for pages 0 to 7 of the Flash memory – see Protecting the Flash. Clearing the bit enables the protection. PROTB0.7: Page 7 PROTB0.6: Page 6 PROTB0.5: Page 5 PROTB0.4: Page 4 PROTB0.3: Page 3 PROTB0.2: Page 2 PROTB0.1: Page 1 PROTB0.0: Page 0 Table 92. Flash Write/Erase Protection 1 SFR (PROTB1, 0xBE) 7-0 PROTB1 0xFF This SFR is used to write the write/erase protection bits for pages 8 to 15 of the Flash memory – see Protecting the Flash. Clearing the bit enables the protection. PROTB1.7: Page 15 PROTB1.6: Page 14 PROTB1.5: Page 13 PROTB1.4: Page 12 PROTB1.3: Page 11 PROTB1.2: Page 10 PROTB1.1: Page 9 PROTB1.0: Page 8 Table 93. Flash Read Protection SFR (PROTR, 0xBF) 7-0 PROTR 0xFF This SFR is used to write the read protection bits for pages 0 to 31 of the Flash memory – see Protecting the Flash. Clearing the bit enables the protection. PROTR.7: Page 28 to 31 PROTR.6: Page 24 to 27 PROTR.5: Page 20 to 23 PROTR.4: Page 16 to 19 PROTR.3: Page 12 to 15 PROTR.2: Page 8 to 11 PROTR.1: Page 4 to 7 PROTR.0: Page 0 to 3 Table 94. Flash Low Byte Address SFR (EADRL, 0xC6) 7-0 EADRL 0 Flash pointer low byte address This SFR is also used to write the write/erase protection bits for pages 16 to 23 of the Flash memory – see Protecting the Flash. Clearing the bit enables the protection. EADRL.7: Page 23 EADRL.6: Page 22 EADRL.5: Page 21

Preliminary Technical Data ADE75xx/ADE71xx Rev. PrE | Page 107 of 148 Remark: The read protection does not prevent MOVC commands from being executed within the code. There is an additional layer of protection offered by a protection security key. The user can setup a protection security key so that the protection scheme cannot be changed without this key. Once the protection key has been configured, it may not be modified. Enabling Flash Protection by Code The protection byts in the Flash can be programmed using Flash controller command and programming ECON to 0x08. The EADRH, EADRL, PROTB1 and PROTB0 bytes are used in this case to store the data to be written to the 32 bits of write protection. Note that the EADRH and EADRL registers are not used as data pointers here, but to store write protection data. PROTR PROTKY PROTB0 PROTB1 EADRL EADRH RP 31-28 RP 27-24 RP 23-20 RP 19-16 RP 15-12 RP 11-8 RP 7-4 RP 3-0 WP WP WP WP WP WP WP WP WP WP WP WP WP WP WP WP WP WP WP WP WP WP WP WP WP WP WP WP WP WP WP WP PROTECTION KEY[7:0] 0x3FFF 0x3FFE 0x3FFD 0x3FFC 0x3FFB 0x3FFA 0x3FF9 0x3E00 WDOG LOCK Figure 68: Flash Protection in Page 31 The sequence for writing the protection bits is: 1. Set up the EADRH, EADRL, PROTB1 and PROTB0 registers with the write/erase protection bits. When erased, the protection bits default to 1, like any other bit of Flash memory. The default protection setting is for no protection. T o enable protection, write a 0 to the bits corresponding to the pages that should be protected. 2. Set up the PROTR register with the read protection bits. Note that every read protection bit protects four pages. To enable the read protection bit, write a 0 to the bits that should be read protected. 3. To enable the protection key, write to the PROTKY register. If enabled, the protection key will be required to modify the protection scheme. The protection key, flash memory address 0x3FFA defaults to FFH so if the PROTKY register is not written to, it will remain 0xFFH. If the protection key is written to, the PROTKY register must be written with this value every time the protection functionality is accessed. Note that once the protection key is configured, it cannot be modified. Also note that the most significant bit of 0x3FFA is used to enable a lock mechanism for the watchdog settings—see the Watchdog Timer section for more information. 4. Run the protection command by writing 08H to the ECON register. 5. Reset the chip to activate the new protection. To enable read and write/erase protection for the last page only, use the following 8051 code. Writing the flash protection command to the ECON register initiates programming the protection bits in the flash. ; enable write/erase protection on the last page only MOV EADRH, #07FH MOV EADRL, #0FFH MOV PROTB1, #FFH MOV PROTB0, #FFH ; enable read protection on the last four pages only MOV PROTR, #07FH ; set up a protection key of 0A3H. This command can be ; omitted to use the default protection key of 0xFF MOV PROTKY , #0A3H ; write the flash key to the FLSHKY register to enable flash ; access. The flash access key is not configurable. MOV FLSHKY , #3BH ; write flash protection command to the ECON register MOV ECON, #08H Enabling Flash Protection by emulator commands Another way to set the Flash protection bytes is to use some reserved emulator commands available only in download mode. These commands write directly to the SFRs and can be used to duplicate the operation mentioned in the Enabling Flash Protection by Code paragraph. Once these Flash bytes are written, the part can exit emulation mode by reset and the protections will be effective. This method can be used in production and implemented after downloading the program. The commands used for this operation are an extension of the commands listed in the application note uC004 – Understanding the Serial Download Protocol: - Command with ASCII code ‘I’ or 0x49 write the data into R0 - Command with ASCII code ‘F’ or 0x46 write R0 into the SFR address defined in the data of this command Omitting the protocol defined in uC004, the sequence to load

ADE75xx/ADE71xx Preliminary Technical Data Rev. PrE | Page 108 of 148 protections are similar to the sequence presented mentioned in the Enabling Flash Protection by Code paragraph.except that two emulator commands are necessary to replace one assembly command. For example to write the protection value in EADRH the two following commands need to be executed: - Command ‘I ‘ with Data = Value of protection byte 0x3FFF - Command ‘F’ with Data = 0xC7 Following this protocol, the protection can be written to the Flash using the same sequence as mentioned in the Enabling Flash Protection by Code paragraph. When the part is reset the protection will be effective. Notes on Flash Protection The flash protection scheme is disabled by default so that none of the pages of the flash are protected from reading or writing/erasing. The last page must be write/erase protected for the protection scheme to work. T o activate the protection settings, the ADE75XX/ADE71XX must be reset after configuring the protection. After configuring protection on the last page and resetting the part, protections that have been enabled can only be removed by mass erasing the flash memory. The protection bits are read and erase protected by enabling read and write/erase protection the last page, but the protection bits are never truly write protected. Protection bits can be programmed modified from a 1 to a 0, even after the last page has been protected. In this way, more protection can be added but none can be removed. The protection scheme is intended to protect the end system. Protection should be disabled while developing and emulating code. Flash memory timing Typical program and erase times for the flash memory are as follows: Command Bytes Affected Flash Memory Timing WRITE BYTE 1 byte 30us ERASE PAGE 512 bytes 20ms ERASEALL 16 or 32kbytes 200ms READ BYTE 1 bytes 100ns ERASEPAGE and WRITE BYTE 512 bytes 21ms VERIFY BYTE 1 byte 100ns Note that the core microcontroller operation is idled until the requested flash memory operation is complete. In practice, this means that even though the Flash operation is typically initiated with a two-machine-cycle MOV instruction (to write to the Flash Control SFR (ECON, 0xB9)), the next instruction is not executed until the Flash/EE operation is complete. This means that the core cannot respond to interrupt requests until the Flash/EE operation is complete, although the core peripheral functions such as counter/ timers continue to count as configured throughout this period. IN CIRCUIT PROGRAMMING Serial Downloading The ADE75XX/ADE71XX facilitates code download via the standard UART serial port. The parts enter serial download mode after a reset or a power cycle if the SDEN pin is pulled low through an external 1 kΩ resistor. Once in serial download mode, the hidden embedded download kernel executes. This allows the user to download code to the full 16 or 32 kbytes of Flash memory while the device is in circuit in its target application hardware. Protection configured in the last page of the ADE75xx/ADE71xx affects whether flash memory can be accessed in serial download mode. Read protected pages cannot be read. Write/erase protected pages cannot be written or erased. The configuration bits cannot be programmed in serial download mode.

Preliminary Technical Data ADE75xx/ADE71xx Rev. PrE | Page 109 of 148 TIMERS The ADE75XX/ADE71XX has three 16-bit timer/ counters: Timer 0, Timer 1, and Timer 2. The timer/counter hardware is included on-chip to relieve the processor core of the overhead inherent in implementing timer/counter functionality in software. Each timer/counter consists of two 8-bit registers: THx and TLx (x = 0, 1, or 2). All three can be configured to operate either as timers or as event counters. When functioning as a timer, the TLx register is incremented every machine cycle. Thus, one can think of it as counting machine cycles. Because a machine cycle on a single-cycle core consists of one core clock period, the maximum count rate is the core clock frequency. When functioning as a counter, the TLx register is incremented by a 1-to-0 transition at its corresponding external input pin: T0, T1, or T2. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. Because it takes two machine cycles (two core clock periods) to recognize a 1-to-0 transition, the maximum count rate is half the core clock frequency. There are no restrictions on the duty cycle of the external input signal, but, to ensure that a given level is sampled at least once before it changes, it must be held for a minimum of one full machine cycle. User configuration and control of all timer operating modes is achieved via the SFRs in Table 96. Table 96. Timer SFRs Table 97. Timer/Counter 0 and 1 Mode SFR (TMOD, 0x89) 7 Gate1 0 Timer 1 Gating Control. Set by software to enable Timer/Counter 1 only while the INT1 pin is high and the TR1 control is set. Cleared by software to enable Timer 1 whenever the TR1control bit is set. 6 C_T1 0 Timer 1 Timer or Counter Select Bit. Set by software to select counter operation (input from T1 pin). Cleared by software to select the timer operation (input from internal system clock). Timer 1 Mode Select bits M1 M0 Description 0 0 TH1 operates as an 8-bit timer/co unter. TL1 serves as 5-bit prescaler. 5-4 T1_M1, T1_M0 0 1 16-Bit Timer/Counter. TH1 and TL1 ar e cascaded; there is no prescaler.

ADE75xx/ADE71xx Preliminary Technical Data Rev. PrE | Page 110 of 148 1 0 8-Bit Autoreload Timer/Counter. TH1 holds a value that is to be reloaded into TL1 each time it overflows. 1 1 Timer/Counter 1 Stopped. 3 Gate0 0 Timer 0 Gating Control. Set by software to enable Timer/Counter 0 only while the INT0 pin is high and the TR0 control bit is set. Cleared by software to enable Timer 0 whenever the TR0 control bit is set. 2 C_T0 0 Timer 0 Timer or Counter Select Bit. Set by software to the select counter operation (input from T0 pin). Cleared by software to the select timer operation (input from internal system clock). Timer 0 Mode Select Bits M1 M0 Description 0 0 TH0 operates as an 8-bit timer/coun ter. TL0 serves as a 5-bit prescaler. 0 1 16-Bit Timer/Counter. TH0 and TL0 ar e cascaded; there is no prescaler. 1 0 8-Bit Autoreload Timer/Counter. TH0 holds a value that is to be reloaded into TL0 each time it overflows. 1-0 T0_M1, T0_M0 1 1 TL0 is an 8-bit timer/counter controlle d by the standard Timer 0 control bits. TH0 is an 8-bit timer only, controlled by Timer 1 control bits. Table 98. Timer/Counter 0 and 1 Control SFR (TCON, 0x88) 7 0x8F TF1 0 Timer 1 Overflow Flag. Set by hardware on a Timer/Counter 1 overflow. Cleared by hardware when the program counter (PC) vectors to the interrupt service routine. 6 0x8E TR1 0 Timer 1 Run Control Bit. Set by the user to turn on Timer/Counter 1. Cleared by the user to turn off Timer/Counter 1. 5 0x8D TF0 0 Timer 0 Overflow Flag. Set by hardware on a Timer/Counter 0 overflow. Cleared by hardware when the PC vectors to the interrupt service routine. 4 0x8C TR0 0 Timer 0 Run Control Bit. Set by the user to turn on Timer/Counter 0. Cleared by the user to turn off Timer/Counter 0. 3 0x8B IE1 1 0 External Interrupt 1 (INT1) Flag. Set by hardware by a falling edge or by a zero level applied to the external interrupt pin, INT1, depending on the state of Bit IT1. Cleared by hardware when the PC vectors to the interrupt service routine only if the interrupt was transition-activated. If level-activated, the external requesting source controls the request flag rather than the on-chip hardware. 2 0x8A IT1 1 0 External Interrupt 1 (IE1) Trigger Type. Set by software to specify edge-sensitive detection, that is, 1-to-0 transition. Cleared by software to specify level-sensitive detection, that is, zero level. 1 0x89 IE0 1 0 External Interrupt 0 (INT0) Flag. Set by hardware by a falling edge or by a zero level being applied to the external interrupt pin, INT0, depending on the statue of Bit IT0. Cleared by hardware when the PC vectors to the interrupt service routine only if the interrupt was transition-activated. If level-activated, the external requesting source controls the request flag rather than the on-chip hardware. 0 0x88 IT0 1 0 External Interrupt 0 (IE0) Trigger Type. Set by software to specify edge-sensitive detection, that is, 1-to-0 transition. Cleared by software to specify level-sensitive detection, that is, zero level.

Preliminary Technical Data ADE75xx/ADE71xx Rev. PrE | Page 111 of 148 2 These bits are not used to control Timer/Counters 0 and 1, but are used instead to control and monitor the external INT0 and INT1 interrupt pins. Table 99. Timer/Counter 2 Control SFR (T2CON, 0xC8) 7 0xCF TF2 0 Timer 2 Overflow Flag. Set by hardware on a Timer 2 overflow. TF2 cannot be set when either RCLK = 1 or TCLK = 1. Cleared by user software. 6 0xCE EXF2 0 Timer 2 External Flag. Set by hardware when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1. Cleared by user software. 5 0xCD RCLK 0 Receive Clock Enable Bit. Set by the user to enable the serial port to use Timer 2 overflow pulses for its receive clock in serial port Modes 1 and 3. Cleared by the user to enable Timer 1 overflow to be used for the receive clock. 4 0xCC TCLK 0 Transmit Clock Enable Bit. Set by the user to enable the serial port to use Timer 2 overflow pulses for its transmit clock in serial port Modes 1 and 3. Cleared by the user to enable Timer 1 overflow to be used for the transmit clock. 3 0xCB EXEN2 0 Timer 2 External Enable Flag. Set by the user to enable a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to clock the serial port. Cleared by the user for Timer 2 to ignore events at T2EX. 2 0xCA TR2 0 Timer 2 Start/Stop Control Bit. Set by the user to start Timer 2. Cleared by the user to stop Timer 2. 1 0xC9 CNT2 0 Timer 2 Timer or Counter Function Select Bit. Set by the user to select the counter function (input from external T2 pin). Cleared by the user to select the timer function (input from on-chip core clock). 0 0xC8 CAP2 0 Timer 2 Capture/Reload Select Bit. Set by the user to enable captures on negative transitions at T2EX if EXEN2 = 1. Cleared by the user to enable autoreloads with Timer 2 overflows or negative transitions at T2EX when EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is forced to autoreload on Timer 2 overflow. Table 100. Timer 0 High byte SFR (TH0, 0x8C) 7-0 TH0 0 Timer 0 Data high byte Table 101. Timer 0 Low byte SFR (TL0, 0x8A) 7-0 TL0 0 Timer 0 Data high byte Table 102. Timer 1 High byte SFR (TH1, 0x8D) 7-0 TH1 0 Timer 1 Data high byte Table 103. Timer 1 Low byte SFR (TL1, 0x8B) 7-0 TL1 0 Timer 1 Data high byte

ADE75xx/ADE71xx Preliminary Technical Data Rev. PrE | Page 112 of 148 Table 104. Timer 2 High byte SFR (TH2, 0xCD) 7-0 TH2 0 Timer 2 Data high byte Table 105. Timer 2 Low byte SFR (TL2, 0xCC) 7-0 TL2 0 Timer 2 Data high byte Table 106. Timer 2 Reload/capture High byte SFR (RACP2H, 0xCB) 7-0 TH2 0 Timer 2 Reload/capture high byte Table 107. Timer 2 Reload/capture Low byte SFR (RACP2L, 0xCA) 7-0 TL2 0 Timer 2 Reload/capture low byte TIMER 0 AND TIMER 1 Timer/Counter 0 and 1 Data Registers Each timer consists of two 8-bit registers: Timer 0 High byte SFR (TH0, 0x8C), Timer 0 Low byte SFR (TL0, 0x8A), Timer 1 High byte SFR (TH1, 0x8D) and Timer 1 Low byte SFR (TL1, 0x8B) These can be used as independent registers or combined into a single 16-bit register, depending on the timers’ mode configuration – see Table 100 to Table 103. Timer/Counter 0 and 1 Operating Modes This section describes the operating modes for Timer/Counters 0 and 1. Unless otherwise noted, these modes of operation are the same for both Timer 0 and Timer 1. Mode 0 (13-Bit Timer/Counter) Mode 0 configures an 8-bit timer/counter. Figure 69 shows Mode 0 operation. Note that the divide-by-12 prescaler is not present on the single-cycle core. 04741-0-049 FCORE CONTROL P0.6/T0 GATE INT0 TR0 TF0TL0 (5 BITS) TH0 (8 BITS) INTERRUPT C/T = 0 C/T = 1 Figure 69. Timer/Counter 0, Mode 0 In this mode, the timer register is configured as a 13-bit register. overflow flag, TF0. TF0 can then be used to request an interrupt.

1 Control SFR (TCON, 0x88); the Gate bit is in Timer/Counter

register runs with all 16 bits. Mode 1 is shown in Figure 70. Figure 70. Timer/Counter 0, Mode 1

Figure 71. Timer/Counter 0, Mode 2 separate counters. This configuration is shown in Figure 72. cycles) and takes over the use of TR1 and TF1 from Timer 1. Figure 72. Timer/Counter 0, Mode 3

2 Low byte SFR (TL2, 0xCC), Timer 2 Reload/capture High byte

Table 108. T2CON Operating Modes

1 X 1 Baud Rate

Figure 74. The

Preliminary Technical Data ADE75xx/ADE71xx Rev. PrE | Page 115 of 148 PLL The ADE75xx/ADE71xx is intended for use with a 32.768 kHz watch crystal. A PLL locks onto a multiple of this frequency to provide a stable 4.096 MHz clock for the system. The core can operate at this frequency or at binary submultiples of it to allow power saving when maximum core performance is not required. The default core clock is the PLL clock divided by 4 or 1.024 MHz. The ADE energy measurement clock is derived from the PLL clock and is maintained at 4.096/5 MHz, 819.2 kHz across all CD settings. The PLL is controlled by the CD[2:0] bits in the Power Control SFR (POWCON, 0xC5). To protect erroneous changes to the Power Control SFR (POWCON, 0xC5), a key is required to modify the register. First the Key SFR (KYREG, 0xC1) is written with the key, 0xA7, and then a new value is written to the Power Control SFR (POWCON, 0xC5). If the PLL loses lock, the MCU is reset and the PLLFAULT bit is set in the Peripheral Configuration SFR (PERIPH, 0xF4). Set the PLLACK bit in the Start ADC Measurement SFR (ADCGO, 0xD8) to acknowledge the PLL fault, clearing the PLL_FLT flag. PLL SFR REGISTER LIST Power Control SFR (POWCON, 0xC5) Bit Location Bit Mnemonic Default Value

7 RESERVED X Reserved

6 METER_OFF 0 Set this bit to turn off the modulators and energy metering DSP circuitry to reduce power if metering functions are not needed in PSM0

5 RESERVED 0 Reserved

4 COREOFF 0 Set this bit to shut down the core if in the PSM1 operating mode.

3 RESERVED Reserved

Controls the core clock frequency, Fcore. Fcore=4.096MHz/2CD CD[2:0] F core (MHz) 0 0 0 4.096 0 0 1 2.048 0 1 0 1.024 0 1 1 0.512 1 0 0 0.256 1 0 1 0.128 1 1 0 0.064 2-0 CD[2:0] 010 1 1 1 0.032 Table 109.Key SFR (KYREG, 0xC1) Bit Location Bit Mnemonic Default Value 7-0 KYREG 0 Write 0xA7 to the KYREG SFR befo re writing the POWCON SFR, to unlock it Write 0xEA to the KYREG SFR before writing to the HTHSEC, SEC, MIN, or HOUR timekeeping register to unlock it. Peripheral Configuration SFR (PERIPH, 0xF4) Bit Location Bit Mnemonic Default Value Indicates the power supply that is connected internally to V SW.

5 VDD_OK 0 If set, indicates that VDD power supply is ok for operation

ADE75xx/ADE71xx Preliminary Technical Data Rev. PrE | Page 116 of 148 2 EXTREFEN 0 Set this bit if an external reference is connected to the REFIN pin. Controls the function of the P1.0/RX pin. RXPROG [1:0] Function 0 0 GPIO 0 1 RX with wakeup disabled 1-0 RXPROG[1:0] 00 1 1 RX with wakeup enabled Start ADC Measurement SFR (ADCGO, 0xD8) Bit Location Bit Addr. Bit Name Default Value 7 0xDF PLL_FTL_ACK 0 Set this bit to clear the PLL fault bit, PLL_FLT in the PERIPH register. A PLL fault is generated if a reset was caused because the PLL lost lock. 6-3 0xDE – 0xDB Reserved 0 Reserved 2 0xDA VDCIN_ADC_GO 0 Set this bit to initiate an external voltage measurement. This bit will be cleared when the measurement request is received by the ADC. 1 0xD9 TEMP_ADC_GO 0 Set this bit to initiate a temperature measurement. This bit will be cleared when the measurement request is received by the ADC. 0 0xD8 BATT_ADC_GO 0 Set this bit to initiate a battery measurement. This bit will be cleared when the measurement request is received by the ADC.

Preliminary Technical Data ADE75xx/ADE71xx Rev. PrE | Page 117 of 148 RTC - REAL TIME CLOCK The ADE75XX/ADE71XX has an embedded Real Time Clock (RTC) – see Figure 75. The external 32.768 kHz crystal is used as the clock source for the RTC. Calibration is provided to compensate the nominal crystal frequency and for variations in the external crystal frequency over temperature. By default, the RTC is maintained active in all the Power Saving Modes. The RTC counters retain their values through watchdog resets and external resets and are only reset during a power on reset. 8-BIT PRESCALER HUNDREDTHS COUNTER HTHSEC SECOND COUNTER SEC MINUTE COUNTER MIN HOUR COUNTER HOUR ITEN ALARM EVENT 8-BIT INTERVAL COUNTER INTVAL SFR INTERVAL TIMEBASE SELECTION MUX RTCEN 32.768kHz CRYSTAL ITS1 ITS0 EQUAL? CALIBRATION RTCCOMP TEMPCAL MIDNIGHT EVENT CALIBRATED 32.768kHz Figure 75: RTC implementation RTC SFR REGISTER LIST SFR Address Bit Addressable Description TIMECON 0xA1 No RTC configuration HTHSEC 0xA2 No Hundred th of a second counter SEC 0xA3 No Seconds counter MIN 0xA4 No Minutes counter HOUR 0xA5 No Hours counter INTV AL 0xA6 No Alarm interval RTCCOMP 0xF6 No RTC nominal compensation

ADE75xx/ADE71xx Preliminary Technical Data Rev. PrE | Page 118 of 148 TEMPCAL 0xF7 No RTC temperature compensation INTPR 0xFF No RTC Calibration output options KYREG 0xC1 No Key Register Table 110. RTC Configuration SFR (TIMECON, 0xA1) Midnight Flag 7 MIDNIGHT 0 This bit is set when the RTC rolls over to 00:00:00:00. It can be cleared by the user to indicate that the midnight event has been serviced. In twenty- four hour mode, the midnight flag is raised once a day at midnight. Twenty-four hour mode 0 256 Hour mode. The HOUR register will roll over from 255 to 0. 1 24 Hour mode. The HOUR regist er will roll over from 23 to 0.

6 TFH 0

Note: This bit is retained during a watchdog reset or an external reset. It is reset after a power on reset (POR). Interval Timer Timebase Selection ITS[1:0] Timebase 0 0 1/128 second 0 1 Second 1 0 Minute 5-4 ITS[1:0] 0 1 1 Hour Interval Timer One-Time Alarm

0 The ALARM flag will be set after INTVAL counts and then another

interval count will start.

3 SIT 0

1 The ALARM flag will be set after one time interval. Interval Timer Alarm Flag 2 ALARM 0 This bit is set when the configured time interval has elapsed. It can be cleared by the user to indicate that the alarm event has been serviced. Interval Timer Enable 0 The interval timer is disabled. The 8-bit interval timer counter is reset.

1 ITEN 0

1 Set this bit to enable the interval timer. The RTCEN bit must also be set to enable the interval timer. RTC Enable. Also Temperature, Battery and Supply ADC Background Strobe Enable

0 RTCEN 1

Note: The RTC is always enabled. Table 111. Hundredths of a Second Counter SFR (HTHSEC, 0xA2) This counter updates every 1/128 second, referenced from the calibrated 32kHz clock. It overflows from 127 to 00, incrementing the seconds counter, SEC. 7-0 HTHSEC 0 Note: This register is retained during a watchdog reset or an external reset. It is reset after a power on reset (POR).

Preliminary Technical Data ADE75xx/ADE71xx Rev. PrE | Page 119 of 148 Table 112. Seconds Counter SFR (SEC, 0xA3) This counter updates every second, referenced from the calibrated 32kHz clock. It overflows from 59 to 00, incrementing the minutes counter, MIN. 7-0 SEC 0 Note: This register is retained during a watchdog reset or an external reset. It is reset after a power on reset (POR). Table 113. Minutes Counter SFR (MIN, 0xA4) This counter updates every minute, referenced from the calibrated 32kHz clock. It overflows from 59 to 00, incrementing the hours counter, HOUR. 7-0 MIN 0 Note: This register is retained during a watchdog reset or an external reset. It is reset after a power on reset (POR). Table 114. Hours Counter SFR (HOUR, 0xA5) This counter updates every hour, referenced from the calibrated 32kHz clock. If the TFH bit in the RTC Configuration SFR (TIMECON, 0xA1) is set, the HOUR SFR overflows from 23 to 00, setting the MIDNIGHT bit and creating a pending RTC interrupt. If the TFH bit in the RTC Configuration SFR (TIMECON, 0xA1) is clear, the HOUR SFR overflows from 255 to 00, setting the MIDNIGHT bit and creating a pending RTC interrupt. 7-0 HOUR 0 Note: This register is retained during a watchdog reset or an external reset. It is reset after a power on reset (POR). Table 115. Alarm Interval SFR (INTV AL, 0xA6) 7-0 INTVAL 0 The interval timer counts according to the timebase established in the ITS[1:0] bits of the RTC Configuration SFR (TIMECON, 0xA1). Once the number of counts is equal to INTVAL, the ALARM flag is set and a pending RTC interrupt is created. Note that the interval counter is 8-bits so it could count up to 255 seconds, for example. Table 116. RTC Nominal Compensation SFR (RTCCOMP , 0xF6) The RTCCOMP SFR holds the nominal RTC compensation value at 25°C. 7-0 RTCCOMP 0 Note: This register is reset after a watchdog reset, an external reset or a power on reset (POR). Table 117. RTC Temperature Compensation SFR (TEMPCAL, 0xF7) 7-0 TEMPCAL 0 The TEMPCAL SFR is adjusted based on the temerature read in the TEMPADC to calibrate the RTC over temperature. This allows the external crystal shift to be compensated over temperature.

ADE75xx/ADE71xx Preliminary Technical Data Rev. PrE | Page 120 of 148 Note: This register is reset after a watchdog reset, an external reset or a power on reset (POR). Table 118. Interrupt pins configuration SFR (INTPR, 0xFF) When set, the RTC calibration frequency selected by FSEL[1:0] is output on the P0.2/CF1/RTCCAL pin. Sets RTC calibration output frequency and calibration window FSEL[1:0] Calibration window, frequency 0 0 30.5 seconds, 1Hz 0 1 30.5 seconds, 512 Hz 1 0 0.244 seconds, 500Hz 6-5 FSEL[1:0] 1 1 0.244 seconds, 16.384 kHz Controls the function of INT1 T INT1PRG[2:0] Function x 0 0 GPIO x 0 1 BCTRL 0 1 x INT1 input disabled 3-1 INT1PRG[2:0] 000 1 1 x INT1 input enabled Controls the function of INT0 INT0PRG Function Table 119. Key SFR (KYREG, 0xC1) 7-0 KYREG 0 Write 0xA7 to the KYREG SFR befo re writing the POWCON SFR, to unlock it Write 0xEA to the KYREG SFR before writing to the HTHSEC, SEC, MIN, or HOUR timekeeping register to unlock it.. READ AND WRITE OPERATIONS Writing the RTC Registers The RTC circuitry runs off a 32.768kHz clock. The timekeeping registers, HTHSEC, SEC, MIN, HOUR are updated with a 32.768 kHz clock. However, the TIMECON and INTV AL SFRs are updated with a 128Hz clock. It takes up to two 128Hz clock cycles from when the MCU writes the TIMECON or INTV AL register until it is successfully updated in the RTC. T o protect the RTC timekeeping registers from runaway code, a key must be written to the KYREG register to obtain write access to the HTHSEC, SEC, MIN and HOUR registers. The KYREG should be set to 0xEA to unlock the timekeeping registers and is reset to zero after a timekeeping register is written to. The RTC registers can be written using the following 8052 assembly code: MOV RTCKey, #0EAh CALL UpdateRTC UpdateRTC: MOV KYREG, RTCKey MOV SEC, #30 MOV KYREG, RTCKey MOV MIN, #05 MOV KYREG, RTCKey MOV HOUR, #04 RET Reading the RTC Counter SFRs The RTC cannot be stopped to read the current time because stopping the RTC would introduce an error in its timekeeping. So the RTC is read on the fly. Therefore the counter registers

Preliminary Technical Data ADE75xx/ADE71xx Rev. PrE | Page 121 of 148 must be checked for overflow. This can be accomplished through the following 8052 assembly code: ReadAgain: MOV R0, HTHSEC ; using Bank 0 MOV R1, SEC MOV R2, MIN MOV R3, HOUR MOV A, HTHSEC CJNE A, 00h, ReadAgain ; 00h is R0 in Bank 0 RTC MODES The RTC can be configured in a 24 hour mode or a 256 hour mode. A midnight event is generated when the RTC hour counter rolls over from 23 to 0 or 255 to 0, depending on whether the TFH bit is set in the RTC Configuration SFR (TIMECON, 0xA1). The midnight event sets the MIDNIGHT flag in the RTC Configuration SFR (TIMECON, 0xA1) and a pending RTC interrupt is created. The RTC midnight event will wake the 8052 MCU core if the MCU is asleep in PSM2 when the midnight event occurs. To acknowledge the midnight event, service the RTC interrupt. In the 24 hour mode, the midnight event is generated once a day, at midnight. The 24 hour mode is useful for updating a software calendar to keep track of the current day. The 256 hour mode will result in power savings during extended operation in PSM2 because the MCU core will be awoken less frequently. RTC INTERRUPTS The RTC Midnight and Alarm Interrupts are enabled by setting the ETI bit in the Interrupt Enable and Priority 2 SFR (IEIP2, 0xA9). When a midnight or alarm event occurs, a pending RTC interrupt is generated. If the RTC interrupt is enabled, the program will vector to the RTC interrupt address and the pending interrupt will be cleared. If the RTC interrupt is disabled, then the RTC interrupt will remain pending until the RTC interrupt is enabled. Then the program will vector to the RTC interrupt address. The MIDNIGHT and ALARM flags are set when the midnight and alarm events occur, respectively. The user should manage these flags to keep track of which event caused an RTC interrupt by servicing the event and clearing the appropriate flag in the RTC ISR. Note that if the ADE7100/7500 is awakened by an RTC event, either the MIDNIGHT or ALARM, then the pending RTC interrupt must be serviced before the ADE7100/7500 can go back to sleep again. The ADE7100/7500 will keep waking up until this interrupt has been serviced. Interval Timer Alarm The RTC can be used as an interval timer. When the interval timer is enabled by setting the ITEN bit in the RTC Configuration SFR (TIMECON, 0xA1), the interval timer clock source selected by the ITS1 and ITS0 bits is passed through to an 8-bit counter. This counter increments on every interval timer clock pulse until the 8-bit counter is equal to the value in the Alarm Interval SFR (INTVAL, 0xA6). Then an alarm event is generated, setting the ALARM flag and creating a pending RTC interrupt. If the SIT bit in the RTC Configuration SFR (TIMECON, 0xA1) is clear then the 8-bit counter is cleared and starts counting again. If the SIT bit is set then the 8-bit counter is held in reset after the alarm occurs. Take care when changing the interval timer timebase. The recommended prodedure is as follows: 1. If the INTV AL SFR is going to be modified, write this register first. Then wait for one 128Hz clock cycle, to synchronize with the RTC, 64000 cycles at a 4.096MHz instruction cycle clock. 2. Disable the interval timer by clearing the ITEN bit in the TIMECON SFR. Then wait for one 128Hz clock cycle, to synchronize with the RTC, 64000 cycles at a 4.096MHz instruction cycle clock. 3. Read the TIMECON SFR to ensure that the ITEN bit is clear. If it is not, wait for another 128Hz clock cycle. 4. Set the timebase bits, ITS[1:0] in the TIMECON SFR to configure the interval. Wait for a 128Hz clock cycle for this change to take effect. The RTC alarm event will wake the 8052 MCU core if the MCU is in PSM2 when the alarm event occurs. RTC CALIBRATION The RTC provides registers to calibrate the nominal external crystal frequency and its variation over temperature. Up to ±248ppm frequency error can be calibrated out by the RTC circuitry, which adds or subtracts pulses from the external crystal signal. The nominal crystal frequency should be calibrated with the RTCCOMP register so that the clock going into the RTC is precisely 32.768 kHz at 25 °C. The RTC Temperature Compensation SFR (TEMPCAL, 0xF7) is used to compensate for the external crystal drift over temperature by adding or subtracting additional pulses based on temperature. The LSB of each RTC compensation register represents a ±2ppm, or 0.17s/day, frequency error. The RTC compensation circuitry adds the RTC Temperature Compensation SFR (TEMPCAL, 0xF7) and the RTC Nominal Compensation SFR (RTCCOMP , 0xF6) to determine how much compensation is required and the sum of these two registers is limited to ±248ppm, or 42.85s/day.

ADE75xx/ADE71xx Preliminary Technical Data Rev. PrE | Page 122 of 148 Calibration Flow: A RTC calibration pulse output is provided on the P0.2/CF1/RTCCAL pin. Enable the RTC output by setting the RTCCAL bit in the INTPR SFR. The RTC calibration is accurate to within ±2ppm over a 30.5 second window in all operational modes: PSM0, PSM1 and PSM2. Two output frequencies are offered for the normal RTC mode: 1Hz with FSEL[1:0]=00 and 512Hz with FSEL[1:0]=01 in the INTPR register. A shorter window of 0.244 seconds is offered for fast calibration during PSM0 or PSM1. Two output frequencies are offered for this RTC calibration output mode: 500Hz with FSEL[1:0]=01 and 16.384kHz with FSEL[1:0]=11 in the INTPR register. Note that for the 0.244s calibration window, the RTC is clocked 125 times faster than in the normal mode, resulting in timekeeping registers that represent seconds/125, minutes/125 and hours/125 instead of seconds, minutes and hours. Therefore this mode should be used for calibration only. Table 120: RTC calibration options When no RTC compensation is applied, when RTCCOMP and TEMPCAL equal to zero, the nominal compensation required to account for the error in the external crystal can be determined. In this case, it is not necessary to wait for an entire calibration window to determine the error in the pulse output. Calculating at the error in frequency between two consecutive pulses on the P0.2/CF1/RTCCAL pin is enough. The value to write to the RTCCOMP register is calculated from the % error or seconds per day error on the frequency output. Each LSB of the RTCCOMP SFR represents 2ppm of correction where1s/day error is equal to 11.57ppm. )(%5000 ErrorRTCCOMP ×= )/(57.112

1 ErrordaysRTCCOMP ××=

to determine how much compensation is required and the sum of these two registers is limited to ±248ppm. During calibration, user software writes the RTC with the current time. Refer to the RTC Read and Write operations section for more information on how to read and write the RTC timekeeping registers. Option FSEL[1:0] Calibration Window (s) FRTCCAL (Hz) Normal Mode 0 00 30.5 1 Normal Mode 1 01 30.5 512 Calibration Mode 0 10 0.244 500 Calibration Mode 1 11 0.244 16384

Preliminary Technical Data ADE75xx/ADE71xx Rev. PrE | Page 123 of 148 UART SERIAL INTERFACE The ADE75XX/ADE71XX UART can be configured in one of four modes: - Shift register with baud rate fixed at Fcore/12 - 8-bit UART with variable baud rate - 9- bit UART with baud rate fixed at Fcore/64 or Fcore/32 - 9 bit UART with variable baud rate Variable baud rates are defined by using an internal timer to generate any rate between 300 and 115200 bauds/s. The UART serial interface provided in the ADE75XX/ADE71XX is a full-duplex serial interface. It is also receive buffered, by storing the first received byte in a receive buffer until the reception of the second byte is complete. The physical interface to the UART is provided via the RxD (P1.0) and TxD (P1.1) pins, while the firmware interface is through the SFRs presented in Table 121. Both the serial port receive and transmit registers are accessed through the SBUF SFR (SFR address = 0x99). Writing to SBUF loads the transmit register, and reading SBUF accesses a physically separate receive register. An enhanced UART mode is offered by using UART Timer and providing enhanced frame error, break error and overwrite error detection. This mode is enabled by setting the EXTEN bit in the CFG SFR—see the UART additional features section. The SBAUDT and SBAUDF SFR are used to configure UART Timer and to indicate the enhanced UART errors. UART SFR REGISTER LIST Table 121. Serial port SFRs Table 122. SCON SFR Bit Description SFR (SCON, 0x98) UART Serial Mode Select Bits. These bits select the serial port operating mode as follows: SM0 SM1 Selected Operating Mode. 0 0 Mode 0: Shift register, fixed baud rate (F core/12). 0 1 Mode 1: 8-bit UART, variable baud rate. 1 0 Mode 2: 9-bit UART, fixed baud rate (F core/32) or (Fcore/16). 7-6 0x9F, 0x9E SM0, SM1 1 1 Mode 3: 9-bit UART, variable baud rate. 5 0x9D SM2 0 Multiprocessor Communication Enable Bit. Enables multiprocessor communication in Modes 2 and 3 and framing error detection in Mode 1. In Mode 0, SM2 should be cleared. In Mode 1, if SM2 is set, RI is not activated if a valid stop bit was not received. If SM2 is

ADE75xx/ADE71xx Preliminary Technical Data Rev. PrE | Page 124 of 148 cleared, RI is set as soon as the byte of data is received. In Modes 2 or 3, if SM2 is set, RI is not activated if the received ninth data bit in RB8 is 0. If SM2 is cleared, RI is set as soon as the byte of data is received. 4 0x9C REN 0 Serial Port Receive Enable Bit. Set by user software to enable serial port reception. Cleared by user software to disable serial port reception. 3 0x9B TB8 0 Serial Port Transmit (Bit 9). The data loaded into TB8 is the ninth data bit transmitted in Modes 2 and 3. 2 0x9A RB8 0 Serial Port Receiver Bit 9. The ninth data bit received in Modes 2 and 3 is latched into RB8. For Mode 1, the stop bit is latched into RB8. 1 0x99 TI 0 Serial Port Transmit Interrupt Flag. Set by hardware at the end of the eighth bit in Mode 0, or at the beginning of the stop bit in Modes 1, 2, and 3. TI must be cleared by user software. 0 0x98 RI 0 Serial Port Receive Interrupt Flag. Set by hardware at the end of the eighth bit in Mode 0, or halfway through the stop bit in Modes 1, 2, and 3. RI must be cleared by user software. Table 123. Serial port Buffer SFR (SBUF, 0x99) 7-0 SBUF 0 Serial port data buffer Table 124. Enhanced Serial baud rate control SFR (SBAUDT, 0x9E) 7 OWE 0 Overwrite Error. This bit is set when new data is received and RI=1. It indicates that SBUF was not read before the next character was transferred in, causing the prior SBUF data to be lost. Write a zero to this bit to clear it.. 6 FE 0 Frame Error. This bit is set when the received frame did not have a valid stop bit. This bit is read only and updated every time a frame is received. 5 BE 0 Break Error. This bit is set whenever the receive data line (Rx) is low for longer than a full transmission frame, the time required for a start bit, 8 data bits, a parity bit and half a stop bit. This bit is updated every time a frame is received. 4-3 SBTH1, SBTH0 0 Extended divider rati o for baud rate setting as shown in Table 126 2, 1, 0 DIV2, DIV1, DIV0

0 Binary Divider

0 0 0 Divide by 1. See Table 126. 0 0 1 Divide by 2. See Table 126. 0 1 0 Divide by 4. See Table 126. 0 1 1 Divide by 8. See Table 126. 1 0 0 Divide by 16. See Table 126. 1 0 1 Divide by 32. See Table 126. 1 1 0 Divide by 64. See Table 126.

1 1 1 Divide by 128. See Table 126. Table 125. UART Timer Fractional Divider SFR (SBAUDF, 0x9D)

7 UARTBAUDEN 0 UART Baud Rate Enable

6 ---- Not Implemented. Write Don’t Care. 5 SBAUDF.5 0 UART Timer Fractional Divider Bit 5. 4 SBAUDF.4 0 UART Timer Fractional Divider Bit 4. 3 SBAUDF.3 0 UART Timer Fractional Divider Bit 3. 2 SBAUDF.2 0 UART Timer Fractional Divider Bit 2. 1 SBAUDF.1 0 UART Timer Fractional Divider Bit 1. 0 SBAUDF.0 0 UART Timer Fractional Divider Bit 0. Table 126. Common Baud Rates Using UART Timer with a 4.096 MHz FLL Clock

Preliminary Technical Data ADE75xx/ADE71xx Rev. PrE | Page 127 of 148 To us e t he 9th data bit as part of a communication protocol for a multiprocessor network such as RS-485, the 9th bit is set to indicate that the frame contains the address of the device that the master would like to communicate with. The devices on the network are always listening for a packet with the 9th bit set and are configured such that if the 9th bit is clear, the frame will not be valid and a receive interrupt will not be generated. If the 9th bit is set, all of the devices on the network will receive the address and get a receive character interrupt. The devices will examine the address and if it matches a device’s preprogrammed address, the device will configure itself to listen to all incoming frames, even those with the 9 th bit clear. Since the master has initiated communication with that device, all the following packets with the 9th bit clear are intended specifically for the addressed device until another packet with the 9th bit set is received. If the address does not match, the device will continue listening for address packets. T o transmit, the 8 data bits must be written into SBUF . The ninth bit must be written to TB8 in SCON. When transmission is initiated, the 8 data bits from SBUF are loaded into the transmit shift register (LSB first). The 9th data bit, held in TB8, is loaded into the 9th bit position of the transmit shift register. The transmission starts at the next valid baud rate clock. The transmit interrupt flag, TI, is set as soon as the transmission has completed, when the stop bit appears on TxD. All of the following conditions must be met at the time the final shift pulse is generated to receive a character:

• If the extended UART is disabled (EXTEN=0 in the CFG SFR), RI must be zero to receive a character. This ensures that the data in SBUF will not be overwritten if the last received character has not been read.
• If multiprocessor communication is enabled by setting SM2, the received 9th bit must be set to receive a character. This ensures that only frames with the 9th bit set, frames that contain addresses, generate a receive interrupt. If any of these conditions are not met, the received frame is irretrievably lost, and the receive interrupt flag, RI, is not set. Reception for Mode 2 is similar to that of Mode 1. The 8 data bytes are input at RxD (LSB first) and loaded onto the receive shift register. If the received frame has met the above criteria, the following events occur:
• The 8 bits in the receive shift register are latched into SBUF.
• The 9th data bit is latched into RB8 in SCON.
• The receiver interrupt flag (RI) is set. Mode 3 (9-Bit UART with Variable Baud Rate) Mode 3 is selected by setting both SM0 and SM1. In this mode, the 8051 UART serial port operates in 9-bit mode with a variable baud rate. The baud rate is set by a timer overflow rate. Timer 1 or Timer 2 can be used to generate baud rates or both timers can be used simultaneously where one generates the transmit rate and the other generates the receive rate. There is also a dedicated timer for baud rate generation, UART Timer, which has a fractional divisor to precisely generate any baud rate—see the UART Timer Generated Baud Rates section. The operation of the 9-bit UART is the same as for Mode 2, but the baud rate can be varied. In all four modes, transmission is initiated by any instruction that uses SBUF as a destination register. Reception is initiated in Mode 0 when RI = 0 and REN = 1. Reception is initiated in the other modes by the incoming start bit if REN = 1. UART BAUD RATE GENERATION Mode 0 Baud Rate Generation The baud rate in Mode 0 is fixed: Mode 0 Baud Rate = ⎟ coreF Mode 2 Baud Rate Generation The baud rate in Mode 2 depends on the value of the SMOD bit in the PCON SFR. If SMOD = 0, the baud rate is 1/32 of the core clock. If SMOD = 1, the baud rate is 1/16 of the core clock: Mode 2 Baud Rate = 32 2SMOD × Fcore Modes 1 and 3 Baud Rate Generation The baud rates in Modes 1 and 3 are determined by the overflow rate of the timer generating the baud rate: either Timer 1 or Timer 2 or the dedicated baud rate generator, UART Timer, which has an integer and fractional divisor. Timer 1 Generated Baud Rates When Timer 1 is used as the baud rate generator, the baud rates in Modes 1 and 3 are determined by the Timer 1 overflow rate and the value of SMOD as follows: Modes 1 and 3 Baud Rate = 2SMOD × Timer 1 Overflow Rate The Timer 1 interrupt should be disabled in this application. The timer itself can be configured for either timer or counter operation, and in any of its three running modes. In the most typical application, it is configured for timer operation in autoreload mode (high nibble of TMOD = 0010 binary). In that case, the baud rate is given by the formula Modes 1 and 3 Baud Rate = )1256(32 TH Fcore SMOD Timer 2 Generated Baud Rates Baud rates can also be generated by using Timer 2. Using Timer 2 is similar to using Timer 1 in that the timer must overflow 16 times before a bit is transmitted or received. Because Timer 2

Preliminary Technical Data ADE75xx/ADE71xx Rev. PrE | Page 129 of 148 The appropriate value to write to the DIV[2:0] and SBTH[1:0] bits can be calculated using the following formula where Fcore is defined in POWCON SFR. Note that the DIV value must be rounded down to the nearest integer. DIV+ SBTH = ()2log 16log ⎟⎟ × RateBaud Fcore SBAUDF is the fractional divider ratio required to achieve the required baud rate. The appropriate value for SBAUDF can be calculated with the following formula: SBAUDF = ⎛ − ∗ + 1 216 RateBaud F SBTHDIV core Note that SBAUDF should be rounded to the nearest integer. Once the values for DIV and SBAUDF are calculated, the actual baud rate can be calculated with the following formula: Actual Baud Rate = ⎛ +⋅⋅ +

641216 SBAUDF

F SBTHDIV core For example, to get a baud rate of 9600 while operating at a core clock frequency of 4.096 MHz, with the PLL CD bits equal to zero, DIV + SBTH = log(4096000/(16 × 9600))/log2 = 4.74 = 4 Note that the DIV result is rounded down. Therefore, the actual baud rate is 9570 bps, which gives an error of 0.31%. UART ADDITIONAL FEATURES Enhanced Error Checking The extended UART provides frame error, break error and overwrite error detection. Framing errors occur when a stop bit is not present at the end of the frame. A missing stop bit implies that the data in the frame may not have been received properly. Break error detection indicates if the Rx line has been low for longer than a 9-bit frame. It indicates that the data just received, a zero, or NUL character, is not valid because the master has disconnected. Overwrite error detection indicates if the received data isn’t read fast enough and as result, a byte of data has been lost. The 8052 standard UART offers frame error checking for an 8- bit UART through the SM2 and RB8 bits. Setting the SM2 bit prevent frames without a stop bit from being received. The stop bit is latched into the RB8 bit in the SCON register. This bit can be examined to determine if a valid frame was received. The 8052 does not however, provide frame error checking for a 9-bit UART. This enhanced error checking functionality is available through the frame error bit, FE in the SBAUDT SFR. The FE bit will be set on framing errors for both 8-bit and 9-bit UARTs. RX D0 D1 D2 D3 D4 D5 D6 D7 START STOP RI FE EXTEN=1 Figure 80: UART Timing in Mode 1 RX D0 D1 D2 D3 D4 D5 D6 D7 START STOPD8 RI FE EXTEN=1 Figure 81: UART Timing in Modes 2 and 3 The 8052 standard UART does not provide break error detection. However for an 8-bit UART, it can be determined that a break error occurred if the received character is zero, a NUL character, and there was no stop bit because the RB8 bit is low. Break error detection is not possible for a 9-bit 8052 UART because the stop bit is not recorded. The ADE75XX/ADE71XX enhanced break error detection is available through the BE bit in the SBAUDT SFR. The 8052 standard UART prevents overwrite errors by not allowing a character to be received if the RI, receive interrupt flag, is set. However, it does not indicate if a character has been lost because the RI bit was set when the frame was received. The enhanced UART overwrite error detection provides this information. When the enhanced 8052 UART is enabled, a frame will be received regardless of the state of the RI flag. If RI=1 when a new byte is received, the byte in SCON is overwritten, and the overwrite error flag will be set. The overwrite error flag will be cleared when SBUF is read. The extended UART is enabled by setting the EXTEN bit in the CFG SFR. UART TxD signal modulation There is an internal 38 kHz signal which can be ORed with the UART transmit signal for use in remote control applications— see the 38 kHz Modulation section. One of the events that can wake the MCU from sleep mode is activity on the UART RX pin—see the 3.3V Peripherals and Wa keup Eve nts s e c t ion.

ADE75xx/ADE71xx Preliminary Technical Data Rev. PrE | Page 130 of 148 SERIAL PERIPHERAL INTERFACE INTERFACE (SPI) The ADE75XX/ADE71XX integrates a complete hardware serial peripheral interface on-chip. The SPI interface is full duplex so that eight bits of data are synchronously transmitted and received simultaneously. This SPI implementation is double buffered. This allows the user to read the last byte of received data while a new byte is shifted in. The next byte to be transmitted can be loaded while the current byte is shifted out. The SPI port can be configured for Master or Slave operation. The physical interface to the SPI is done via MISO (P0.3), MOSI (P0.2), SCLK (P0.4) and SS (P0.5) pins, while the firmware interface is done via the SPI Configuration Register SFR (SPIMOD1, 0xE8), SPI Configuration Register SFR (SPIMOD2, 0xE9), SPI Interrupt Status Register SFR (SPISTAT, 0xEA), SPI/I2C Transmit Buffer SFR (SPI2CTx, 0x9A) and SPI Receive Buffer SFR (SPI2CRx, 0x9B). Note that the SPI pins are shared with the I2C pins. Therefore, the user can enable only one interface at a time. The SCPS bit in the CFG SFR selects which peripheral is active. SPI SFR REGISTER LIST SFR Address Name R/W Length Default Value 0x9A SPI2CTx W 8 SPI Data out register 0x9B SPI2CRx R 8 0 SPI Data in register 0xE8 SPIMOD1 R/W 8 0x10 SPI configuration register 0xE9 SPIMOD2 R/W 8 0 SPI configuration register 0xEA SPISTAT R/W 8 0 SPI In terrupt Status register Table 127: SPI SFR register list Table 128. SPI/I2C Transmit Buffer SFR (SPI2CTx, 0x9A) 7-0 SPI2CTx 0 SPI or I2C transmit buffer When SPI2CTx SFR is written, its content is transfered to the transmit FIFO input. When a write is requested, the FIFO output is sent on the SPI or I2C bus. Table 129. SPI Receive Buffer SFR (SPI2CRx, 0x9B) 7-0 SPI2CRx 0 SPI or I2C receive buffer When SPI2CRx SFR is read, one byte from the Receive FIFO output is transfered to SPI2CRx SFR. A new data from the SPI or I2C bus is written to the FIFO input. Table 130. SPI Configuration Register SFR (SPIMOD1, 0xE8) 7-5 0xEF – 0xEE Reserved 0 Reserved 5 0xED INTMOD 0 SPI Interrupt mode 0: SPI Interrupt set when SPI Rx buffer full 1: SPI interrupt set when SPI Tx buffer empty 0xEC Master Mode: SS output control. See Figure 82. 0 The SS is held low while this bit is clear. This allows manual chip select control using the SS pin. Single Byte Read or Write: The SS will go low during a single byte transmission and then return high. AUTO_SS 1 Continuous Transfer: The SS will go low during the duration of the multi- byte continuous transfer and then return high. 3 0xEB SSE 0 Slave Mode: SS input enable

Preliminary Technical Data ADE75xx/ADE71xx Rev. PrE | Page 131 of 148 When this bit is set to logic one, the SS pin is defined as the Slave Select input pin for the SPI slave interface 0xEA Receive buffer overflow write enable

0 If the SPI2CRX SFR has not been read when a new data byte is

received, the new byte will be discarded. RxOFW 0

1 If the SPI2CRX SFR has not been read when a new data byte is

received, the new byte will overwrite the old data. 1-0 0xE9 – 0xE8 SPIR[1:0] 0 Master Mode: SPI SCLK frequency [1:0] 00 F core / 8 = 512kHz if Fcore = 4.096MHz 01 F core / 16 = 256kHz if Fcore = 4.096MHz 10 F core / 32 = 128kHz if Fcore = 4.096MHz 11 F core / 64 = 64kHz if Fcore = 4.096MHz Table 131. SPI Configuration Register SFR (SPIMOD2, 0xE9) SPI continuous transfer mode enable bit

0 The SPI interface will stop after one byte is transferred and SS will

be deasserted. A new data transfer can be intiated after a stalled period.

7 SPICONT 0

1 The SPI interface will continue transferring data until no valid data is

availbale in the SPI2CTx SFR. SS will remain asserted until SPI2CTx SFR and the transmit shift register is empty. SPI interface enable bit 0 The SPI interface is disabled.

6 SPIEN 0

1 The SPI interface is enabled

SPI Open Drain Outputs configuration bit

0 Internal pull-up resistors ar e connected to the SPI outputs

5 SPIODO 0

1 The SPI outputs are open-drain and need external pull-up resistors

SPI Master Mode enable bit

0 The SPI interface is defined as a Slave

4 SPIMS_b 0

1 The SPI interface is defined as a Master

SPI clock polarity configuration bit – see Figure 84. 0 The default state of SCLK is low and the first SCLK edge is rising. Depending on SPICPHA bit, the SPI data output changes state on the falling or rising edge of SCLK while the SPI data input is sampled on the rising or falling edge of SCLK.

3 SPICPOL 0

1 The default state of SCLK is high and the first SCLK edge is falling. Depending on SPICPHA bit, the SPI data output changes state on the rising or falling edge of SCLK while the SPI data input is sampled on the falling or rising edge of SCLK. SPI clock phase configuration bit – see Figure 84.

0 The SPI data output changes state when SS goes low, at the second

edge of SCLK and then every two subsequent edges while the SPI data input is sampled at the first SCLK edge and then every two subsequent edges.

2 SPICPHA 0

1 The SPI data output changes state at the first edge of SCLK and then

every two subsequent edges while the SPI data input is sampled at the second SCLK edge and then every two subsequent edges.

1 SPILSBF 0 Master Mode: LSB first configuration bit

ADE75xx/ADE71xx Preliminary Technical Data Rev. PrE | Page 132 of 148

0 The MSB of the SPI outp uts is transmitted first

1 The LSB of the SPI outp uts is transmitted first

0 Reserved 1 This bit must be kept as 1. Table 132. SPI Interrupt Status Register SFR (SPISTAT, 0xEA)

0 The SPI peripheral is idle

7 BUSY 0

1 The SPI peripheral is busy transferring data in slave or master mode. SPI Multi-Master Error Flag 0 A multiple master error has not occurred.

6 MMERR 0

1 If the SS_EN bit is set, enabling the Slave Select input and the SS is asserted

while the SPI peripheral is transferring data as a master, then this flag is raised to indicate the error. Write a zero to this bit to clear it.. SPI Receive Overflow Error Flag. Reading the SPI2CRx SFR will clear this bit. SPIRxOF

0 The SPI2CRX register contains valid data

5 SPIRxOF 0

1 This bit is set if the SPI2CRX register is not read before the end of the

next byte transfer. If the RxOF_EN bit is set and this condition occurs, SPI2CRX will be overwritten.

4 Reserved Reserved

3 SPIRxBF 0 Status bit for SPI Rx buffer. When set the Rx FIFO is full. Reading the SPI2CRx SFR will clear this bit. 2 SPITxUF 0 Status bit for SPI Tx buffer. When set the Tx FIFO is underflowing and data can be write into SPI2CTx. Write a zero to this bit to clear it. SPI Transmit Interrupt Flag. SPITxIRQ 0 The SPI2CTX register is full.

1 SPITxIRQ 0

1 This bit is set when the SPI2CTX register is empty. If the SPI/I2C interrupt is enabled, an interrupt will be generated when this bit is set. If new data isn’t written into the SPI2CTX SFR before the end of the current byte transfer, the transfer will stop and the SS will be deasserted. Write a zero to this bit to clear it.. 0 SPITxBF 0 Status bit for SPI Tx buffer. When set, the SPI Tx buffer is full. Write a zero to this bit to clear it.. SPI PINS MISO (Master In, Slave Out Data I/O Pin) The MISO pin is configured as an input line in master mode and as an output line in slave mode. The MISO line on the master (data in) should be connected to the MISO line in the slave device (data out).The data is transferred as byte-wide (8- bit) serial data, MSB first. MOSI (Master Out, Slave In Pin) The MOSI pin is configured as an output line in master mode and as an input line in slave mode. The MOSI line on the master (data out) should be connected to the MOSI line in the slave device (data in).The data is transferred as byte-wide (8-bit) serial data, MSB first. SCLK (Serial Clock I/O Pin) The master serial clock (SCLK) is used to synchronize the data being transmitted and received through the MOSI and MISO data lines. The SCLK pin is configured as an output in master mode and as an input in slave mode. In master mode, the bit rate, polarity, and phase of the clock are controlled by the SPI Configuration Register SFR (SPIMOD1, 0xE8) and SPI Configuration Register SFR (SPIMOD2, 0xE9). In slave mode, the SPI Configuration Register SFR (SPIMOD2, 0xE9) must be configured with the phase and polarity of the expected input clock. In both master and slave modes, the data is transmitted on one edge of the SCLK signal and sampled on the other. It is

same for the master and slave devices. deselect the slave device after the transfer is complete. should be generated with general I/O pins. single byte read and a single byte write function. these events will take place automatically. Table 133. Procedures for using SPI as a Master continue until the SPI2CTX register and transmit shift registers are empty. mode is not used, a short delay is inserted between transfers.

Figure 84. SPI timing configurations

Preliminary Technical Data ADE75xx/ADE71xx Rev. PrE | Page 136 of 148 I2C COMPATIBLE INTERFACE The ADE75XX/ADE71XX supports a fully licensed* I2C interface. The I2C interface is implemented as a full hardware master. SDATA is the data I/O pin, and SCLK is the serial clock. These two pins are shared with the MOSI and SCLK pins of the on- chip SPI interface. Therefore, the user can enable only one interface or the other on these pins at any given time. The SCPS bit in the CFG SFR selects which peripheral is active. The two pins used for data transfer, SDA and SCL are configured in a Wired-AND format that allows arbitration in a multi-master system. The transfer sequence of a I2C system consists of a master device initiating a transfer by generating a START condition while the bus is idle. The master transmits the address of the slave device and the direction of the data transfer in the initial address transfer. If the slave acknowledges then the data transfer is initiated. This continues until the master issues a STOP condition and the bus becomes idle. SERIAL CLOCK GENERATION The I2C master in the system generates the serial clock for a transfer. The master channel can b e c o n f i g u r e d t o o p e r a t e i n Fast mode (256 kHz) or Standard mode (32 kHz). The bit-rate is defined in the I2CMODE SFR as follow: ]0:1[216 SCLDIV core SCL ff SLAVE ADDRESSES The I2CADR SFR contains the slave device ID. The LSB of this register contains a read/write re quest. A write to this SFR will start the I2C communication. I2C SFR REGISTER LIST The I2C peripheral interface consists of five SFRs: - I2CMOD - I2CSTAT - I2CADR - SPI2CTx - SPI2CRx. As the SPI and I2C serial interfaces share the same pins, I2CMOD , I2CADR, I2CSTAT, SPI2CTx and SPI2CRx SFRs are also shared wit h SPIMOD1, SPIMOD2, SPISTAT, SPI2CTx and SPI2CRx SFRs respectively. SFR Address Name R/W Length Default Value 0x9A SPI2CTx W 8 SPI Data out register 0x9B SPI2CRx R 8 0 SPI Data in register 0xE8 I2CMOD R/W 8 0 SPI configuration register 0xE9 I2CADR R/W 8 0 SPI configuration register 0xEA I2CSTAT R/W 8 0 SPI/I2C Interrupt Status register Table 134: SPI SFR register list Table 135. I2C Mode Register SFR (I2CMOD, 0xE8) 7 0xEF I2CEN 0 I2C enable bit When this bit is set to logic one, the I2C interface is enabled. A write to the I2CADR SFR will start a communication 6-5 0xEE – 0xED I2CR[1:0] 0 I2C SCLK frequency [1:0]

Preliminary Technical Data ADE75xx/ADE71xx Rev. PrE | Page 137 of 148 00 F core / 16 = 256kHz if Fcore = 4.096MHz 01 F core / 32 = 128kHz if Fcore = 4.096MHz 10 F core / 64 = 64Hz if Fcore = 4.096MHz 11 F core / 128= 32kHz if Fcore = 4.096MHz 4-0 0xEC – oxE8 I2CRCT[4:0] 0 Configures the length of the I2C received FIFO buffer. The I2C peripheral will stop when I2CRCT[4:0] + 1 bytes have been read or if an error has occured Table 136. I2C Slave Address SFR (I2CADR, 0xE9) 7-1 I2CSLVADR 0 Address of the I2C slave being adressed Writing to this register start the I2C transmission (Read or write)

0 I2CR_W 0 Command bit for Read or Write

When this bit is set to logic one, a read command will be transmitted on the I2C bus. Data from slave in SPI2CRx SFR is expected after command byte When this bit is set to logic zero, a write command will be transmitted on the I2C bus. Data to slave is expected in SPI2CTx SFR Table 137. I2C Interrupt Status Register SFR (I2CSTAT, 0xEA) 7 I2CBUSY 0 This bit is set to logic one when the I2C interface is used. When this bit is set by user code, the Tx FIFO is emptied

6 I2CNOACK 0 I2C no acknlowle dgement transmit interrupt

This bit is set to logic one when the slave device did not send an acknlowledgement. The I2C communication is stopped after this event. Write a zero to this bit to clear it.

5 I2CRxIRQ 0 I2C receive interrupt

This bit is set to logic one when the receive FIFO is not empty Write a zero to this bit to clear it.

4 I2CTxIRQ 0 I2C transmit interrupt

This bit is set to logic one when the transmit FIFO is empty Write a zero to this bit to clear it. 3-2 I2CFIFOSTAT[1:0] 0 Status bit for 3 or 4 bytes deep I2C FIFO. The FIFO monitored in these 2 bits is the one currently used in I2C communication (Receive or Transmit) as only one of them is active at a time [1:0]

00 FIFO empty

01 Reserved

10 FIFO Half full

11 FIFO Full

1 I2CACC_ERR 0 Set when trying to write and read at the same time. Write a zero to this bit to clear it. 0 I2CTxWR_ERR 0 Set when write was attempted when I2C transmit FIFO was full. Write a zero to this bit to clear it. An I2C interrupt occurs * Purchase of licensed I 2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Phi lips I 2C Patent Rights to use the ADE7XXX in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. READ AND WRITE OPERATIONS

ADE75xx/ADE71xx Preliminary Technical Data Rev. PrE | Page 138 of 148 Figure 85 and Figure 86 depict I2C read and write operations, respectively. Note that the LSB of the I2CADR register is used to select whether a read or write operation is performed on the slave device. During the read operation, the master acknowledges are generated automatically by the I2C peripheral. The master generated NACK before the end of a read operation is also generated automatically after I2CRCT[4:0] bytes have been read from the slave. If the I2CADR register is updated during a transmission, instead of generating a STOP at the end of the read or write operation, the master will generate a START condition and continue with the next communication. STOP BY MASTER SCL SDA START BY MASTER ACK BY SLAVE ACK BY MASTER FRAME 2 DATA BYTE 1 FROM SLAVE FRAME 1 SERIAL BUS ADDRESS BYTE 19 9 1 A5 A4 A3 A2 A1 A0 D6 D5 D4 D3 D2 D1 D0 R/W D7 NACK BY MASTER FRAME N+1 DATA BYTE N FROM SLAVE D6 D5 D4 D3 D2 D1 D0D7 Figure 85: I2C Read operation SCL SDA START BY MASTER ACK BY SLAVE ACK BY SLAVE FRAME 2 DATA BYTE 1 FROM MASTER FRAME 1 SERIAL BUS ADDRESS BYTE 19 9 1 A5 A4 A3 A2 A1 A0 D6 D5 D4 D3 D2 D1 D0 STOP BY MASTER R/W D7 Figure 86: I2C Write operation I2C RECEIVE AND TRANSMIT FIFOS The I2C peripheral has a four byte receive FIFO and a four byte transmit FIFO. The buffers reduce the overhead associated with using the I2C peripheral. Figure 87 shows the operation of the I2C receive and transmit FIFOs. The TX FIFO can be loaded with four bytes to be transmitted to the slave at the beginning of a write operation. When the transmit FIFO is empty, the I2C transmit interrupt flag will be set and the PC will vector to the I2C interrupt vector if this interrupt is enabled. If a new byte is not loaded into the TX FIFO before it is needed in the transmit shift register, the communication will stop. An error such as not receiving an acknowledge will also cause the communication to terminate. In case of an error during a write operation, the TX FIFO will be flushed. The RX FIFO allows four bytes to be read in from the slave before the MCU has to read the data. A receive interrupt can be generated after each byte is received or when the RX FIFO is full. If the peripheral is reading from a slave address, the communication will stop once the number of received bytes equals the number set in the I2CRCT[4:0] bits. An error such as not receiving an acknowledge will also cause the communication to terminate. I2CTX TXDATA3 TXDATA2 TXDATA1 TRANSMIT SHIFT REGISTER

4 Byte FIFO

MOV I2CTX, TXDATA1 MOV I2CTX, TXDATA2 MOV I2CTX, TXDATA3 Code to fill TX FIFO: I2CTX TXDATA3 TXDATA2 TXDATA1 TRANSMIT SHIFT REGISTER MOV I2CTX, TXDATA1 MOV I2CTX, TXDATA2 MOV I2CTX, TXDATA3 MOV I2CTX, TXDATA4 Code to fill TX FIFO: I2CRX RXDATA1 RXDATA2 RXDATA3 RXDATA4 RECEIVE SHIFT REGISTER MOV A, I2CRX ; Result: A=RXDATA1 MOV A, I2CRX ; Result: A=RXDATA2 MOV A, I2CRX ; Result: A=RXDATA3 MOV A, I2CRX ; Result: A=RXDATA4 Code to read RX FIFO: TXDATA4 Figure 87: I2C FIFO operation

Preliminary Technical Data ADE75xx/ADE71xx Rev. PrE | Page 139 of 148 DUAL DATA POINTERS The ADE75XX/ADE71XX incorporates two data pointers. The second data pointer is a shadow data pointer and is selected via the data pointer control SFR (DPCON). DPCON features automatic hardware post-increment and post-decrement as well as an automatic data pointer toggle. Table 138. Data Pointer Control SFR SFR (DPCON, 0xA7) 7 ---- 0 Not Implemented. Write Don’t Care. 6 DPT 0 Data Pointer Automatic Toggle Enable. Cleared by the user to disable auto swapping of the DPTR. Set in user software to enable automatic toggling of the DPTR after each MOVX or MOVC instruction. DP1m1, DP1m0 0 Shadow Data Pointer Mode. These bits enable extra modes of the shadow data pointer operation, allowing more compact and more efficient code size and execution. DP1m1 DP1m0 Behavior of the Shadow Data Pointer 0 0 8052 behavior. 0 1 DPTR is post-incremented after a MOVX or a MOVC instruction. 1 0 DPTR is post-decremented after a MOVX or MOVC instruction. 5, 4 1 1 DPTR LSB is toggled after a MOVX or MOVC instruction. (This instruction can be useful for moving 8-bit blocks to/from 16-bit devices.) DP0m1, DP0m0 0 Main Data Pointer Mode. These bits enable extra modes of the main data pointer operation, allowing more compact and more efficient code size and execution. DP0m1 DP0m0 Behavior of the Main Data Pointer 0 0 8052 behavior. 0 1 DPTR is post-incremented after a MOVX or a MOVC instruction. 1 0 DPTR is post-decremented after a MOVX or MOVC instruction. 3, 2 1 1 DPTR LSB is toggled after a MOVX or MOVC instruction. (This instruction is useful for moving 8-bit blocks to/from 16-bit devices.) 1 ---- 0 Not Implemented. Write Don’t Care. 0 DPSEL 0 Data Pointer Select. Cleared by the user to select the main data pointer. This means that the contents of this 16- bit register are placed into the DPL, and DPH SFRs. Set by the user to select the shadow data pointer. This means that the contents of a separate 16-bit register appear in the DPL, and DPH SFRs. Note the following: • The Dual Data Pointer section is the only place in which main and shadow data pointers are distinguished.

ADE75xx/ADE71xx Preliminary Technical Data Rev. PrE | Page 140 of 148 Whenever the DPTR is mentioned elsewhere in this data sheet, active DPTR is implied.

• Only the MOVC/MOVX @DPTR instructions automatically post-increment and post-decrement the DPTR. Other MOVC/MOVX instructions, such as MOVC PC or MOVC @Ri, do not cause the DPTR to automatically post-increment and post-decrement. To illustrate the operation of DPCON, the following code copies 256 bytes of code memory at Address D000H into XRAM, starting from Address 0000H. MOV DPTR,#0 ;Main DPTR = 0 MOV DPCON,#55H ;Select shadow DPTR ;DPTR1 increment mode ;DPTR0 increment mode ;DPTR auto toggling ON MOV DPTR,#0D000H ;DPTR = D000H MOVELOOP: CLR A MOVC A,@A+DPTR ;Get data ;Post Inc DPTR ;Swap to Main DPTR(Data) MOVX @DPTR,A ;Put ACC in XRAM ;Increment main DPTR ;Swap Shadow DPTR(Code) MOV A, DPL JNZ MOVELOOP

ADE75xx/ADE71xx Preliminary Technical Data Rev. PrE | Page 142 of 148 UART transmit signal or a low power signal to drive a LED. The modulation can be enabled or disabled with the MOD38EN bit in the CFG SFR. The 38 kHz modulation is available on eight pins, selected by the MOD38[7:0] bits in the Extended Port Configuration SFR (EPCFG, 0x9F). I/O SFR REGISTER LIST Table 140. Extended Port Configuration SFR (EPCFG, 0x9F) 7 MOD38_FP21 0 Enable 38kHz modulation on P1.6/FP21 pin 6 MOD38_FP22 0 Enable 38kHz modulation on P1.5/FP22 pin 5 MOD38_FP23 0 Enable 38kHz modulation on P1.4/FP23/T2 pin 4 MOD38_TxD 0 Enable 38kHz modulation on P1.1/Tx pin 3 MOD38_CF1 0 Enable 38kHz modulation on P0.2/CF1/RTCCAL pin 2 MOD38_SSb 0 Enable 38kHz modulation on P0.7/SS/T1pin 1 MOD38_MISO 0 Enable 38kHz modulation on P0.5/MISO pin 0 MOD38_CF2 0 Enable 38kHz modulation on P0.3/CF2 pin Table 141. Port 0 Weak pull-up enable SFR (PINMAP0, 0xB2) 7 PINMAP0.7 0 The weak pull-up on P0.7 is disabled when this bit is set 6 PINMAP0.6 0 The weak pull-up on P0.6 is disabled when this bit is set 5 PINMAP0.5 0 The weak pull-up on P0.5 is disabled when this bit is set 4 PINMAP0.4 0 The weak pull-up on P0.4 is disabled when this bit is set 3 PINMAP0.3 0 The weak pull-up on P0.3 is disabled when this bit is set 2 PINMAP0.2 0 The weak pull-up on P0.2 is disabled when this bit is set 1 PINMAP0.1 0 The weak pull-up on P0.1 is disabled when this bit is set 0 PINMAP0.0 0 The weak pull-up on P0.0 is disabled when this bit is set Table 142. Port 1 Weak pull-up enable SFR (PINMAP1, 0xB3) 7 PINMAP1.7 0 The weak pull-up on P1.7 is disabled when this bit is set 6 PINMAP1.6 0 The weak pull-up on P1.6 is disabled when this bit is set 5 PINMAP1.5 0 The weak pull-up on P1.5 is disabled when this bit is set 4 PINMAP1.4 0 The weak pull-up on P1.4 is disabled when this bit is set 3 PINMAP1.3 0 The weak pull-up on P1.3 is disabled when this bit is set 2 PINMAP1.2 0 The weak pull-up on P1.2 is disabled when this bit is set 1 PINMAP1.1 0 The weak pull-up on P1.1 is disabled when this bit is set 0 PINMAP1.0 0 The weak pull-up on P1.0 is disabled when this bit is set Table 143. Port 2 Weak pull-up enable SFR (PINMAP2, 0xB4) 7 - 6 Reserved 0 Reserved. Should be left cleared 5 PINMAP2.5 0 The weak pull-up on Rese t is disabled when this bit is set

4 Reserved 0 The weak pull-up on EA is disabled when this bit is set

3 PINMAP2.3 0 Reserved. Should be left cleared 2 PINMAP2.2 0 The weak pull-up on P2.2 is disabled when this bit is set 1 PINMAP2.1 0 The weak pull-up on P2.1 is disabled when this bit is set 0 PINMAP2.0 0 The weak pull-up on P2.0 is disabled when this bit is set

Preliminary Technical Data ADE75xx/ADE71xx Rev. PrE | Page 143 of 148 Table 144. Port 0 SFR (P0, 0x80) 7 0x87 T1 1 This bit reflects the state of P0.7/SS/T1 pin. It can be written or read. 6 0x86 T0 1 This bit reflects the state of P0 .6/SCLK/T0 pin. It can be written or read. 5 0x85 1 This bit reflects the state of P0.5/MISO pin. It can be written or read. 4 0x84 1 This bit reflects the state of P0.4 /MOSI/SDATA pin. It can be written or read. 3 0x83 CF2 1 This bit reflects the state of P0.3/CF2 pin. It can be written or read. 2 0x82 CF1 1 This bit reflects the state of P0.2 /CF1/RTCCAL pin. It can be written or read. 1 0x81 1 This bit reflects the state of P0.1 pin. It can be written or read. 0 0x80 INT1 1 This bit reflects the state of P0.0/INT1/BCTRL pin. It can be written or read. Table 145. Port 1 SFR (P1, 0x90) 7 0x97 1 This bit reflects the state of P1.7 pin. It can be written or read. 6 0x96 1 This bit reflects the state of P1.6 pin. It can be written or read. 5 0x95 1 This bit reflects the state of P1.5 pin. It can be written or read. 4 0x94 T2 1 This bit reflects the state of P1.4/T2 pin. It can be written or read. 3 0x93 T2EX 1 This bit reflects the state of P1.3/T2EX pin. It can be written or read. 2 0x92 1 This bit reflects the state of P1.2 pin. It can be written or read. 1 0x91 TxD 1 This bit reflects the state of P1.1/TxD pin. It can be written or read. 0 0x90 RxD 1 This bit reflects the state of P1.0/RxD pin. It can be written or read. Table 146. Port 2 SFR (P2, 0xA0) 7 - 2 0x97 – 0x92 0x3F These bits are unused and should be left set 1 0x91 P2.1 1 This bit reflects the state of P2.1 pin. It can be written or read. 0 0x90 P2.0 1 This bit reflects the state of P2.0 pin. It can be written or read. Interrupt pins configuration SFR (INTPR, 0xFF) Bit Location Bit Mnemonic Default Value When set, the RTC calibration frequency selected by FSEL[1:0] is output on the P0.2/CF1/RTCCAL pin. Sets RTC calibration output frequency and calibration window FSEL[1:0] Calibration window, frequency 0 0 30.5 seconds, 1Hz 0 1 30.5 seconds, 512 Hz 1 0 0.244 seconds, 500Hz 6-5 FSEL[1:0] 1 1 0.244 seconds, 16.384 kHz Controls the function of INT1 T 3-1 INT1PRG[2:0] 000 INT1PRG[2:0] Function

ADE75xx/ADE71xx Preliminary Technical Data Rev. PrE | Page 144 of 148 x 0 0 GPIO x 0 1 BCTRL 0 1 x INT1 input disabled 1 1 x INT1 input enabled Controls the function of INT0 INT0PRG Function Table 147.Table 148. Port 0 Alternate Functions Pin No. Alternate Function Alternate Function Enable BCTRL external battery control input Set INT1PROG[2:0]=X01 in the Interrupt pins configuration SFR (INTPR, 0xFF) INT1 external interrupt Set EX1 in the Interrupt Enable SFR (IE, 0xA8). P0.0 INT1 wakeup from PSM2 operating mode Set INT1PROG[2:0]=11X in the Interrupt pins configuration SFR (INTPR, 0xFF) P0.1 FP19 LCD Segment Pin Set FP19EN in the LCD Segment Enable 2 SFR (LCDSEGE2, 0xED) CF1 ADE Calibration Frequency output Clear the DISCF1 bit in the ADE energy measurement internal MODE1 register (0x0B) RTC Calibration output Select the calibration window and frequency options and then set the RTCCAL bit in the Interrupt pins configuration SFR (INTPR, 0xFF) P0.2 Note: The RTC Calibration output has priority over the CF1 output, so if the DISCF1 in the MODE1 register (0x0B) is clear and RTCCAL bit in the Interrupt pins configuration SFR (INTPR, 0xFF) is set, the P0.2/CF1/RTCCAL pin will follow the RTC Calibration output. P0.2 CF1 ADE Calibration Frequency output Clear the DISCF1 bit in the ADE energy measurement internal MODE1 register (0x0B) P0.3 CF2 ADE Calibration Frequency output Clear the DISCF2 bit in the ADE energy measurement internal MODE1 register (0x0B) MOSI SPI Data line Set the SCPS bit in the CFG SFR and set the SPIEN bit in the SPI Configuration Register SFR (SPIMOD1, 0xE8). P0.4 SDATA I2C Data line Clear the SCPS bit in the Configuration SFR (CFG, 0xAF) and set the I2CEN bit in the I2C Mode Register SFR (I2CMOD, 0xE8). P0.5 MISO SPI Data line Set the SCPS bit in the Configuration SFR (CFG, 0xAF) and set the SPIEN bit in the SPI Configuration Register SFR (SPIMOD2, 0xE9) SCLK serial clock for I2C or SPI Set the I2CEN bit in the I2CMOD SFR or the SPIEN bit in the SPI Configuration Register SFR (SPIMOD2, 0xE9) to enable the I 2C or SPI interface P0.6 T0 Timer0 input Set the CNT0 bit in the Timer/Counter 0 and 1 Mode SFR (TMOD, 0x89) to enable T0 as an external event counter SS SPI slave select input for SPI in slave mode Set the SS_EN bit in the SPI Configuration Register SFR (SPIMOD1, 0xE8) SS SPI slave select output for SPI in master mode Set the SPIMS_b bit in the SPI Configuration Register SFR (SPIMOD2, 0xE9) P0.7 T1 Timer 1 input Set the CNT1 bit in the Timer/Counter 0 and 1 Mode SFR (TMOD, 0x89) to enable T1 as an external event counter

Preliminary Technical Data ADE75xx/ADE71xx Rev. PrE | Page 145 of 148 Table 149. Port 1 Alternate Functions Table 150. Port 2 Alternate Functions P2.3 SDEN Serial Download pin sampled on reset. When set, the RTC calibration frequency selected by FSEL[1:0] is output on the P0.2/CF1/RTCCAL pin. Sets RTC calibration output frequency and calibration window FSEL[1:0] Calibration window, frequency 0 0 30.5 seconds, 1Hz 0 1 30.5 seconds, 512 Hz 1 0 0.244 seconds, 500Hz 6-5 FSEL[1:0] 1 1 0.244 seconds, 16.384 kHz Controls the function of T INT1PRG[2:0] Function 3-1 INT1PRG[2:0] 000 x 0 0 GPIO

Table 147.Table 148. The alternate functions of Port 0 pins can be activated only if the corresponding bit latch in the P0 SFR contains a 1. Otherwise, the port pin remains at 0. pull-up by writing a one to P1CFG..x. the corresponding bit latch in the P1 SFR contains a 1. Otherwise, the port pin remains at 0. enabled by default. Disable the weak internal pull-up by writing a one to P2CFG..x. Table 150. The alternate functions of Port 2 pins can be activated only if the corresponding bit latch in the P2 SFR contains a 1. Otherwise, the port pin remains at 0.

Preliminary Technical Data ADE75xx/ADE71xx Rev. PrE | Page 147 of 148 OUTLINE DIMENSIONS LQFP package LFCSP package17 Dimensions shown in millimeters

17 Please contact your Analog Devices representative to check availability of this package

Table 151. Selection Guide Table 152. Ordering Guide

1 Please contact your Analog Devices representative to check availability of this package

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