ADE7169

ADE7169_15 AD | Alldatasheet

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license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2007–2008 Analog Devices, Inc. All rights reserved. Table 1. Features Available on Each Part 1 Not available in the ADE7116. 2 Not available in the ADE7116 or ADE7156.

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Rev. B | Page 2 of 152 TABLE OF CONTENTS Performance Curves for the ADE7169 and ADE7569 Only 25 di/dt Current Sensor and Digital Integrator for the

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Rev. B | Page 3 of 152

REVISION HISTORY

11/08—Rev. A to Rev. B 12/07—Rev. 0 to Rev. A 11/07—Revision 0: Initial Version

LCD display in a single part. measurement DSP to simplify energy meter design. voltages capable of driving LCDs up to 5 V .

256 BYTES

Figure 1. ADE7566/ADE7569 Functional Block Diagram

1 FP27

Figure 2. ADE7116/ADE7156/ADE7166/ADE7169 Functional Block Diagram

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Rev. B | Page 6 of 152 SPECIFICATIONS VDD = 3.3 V ± 5%, AGND = DGND = 0 V , on-chip reference XTALx = 32.768 kHz, TMIN to TMAX = −40°C to +85°C, unless otherwise noted. ENERGY METERING Table 2. Parameter Min Typ Max Unit Test Conditions/Comments MEASUREMENT ACCURACY1 Phase Error Between Channels2 PF = 0.8 Capacitive ±0.05 Degrees Phase lead: 37° PF = 0.5 Inductive ±0.05 Degrees Phase lag: 60° Active Energy Measurement Error2 0.1 % of reading Over a dynamic range of 1000 to 1 at 25°C AC Power Supply Rejection2 VDD = 3.3 V + 100 mV rms/120 Hz Output Frequency Variation 0.01 % IPx = VP = ±100 mV rms DC Power Supply Rejection2 VDD = 3.3 V ± 117 mV dc Output Frequency Variation 0.01 % Active Energy Measurement Bandwidth1 8 kHz Reactive Energy Measurement Error2, 3 0.5 % of reading Over a dynamic range of 1000 to 1 at 25°C Vrms Measurement Error2 0.5 % of reading Over a dynamic range of 100 to 1 at 25°C Vrms Measurement Bandwidth1 3.9 kHz Irms Measurement Error2 0.5 % of reading Over a dynamic range of 500 to 1 at 25°C Irms Measurement Bandwidth1 3.9 kHz ANALOG INPUTS Maximum Signal Levels ±400 mV peak VP − VN differential input ADE7566/ADE7569 ±400 mV peak IP − IN differential input ADE7116/ADE7156/ADE7166/ADE7169 ±250 mV peak IPA − IN and IPB − IN differential inputs Input Impedance (DC) 770 kΩ ADC Offset Error2 ±10 mV PGA1 = PGA2 = 1 ±1 mV PGA1 = 16 Gain Error2 Current Channel ±3 % IPA = IPB = 0.4 V dc or IP = 0.4 V dc Voltage Channel ±3 +3 % VP − VN = 0.4 V dc Gain Error Match ±0.2 % CF1 AND CF2 PULSE OUTPUT Maximum Output Frequency 13.5 kHz VP − VN = 400 mV peak, IPA − IN = 250 mV, PGA1 = 2 sine wave Duty Cycle 50 % If CF1 or CF2 frequency, >5.55 Hz Active High Pulse Width 90 ms If CF1 or CF2 frequency, <5.55 Hz FAULT DETEC TION4 Fault Detection Threshold Inactive Input ≠ Active Input 6.25 % of active IPA or IPB active Input Swap Threshold Inactive Input > Active Input 6.25 % of active IPA or IPB active Accuracy Fault Mode Operation IPA Active, IPB = AGND 0.1 % of reading Over a dynamic range of 500 to 1 IPB Active, IPA = AGND 0.1 % of reading Over a dynamic range of 500 to 1 Fault Detection Delay 3 Seconds Swap Delay 3 Seconds 1 These specifications are not production tested but are guaranteed by design and/or characterization data on production release. 2 See the Terminology section for definition. 3 This function is not available in the ADE7166 or ADE7566. 4 This function is not available in the ADE7566 or ADE7569.

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Rev. B | Page 7 of 152 ANALOG PERIPHERALS Table 3. Parameter Min Typ Max Unit Test Conditions/Comments INTERNAL ADCs (BATTERY, TEMPERATURE, VDCIN)1 Power Supply Operating Range 2.4 3.7 V Measured on VSWOUT No Missing Codes2 8 Bits Conversion Delay3 38 μs ADC Gain VDCIN Measurement 15.3 mV/LSB VBAT Measurement 14.6 mV/LSB Temperature Measurement 0.78 °C/LSB ADC Offset VDCIN Measurement at 3 V 206 LSB VBAT Measurement at 3.7 V 205 LSB Temperature Measurement at 25°C 129 LSB VDCIN Analog Input Maximum Signal Levels 0 3.3 V Input Impedance (DC) 1 MΩ Low VDCIN Detection Threshold 1.09 1.2 1.27 V POWER-ON RESET (POR) VDD POR Detection Threshold 2.5 2.95 V POR Active Timeout Period 33 ms VSWOUT POR Detection Threshold 1.8 2.2 V POR Active Timeout Period 20 ms VINTD POR Detection Threshold 2.0 2.25 V POR Active Timeout Period 16 ms VINTA POR Detection Threshold 2.05 2.25 V POR Active Timeout Period 120 ms BATTERY SWITCHOVER Voltage Operating Range (VSWOUT) 2.4 3.7 V VDD to VBAT Switching Switching Threshold (VDD) 2.5 2.95 V Switching Delay 10 ns When VDD to VBAT switch activated by VDD 30 ms When VDD to VBAT switch activated by VDCIN VBAT to VDD Switching Switching Threshold (VDD) 2.5 2.95 V Switching Delay 30 ms Based on VDD > 2.75 V VSWOUT to VBAT Leakage Current 10 nA VBAT = 0 V, VSWOUT = 3.43 V, TA = 25°C LCD, CHARGE PUMP ACTIVE4 Charge Pump Capacitance Between LCDVP1 and LCDVP2 100 nF LCDVA, LCDVB, LCDVC Decoupling Capacitance 470 nF LCDVA 0 1.75 V LCDVB 0 3.5 V 1/3 bias mode LCDVC 0 5.3 V 1/3 bias mode V1 Segment Line Voltage LCDVA − 0.1 LCDVA V Current on segment line = −2 μA V2 Segment Line Voltage LCDVB − 0.1 LCDVB V Current on segment line = −2 μA V3 Segment Line Voltage LCDVC − 0.1 LCDVC V Current on segment line = −2 μA DC Voltage Across Segment and COMx Pin 50 mV LCDVC − LCDVB, LCDVC − LCDVA, or LCDVB − LCDVA

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Rev. B | Page 8 of 152 Parameter Min Typ Max Unit Test Conditions/Comments LCD, RESISTOR LADDER ACTIVE Leakage Current ±20 nA 1/2 and 1/3 bias modes, no load V1 Segment Line Voltage LCDVA − 0.1 LCDVA V Current on segment line = −2 μA V2 Segment Line Voltage LCDVB − 0.1 LCDVB V Current on segment line = −2 μA V3 Segment Line Voltage LCDVC − 0.1 LCDVC V Current on segment line = −2 μA ON-CHIP REFERENCE Reference Error ±0.9 mV TA = 25°C Power Supply Rejection 80 dB Temperature Coefficient2 10 50 ppm/°C 1 This function is not available in the ADE7116. 2 These specifications are not production tested but are guaranteed by design and/or characterization data on production release. 3 Delay between ADC conversion request and interrupt set. 4 This function is not available in the ADE7116 or ADE7156. DIGITAL INTERFACE Table 4. Parameter Min Typ Max Unit Test Conditions/Comments LOGIC INPUTS1 All Inputs Except XTAL1, XTAL2, BCTRL, INT0, INT1, RESET Input High Voltage, VINH 2.0 V Input Low Voltage, VINL 0.8 V BCTRL, INT0, INT1, RESET Input High Voltage, VINH 1.3 V Input Low Voltage, VINL 0.8 V Input Currents RESET 100 nA RESET = VSWOUT = 3.3 V Port 0, Port 1, Port 2 ±100 nA Internal pull-up disabled, input = 0 V or VSWOUT −3.75 −8.5 μA Internal pull-up enabled, input = 0 V, VSWOUT = 3.3 V Input Capacitance 10 pF All digital inputs FLASH MEMORY Endurance2 20,000 Cycles Data Retention3 20 Years TJ = 85°C CRYSTAL OSCILLATOR4 Crystal Equivalent Series Resistance 30 50 kΩ Crystal Frequency 32 32.768 33.5 kHz XTAL1 Input Capacitance 12 pF XTAL2 Output Capacitance 12 pF MCU CLOCK RATE (fCORE) 4.096 MHz Crystal = 32.768 kHz and CD bits = 000 32 kHz Crystal = 32.768 kHz and CD bits = 111 LOGIC OUTPUTS Output High Voltage, VOH 2.4 V VDD = 3.3 V ± 5% ISOURCE 80 μA Output Low Voltage, VOL5 0.4 V VDD = 3.3 V ± 5% ISINK 2 m A START-UP TIME6 PSM0 Power-On Time 880 ms VDD at 2.75 V to PSM0 code execution From Power Saving Mode 1 (PSM1) PSM1 to PSM0 130 ms V DD at 2.75 V to PSM0 code execution From Power Saving Mode 2 (PSM2) PSM2 to PSM1 48 ms Wake-up event to PSM1 code execution PSM2 to PSM0 186 ms V DD at 2.75 V to PSM0 code execution

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Rev. B | Page 9 of 152 Parameter Min Typ Max Unit Test Conditions/Comments POWER SUPPLY INPUTS VDD 3.13 3.3 3.46 V VBAT 2.4 3.3 3.7 V INTERNAL POWER SUPPLY SWITCH (VSWOUT) VBAT to VSWOUT On Resistance 22 Ω VBAT = 2.4 V VDD to VSWOUT On Resistance 10.2 Ω VDD = 3.13 V VBAT to/from VDD Switching Open Time 40 ns BCTRL State Change and Switch Delay 18 μs VSWOUT Output Current Drive 6 mA POWER SUPPLY OUTPUTS VINTA 2.3 2.70 V VINTD 2.3 2.70 V VINTA Power Supply Rejection 60 dB VINTD Power Supply Rejection 50 dB POWER SUPPLY CURRENTS Current in Normal Mode (PSM0) 4 5.3 mA fCORE = 4.096 MHz, LCD and meter active 2.1 mA fCORE = 1.024 MHz, LCD and meter active 1.6 mA fCORE = 32.768 kHz, LCD and meter active 3 3.9 mA fCORE = 4.096 MHz, metering ADC and DSP powered down Current in PSM1 3.2 5.05 mA fCORE = 4.096 MHz, LCD active, VBAT = 3.7 V 880 μA fCORE = 1.024 MHz, LCD active Current in PSM2 38 μA LCD active with charge pump at 3.3 V + RTC, VBAT = 3.3 V 1.5 μA RTC only, TA = 25°C, VBAT = 3.3 V 1 Specifications guaranteed by design. 2 Endurance is qualified as per JEDEC Standard 22 Method A117 and measured at −40°C, +25°C, +85°C, and +125°C. 3 Retention lifetime equivalent at junction temperature (TJ) = 85°C as per JEDEC Standard 22 Method A117. Retention lifetime derates with junction temperature. 4 Recommended crystal specifications. 5 Test carried out with all the I/Os set to a low output level. 6 Delay between power supply valid and execution of first instruction by 8052 core.

Table 7. SPI Master Mode Timing (SPICPHA = 1) Parameters 1 tCORE depends on the clock divider or CD[2:0] bits of the POWCON SFR, Address 0xC5 (see Table 26); tCORE = 2CD/4.096 MHz. Figure 5. SPI Master Mode Timing (SPICPHA = 1)

Table 8. SPI Master Mode Timing (SPICPHA = 0) Parameters 1 tCORE depends on the clock divider or CD[2:0] bits of the POWCON SFR, Address 0xC5 (see Table 26); tCORE = 2CD/4.096 MHz. Figure 6. SPI Master Mode Timing (SPICPHA = 0)

Table 9. SPI Slave Mode Timing (SPICPHA = 1) Parameters 1 tCORE depends on the clock divider or CD[2:0] bits of the POWCON SFR, Address 0xC5 (see Table 26); tCORE = 2CD/4.096 MHz. Figure 7. SPI Slave Mode Timing (SPICPHA = 1)

Table 10. SPI Slave Mode Timing (SPICPHA = 0) Parameters 1 tCORE depends on the clock divider or CD[2:0] bits of the POWCON SFR, Address 0xC5 (see Table 26); tCORE = 2CD/4.096 MHz. Figure 8. SPI Slave Mode Timing (SPICPHA = 0)

TA = 25°C, unless otherwise noted. 1 When used with external resistor divider. soldered in a circuit board for surface-mount packages. Table 12. Thermal Resistance

1. IT IS RECOMMENDED THAT THE EXPOSED PAD ON THE BOTTOM OF THE LFCSP BE

CONNECTED TO THE GROUND PLANE ON THE BOARD. Figure 9. Pin Configuration for the ADE7566/ADE7569 Table 13. Pin Function Descriptions 1 COM3/FP27 Common Output 3/LCD Segment Output 27. COM3 is used for the LCD backplane. 2 COM2/FP28 Common Output 2/LCD Segment Output 28. COM2 is used for the LCD backplane. 3 COM1 Common Output 1. COM1 is used for the LCD backplane. 4 COM0 Common Output 0. COM0 is used for the LCD backplane. 5 P1.2/FP25 General-Purpose Digital I/O Port 1.2/LCD Segment Output 25. 6 P1.3/T2EX/FP24 General-Purpose Digital I/O Port 1.3/Timer 2 Control Input/LCD Segment Output 24. 7 P1.4/T2/FP23 General-Purpose Digital I/O Port 1.4/Timer 2 Input/LCD Segment Output 23. 8 P1.5/FP22 General-Purpose Digital I/O Port 1.5/LCD Segment Output 22. 9 P1.6/FP21 General-Purpose Digital I/O Port 1.6/LCD Segment Output 21. 10 P1.7/FP20 General-Purpose Digital I/O Port 1.7/LCD Segment Output 20. 11 P0.1/FP19 General-Purpose Digital I/O Port 0.1/LCD Segment Output 19. 12 P2.0/FP18 General-Purpose Digital I/O Port 2.0/LCD Segment Output 18. 13 P2.1/FP17 General-Purpose Digital I/O Port 2.1/LCD Segment Output 17. 14 P2.2/FP16 General-Purpose Digital I/O Port 2.2/LCD Segment Output 16. LCDVB and LCDVA are internally connected (see the LCD Driver section).

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Rev. B | Page 17 of 152 Pin No. Mnemonic Description 18 LCDVA This pin can be either an analog input when the LCD resistor driver is enabled or an analog output when the LCD charge pump is enabled. When this pin is an analog output, it should be decoupled with a 470 nF capacitor. When this pin is an analog input, a resistor should be connected between this pin and LCDVP1 to generate an intermediate voltage for the LCD driver. In 1/3 bias LCD mode, another resistor must be connected between this pin and LCDVB to generate another intermediate voltage. In 1/2 bias LCD mode, LCDVA and LCDVB are internally connected (see the LCD Driver section). 19 LCDVP1 This pin can be either an analog input when the LCD resistor driver is enabled or an analog output when the LCD charge pump is enabled. When this pin is an analog output, a 100 nF capacitor should be connected between this pin and LCDVP2. When this pin is an analog input, a resistor should be connected between this pin and LCDVA to generate an intermediate voltage for the LCD driver. Another resistor must be connected between LCDVP1 and DGND to generate another intermediate voltage (see the LCD Driver section). 20 to 35 FP15 to FP0 LCD Segment Output 15 to LCD Segment Output 0. 36 P1.1/TxD General-Purpose Digital I/O Port 1.1/Transmitter Data Output (Asynchronous). 37 P1.0/RxD General-Purpose Digital I/O Port 1.0/Receiver Data Input (Asynchronous). 38 P0.7/SS/T1 General-Purpose Digital I/O Port 0.7/Slave Select When SPI Is in Slave Mode/Timer 1 Input. 39 P0.6/SCLK/T0 General-Purpose Digital I/O Port 0.6/Clock Output for I2C or SPI Port/Timer 0 Input. 40 P0.5/MISO General-Purpose Digital I/O Port 0.5/Data Input for SPI Port. 41 P0.4/MOSI/SDATA General-Purpose Digital I/O Port 0.4/Data Output for SPI Port/I2C-Compatible Data Line. 42 P0.3/CF2 General-Purpose Digital I/O Port 0.3/Calibration Frequency Logic Output 2. The CF2 logic output gives instantaneous active, reactive, I rms, or apparent power information. 43 P0.2/CF1/RTCCAL General-Purpose Digital I/O Port 0.2/Calibration Frequency Logic Output 1/RTC Calibration Frequency Logic Output. The CF1 logic output gives instantaneous active, reactive, Irms, or apparent information. The RTCCAL logic output gives access to the calibrated RTC output. 44 SDEN/P2.3 Serial Download Mode Enable/General-Purpose Digital I/O Port 2.3. This pin is used to enable serial download mode through a resistor when pulled low on power-up or reset. On reset, this pin momentarily becomes an input, and the status of the pin is sampled. If there is no pull-down resistor in place, the pin momentarily goes high and then user code is executed. If the pin is pulled down on reset, the embedded serial download/debug kernel executes, and this pin remains low during the internal program execution. After reset, this pin can be used as a digital output port pin (P2.3). 45 BCTRL/INT1/P0.0 Digital Input for Battery Control/External Interrupt Input 1/General-Purpose Digital I/O Port 0.0. This logic input connects VDD or VBAT to VSWOUT internally when set to logic high or logic low, respectively. When left open, the connection between VDD or VBAT and VSWOUT is selected internally. 46 XTAL2 A crystal can be connected across this pin and XTAL1 to provide a clock source for the ADE7566/ADE7569. The XTAL2 pin can drive one CMOS load when an external clock is supplied at XTAL1 or by the gate oscillator circuit. An internal 6 pF capacitor is connected to this pin. 47 XTAL1 An external clock can be provided at this logic input. Alternatively, a tuning fork crystal can be connected across XTAL1 and XTAL2 to provide a clock source for the ADE7566/ADE7569. The clock frequency for specified operation is 32.768 kHz. An internal 6 pF capacitor is connected to this pin. 48 INT0 External Interrupt Input 0. 49, 50 VP, VN Analog Inputs for Voltage Channel. These inputs are fully differential voltage inputs with a maximum differential level of ±400 mV for specified operation. This channel also has an internal PGA. 51 EA This pin is used as an input for emulation. When held high, this input enables the device to fetch code from internal program memory locations. The ADE7566/ADE7569 do not support external code memory. This pin should not be left floating. 52, 53 IP, IN Analog Inputs for Current Channel. These inputs are fully differential voltage inputs with a maximum differential level of ±400 mV for specified operation. This channel also has an internal PGA. 54 AGND This pin provides the ground reference for the analog circuitry. 55 FP26 LCD Segment Output 26. 56 RESET Reset Input, Active Low. 57 REF IN/OUT This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of 1.2 V ± 0.1% and a maximum temperature coefficient of 50 ppm/°C. This pin should be decoupled with a 1 μF capacitor in parallel with a ceramic 100 nF capacitor. 58 V BAT Power Supply Input from the Battery with a 2.4 V to 3.7 V Range. This pin is connected internally to VDD when the battery is selected as the power supply for the ADE7566/ADE7569. 59 V INTA This pin provides access to the on-chip 2.5 V analog LDO. No external active circuitry should be connected to this pin. This pin should be decoupled with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor.

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Rev. B | Page 18 of 152 Pin No. Mnemonic Description 60 V DD 3.3 V Power Supply Input from the Regulator. This pin is connected internally to VSWOUT when the regulator is selected as the power supply for the ADE7566/ADE7569. This pin should be decoupled with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor. 61 V SWOUT 3.3 V Power Supply Output. This pin provides the supply voltage for the LDOs and internal circuitry of the ADE7566/ADE7569. This pin should be decoupled with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor. 62 V INTD This pin provides access to the on-chip 2.5 V digital LDO. No external active circuitry should be connected to this pin. This pin should be decoupled with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor. 63 DGND Ground Reference for Digital Circuitry. 64 V DCIN Analog Input for DC Voltage Monitoring. The maximum input voltage on this pin is VSWOUT with respect to AGND. This pin is used to monitor the preregulated dc voltage. EP Exposed Pad The exposed pad on the bottom of the LFCSP enhances thermal performance and is electrically connected to ground inside the package. It is recommended that the exposed pad be connected to the ground plane on the board.

1. IT IS RECOMMENDED THAT THE EXPOSED PAD ON THE BOTTOM OF THE LFCSP BE

CONNECTED TO THE GROUND PLANE ON THE BOARD. Figure 10. Pin Configuration for the ADE7116/ADE7156/ADE7166/ADE7169 Table 14. Pin Function Descriptions 1 COM3/FP27 Common Output 3/LCD Segment Output 27. COM3 is used for the LCD backplane. 2 COM2/FP28 Common Output 2/LCD Segment Output 28. COM2 is used for the LCD backplane. 3 COM1 Common Output 1. COM1 is used for the LCD backplane. 4 COM0 Common Output 0. COM0 is used for the LCD backplane. 5 P1.2/FP25 General-Purpose Digital I/O Port 1.2/LCD Segment Output 25. 6 P1.3/T2EX/FP24 General-Purpose Digital I/O Port 1.3/Timer 2 Control Input/LCD Segment Output 24. 7 P1.4/T2/FP23 General-Purpose Digital I/O Port 1.4/Timer 2 Input/LCD Segment Output 23. 8 P1.5/FP22 General-Purpose Digital I/O Port 1.5/LCD Segment Output 22. 9 P1.6/FP21 General-Purpose Digital I/O Port 1.6/LCD Segment Output 21. 10 P1.7/FP20 General-Purpose Digital I/O Port 1.7/LCD Segment Output 20. 11 P0.1/FP19 General-Purpose Digital I/O Port 0.1/LCD Segment Output 19. 12 P2.0/FP18 General-Purpose Digital I/O Port 2.0/LCD Segment Output 18. 13 P2.1/FP17 General-Purpose Digital I/O Port 2.1/LCD Segment Output 17. 14 P2.2/FP16 General-Purpose Digital I/O Port 2.2/LCD Segment Output 16. LCDVB to generate the two highest voltages for the LCD waveforms (see the LCD Driver section). LCDVP1. When this pin is an analog input, it is internally connected to LCDVP1 (see the LCD Driver section). internally connected (see the LCD Driver section).

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Rev. B | Page 20 of 152 Pin No. Mnemonic Description 18 LCDVA In the ADE7166/ADE7169, this pin can be either an analog input when the LCD resistor driver is enabled or an analog output when the LCD charge pump is enabled. In the ADE7116/ADE7156, this pin is always an analog input. When this pin is an analog output, it should be decoupled with a 470 nF capacitor. When this pin is an analog input, a resistor should be connected between this pin and LCDVP1 to generate an inter- mediate voltage for the LCD driver. In 1/3 bias LCD mode, another resistor must be connected between this pin and LCDVB to generate another intermediate voltage. In 1/2 bias LCD mode, LCDVA and LCDVB are internally connected (see the LCD Driver section). 19 LCDVP1 In the ADE7166/ADE7169, this pin can be either an analog input when the LCD resistor driver is enabled or an analog output when the LCD charge pump is enabled. In the ADE7116/ADE7156, this pin is always an analog input. When this pin is an analog output, a 100 nF capacitor should be connected between this pin and LCDVP2. When this pin is an analog input, a resistor should be connected between this pin and LCDVA to generate an intermediate voltage for the LCD driver. Another resistor must be connected between LCDVP1 and DGND to generate another intermediate voltage (see the LCD Driver section). 20 to 35 FP15 to FP0 LCD Segment Output 0 to LCD Segment Output 15. 36 P1.1/TxD General-Purpose Digital I/O Port 1.1/Transmitter Data Output (Asynchronous). 37 P1.0/RxD General-Purpose Digital I/O Port 1.0/Receiver Data Input (Asynchronous). 38 P0.7/SS/T1 General-Purpose Digital I/O Port 0.7/Slave Select When SPI Is in Slave Mode/Timer 1 Input. 39 P0.6/SCLK/T0 General-Purpose Digital I/O Port 0.6/Clock Output for I2C or SPI Port/Timer 0 Input. 40 P0.5/MISO General-Purpose Digital I/O Port 0.5/Data Input for SPI Port. 41 P0.4/MOSI/SDATA General-Purpose Digital I/O Port 0.4/Data Output for SPI Port/I2C-Compatible Data Line. 42 P0.3/CF2 General-Purpose Digital I/O Port 0.3/Calibration Frequency Logic Output 2. The CF2 logic output gives instantaneous active, reactive, Irms, or apparent power information. 43 P0.2/CF1/RTCCAL General-Purpose Digital I/O Port 0.2/Calibration Frequency Logic Output 1/RTC Calibration Frequency Logic Output. The CF1 logic output gives instantaneous active, reactive, I rms, or apparent power information. The RTCCAL logic output gives access to the calibrated RTC output. 44 SDEN/P2.3 Serial Download Mode Enable/General-Purpose Digital I/O Port 2.3. This pin is used to enable serial download mode through a resistor when pulled low on power-up or reset. On reset, this pin momentarily becomes an input, and the status of the pin is sampled. If there is no pull-down resistor in place, the pin momentarily goes high and then user code is executed. If the pin is pulled down on reset, the embedded serial download/debug kernel executes, and this pin remains low during the internal program execution. After reset, this pin can be used as a digital output port pin (P2.3). 45 BCTRL/INT1/P0.0 Digital Input for Battery Control/External Interrupt Input 1/General-Purpose Digital I/O Port 0.0. This logic input connects VDD or VBAT to VSWOUT internally when set to logic high or logic low, respectively. When left open, the connection between VDD or VBAT and VSWOUT is selected internally. 46 XTAL2 A crystal can be connected across this pin and XTAL1 to provide a clock source for the ADE7116/ADE7156/ ADE7166/ADE7169. The XTAL2 pin can drive one CMOS load when an external clock is supplied at XTAL1 or by the gate oscillator circuit. An internal 6 pF capacitor is connected to this pin. 47 XTAL1 An external clock can be provided at this logic input. Alternatively, a tuning fork crystal can be connected across XTAL1 and XTAL2 to provide a clock source for the ADE7116/ADE7156/ADE7166/ADE7169. The clock frequency for specified operation is 32.768 kHz. An internal 6 pF capacitor is connected to this pin. 48 INT0 External Interrupt Input 0. 49, 50 VP, VN Analog Inputs for Voltage Channel. These inputs are fully differential voltage inputs with a maximum differential level of ±400 mV for specified operation. This channel also has an internal PGA. 51 EA This pin is used as an input for emulation. When held high, this input enables the device to fetch code from internal program memory locations. The ADE7116/ADE7156/ADE7166/ADE7169 do not support external code memory. This pin should not be left floating. 52, 53 IPA, IN Analog Inputs for Current Channel. These inputs are fully differential voltage inputs with a maximum differential level of ±400 mV for specified operation. This channel also has an internal PGA. 54 AGND This pin provides the ground reference for the analog circuitry. 55 I PB Analog Input for Second Current Channel (IPB). This input is fully differential with a maximum differential level of ±400 mV, referred to IN for specified operation. This channel also has an internal PGA. 56 RESET Reset Input, Active Low. 57 REF IN/OUT This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of 1.2 V ± 0.1% and a maximum temperature coefficient of 50 ppm/°C. This pin should be decoupled with a 1 μF capacitor in parallel with a ceramic 100 nF capacitor. 58 V BAT Power Supply Input from the Battery with a 2.4 V to 3.7 V Range. This pin is connected internally to VDD when the battery is selected as the power supply for the ADE7116/ADE7156/ADE7166/ADE7169.

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Rev. B | Page 21 of 152 Pin No. Mnemonic Description 59 V INTA This pin provides access to the on-chip 2.5 V analog LDO. No external active circuitry should be connected to this pin. This pin should be decoupled with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor. 60 V DD 3.3 V Power Supply Input from the Regulator. This pin is connected internally to VSWOUT when the regulator is selected as the power supply for the ADE7116/ADE7156/ADE7166/ADE7169. This pin should be decoupled with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor. 61 V SWOUT 3.3 V Power Supply Output. This pin provides the supply voltage for the LDOs and internal circuitry of the ADE7116/ADE7156/ADE7166/ADE7169. This pin should be decoupled with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor. 62 V INTD This pin provides access to the on-chip 2.5 V digital LDO. No external active circuitry should be connected to this pin. This pin should be decoupled with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor. 63 DGND Ground Reference for Digital Circuitry. 64 V DCIN Analog Input for DC Voltage Monitoring. The maximum input voltage on this pin is VSWOUT with respect to AGND. This pin is used to monitor the preregulated dc voltage. EP Exposed Pad The exposed pad on the bottom of the LFCSP enhances thermal performance and is electrically connected to ground inside the package. It is recommended that the exposed pad be connected to the ground plane on the board.

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Rev. B | Page 26 of 152 TERMINOLOGY Measurement Error The error associated with the energy measurement made by the ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 is defined by the following formula: Percentage Error = % 100×⎟⎟ ⎛ − EnergyTrue EnergyTrueRegisterEnergy (1) Phase Error Between Channels The digital integrator and the high-pass filter (HPF) in the current channel have a nonideal phase response. To offset this phase response and equalize the phase response between channels, two phase correction networks are placed in the current channel: one for the digital integrator and the other for the HPF. The phase correction networks correct the phase response of the corresponding component and ensure a phase match between current channel and voltage channel to within ±0.1° over a range of 45 Hz to 65 Hz with the digital integrator off. With the digital integrator on, the phase is corrected to within ±0.4° over a range of 45 Hz to 65 Hz. Power Supply Rejection (PSR) PSR quantifies the ADE7116/ADE7156/ADE7166/ADE7169/ ADE7566/ADE7569 measurement error as a percentage of reading when the power supplies are varied. For the ac PSR measurement, a reading at nominal supplies (3.3 V) is taken. A second reading is obtained with the same input signal levels when an ac (100 mV rms/120 Hz) signal is introduced onto the supplies. Any error introduced by this ac signal is expressed as a percentage of reading (see the Measurement Error definition). For the dc PSR measurement, a reading at nominal supplies (3.3 V) is taken. A second reading is obtained with the same input signal levels when the supplies are varied ±5%. Any error introduced is again expressed as a percentage of the reading. ADC Offset Error ADC offset error is the dc offset associated with the analog inputs to the ADCs. It means that, with the analog inputs connected to AGND, the ADCs still see a dc analog input signal. The magnitude of the offset depends on the gain and input range selection (see the Typical Performance Characteristics section). However, when HPF1 is switched on, the offset is removed from the current channel, and the power calculation is not affected by this offset. The offsets can be removed by performing an offset calibration (see the Analog Inputs section). Gain Error Gain error is the difference between the measured ADC output code (minus the offset) and the ideal output code (see the Current Channel ADC section and Voltage Channel ADC section). It is measured for each of the gain settings on the current channel (1, 2, 4, 8, and 16). The difference is expressed as a percentage of the ideal code.

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Rev. B | Page 27 of 152 SPECIAL FUNCTION REGISTER (SFR) MAPPING Table 15. Mnemonic Address Description INTPR 0xFF Interrupt pins configuration (see Table 17). SCRATCH4 0xFE Scratch Pad 4 (see Table 25). SCRATCH3 0xFD Scratch Pad 3 (see Table 24). SCRATCH2 0xFC Scratch Pad 2 (see Table 23). SCRATCH1 0xFB Scratch Pad 1 (see Table 22). BATVTH 0xFA Battery detection threshold (see Table 52). STRBPER 0xF9 Peripheral ADC strobe period (see Table 49). IPSMF 0xF8 Power management interrupt flag (see Table 18). TEMPCAL 0xF7 RTC temperature compensation (see Table 135). RTCCOMP 0xF6 RTC nominal compensation (see Table 134). BATPR 0xF5 Battery switchover configuration (see Table 19). PERIPH 0xF4 Peripheral configuration (see Table 20). DIFFPROG 0xF3 Temperature and supply delta (see Table 50). B 0xF0 Auxiliary math (see Table 56). VDCINADC 0xEF V DCIN ADC value (see Table 53). LCDSEGE2 0xED LCD Segment Enable 2 (see Table 98). IPSME 0xEC Power management interrupt enable (see Table 21). SPISTAT 0xEA SPI interrupt status (see Table 150). SPI2CSTAT 0xEA I 2C interrupt status (see Table 154). SPIMOD2 0xE9 SPI Configuration SFR 2 (see Table 149). I2CADR 0xE9 I 2C slave address (see Table 153). SPIMOD1 0xE8 SPI Configuration SFR 1 (see Table 148). I2CMOD 0xE8 I 2C mode (see Table 152). WAV2H 0xE7 Selection 2 sample MSB (see Table 31). WAV2M 0xE6 Selection 2 sample middle byte (see Table 31). WAV2L 0xE5 Selection 2 sample LSB (see Table 31). WAV1H 0xE4 Selection 1 sample MSB (see Table 31). WAV1M 0xE3 Selection 1 sample middle byte (see Table 31). WAV1L 0xE2 Selection 1 sample LSB (see Table 31). ACC 0xE0 Accumulator (see Table 56). BATADC 0xDF Battery ADC value (see Table 54). MIRQSTH 0xDE Interrupt Status 3 (see Table 42). MIRQSTM 0xDD Interrupt Status 2 (see Table 41). MIRQSTL 0xDC Interrupt Status 1 (see Table 40). MIRQENH 0xDB Interrupt Enable 3 (see Table 45). MIRQENM 0xDA Interrupt Enable 2 (see Table 44). MIRQENL 0xD9 Interrupt Enable 1 (see Table 43). ADCGO 0xD8 Start ADC measurement (see Table 51). Mnemonic Address Description TEMPADC 0xD7 Temperature ADC value (see Table 55). IRMSH 0xD6 I rms measurement MSB (see Table 31). IRMSM 0xD5 Irms measurement middle byte (see Table 31). IRMSL 0xD4 I rms measurement LSB (see Table 31). VRMSH 0xD3 V rms measurement MSB (see Table 31). VRMSM 0xD2 Vrms measurement middle byte (see Table 31). VRMSL 0xD1 V rms measurement LSB (see Table 31). PSW 0xD0 Program status word (see Table 57). TH2 0xCD Timer 2 high byte (see Table 120). TL2 0xCC Timer 2 low byte (see Table 121). RCAP2H 0xCB Timer 2 reload/capture high byte (see Table 122). RCAP2L 0xCA Timer 2 reload/capture low byte (see Table 123). T2CON 0xC8 Timer/Counter 2 control (see Table 115). EADRH 0xC7 Flash high byte address (see Table 110). EADRL 0xC6 Flash low byte address (see Table 109). POWCON 0xC5 Power control (see Table 26). KYREG 0xC1 Key (see Table 126). WDCON 0xC0 Watchdog timer (see Table 85). PROTR 0xBF Flash read protection (see Table 108). PROTB1 0xBE Flash Write/Erase Protection 1 (see Table 107). PROTB0 0xBD Flash Write/Erase Protection 0 (see Table 106). EDATA 0xBC Flash data (see Table 105). PROTKY 0xBB Flash protection key (see Table 104). FLSHKY 0xBA Flash key (see Table 103). ECON 0xB9 Flash control (see Table 102). IP 0xB8 Interrupt priority (see Table 79). PINMAP2 0xB4 Port 2 weak pull-up enable (see Table 159). PINMAP1 0xB3 Port 1 weak pull-up enable (see Table 158). PINMAP0 0xB2 Port 0 weak pull-up enable (see Table 157). LCDCONY 0xB1 LCD Configuration Y (see Table 91). CFG 0xAF Configuration (see Table 63). LCDDAT 0xAE LCD data (see Table 97). LCDPTR 0xAC LCD pointer (see Table 96). IEIP2 0xA9 Interrupt Enable and Priority 2 (see Table 80). IE 0xA8 Interrupt enable (see Table 78). DPCON 0xA7 Data pointer control (see Table 76). INTVAL 0xA6 RTC alarm interval (see Table 133). HOUR 0xA5 RTC hours counter (see Table 132). MIN 0xA4 RTC minutes counter (see Table 131). SEC 0xA3 RTC seconds counter (see Table 130).

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Rev. B | Page 28 of 152 Mnemonic Address Description HTHSEC 0xA2 RTC hundredths of a second counter (see Table 129). TIMECON 0xA1 RTC configuration (see Table 128). P2 0xA0 Port 2 (see Table 162). EPCFG 0x9F Extended port configuration (see Table 156). SBAUDT 0x9E Enhanced serial baud rate control (see Table 142). SBAUDF 0x9D UART timer fractional divider (see Table 143). LCDCONX 0x9C LCD Configuration X (see Table 89). SPI2CRx 0x9B SPI/I2C receive buffer (see Table 147). SPI2CTx 0x9A SPI/I2C transmit buffer (see Table 146). SBUF 0x99 Serial port buffer (see Table 141). SCON 0x98 Serial communications control (see Table 140). LCDSEGE 0x97 LCD segment enable (see Table 95). LCDCLK 0x96 LCD clock (see Table 92). LCDCON 0x95 LCD configuration (see Table 88). MDATH 0x94 Energy measurement pointer data MSB (see Table 31). Mnemonic Address Description MDATM 0x93 Energy measurement pointer data middle byte (see Table 31). MDATL 0x92 Energy measurement pointer data LSB (see Table 31). MADDPT 0x91 Energy measurement pointer address (see Table 30). P1 0x90 Port 1 (see Table 161). TH1 0x8D Timer 1 high byte (see Table 118). TH0 0x8C Timer 0 high byte (see Table 116). TL1 0x8B Timer 1 low byte (see Table 119). TL0 0x8A Timer 0 low byte (see Table 117). TMOD 0x89 Timer/Counter 0 and Timer/Counter 1 mode (see Table 113). TCON 0x88 Timer/Counter 0 and Timer/Counter 1 control (see Table 114). PCON 0x87 Program control (see Table 58). DPH 0x83 Data pointer high (see Table 60). DPL 0x82 Data pointer low (see Table 59). SP 0x81 Stack pointer (see Table 62). P0 0x80 Port 0 (see Table 160).

Table 16. Power Management SFRs 0xEC R/W IPSME Power management interrupt enable (see Table 21). 0xF5 R/W BATPR Battery switchover configuration (see Table 19). 0xF8 R/W IPSMF Power management interrupt flag (see Table 18). 0xFF R/W INTPR Interrupt pins configuration (see Table 17). 0xF4 R/W PERIPH Peripheral configuration (see Table 20). 0xC5 R/W POWCON Power control (see Table 26). 0xFB R/W SCRATCH1 Scratch Pad 1 (see Table 22). 0xFC R/W SCRATCH2 Scratch Pad 2 (see Table 23). 0xFD R/W SCRATCH3 Scratch Pad 3 (see Table 24). 0xFE R/W SCRATCH4 Scratch Pad 4 (see Table 25). Table 17. Interrupt Pins Configuration SFR (INTPR, Address 0xFF) output on the P0.2/CF1/RTCCAL pin. [6:5] FSEL 00 Sets RTC calibration output frequency and calibration window.

4 Reserved N/A

[3:1] INT1PRG 000 Controls the function of INT1. 0 INT0PRG 0 Controls the function of INT0.

0 INT0 input disabled

1 INT0 input enabled

To protect the RTC from runaway code, a key must be written to the key SFR (KYREG, Address 0xC1) to obtain write access to INTPR.

Table 18. Power Management Interrupt Flag SFR (IPSMF, Address 0xF8) 7 0xFF FPSR 0 Power supply restored interrupt flag. Set when the VDD power supply has been restored. This occurs when the source of VSWOUT changes from VBAT to VDD. 6 0xFE FPSM 0 PSM interrupt flag. Set when an enabled PSM interrupt condition occurs. 5 0xFD FSAG 0 Voltage SAG interrupt flag. Set when an ADE energy measurement SAG condition occurs. 4 0xFC Reserved 0 This bit must be kept at 0 for proper operation. 0 V BAT monitor interrupt flag. Set when VBAT falls below BATVTH or when VBAT measurement is ready. 1 0xF9 FBSO 0 Battery switchover interrupt flag. Set when VSWOUT switches from VDD to VBAT. 0 V DCIN monitor interrupt flag. Set when VDCIN falls below 1.2 V. 1 This feature is not available in the ADE7116. Table 19. Battery Switchover Configuration SFR (BATPR, Address 0xF5) [7:2] Reserved 00 These bits must be kept at 0 for proper operation. [1:0] BATPRG 00 Control bits for battery switchover.

00 Battery switchover enabled on low VDD

01 Battery switchover enabled on low VDD and low VDCIN

Table 20. Peripheral Configuration SFR (PERIPH, Address 0xF4) 7 RXFLAG 0 If set, indicates that an Rx edge event triggered wake-up from PSM2. 6 VSWSOURCE 1 Indicates the power supply that is internally connected to VSWOUT (0: VSWOUT = VBAT; 1: VSWOUT = VDD). 5 VDD_OK 1 If set, indicates that VDD power supply is ready for operation. 2 Reserved 0 This bit must be kept at 0 for proper operation. [1:0] RXPROG 00 Controls the function of the P1.0/RxD pin.

00 GPIO

01 RxD with wake-up disabled

11 RxD with wake-up enabled

Table 21. Power Management Interrupt Enable SFR (IPSME, Address 0xEC) 7 EPSR 0 Enables a PSM interrupt when the power supply restored interrupt flag (FPSR) is set. 5 ESAG 0 Enables a PSM interrupt when the voltage SAG interrupt flag (FSAG) is set. 4 Reserved 0 This bit must be kept at 0 for proper operation. 3 EVADC 1 0 Enables a PSM interrupt when the VDCINADC monitor interrupt flag (FVADC) is set. 2 EBAT 1 0 Enables a PSM interrupt when the VBAT monitor interrupt flag (FBAT) is set. 1 EBSO 0 Enables a PSM interrupt when the battery switchover interrupt flag (FBSO) is set. 0 EVDCIN 1 0 Enables a PSM interrupt when the VDCIN monitor interrupt flag (FVDCIN) is set. 1 This feature is not available in the ADE7116.

Table 22. Scratch Pad 1 SFR (SCRATCH1, Address 0xFB) [7:0] SCRATCH1 0 Value can be written/read in this register. This value is maintained in all the power saving modes. Table 23. Scratch Pad 2 SFR (SCRATCH2, Address 0xFC) [7:0] SCRATCH2 0 Value can be written/read in this register. This value is maintained in all the power saving modes. Table 24. Scratch Pad 3 SFR (SCRATCH3, Address 0xFD) [7:0] SCRATCH3 0 Value can be written/read in this register. This value is maintained in all the power saving modes. Table 25. Scratch Pad 4 SFR (SCRATCH4, Address 0xFE) [7:0] SCRATCH4 0 Value can be written/read in this register. This value is maintained in all the power saving modes. Note that these scratch pad registers are cleared only when the part loses VDD and VBAT. Table 26. Power Control SFR (POWCON, Address 0xC5) metering functions are not needed in PSM0 mode. 5 Reserved 0 This bit should be kept at 0 for proper operation. 4 COREOFF 0 Set this bit to shut down the core and enter PSM2 mode if in the PSM1 operating mode. [2:0] CD 010 Controls the core clock frequency, fCORE. fCORE = 4.096 MHz/2CD.

require only a single 3.3 V power supply at VDD for full operation. ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 circuitry. *NOT AVAILABLE IN THE ADE7116. Figure 32. Power Supply Architecture

• VDCIN < 1.2 V . When VDCIN falls below 1.2 V , VSWOUT switches from VDD to VBAT. This event is enabled when the BATPRG[1:0] bits in the battery switchover configuration SFR (BATPR, Address 0xF5) = 0b01. Setting these bits disables switchover based on V DCIN. Battery switchover on low VDCIN is disabled by default.
• VDD < 2.75 V . When VDD falls below 2.75 V , VSWOUT switches from VDD to VBAT. This event is enabled when the BATPRG[1:0] bits in the BATPR SFR are cleared.
• Falling edge on BCTRL. When the battery control pin, BCTRL, goes low, V SWOUT switches from VDD to VBAT. This external switchover signal can trigger a switchover to VBAT at any time. Setting the INT1PRG bits to X01 in the interrupt pins configuration SFR (INTPR, Address 0xFF) enables the battery control pin (see Table 17). Switching from VBAT to VDD To s witch VSWOUT from VBAT to VDD, all of the following events must be true:
• VDD > 2.75 V . VSWOUT switches back to VDD after VDD remains above 2.75 V .
• VDCIN > 1.2 V and VDD > 2.75 V . If the low VDCIN condition is enabled, VSWOUT switches to VDD after VDCIN remains above 1.2 V and VDD remains above 2.75 V .
• Rising edge on BCTRL. If the battery control pin is enabled, VSWOUT switches back to VDD after BCTRL is high, and the first or second bullet point is satisfied.

power supply events. The PSM interrupt is disabled by default. (IEIP2, Address 0xA9) enables the PSM interrupt (see Table 80). interrupt vector is shared among the PSM interrupt sources. Address 0xF8 (see Table 18). NOT INVOLVED IN PSM INTERRUPT SIGNAL CHAIN. *NOT AVAILABLE IN THE ADE7116. Figure 33. Power Supply Management Interrupt Sources

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Rev. B | Page 34 of 152 Battery Switchover and Power Supply Restored PSM Interrupt The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 can be configured to generate a PSM interrupt when the source of V SWOUT changes from VDD to VBAT, indicating battery switchover. Setting the EBSO bit in the power manage- ment interrupt enable SFR (IPSME, Address 0xEC) enables this event to generate a PSM interrupt (see Table 21). The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 can also be configured to generate an interrupt when the source of V SWOUT changes from VBAT to VDD, indicating that the VDD power supply has been restored. Setting the EPSR bit in the power management interrupt enable SFR (IPSME, Address 0xEC) enables this event to generate a PSM interrupt. The flags in the IPSMF SFR for these interrupts, FBSO and FPSR, are set regardless of whether the respective enable bits have been set. The battery switchover and power supply restore event flags, FBSO and FPSR, are latched. These events must be cleared by writing a 0 to these bits. Bit 6 (VSWSOURCE) in the peripheral configuration SFR (PERIPH, Address 0xF4) tracks the source of V SWOUT. The bit is set when VSWOUT is connected to VDD and cleared when VSWOUT is connected to VBAT. VDCIN ADC PSM Interrupt The ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 can be configured to generate a PSM interrupt when VDCIN changes magnitude by more than a configurable threshold. This threshold is set in the temperature and supply delta SFR (DIFFPROG, Address 0xF3), which is described in Table 50. See the External Voltage Measurement section for more information. Setting the EV ADC bit in the power management interrupt enable SFR (IPSME, Address 0xEC) enables this event to generate a PSM interrupt. Note that this feature is not available in the ADE7116. The V DCIN voltage is measured using a dedicated ADC. These measurements take place in the background at intervals to check the change in VDCIN. Conversions can also be initiated by writing to the start ADC measurement SFR (ADCGO, Address 0xD8), as described in Table 51. The FV ADC flag in the power manage- ment interrupt flag SFR (IPSMF , Address 0xF8) indicates when a VDCIN measurement is ready. See the External Voltage Measurement section for details on how VDCIN is measured. VBAT Monitor PSM Interrupt The VBAT voltage is measured using a dedicated ADC. These measurements take place in the background at intervals to check the change in VBAT. The FBAT bit is set when the battery level is lower than the threshold set in the battery detection threshold SFR (BATVTH, Address 0xFA), described in Table 52, or when a new measurement is ready in the battery ADC value SFR (BATADC, Address 0xDF), described in Table 54. See the Battery Measurement section for more information. Setting the EBAT bit in the power management interrupt enable SFR (IPSME, Address 0xEC) enables this event to generate a PSM interrupt. Note that this feature is not available in the ADE7116. VDCIN Monitor PSM Interrupt The VDCIN voltage is monitored by a comparator. The FVDCIN bit in the power management interrupt flag SFR (IPSMF, Address 0xF8) is set when the VDCIN input level is lower than 1.2 V . Setting the EVDCIN bit in the IPSME SFR enables this event to generate a PSM interrupt. This event, which is associated with the SAG monitoring, can be used to detect that a power supply (V DD) is compromised and to trigger further actions prior to initiating a switch from VDD to VBAT. Note that this feature is not available in the ADE7116. SAG Monitor PSM Interrupt The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 energy measurement DSP monitors the ac voltage input at the V P and VN input pins. The SAGLVL register (Address 0x14) is used to set the threshold for a line voltage SAG event. The FSAG bit in the power management interrupt flag SFR (IPSMF, Address 0xF8) is set if the line voltage stays below the level set in the SAGLVL register for the number of line cycles set in the SAGCYC register (Address 0x13). See the Line Voltage SAG Detection section for more information. Setting the ESAG bit in the power management interrupt enable SFR (IPSME, Address 0xEC) enables this event to generate a PSM interrupt.

5 V to 12 V , can be connected to V

DCIN through a resistor divider. ADE7569 power supply inputs are set up in this application. provide the earliest warning of a potential problem on VDD. represented in Figure 37 and Figure 38. Figure 34. Power Supply Management for Energy Meter Application OCCURS. VSWOUT IS CONNECTED TO VBAT. Figure 35. Power Supply Management Interrupts and Battery Switchover with Only VDD Enabled for Battery Switchover

power-on reset or software reset, is 1.024 MHz. software reset, is 1.024 MHz.

2.5 V digital and analog circuitry powered through VINTA and VINTD

• The RAM in the MCU is no longer valid.
• The program counter for the 8052, also held in volatile memory, becomes invalid when the 2.5 V supply is shut down. Therefore, the program does not resume from where it left off but always starts from the power-on reset vector when the ADE7116/ADE7156/ADE7166/ADE7169/ ADE7566/ADE7569 exit PSM2. The 3.3 V peripherals (temperature ADC 1, VDCIN ADC1, RTC, and LCD) are active in PSM2. They can be enabled or disabled to reduce power consumption and are configured for PSM2 operation when the MCU core is active (see Table 29 for more information about the peripherals and their PSM2 configuration). The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 remain in PSM2 until an event occurs to wake them up. In PSM2 mode, the ADE7116/ADE7156/ADE7166/ADE7169/ ADE7566/ADE7569 provide four scratch pad RAM SFRs that are maintained during this mode. These SFRs can be used to save data from PSM0 or PSM1 mode when entering PSM2 mode (see Table 22 to Table 25). In PSM2, the ADE7116/ADE7156/ADE7166/ADE7169/ ADE7566/ADE7569 maintain some SFRs (see Table 28). The SFRs that are not listed in this table should be restored when the part enters PSM0 or PSM1 mode from PSM2 mode.

Table 28. SFRs Maintained in PSM2 Mode 1 This feature is not available in the ADE7116.

3.3 V PERIPHERALS AND WAKE-UP EVENTS

PSM2 mode are listed in the Wake-Up Event column in Table 29. Table 29. 3.3 V Peripherals and Wake-Up Events serviced and acknowledged prior to entering PSM2 mode. FVADC flag needs to be cleared prior to entering PSM2 mode. (PERIPH, Address 0xF4), is set to indicate that VSWOUT is connected to VDD. and acknowledged prior to entering PSM2 mode. (TCON, Address 0x88). The IE0 flag bit in the TCON SFR is not affected. prior to entering PSM2 mode. (TCON, Address 0x88). The IE1 flag bit in the TCON SFR is not affected. prior to entering PSM2 mode. Scratch Pad The four SCRATCHx registers remain intact in PSM2 mode.

describes events that change the operating mode. enabled (see the 3.3 V Peripherals and Wake-Up Events section). wake-up events (see the 3.3 V Peripherals and Wake-Up Events). 0xC5) to shut down the MCU core. ormed to start PSM0 code execution at the power-on reset vector.

• Enable the battery switchover interrupt (EBSO) if VSWOUT = VDD at power-up.
• Enable the power supply restored interrupt (EPSR) if VSWOUT = VBAT at power-up. An early warning that battery switchover is about to occur is provided by SAG detection and, possibly, by low VDCIN detection (see the Battery Switchover section). For a user-controlled battery switchover, enable automatic battery switchover on low V DD only. Next, enable the low VDCIN event to generate the PSM interrupt. When a low VDCIN event occurs, start data backup. Upon completion of the data backup, enable battery switchover on low V DCIN. Battery switchover occurs 30 ms later. PSM1 BATTERY MODE VSWOUT CONNECTED TO VBAT PSM0 NORMAL MODE VSWOUT CONNECTED TO VDD PSM2 SLEEP MODE VSWOUT CONNECTED TO VBAT POWER SUPPLY RESTORED AUTOMATIC BATTERY SWITCHOVER WAKE-UP EVENT USER CODE DIRECTS MCU TO SHUT DOWN CORE AFTER SERVICING WAKE-UP EVENT POWER SUPPLY RESTORED 06353-017

Figure 38. Transitioning Between Operating Modes

are readily available through the SFRs, as shown in Table 31. the SFR when the SFR is read. byte results in reading the data from the previous latched sample. a write is performed (see Table 30). Table 30. Energy Measurement Pointer Address SFR and the MDATM SFR and MDATH SFR contents are ignored. or write to these registers can take place. SFR contents are reset to 0x00. SFRs are transferred to another SFR.

Table 31. Energy Measurement SFRs 0x91 R/W MADDPT Energy measurement pointer address. 0x92 R/W MDATL Energy measurement pointer data LSB. 0x93 R/W MDATM Energy measurement pointer data middle byte. 0x94 R/W MDATH Energy measurement pointer data MSB. 0xD1 R VRMSL Vrms measurement LSB. 0xD2 R VRMSM Vrms measurement middle byte. 0xD3 R VRMSH Vrms measurement MSB. 0xD4 R IRMSL Irms measurement LSB. 0xD5 R IRMSM Irms measurement middle byte. 0xD6 R IRMSH Irms measurement MSB. 0xD9 R/W MIRQENL Energy measurement interrupt enable LSB. 0xDA R/W MIRQENM Energy measurement interrupt enable middle byte. 0xDB R/W MIRQENH Energy measurement interrupt enable MSB. 0xDC R/W MIRQSTL Energy measurement interrupt status LSB. 0xDD R/W MIRQSTM Energy measurement interrupt status middle byte. 0xDE R/W MIRQSTH Energy measurement interrupt status MSB. 0xE2 R WAV1L Selection 1 sample LSB. 0xE3 R WAV1M Selection 1 sample middle byte. 0xE4 R WAV1H Selection 1 sample MSB. 0xE5 R WAV2L Selection 2 sample LSB. 0xE6 R WAV2M Selection 2 sample middle byte. 0xE7 R WAV2H Selection 2 sample MSB. Figure 39. ADE7566 and ADE7569 Energy Metering Block Diagram

Figure 40. ADE7116, ADE7156, ADE7166, and ADE7169 Energy Metering Block Diagram

Table 32. Energy Measurement Register List 0x01 WATTHR R 24 S 0 Reads Wh accumulator without reset. 0x02 RWATTHR R 24 S 0 Reads Wh accumulator with reset. 0x03 LWATTHR R 24 S 0 Reads Wh accumulator synchronous to line cycle. 0x04 VARHR 1 R 24 S 0 Reads VARh accumulator without reset. R 24 S 0 Reads VARh accumulator with reset. R 24 S 0 Reads VARh accumulator synchronous to line cycle. MODE2 register (Address 0x0C) is set, this register accumulates Irms. 0x0A PER_FREQ R 16 U 0 Reads line period or frequency register depending on MODE2 register. 0x0B MODE1 R/W 8 U 0x06 Sets basic configuration of energy measurement (see Table 33). 0x0C MODE2 R/W 8 U 0x40 Sets basic configuration of energy measurement (see Table 34). 0x0E NLMODE R/W 8 U 0 Sets level of energy no load thresholds (see Table 36). 0x10 PHCAL R/W 8 S 0x40 Sets phase calibration register (see the Phase Compensation section). Voltage SAG Detection section). 0x17 IPEAK R 24 U 0 Reads current peak level without reset (see the Peak Detection section). 0x18 RSTIPEAK R 24 U 0 Reads current peak level with reset (see the Peak Detection section). 0x1A RSTVPEAK R 24 U 0 Reads voltage peak level with reset (see the Peak Detection section). 0x1B GAIN R/W 8 U 0 Sets PGA gain of analog inputs (see Table 38). 0x1C IBGAIN 2 R/W 12 S 0 Sets matching gain for IPB current input. 0x1D WGAIN R/W 12 S 0 Sets watt gain register. R/W 12 S 0 Sets var gain register. 0x1F VAGAIN R/W 12 S 0 Sets VA gain register. 0x20 WATTOS R/W 16 S 0 Sets watt offset register. R/W 16 S 0 Sets var offset register. 0x22 IRMSOS R/W 12 S 0 Sets current rms offset register. 0x23 VRMSOS R/W 12 S 0 Sets voltage rms offset register. 0x24 WDIV R/W 8 U 0 Sets watt energy scaling register.

0x25 VARDIV R/W 8 U 0 Sets var energy scaling register. 0x26 VADIV R/W 8 U 0 Sets VA energy scaling register. 0x27 CF1NUM R/W 16 U 0 Sets CF1 numerator register. 0x28 CF1DEN R/W 16 U 0x003F Sets CF1 denominator register. 0x29 CF2NUM R/W 16 U 0 Sets CF2 numerator register. 0x2A CF2DEN R/W 16 U 0x003F Sets CF2 denominator register. 0x3B Reserved 0 This register must be set to its default value for proper operation. 0x3C Reserved 0x0300 This register must be set to its default value for proper operation. R/W 8 U 0 Set calibration mode. 0x3E Reserved 0 This register must be set to its default value for proper operation. 0x3F Reserved 0 This register must be set to its default value for proper operation. 1 This function is not available in the ADE7116, ADE7156, ADE7166, or ADE7566. 2 This function is not available in the ADE7566 or ADE7569. Table 33. MODE1 Register (MODE1, Address 0x0B) 7 SWRST 0 Setting this bit resets all of the energy measurement registers to their default values. 6 DISZXLPF 0 Setting this bit disables the zero-crossing low-pass filter. 5 INTE 0 Setting this bit enables the digital integrator for use with a di/dt sensor. 4 SWAPBITS 0 Setting this bit swaps CH1 ADC and CH2 ADC. 3 PWRDN 0 Setting this bit powers down voltage and current ADCs. 2 DISCF2 1 Setting this bit disables Frequency Output CF2. 1 DISCF1 1 Setting this bit disables Frequency Output CF1. 0 DISHPF 0 Setting this bit disables the HPFs in voltage and current channels. Table 34. MODE2 Register (MODE2, Address 0x0C) [7:6] CF2SEL 01 Configuration bits for CF2 output. 00 CF2 frequency is proportional to active power. 1X CF2 frequency is proportional to apparent power or Irms. [5:4] CF1SEL 00 Configuration bits for CF1 output. 00 CF1 frequency is proportional to active power. 1X CF1 frequency is proportional to apparent power or Irms. 0 If CF1SEL[1:0] = 1X, CF1 is proportional to VA. If CF2SEL[1:0] = 1X, CF2 is proportional to VA. 1 If CF1SEL[1:0] = 1X, CF1 is proportional to Irms. If CF2SEL[1:0] = 1X, CF2 is proportional to Irms. 2 ZXRMS 0 Logic 1 enables update of rms values synchronously to Voltage ZX.

1 FREQSEL 0 Configuration bits to select period or frequency measurement for PER_FREQ register

0 PER_FREQ register holds a period measurement. 1 PER_FREQ register holds a frequency measurement. 0 WAVEN 0 When this bit is set, waveform sampling mode is enabled. 1 This function is not available in the ADE7116, ADE7156, ADE7166, or ADE7566. Table 35. Waveform Mode Register (WAVMODE, Address 0x0D) [7:5] WAV2SEL 000 Waveform Sample 2 selection for samples mode.

000 Current

001 Voltage

010 Active power multiplier output

011 Reactive power multiplier output1

100 VA multiplier output

101 Irms LPF output

[4:2] WAV1SEL 000 Waveform Sample 1 selection for samples mode.

101 Irms LPF output (low 24-bit)

[1: 0] DTRT 00 Waveform samples output data rate. 1 This function is not available in the ADE7116, ADE7156, ADE7166, or ADE7566. Table 36. No Load Configuration Register (NLMODE, Address 0x0E) 7 DISVARCMP 1 0 Setting this bit disables fundamental var gain compensation over line frequency. [5:4] VANOLOAD 00 Apparent power no load threshold.

00 No load detection disabled

00 Reactive power no load threshold. [1:0] APNOLOAD 00 Active power no load threshold. 1 This function is not available in the ADE7116, ADE7156, ADE7166, or ADE7566. Table 37. Accumulation Mode Register (ACCMODE, Address 0x0F) 7 ICHANNEL 1 0 This bit indicates the current channel used to measure energy in antitampering mode.

6 FAULTSIGN 1

0 Configuration bit to select the event that triggers a fault interrupt. VARSIGN interrupt occurs when reactive power changes from negative to positive. APSIGN interrupt occurs when active power changes from negative to positive.

3 ABSVARM 2

0 Logic 1 enables absolute value accumulation of reactive power in energy register and pulse

2 SAVARM 2

1 POAM 0 Logic 1 enables positive-only accumulation of active power in energy register and pulse output.

0 ABSAM 0 Logic 1 enables absolute value accumulation of active power in energy register and pulse

1 This function is not available in the ADE7566 or ADE7569. 2 This function is not available in the ADE7116, ADE7156, ADE7166, or ADE7566. Table 38. Gain Register (GAIN, Address 0x1B) [7:5] PGA2 000 These bits define the voltage channel input gain.

000 Gain = 1

001 Gain = 2

010 Gain = 4

011 Gain = 8

100 Gain = 16

3 CFSIGN_OPT 0 This bit defines where the CF change of sign detection (APSIGN or VARSIGN) is

[2:0] PGA1 000 These bits define the current channel input gain.

000 Gain = 11

1 This gain is not recommended in the ADE7166 or ADE7169 because it can create an overranging of the ADC when both current inputs are in opposite phase. Table 39. Calibration Mode Register (CALMODE, Address 0x3D) 1 [7:6] Reserved 0 These bits must be kept at 0 for proper operation. [5:4] SEL_I_CH 0 These bits define the current channel used for energy measurements.

00 Current channel automatically selected by the tampering condition

01 Current channel connected to IPA

10 Current channel connected to IPB

11 Current channel automatically selected by the tampering condition

3 V_CH_SHORT 0 Logic 1 shorts the voltage channel to ground. 2 I_CH_SHORT 0 Logic 1 shorts the current channel to ground. [1:0] Reserved These bits must be kept at 0 for proper operation. 1 This register is not available in the ADE7566 or ADE7569. Table 40. Interrupt Status 1 SFR (MIRQSTL, Address 0xDC) automatically cleared when all of the enabled ADE status flags are cleared. 5 FAULTSIGN 1 Logic 1 indicates that the fault mode has changed according to the configuration of the ACCMODE register. 3 APSIGN Logic 1 indicates that the active power sign has changed according to the configuration of the ACCMODE register. also used to reflect that the part is entering the Irms no load mode.

1 RNOLOAD 2

Logic 1 indicates that an interrupt has been caused by reactive power no load detection. 0 APNOLOAD Logic 1 indicates that an interrupt has been caused by active power no load detection. 1 This function is not available in the ADE7566 or ADE7569. 2 This function is not available in the ADE7116, ADE7156, ADE7166, or ADE7566.

Table 41. Interrupt Status 2 SFR (MIRQSTM, Address 0xDD) enabled by clearing Bit 2 of the MODE1 register. enabled by clearing Bit 1 of the MODE1 register. 5 VAEOF Logic 1 indicates that the VAHR register has overflowed. 4 REOF 1 Logic 1 indicates that the VARHR register has overflowed. 3 AEOF Logic 1 indicates that the WATTHR register has overflowed. 2 VAEHF Logic 1 indicates that the VAHR register is half full.

1 REHF 1

Logic 1 indicates that the VARHR register is half full. 0 AEHF Logic 1 indicates that the WATTHR register is half full. 1 This function is not available in the ADE7116, ADE7156, ADE7166, or ADE7566. Table 42. Interrupt Status 3 SFR (MIRQSTH, Address 0xDE) 7 RESET Indicates the end of a reset (for both software and hardware reset). 5 WFSM Logic 1 indicates that new data is present in the waveform registers (Address 0xE2 to Address 0xE7). 4 PKI Logic 1 indicates that the current channel has exceeded the IPKLVL value. 3 PKV Logic 1 indicates that the voltage channel has exceeded the VPKLVL value. 2 CYCEND Logic 1 indicates the end of the energy accumulation over an integer number of half-line cycles. 1 ZXTO Logic 1 indicates that no zero crossing on the line voltage happened for the last ZXTOUT half-line cycles. 0 ZX Logic 1 indicates detection of a zero crossing in the voltage channel. Table 43. Interrupt Enable 1 SFR (MIRQENL, Address 0xD9) 5 FAULTSIGN 1 When this bit is set to Logic 1, the FAULTSIGN bit set creates a pending ADE interrupt to the 8052 core. 4 VARSIGN 2 When this bit is set to Logic 1, the VARSIGN flag set creates a pending ADE interrupt to the 8052 core. 3 APSIGN When this bit is set to Logic 1, the APSIGN flag set creates a pending ADE interrupt to the 8052 core. 2 VANOLOAD When this bit is set to Logic 1, the VANOLOAD flag set creates a pending ADE interrupt to the 8052 core. When this bit is set to Logic 1, the RNOLOAD flag set creates a pending ADE interrupt to the 8052 core. 0 APNOLOAD When this bit is set to Logic 1, the APNOLOAD flag set creates a pending ADE interrupt to the 8052 core. 1 This function is not available in the ADE7566 or ADE7569. 2 This function is not available in the ADE7116, ADE7156, ADE7166, or ADE7566. Table 44. Interrupt Enable 2 SFR (MIRQENM, Address 0xDA) 7 CF2 When this bit is set to Logic 1, a CF2 pulse creates a pending ADE interrupt to the 8052 core. 6 CF1 When this bit is set to Logic 1, a CF1 pulse creates a pending ADE interrupt to the 8052 core. 5 VAEOF When this bit is set to Logic 1, the VAEOF flag set creates a pending ADE interrupt to the 8052 core. 4 REOF 1 When this bit is set to Logic 1, the REOF flag set creates a pending ADE interrupt to the 8052 core. 3 AEOF When this bit is set to Logic 1, the AEOF flag set creates a pending ADE interrupt to the 8052 core. 2 VAEHF When this bit is set to Logic 1, the VAEHF flag set creates a pending ADE interrupt to the 8052 core. When this bit is set to Logic 1, the REHF flag set creates a pending ADE interrupt to the 8052 core. 0 AEHF When this bit is set to Logic 1, the AEHF flag set creates a pending ADE interrupt to the 8052 core. 1 This function is not available in the ADE7116, ADE7156, ADE7166, or ADE7566.

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Rev. B | Page 54 of 152 FAULT DETECTION The ADE7116/ADE7156/ADE7166/ADE7169 incorporate a fault detection scheme that warns of fault conditions and allows the part to continue accurate measurement during a fault event. (This function is not available in the ADE7566/ ADE7569.) The ADE7116/ADE7156/ADE7166/ADE7169 do this by continu- ously monitoring both current inputs (I PA and IPB). For ease of understanding, these currents are referred to as phase and neutral (return) currents. A fault condition is defined when the difference between I PA and IPB is greater than 6.25% of the active channel. If a fault condition is detected and the inactive channel is larger than the active channel, the ADE7116/ADE7156/ ADE7166/ADE7169 automatically switch current measurement to the inactive channel. During a fault, the active, reactive, and apparent power and the I rms are generated using the larger of the two currents. On power-up, IPA is the current input selected for active, reactive, and apparent power and Irms calculations. To prevent a false alarm, averaging is done for the fault detection, and a fault condition is detected approximately 1 second after the event. Fault detection is automatically disabled when the voltage signal is less than 0.3% of the full- scale input range. This eliminates false detection of a fault due to noise at light loads. Because the ADE7116/ADE7156/ADE7166/ADE7169 look for a difference between the voltage signals on I PA and IPB, it is important that both current transducers be closely matched. Channel Selection Indication The current channel selected for measurement is indicated by Bit 7 (ICHANNEL) in the ACCMODE register (Address 0x0F). When this bit is cleared, IPA is selected and, when it is set, IPB is selected. The ADE7166/ADE7169 automatically switch from one channel to the other and report the channel configuration in the ACCMODE register (Address 0x0F). The current channel selected for measurement can also be forced. Setting the SEL_I_CH[1:0] bits in the CALMODE register (Address 0x3D) selects I PA and IPB, respectively. When both bits are cleared or set, the current channel used for measurement is selected automatically based on the fault detection. Fault Indication The ADE7116/ADE7156/ADE7166/ADE7169 provide an indication of the part going in or out of a fault condition. The new fault condition is indicated by the FAULTSIGN flag (Bit 5) in the Interrupt Status 1 SFR (MIRQSTL, Address 0xDC). When the FAULTSIGN bit (Bit 6) of the ACCMODE register (Address 0x0F) is cleared, the FAULTSIGN flag in the Interrupt Status 1 SFR (MIRQSTL, Address 0xDC) is set when the part is entering a fault condition or a normal condition. When the FAULTSIGN bit (Bit 5) is set in the Interrupt Enable

1 SFR (MIRQENL, Address 0xD9), and the FAULTSIGN flag

(Bit 5) in the Interrupt Status 1 SFR (MIRQSTL, Address 0xDC) is set, the 8052 core has a pending ADE interrupt. Fault with Active Input Greater Than Inactive Input If IPA is the active current input (that is, being used for billing), and the voltage signal on IPB (the inactive input) falls below 93.75% of IPA, and the FAULTSIGN bit (Bit 6) of the ACCMODE register (Address 0x0F) is cleared, the FAULTSIGN flag (Bit 5) in the Interrupt Status 1 SFR (MIRQSTL, Address 0xDC) is set. Both analog inputs are filtered and averaged to prevent false triggering of this logic output. As a consequence of the filtering, there is a time delay of approximately 3 seconds on the logic output after the fault event. The FAULTSIGN flag is indepen- dent of any activity. Because I PA is the active input and it is still greater than IPB, billing is maintained on IPA; that is, no swap to the IPB input occurs. IPA remains the active input.

3 LINE CYCLES

Figure 57. SAG Detection 0x14) are compared to the absolute value of the output from LPF1.

1. The SAG level register is compared to the input of the ZX

the contents of the SAG level register. Figure 58. Peak Level Detection cleared (see the Energy Measurement Interrupts section). value. Writing 0x00 puts the current channel detection level at 0. 8052 core has a pending ADE interrupt. maximum absolute value observed on the voltage channel input. contents after the read operation.

be used to remove offset in the current channel rms calculation. 16,384 LSBs of the square of the current channel rms register. where Irms0 is the rms measurement without offset correction. *NOT AVAILABLE IN THE ADE7566. Figure 61. ADE7566/ADE7569 Current Channel RMS Signal Processing with PGA1 = 1, 2, 4, 8, or 16

Figure 65. Frequency Response of LPF2 adjustment is related to the contents of the watt gain register.

1 WGAINPowerActiveWGAINOutput (12)

average word value output from LPF2 is 838.861 (838,861/1000). transition from positive to negative active power occurs. positive active power occurs. output frequency of the multiplier.

expressed mathematically, as shown in Equation 13. Conversely, energy is given as the integral of power. summation is equivalent to integration in continuous time. Equation 15 expresses the relationship. n is the discrete time sample number. the internal active energy register. restrictive mode, the positive-only accumulation mode. equal to 0, the internal active energy register is divided by 1. register, and the upper 24 bits of the internal register are cleared. Figure 66. Active Energy Calculation

gain adjustment is related to the contents of the var gain register. power (or energy) calculation in the ADE7169/ADE7569. when no power is being consumed. Note that the average reactive power is a signed calculation. is enabled, and +90° phase shift when the integrator is disabled. Table 46. Sign of Reactive Power Calculation Measurement Interrupts section). a transition from positive to negative reactive power occurs. cleared (see the Energy Measurement Interrupts section). the full-scale output frequency of the multiplier, respectively. added to the internal reactive energy register.

time varies, as shown in Equation 27. no load threshold are active in this mode. Figure 73. Reactive Energy Accumulation in

Figure 78. The line apparent energy accumulation mode is register (Address 0x12), which is an unsigned 16-bit register. needed for reactive power and power factor calculation. in the Interrupt Status 3 SFR (MIRQSTH, Address 0xDE) is set. CYCEND interrupt after writing to the LINCYC register. two registers is equivalent. Address 0xD9), the 8052 core has a pending ADE interrupt. is cleared (see the Energy Measurement Interrupts section). scale output frequency of the multiplier, respectively. is the same as for the apparent energy.

If 0 is written to any of these registers, 1 is applied to the register. is greater than 1, the register values are adjusted to a ratio of 1. set to 6.1 Hz by writing 0xFF to the CFxDEN register. these registers is shown in Table 47. Table 47. Energy Registers Scaling event is not enabled, it cannot create a system interrupt. written to this register bit.

configured through the SFRs, as shown in Table 48. be configured to continue functioning in PSM1 and PSM2. before using it for compensation. Table 48. Temperature, Battery, and Supply Voltage Measurement SFRs 0xF9 R/W STRBPER Peripheral ADC strobe period (see Table 49). 0xF3 R/W DIFFPROG Temperature and supply delta (see Table 50). 0xD8 R/W ADCGO Start ADC measurement (see Table 51). 0xFA R/W BATVTH Battery detection threshold (see Table 52). 0xEF R/W VDCINADC VDCIN ADC value (see Table 53). 0xDF R/W BATADC Battery ADC value (see Table 54). 0xD7 R/W TEMPADC Temperature ADC value (see Table 55). Table 49. Peripheral ADC Strobe Period SFR (STRBPER, Address 0xF9) [7:6] Reserved 00 These bits must be kept at 0 for proper operation. [5:4] VDCIN_PERIOD 0 Period for background external voltage measurements.

00 No VDCIN measurement

[3:2] BATT_PERIOD 0 Period for background battery level measurements.

00 No battery measurement

[1:0] TEMP_PERIOD 0 Period for background temperature measurements.

00 No temperature measurement

Table 50. Temperature and Supply Delta SFR (DIFFPROG, Address 0xF3) temperature measurement that should interrupt 8052.

000 No interrupt

111 Every temperature measurement

external measurement that should interrupt 8052.

111 Every VDCIN measurement

Table 51. Start ADC Measurement SFR (ADCGO, Address 0xD8) 0xF4). A PLL fault is generated if a reset is caused because the PLL lost lock. [6:3] 0xDE to 0xDB Reserved 0 Reserved. when the measurement request is received by the ADC. the measurement request is received by the ADC. measurement request is received by the ADC. Table 52. Battery Detection Threshold SFR (BATVTH, Address 0xFA) BATADC is lower than the threshold, an interrupt is generated. Table 53. VDCIN ADC Value SFR (VDCINADC, Address 0xEF) [7:0] VDCINADC 0 The VDCINADC value in this register is updated when an ADC interrupt occurs. Table 54. Battery ADC Value SFR (BATADC, Address 0xDF) [7:0] BATADC 0 The battery ADC value in this register is updated when an ADC interrupt occurs. Table 55. Temperature ADC Value SFR (TEMPADC, Address 0xD7) [7:0] TEMPADC 0 The temperature ADC value in this register is updated when an ADC interrupt occurs.

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Rev. B | Page 79 of 152 TEMPERATURE MEASUREMENT To provide a digital temperature measurement, each ADE7156/ ADE7166/ADE7169/ADE7566/ADE7569 includes a dedicated ADC. An 8-bit temperature ADC value SFR (TEMPADC, Address 0xD7) holds the results of the temperature conversion. The resolution of the temperature measurement is 0.78°C/LSB. There are two ways to initiate a temperature conversion: a single temperature measurement or background temperature measurements. Single Temperature Measurement Set the TEMP_ADC_GO bit (Bit 1) in the start ADC measure- ment SFR (ADCGO, Address 0xD8) to obtain a temperature measurement (see Table 51). An interrupt is generated when the conversion is complete and when the temperature measurement is available in the temperature ADC value SFR (TEMPADC, Address 0xD7). Background Temperature Measurements Background temperature measurements are disabled by default. To configure the background temperature measurement mode, set a temperature measurement interval in the peripheral ADC strobe period SFR (STRBPER, Address 0xF9). Temperature measurements are then performed periodically in the background (see Table 49). When a temperature conversion completes, the new temperature ADC value is compared to the last temperature ADC value that created an interrupt. If the absolute difference between the two values is greater than the setting in the TEMP_DIFF bits in the temperature and supply delta SFR (DIFFPROG, Address 0xF3), a TEMPADC interrupt is generated (see Table 50). This allows temperature measurements to take place completely in the background, requiring MCU activity only if the temperature changes more than a configurable delta. To set up background temperature measurement, Initiate a single temperature measurement by setting the TEMP_ADC_GO bit in the start ADC measurement SFR (ADCGO, Address 0xD8). Upon completion of this measurement, configure the TEMP_DIFF bits in the temperature and supply delta SFR (DIFFPROG, Address 0xF3) to establish the change in temperature that triggers an interrupt. Set up the interval for background temperature measurements by configuring the TEMP_PERIOD[1:0] bits in the periph- eral ADC strobe period SFR (STRBPER, Address 0xF9). Temperature ADC in PSM0, PSM1, and PSM2 Depending on the operating mode of the ADE7156/ADE7166/ ADE7169/ADE7566/ADE7569, a temperature conversion is initiated only by certain actions.

• In PSM0 operating mode, the 8052 is active. Temperature measurements are available in the background measurement mode and by initiating a single measurement.
• In PSM1 operating mode, the 8052 is active, and the part is battery powered. Single temperature measurements can be initiated by setting the TEMP_ADC_GO bit in the start ADC measurement SFR (ADCGO, Address 0xD8). Background temperature measurements are not available. In PSM2 operating mode, the 8052 is not active. Temperature conversions are available through the background measurement mode only. The temperature ADC value SFR (TEMPADC, Address 0xD7) is updated with a new value only when a temperature ADC interrupt occurs. Temperature ADC Interrupt The temperature ADC can generate an ADC interrupt when at least one of the following conditions occurs: The difference between the new temperature ADC value and the last temperature ADC value generating an ADC interrupt is larger than the value set in the TEMP_DIFF bits. The temperature ADC conversion, initiated by setting the start ADC measurement SFR (ADCGO, Address 0xD8), finishes. When the ADC interrupt occurs, a new value is available in the temperature ADC value SFR (TEMPADC, Address 0xD7). Note that there is no flag associated with this interrupt. BATTERY MEASUREMENT To provide a digital battery measurement, each ADE7156/ ADE7166/ADE7169/ADE7566/ADE7569 includes a dedicated ADC. The battery measurement is available in the 8-bit battery ADC value SFR (BATADC, Address 0xDF). The battery measurement has a resolution of 14.6 mV/LSB. A battery conversion can be initiated by two methods: a single battery measurement or background battery measurements. Single Battery Measurement Set the BATT_ADC_GO bit (Bit 0) in the start ADC measurement SFR (ADCGO, Address 0xD8) to obtain a battery measurement. An interrupt is generated when the conversion is done and when the battery measurement is available in the battery ADC value SFR (BATADC, Address 0xDF). Background Battery Measurements To configure background measurements for the battery, establish a measurement interval in the peripheral ADC strobe period SFR (STRBPER, Address 0xF9). Battery measurements are then performed periodically in the background (see Table 49). When a battery conversion completes, the battery ADC value is compared to the low battery threshold, established in the battery detection threshold SFR (BATVTH, Address 0xFA). If the battery ADC value is below this threshold, a low battery flag is set. This low battery flag is the FBAT bit (Bit 2) in the power manage- ment interrupt flag SFR (IPSMF, Address 0xF8), used for power supply management.

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Rev. B | Page 80 of 152 This low battery flag can be enabled to generate the PSM interrupt by setting the EBAT bit (Bit 2) in the power management interrupt enable SFR (IPSME, Address 0xEC). This method allows battery measurements to take place completely in the background, requiring MCU activity only if the battery drops below a user-specified threshold. T o set up background battery measurements, follow these steps: Configure the battery detection threshold SFR (BATVTH, Address 0xFA) to establish a low battery threshold. If the BATADC measurement is below this threshold, the FBAT bit (Bit 2) in the power management interrupt flag SFR (IPSMF, Address 0xF8) is set. Set up the interval for background battery measurements by configuring the BATT_PERIOD bits in the peripheral ADC strobe period SFR (STRBPER, Address 0xF9). Battery ADC in PSM0, PSM1, and PSM2 Modes Depending on the operating mode, a battery conversion is initiated only by certain actions.

• In PSM0 operating mode, the 8052 is active. Battery measurements are available in the background measure- ment mode and by initiating a single measurement. In PSM1 operating mode, the 8052 is active and the part is battery powered. Single battery measurements can be initiated by setting the BATT_ADC_GO bit (Bit 0) in the start ADC measurement SFR (ADCGO, Address 0xD8). Background battery measurements are not available. In PSM2 operating mode, the 8052 is not active. Unlike temperature and VDCIN measurements, the battery conversions are not available in this mode. Battery ADC Interrupt The battery ADC can generate an ADC interrupt when at least one of the following conditions occurs: The new battery ADC value is smaller than the value set in the battery detection threshold SFR (BATVTH, Address 0xFA), indicating a battery voltage loss.
• A single battery measurement initiated by setting the BATT_ADC_GO bit finishes. When the battery flag (FBAT, Bit 2) is set in the power manage- ment interrupt flag SFR (IPSMF, Address 0xF8), a new ADC value is available in the battery ADC value SFR (BATADC, Address 0xDF). This battery flag can be enabled as a source of the PSM interrupt to generate a PSM interrupt every time the battery drops below a set voltage threshold or after a single conversion initiated by setting the BATT_ADC_GO bit is ready. The battery ADC value SFR (BATADC, Address 0xDF) is updated with a new value only when the battery flag (FBAT) is set in the power management interrupt flag SFR (IPSMF , Address 0xF8). EXTERNAL VOLTAGE MEASUREMENT The ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 include a dedicated ADC to provide a digital measurement of an external voltage on the VDCIN pin. An 8-bit SFR, the VDCIN ADC value SFR (VDCINADC, Address 0xEF), holds the results of the conversion. The resolution of the external voltage measure- ment is 15.3 mV/LSB. There are two ways to initiate an external voltage conversion: a single external voltage measurement or background external voltage measurements. Single External Voltage Measurement To obtain an external voltage measurement, set the VDCIN_ADC_GO bit (Bit 2) in the start ADC measurement SFR (ADCGO, Address 0xD8). An interrupt is generated when the conversion is done and when the external voltage measure- ment is available in the V DCIN ADC value SFR (VDCINADC, Address 0xEF). Background External Voltage Measurements Background external voltage measurements are disabled by default. To configure the background external voltage measurement mode, set an external voltage measurement interval in the peripheral ADC strobe period SFR (STRBPER, Address 0xF9). External voltage measurements are performed periodically in the background (see Table 49). When an external voltage conversion is complete, the new external voltage ADC value is compared to the last external voltage ADC value that created an interrupt. If the absolute diff- erence between the two values is greater than the setting in the VDCIN_DIFF[2:0] bits in the temperature and supply delta SFR (DIFFPROG, Address 0xF3), a V DCIN ADC flag is set. This VDCIN ADC flag is FV ADC (Bit 3) in the power management interrupt flag SFR (IPSMF, Address 0xF8), which is used for power supply management. This V DCIN ADC flag can be enabled to generate a PSM interrupt by setting the EV ADC bit (Bit 3) in the power management interrupt enable SFR (IPSME, Address 0xEC). This method allows external voltage measurements to take place completely in the background, requiring MCU activity only if the external voltage has changed more than a configurable delta. To set up background external voltage measurements, follow these steps: Initiate a single external voltage measurement by setting the VDCIN_ADC_GO bit (Bit 2) in the start ADC measurement SFR (ADCGO, Address 0xD8). Upon completion of this measurement, configure the VDCIN_DIFF[2:0] bits to establish the change in voltage that sets the FVDCIN bit (Bit 0) in the power management interrupt flag SFR (IPSMF, Address 0xF8). Set up the interval for background external voltage measure- ments by configuring the VDCIN_PERIOD bits in the peripheral ADC strobe period SFR (STRBPER, Address 0xF9).

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Rev. B | Page 81 of 152 External Voltage ADC in PSM0, PSM1, and PSM2 Modes An external voltage conversion is initiated only by certain actions that depend on the operating mode of the ADE7156/ADE7166/ ADE7169/ADE7566/ADE7569. In PSM0 operating mode, the 8052 is active. External voltage measurements are available in the background measurement mode and by initiating a single measurement. In PSM1 operating mode, the 8052 is active and the part is powered from battery. Single external voltage measurements can be initiated by setting the VDCIN_ADC_GO bit (Bit 2) in the start ADC measurement SFR (ADCGO, Address 0xD8). Background external voltage measurements are not available. In PSM2 operating mode, the 8052 is not active. External voltage conversions are available through the background measurement mode only. The external voltage ADC in the V DCIN ADC value SFR (VDCINADC, Address 0xEF) is updated with a new value only when an external voltage ADC interrupt occurs. External Voltage ADC Interrupt The external voltage ADC can generate an ADC interrupt when at least one of the following conditions occurs:

• The difference between the new external voltage ADC value and the last external voltage ADC value generating an ADC interrupt is larger than the value set in the VDCIN_DIFF[2:0] bits in the temperature and supply delta SFR (DIFFPROG, Address 0xF3). The external voltage ADC conversion initiated by setting VDCIN_ADC_GO, finishes. When the ADC interrupt occurs, a new value is available in the V DCIN ADC value SFR (VDCINADC, Address 0xEF). Note that there is no flag associated with this interrupt.

8052 MCU CORE ARCHITECTURE

ADE7169/ADE7566/ADE7569 via the SFR area. between the CPU and all on-chip peripherals.

256 BYTES XRAM OTHER ON-CHIP

• SERIAL I/O
• WDT
• TIMERS BATTERY ADC LCD DRIVER TEMPERATURE ADC RTC POWER MANAGEMENT 128-BYTE SPECIAL FUNCTION REGISTER AREAIR STACK

Figure 81. Block Diagram Showing Programming Model via the SFRs The registers used by the MCU are summarized in this section. Table 56. 8052 SFRs PSW 0xD0 Yes Program status word (see Table 57). PCON 0x87 No Program control (see Table 58). DPL 0x82 No Data pointer low (see Table 59). DPH 0x83 No Data pointer high (see Table 60). DPTR 0x82 and 0x83 No Data pointer (see Table 61). SP 0x81 No Stack pointer (see Table 62). CFG 0xAF No Configuration (see Table 63). Table 57. Program Status Word SFR (PSW, Address 0xD0) 7 0xD7 CY Carry flag. Modified by ADD, ADDC, SUBB, MUL, and DIV instructions. 6 0xD6 AC Auxiliary carry flag. Modified by ADD and ADDC instructions. 5 0xD5 F0 General-purpose flag available to the user. [4:3] 0xD4, 0xD3 RS1, RS0 Register bank select bits. 2 0xD2 OV Overflow flag. Modified by ADD, ADDC, SUBB, MUL, and DIV instructions. 1 0xD1 F1 General-purpose flag available to the user.

Table 58. Program Control SFR (PCON, Address 0x87) 7 SMOD 0 Double baud rate control. [6:0] Reserved 0 Reserved. These bits must be kept at 0 for proper operation. Table 59. Data Pointer Low SFR (DPL, Address 0x82) [7:0] DPL 0 These bits contain the low byte of the data pointer. Table 60. Data Pointer High SFR (DPH, Address 0x83) [7:0] DPH 0 These bits contain the high byte of the data pointer. Table 61. Data Pointer SFR (DPTR, Address 0x82 and Address 0x83) Table 62. Stack Pointer SFR (SP, Address 0x81) [7:0] SP 7 These bits contain the eight LSBs of the pointer for the stack. Table 63. Configuration SFR (CFG, Address 0xAF) 7 Reserved 1 Reserved. This bit should be left set for proper operation. 6 EXTEN 0 Enhanced UART enable bit. 0 Standard 8052 UART without enhanced error-checking features.

1 Enhanced UART with enhanced error checking (see the UART Additional

5 SCPS 0 Synchronous communication selection bit. 0 I 2C port is selected for control of the shared I2C/SPI pins and SFRs. 1 SPI port is selected for control of the shared I2C/SPI pins and SFRs. 4 MOD38EN 0 38 kHz modulation enable bit. 0 38 kHz modulation is disabled. bits in the extended port configuration SFR (EPCFG, Address 0x9F). [3:2] Reserved 00 Reserved. These bits should be kept at 0 for proper operation. XREN1 OR XREN0 = 1 Enable MOVX instruction to use 256 bytes of extended RAM. XREN1 AND XREN0 = 0 Disable MOVX instruction.

JMP instructions that change which part of the program is active. the program status word SFR (PSW , Address 0xD0). in the SFR space (see Table 56). in the SFR space (see Table 56). (see the 8052 MCU Core Architecture section). addition to the stack is the first to come off it. for interrupts to keep track of the prior state of the PC. SP register holds the address of the stack in the extended RAM. Data can still be stored in XRAM by using the MOVX command.

256 BYTES OF

Figure 82. Extended Stack Pointer Operation

port interfaces, interrupts, I/O ports, and power-down modes. There is a two-tiered interrupt system standard in the 8052 core. the Interrupt System section. others that can be configured as LCD or general-purpose I/O. do not allow access to external code and data spaces. disabled to make open-drain outputs, as is standard on Port 0. 0x87) is not bit addressable. See the Power Management section.

• RTC
• LCD driver
• Battery switchover/power management
• Temperature ADC
• Battery ADC
• SPI/I2C communication
• Flash memory controller
• Watchdog timer MEMORY OVERVIEW The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 contain three memory blocks:
• 16 kB of on-chip Flash/EE program and data memory
• 256 bytes of general-purpose RAM
• 256 bytes of internal extended RAM (XRAM) The 256 bytes of general-purpose RAM share the upper 128 bytes of its address space with the SFRs. All of the memory spaces are shown in Figure 81. The addressing mode specifies which memory space to access. General-Purpose RAM General-purpose RAM resides in Memory Location 0x00 through Memory Location 0xFF. It contains the register banks. 11 RESET VALUE OF STACK POINTER FOUR BANKS OF EIGHT REGISTERS R0 TO R7 BIT-ADDRESSABLE (BIT ADDRESSES) GENERAL-PURPOSE AREA BANKS SELECTED VIA BITS IN PSW 0x08 0x10 0x18 0x20 0x30 0x07 0x0F 0x17 0x1F 0x2F 0x7F 06353-058

Figure 83. Lower 128 Bytes of Internal Data Memory

which memory space is accessed, as shown in Figure 84. Figure 84. General-Purpose RAM and SFR Memory Address Overlap address space with the SFRs. Address 0x20 through Address 0x2F can be seen in Figure 85. Figure 85. Bit Addressable Area of General-Purpose RAM only through direct addressing as shown in Figure 84. Figure 86. Extended Internal RAM (XRAM) Space memory, code indirect addressing is used. code. There are six addressing modes, as shown in Table 64. Table 64. 8052 Addressing Modes

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Rev. B | Page 87 of 152 Immediate Addressing In immediate addressing, the expression entered after the number sign (#) is evaluated by the assembler and stored in the memory address specified. This number is referred to as a literal because it refers only to a value and not to a memory location. Instructions using this addressing mode are slower than those between two registers because the literal must be stored and fetched from memory. The expression can be entered as a symbolic variable or as an arithmetic expression; the value is computed by the assembler. Direct Addressing With direct addressing, the value at the source address is moved to the destination address. Direct addressing provides the fastest execution time of all the addressing modes when an instruction is performed between registers. Note that indirect or direct addressing modes can be used to access general-purpose RAM Address 0x00 through Address 0x7F. An instruction with direct addressing that uses an address between 0x80 and 0xFF refers to a special function memory location. Indirect Addressing With indirect addressing, the value pointed to by the register is moved to the destination address. For example, to move the contents of internal RAM Address 0x82 to the accumulator, use the following two instructions, which require a total of four clock cycles and three bytes of storage in the program memory: MOV R0,#82h MOV A,@R0 Indirect addressing allows addresses to be computed and is useful for indexing into data arrays stored in RAM. Note that an instruction that refers to Address 0x00 through Address 0x7F is referring to internal RAM, and indirect or direct addressing mode can be used. An instruction with indirect addressing that uses an address between 0x80 and 0xFF refers to internal RAM, not to an SFR. Extended Direct Addressing The DPTR register (see Table 61) is used to access internal extended RAM in extended indirect addressing mode. The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 have 256 bytes of XRAM, accessed through MOVX instructions. External memory spaces are not supported on this device. In extended direct addressing mode, the DPTR register points to the address of the byte of extended RAM. The following code moves the contents of extended RAM Address 0x100 to the accumulator: MOV DPTR,#100h MOVX A,@DPTR These two instructions require a total of seven clock cycles and four bytes of storage in the program memory. Extended Indirect Addressing The internal extended RAM is accessed through a pointer to the address in indirect addressing mode. The ADE7116/ADE7156/ ADE7166/ADE7169/ADE7566/ADE7569 have 256 bytes of internal extended RAM, accessed through MOVX instructions. External memory is not supported on the devices. In extended indirect addressing mode, a register holds the address of the byte of extended RAM. The following code moves the contents of extended RAM Address 0x80 to the accumulator: MOV R0,#80h MOVX A,@R0 These two instructions require six clock cycles and three bytes of storage. Note that there are 256 bytes of extended RAM, so both extended direct and extended indirect addressing can cover the whole address range. There is a storage and speed advantage to using extended indirect addressing because the additional byte of addressing available through the DPTR register that is not needed is not stored. From the three examples demonstrating the access of internal RAM from 0x80 through 0xFF and extended internal RAM from 0x00 through 0xFF, it can be seen that it is most efficient to use the entire internal RAM accessible through indirect access before moving to extended RAM. Code Indirect Addressing The internal code memory can be accessed indirectly. This can be useful for implementing lookup tables and other arrays of constants that are stored in flash memory. For example, to move the data stored in flash memory at Address 0x8002 into the accumulator, use the following code: MOV DPTR,#8002h CLR A MOVX A,@A+DPTR The accumulator can be used as a variable index into the array of flash memory located at DPTR.

resulting in a 4-MIPS peak performance. Note that throughout this section, A represents the accumulator. Table 65. Instruction Set

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Rev. B | Page 89 of 152 Mnemonic Description Bytes Cycles RLC A Rotate A left through carry 1 1 RR A Rotate A right 1 1 RRC A Rotate A right through carry 1 1 Data Transfer MOV A,Rn Move register to A 1 1 MOV A,@Ri Move indirect memory to A 1 2 MOV Rn,A Move A to register 1 1 MOV @Ri,A Move A to indirect memory 1 2 MOV A,dir Move direct byte to A 2 2 MOV A,#data Move immediate to A 2 2 MOV Rn,#data Move register to immediate 2 2 MOV dir,A Move A to direct byte 2 2 MOV Rn,dir Move register to direct byte 2 2 MOV dir,Rn Move direct to register 2 2 MOV @Ri,#data Move immediate to indirect memory 2 2 MOV dir,@Ri Move indirect to direct memory 2 2 MOV @Ri,dir Move direct to indirect memory 2 2 MOV dir,dir Move direct byte to direct byte 3 3 MOV dir,#data Move immediate to direct byte 3 3 MOV DPTR,#data Move immediate to data pointer 3 3 MOVC A,@A+DPTR Move code byte relative DPTR to A 1 4 MOVC A,@A+PC Move code byte relative PC to A 1 4 MOVX A,@Ri Move external (A8) data to A 1 4 MOVX A,@DPTR Move external (A16) data to A 1 4 MOVX @Ri,A Move A to external data (A8) 1 4 MOVX @DPTR,A Move A to external data (A16) 1 4 PUSH dir Push direct byte onto stack 2 2 POP dir Pop direct byte from stack 2 2 XCH A,Rn Exchange A and register 1 1 XCH A,@Ri Exchange A and indirect memory 1 2 XCHD A,@Ri Exchange A and indirect memory nibble 1 2 XCH A,dir Exchange A and direct byte 2 2 Boolean CLR C Clear carry 1 1 CLR bit Clear direct bit 2 2 SETB C Set carry 1 1 SETB bit Set direct bit 2 2 CPL C Complement carry 1 1 CPL bit Complement direct bit 2 2 ANL C,bit AND direct bit and carry 2 2 ANL C,/bit AND direct bit inverse to carry 2 2 ORL C,bit OR direct bit and carry 2 2 ORL C,/bit OR Direct bit inverse to carry 2 2 MOV C,bit Move direct bit to carry 2 2 MOV bit,C Move carry to direct bit 2 2 Branching JMP @A+DPTR Jump indirect relative to DPTR 1 3 RET Return from subroutine 1 4 RETI Return from interrupt 1 4 ACALL addr11 Absolute jump to subroutine 2 3 AJMP addr11 Absolute jump unconditional 2 3 SJMP rel Short jump (relative address) 2 3 JC rel Jump on carry equal to 1 2 3

Some 8052 instructions read the latch and others read the pin. The state of the pin is read for instructions that input a port bit. that read a value, possibly change it, and rewrite it to the latch. rather than the pin returns the correct value of 1. called read-modify-write instructions and are listed in Table 66. instructions read the latch rather than the pin. Table 66. Read-Modify-Write Instructions

1 These instructions read the port byte (all eight bits), modify the addressed

bit, and write the new byte back to the latch. affect status flags are listed in this section. flags are referenced by the instruction. Table 67. ADD A (Source) Affected Status Flags C Set if there is a carry out of Bit 7. Cleared otherwise. AC Set if there is a carry out of Bit 3. Cleared otherwise. mulator. The carry status flag is referenced by the instruction. Table 68. ADDC A (Source) Affected Flags C Set if there is a carry out of Bit 7. Cleared otherwise. AC Set if there is a carry out of Bit 3. Cleared otherwise.

Table 69. SUBB A (Source) Affected Status Flags negative number yields a positive result. AC Set if a borrow is needed for Bit 3. Cleared otherwise. register. No status flags are referenced by the instruction. Table 70. MUL AB Affected Status Flags OV Set if the result is greater than 255. Cleared otherwise. in the accumulator and the remainder goes into the B register. No status flags are referenced by the instruction. Table 71. DIV AB Affected Status Flags The carry and AC status flags are referenced by this instruction. Table 72. DA A Affected Status Flag The carry status flag is referenced by this instruction. Table 73. RRC A Affected Status Flag The carry status flag is referenced by this instruction. Table 74. RLC A Affected Status Flag continues with the instruction after the CJNE instruction. No status flags are referenced by this instruction. Table 75. CJNE Destination (Source, Relative Jump) Affected

an automatic data pointer toggle. automatically postincrement and postdecrement the DPTR. postincrement and postdecrement. Table 76. Data Pointer Control SFR (DPCON, Address 0xA7) 7 0 Not implemented. Write don’t care. 6 DPT 0 Data pointer automatic toggle enable. Cleared by the user to disable autoswapping of the DPTR. Set in user software to enable automatic toggling of the DPTR after each MOVX or MOVC instruction. allowing more compact and more efficient code size and execution. 0 1 DPTR is postincremented after a MOVX or a MOVC instruction. 1 0 DPTR is postdecremented after a MOVX or MOVC instruction. useful for moving 8-bit blocks to/from 16-bit devices. more compact and more efficient code size and execution. 0 1 DPTR is postincremented after a MOVX or a MOVC instruction. 1 0 DPTR is postdecremented after a MOVX or MOVC instruction. for moving 8-bit blocks to/from 16-bit devices. 1 0 Not implemented. Write don’t care. pointer, meaning that the contents of a separate 16-bit register appear in the DPL SFR and DPH SFR.

Table 79. Interrupt Priority SFR (IP, Address 0xB8) 7 0xBF PADE ADE energy measurement interrupt Priority (1 = high, 0 = low). 6 0xBE PTEMP Temperature ADC interrupt priority (1 = high, 0 = low). 5 0xBD PT2 Timer 2 interrupt priority (1 = high, 0 = low). 4 0xBC PS UART serial port interrupt priority (1 = high, 0 = low). 3 0xBB PT1 Timer 1 interrupt priority (1 = high, 0 = low). 2 0xBA PX1 INT1 (External Interrupt 1) priority (1 = high, 0 = low). 1 0xB9 PT0 Timer 0 interrupt priority (1 = high, 0 = low). 0 0xB8 PX0 INT0 (External Interrupt 0) priority (1 = high, 0 = low). Table 80. Interrupt Enable and Priority 2 SFR (IEIP2, Address 0xA9)

7 Reserved

6 PTI RTC interrupt priority (1 = high, 0 = low).

5 Reserved

4 PSI SPI/I2C interrupt priority (1 = high, 0 = low). 3 EADE Enables the energy metering interrupt (ADE). Set by the user. 2 ETI Enables the RTC interval timer interrupt. Set by the user. 1 EPSM Enables the PSM power supply management interrupt. Set by the user. 0 ESI Enables the SPI/I2C interrupt. Set by the user. If two interrupts of the same priority level occur simultaneously, the polling sequence is observed (as shown in Table 81). Table 81. Priority Within Interrupt Level IPSM 0 (highest) Power supply monitor interrupt. IRTC 1 RTC interval timer interrupt. IADE 2 ADE energy measurement interrupt. WDT 3 Watchdog timer overflow interrupt. TF0 6 Timer/Counter 0 interrupt. TF1 8 Timer/Counter 1 Interrupt. ISPI/I2CI 9 SPI/I2C interrupt. RI/TI 10 UART serial port interrupt. TF2/EXF2 11 (lowest) Timer/Counter 2 interrupt. 1 This feature is not available in the ADE7116.

*NOT AVAILABLE IN THE ADE7116. Figure 89. Interrupt System Functional Block Diagram

Table 84. Interrupt Vector Addresses 1 This feature is not available in the ADE7116. access of the IP and IE SFRs. latency of 16.25 instruction cycles, 4 μs with a clock of 4.096 MHz.

a predetermined amount of time (set by the PRE bits). crystal connected between the XTAL1 and XTAL2 pins. every write access to the WDCON SFR. 0x3FFA (see the Protecting the Flash section). Table 85. Watchdog Timer SFR (WDCON, Address 0xC0) interrupt when the watchdog timeout period has expired. interrupt, depending on the WDIR bit.

Table 86. Watchdog and Flash Protection Byte in Flash (Flash Address = 0x3FFA) 7 WDPROT_PROTKY7 1 This bit holds the protection for the watchdog timer and the seventh bit of the flash protection key. timeout in the PRE bits can still be modified by user code. Protecting the Flash section for more information on how to clear this bit). instruction must be a write instruction to the WDCON SFR. the consecutive instruction cycles. allows the watchdog to be used as a long interval timer. in the interrupt enable SFR (IE, Address 0xA8; see Table 78). kept active to watch over the program.

ladder for LCD waveform voltage generation is also supported. operating modes (see the Operating Modes section). SFR (LCDSEGE2, Address 0xED). Table 87. LCD Driver SFRs 0x95 R/W LCDCON LCD configuration SFR (see Table 88). 0x97 R/W LCDSEGE LCD segment Enable (see Table 95). 0x9C R/W LCDCONX LCD configuration X (see Table 89). 0xAC R/W LCDPTR LCD pointer (see Table 96). 0xAE R/W LCDDAT LCD data (see Table 97). 0xB1 R/W LCDCONY LCD configuration Y (see Table 91). 0xED R/W LCDSEGE2 LCD segment Enable 2 (see Table 98). Table 88. LCD Configuration SFR (LCDCON, Address 0x95) 7 LCDEN 0 LCD enable. If this bit is set, the LCD driver is enabled. 6 LCDRST 0 LCD data registers reset. If this bit is set, the LCD data registers are reset to 0. BLKMOD and BLKFREQ bits in the LCD clock SFR (LCDCLK, Address 0x96).

0 The LCD is disabled or enabled in PSM2 by the LCDEN bit

1 The LCD is disabled in PSM2 regardless of LCDEN setting

3 CLKSEL 0 LCD clock selection. [1:0] LMUX 0 LCD multiplex level. 01 2× multiplexing. FP27/COM3 is used as FP27, and FP28/COM2 is used as FP28. 10 3× multiplexing. FP27/COM3 is used as FP27, and FP28/COM2 is used as COM2. 11 4× multiplexing. FP27/COM3 is used as COM3, and FP28/COM2 is used as COM2.

Table 89. LCD Configuration X SFR (LCDCONX, Address 0x9C) 6 EXTRES 0 External resistor ladder selection bit. 0 External resistor ladder is disabled. Charge pump is enabled. 1 External resistor ladder is enabled. Charge pump is disabled. 1 This feature is not available in the ADE7116. Table 90. LCD Bias Voltage When Contrast Control Is Enabled1 1 This feature is not available in the ADE7116. Table 91. LCD Configuration Y SFR (LCDCONY, Address 0xB1) 7 Reserved 0 This bit should be kept cleared for proper operation. cleared, frames are not inverted. [5:2] Reserved 0000 These bits should be kept cleared to 0 for proper operation. LCD memory has been updated and a new frame has begun. Table 92. LCD Clock SFR (LCDCLK, Address 0x96) [7:6] BLKMOD 0 Blink mode clock source configuration bits. 00 The blink rate is controlled by software; the display is off. 01 The blink rate is controlled by software; the display is on. 11 The blink rate is set by BLKFREQ. [5:4] BLKFREQ 0 Blink rate configuration bits. These bits control the LCD blink rate if the BLKMOD bits = 11. [3:0] FD 0 LCD frame rate selection bits. See Table 93 and Table 94.

Table 93. LCD Frame Rate Selection for fLCDCLK = 2048 Hz (LCDCON[3] = 0) 1 Not within the range of typical LCD frame rates. Table 94. LCD Frame Rate Selection for fLCDCLK = 128 Hz (LCDCON[3] = 1) 1 Not within the range of typical LCD frame rates.

Table 95. LCD Segment Enable SFR (LCDSEGE, Address 0x97) 7 FP25EN 0 FP25 function select bit. 0 = general-purpose I/O, 1 = LCD function. 6 FP24EN 0 FP24 function select bit. 0 = general-purpose I/O, 1 = LCD function. 5 FP23EN 0 FP23 function select bit. 0 = general-purpose I/O, 1 = LCD function. 4 FP22EN 0 FP22 function select bit. 0 = general-purpose I/O, 1 = LCD function. 3 FP21EN 0 FP21 function select bit. 0 = general-purpose I/O, 1 = LCD function. 2 FP20EN 0 FP20 function select bit. 0 = general-purpose I/O, 1 = LCD function. [1:0] Reserved 0 These bits must be kept at 0 for proper operation. Table 96. LCD Pointer SFR (LCDPTR, Address 0xAC) written to the address indicated by the ADDRESS bits (LCDPTR, Address 0xAC). [5:0] ADDRESS 0 LCD memory address (see Table 99). Table 97. LCD Data SFR (LCDDAT, Address 0xAE) [7:0] LCDDATA 0 Data to be written into or read out of the LCD memory SFRs. Table 98. LCD Segment Enable 2 SFR (LCDSEGE2, Address 0xED) 3 FP19EN 0 FP19 function select bit. 0 = general-purpose I/O, 1 = LCD function. 2 FP18EN 0 FP18 function select bit. 0 = general-purpose I/O, 1 = LCD function. 1 FP17EN 0 FP17 function select bit. 0 = general-purpose I/O, 1 = LCD function. 0 FP16EN 0 FP16 function select bit. 0 = general-purpose I/O, 1 = LCD function. should be set according to the LCD specifications. addition, a faster refresh rate consumes more power. independent of the multiplex level.

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Rev. B | Page 104 of 152 The LCD waveform frequency, fLCD, is the frequency at which the LCD switches the active common line. Thus, the LCD waveform frequency depends heavily on the multiplex level. The frame rate and LCD waveform frequency are set by f LCDCLK, the multiplex level, and the FD[3:0] frame rate selection bits in the LCD clock SFR (LCDCLK, Address 0x96). The LCD module provides 16 different frame rates for fLCDCLK = 2048 Hz, ranging from 8 Hz to 128 Hz for an LCD with 4× multiplexing. Fewer options are available with f LCDCLK = 128 Hz, ranging from 8 Hz to 32 Hz for a 4× multi- plexed LCD. The 128 Hz clock is beneficial for battery operation because it consumes less power than the 2048 Hz clock. The frame rate is set by the FD bits in the LCD clock SFR (LCDCLK, Address 0x96); see Table 93 and Table 94. The LCD waveform is inverted at twice the LCD waveform frequency, fLCD. This way, each frame has an average dc offset of 0. ADC offset degrades the lifetime and performance of the LCD. BLINK MODE Blink mode is enabled by setting the BLINKEN bit (Bit 5) in the LCD Configuration SFR (LCDCON, Address 0x95). This mode is used to alternate between the LCD on state and LCD off state so that the LCD screen appears to blink. There are two blinking modes: a software controlled blink mode and an automatic blink mode. Software Controlled Blink Mode The LCD blink rate can be controlled by user code with the BLKMOD bits in the LCD clock SFR (LCDCLK, Address 0x96) by toggling the bits to turn the display on and off at a rate determined by the MCU code. Automatic Blink Mode There are five blink rates available if the RTC peripheral is enabled. These blink rates are selected by the BLKMOD and BLKFREQ bits in the LCD clock SFR (LCDCLK, Address 0x96); see Table 92. DISPLAY ELEMENT CONTROL A bank of 15 bytes of data memory located in the LCD module controls the on or off state of each segment of the LCD. The LCD data memory is stored in Address 0 through Address 14 in the LCD module. Each byte configures the on and off states of two segment lines. The LSBs store the state of the even numbered segment lines, and the MSBs store the state of the odd numbered segment lines. For example, LCD Data Address 0 refers to Segment Line 1 and Segment Line 0 (see Table 99). Note that the LCD data memory is maintained in the PSM2 operating mode. The LCD data memory is accessed indirectly through the LCD pointer SFR (LCDPTR, Address 0xAC) and LCD Data SFR (LCDDAT, Address 0xAE). Moving a value to the LCDPTR SFR selects the LCD data byte to be accessed and initiates a read or write operation (see Table 96). Writing to LCD Data Registers To update the LCD data memory, first set the LSB of the LCD Configuration Y SFR (LCDCONY , Address 0xB1) to freeze the data being displayed on the LCD while updating it. This operation ensures that the data displayed on the screen does not change while the data is being changed. Then, move the data to the LCD data SFR (LCDDAT, Address 0xAE) prior to accessing the LCD pointer SFR (LCDPTR, Address 0xAC). When the MSB of the LCD pointer SFR (LCDPTR, Address 0xAC) is set, the content of the LCD data SFR (LCDDAT, Address 0xAE) is transferred to the internal LCD data memory designated by the address in the LCDPTR SFR. Clear the LSB of the LCD Configuration Y SFR (LCDCONY , Address 0xB1) when all of the data memory has been updated to allow the use of the new LCD setup for display. Sample 8052 code to update the segments attached to FP10 and FP11 pins, use the following sample 8052 code: ORL LCDCONY,#01h ;start updating the data MOV LCDDAT,#FFh MOV LCDPTR,#80h OR 05h ANL LCDCONY,#0FEh ;update finished Reading LCD Data Registers When the MSB of the LCD Pointer SFR (LCDPTR, Address 0xAC) is cleared, the content of the LCD data memory address designated by LCDPTR is transferred to the LCD data SFR (LCDDAT, Address 0xAE). Sample 8052 code to read the contents of LCD Data Memory Address 0x07, which holds the on and off state of the segments attached to FP14 and FP15, is as follows. MOV LCDPTR,#07h MOV R1, LCDDAT

Table 99. LCD Data Memory Accessed Indirectly Through LCD Pointer SFR (LCDPTR, Address 0xAC) and LCD Data SFR (LCDDAT, 1 COMx designates the common lines. 2 FPx designates the segment lines. LCDs with the 3.3 V ADE7166/ADE7169/ADE7566/ADE7569.

• Contrast control Lifetime Performance Power Consumption In most LCDs, a high amount of current is required when the LCD waveforms change state. The external resistor ladder option draws a constant amount of current, whereas the charge pump circuitry allows dynamic current consumption. If the LCD module is used with the internal charge pump option when the display is disabled, the voltage generation is disabled so that no power is consumed by the LCD function. This feature results in significant power savings if the display is turned off during battery operation. Contrast Control The electrical characteristics of the liquid in the LCD change over temperature. This requires adjustments in the LCD waveform voltages to ensure a readable display. An added benefit of the internal charge pump voltage generation is a configurable bias voltage that can be compensated over temperature and supply to maintain contrast on the LCD. These compensations can be performed based on the ADE7166/ADE7169/ADE7566/ ADE7569 temperature and supply voltage measurements (see the Temperature, Battery, and Supply Voltage Measurements section). This dynamic contrast control is not easily implemented with external resistor ladder voltage generation. The LCD bias voltage sets the contrast of the display when the charge pump provides the LCD waveform voltages. The ADE7166/ADE7169/ADE7566/ADE7569 provide 64 bias levels selected by the BIASLVL[5:0] bits in the LCD Configuration X SFR (LCDCONX, Address 0x9C). The voltage level on LCDV A, LCDVB, and LCDVC depend on the internal voltage reference value (VREF), BIASLVL[5:0] selection, and the biasing selected as described in Table 90. Lifetime Performance DC offset on a segment degrades its performance over time. The voltages generated through the internal charge pump switch faster than those generated by the external resistor ladder, reducing the likelihood of a dc voltage being applied to a segment and increasing the lifetime of the LCD.

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Rev. B | Page 107 of 152 The LCD is set up with the following 8052 code: ; set up LCD pins to have LCD functionality MOV LCDSEG,#FP20EN+FP21EN+FP22EN+FP23EN MOV LCDSEGX,#FP16EN+FP17EN+FP18EN+FP19EN ; set up LCDCON for fLCDCLK=2048Hz, 1/3 bias and 4x multiplexing MOV LCDCON,#BIAS+LMUX1+LMUX0 ; setup LCDCONX for charge pump and BIASLVL[110111] MOV LCDCONX,#BIASLVL5+BIASLVL4+BIASLVL3+BIASLVL2+BIASLVL1+BIASLVL0 ; set up refresh rate for 64Hz with fLCDCLK=2048Hz MOV LCDCLK,#FD3+FD2+FD1+FD0 ; set up LCD data registers with data to be displayed using ; LCDPTR and LCDDATA registers ; turn all segments on FP27 ON and FP26 OFF ORL LCDCONY,#01h ; start data memory refresh MOV LCDDAT,#F0H MOV LCDPTR, #80h OR 0DH ANL LCDCONY,#0FEh ; end of data memory refresh ORL LCDCON,#LCDEN ; enable LCD To set up the same 3.3 V LCD for use with an external resistor ladder: ; set up LCDCONX for external resistor ladder MOV LCDCONX,#EXTRES

memory that contains the byte must be erased. ADE7569 provide 16 kB of flash program/information memory. to verify that a flash write operation has completed successfully. conventional third party memory programmers. cycling endurance and Flash/EE memory data retention. Initial page erase sequence.

1. Second read/verify sequence.

endurance figure of 20,000 cycles of operation at 25°C. Figure 93. Flash/EE Memory Data Retention

Figure 95. Flash Memory Read/Write/Erase Protection Block Diagram it must be written to before another flash memory operation. increments to continue with the next instruction. to operate as configured throughout the flash memory access. Table 102. Flash Control SFR (ECON, Address 0xB9) during serial mode and parallel download mode but should not be executed by user code. 4 Read byte. The byte in the flash memory addressed by EADRH/EADRL is read into EDATA. 5 Erase Page and Write Byte. The page that holds the byte addressed by EADRH/EADRL is erased. Data in EDATA is then written to the byte of flash memory addressed by EADRH/EADRL. 8 Protect code (see the Protecting the Flash section). Table 103. Flash Key SFR (FLSHKY, Address 0xBA) operation is allowed (see the Protecting the Flash section). Table 104. Flash Protection Key SFR (PROTKY, Address 0xBB) and by writing 0x08 in the ECON SFR. This operation can only be done once. Table 105. Flash Data SFR (EDATA, Address 0xBC) [7:0] EDATA 0 Flash pointer data.

Table 106. Flash Write/Erase Protection 0 SFR (PROTB0, Address 0xBD) (see the Protecting the Flash section). Clearing the bits enables the protection. Table 107. Flash Write/Erase Protection 1 SFR (PROTB1, Address 0xBE) (see the Protecting the Flash section). Clearing the bits enables the protection. Table 108. Flash Read Protection SFR (PROTR, Address 0xBF) (see the Protecting the Flash section). Clearing the bits enables the protection. Table 109. Flash Low Byte Address SFR (EADRL, Address 0xC6) Table 110. Flash High Byte Address SFR (EADRH, Address 0xC7) Memory Byte 0x3C00 is accessed. Write 0xF3 into flash memory byte 0x3C00. Erase the page containing Flash Memory Byte 0x3C00.

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Rev. B | Page 112 of 152 Erase All Erase all of the 16 kB flash memory. MOV FLSHKY,#3Bh ; Write Flash security key. MOV ECON,#03h ; Erase all Read Byte Read flash memory byte 0x3C00. MOV EADRH,#3Ch ; Setup byte address MOV EADRL,#00h MOV FLSHKY,#3Bh ; Write Flash security key. MOV ECON,#04h ; Read Byte ; Data is ready in EDATA register Erase Page and Write Byte Erase the page containing flash memory byte 0x3C00 and then write 0xF3 to that address. Note that the other 511 bytes in this page are erased. MOV EDATA,#F3h ; Data to be written MOV EADRH,#3Ch ; Set up byte address MOV EADRL,#00h MOV FLSHKY,#3Bh ; Write flash security key. MOV ECON,#05h ; Erase page and then write byte

Write/erase protection is individually selectable for all 32 pages. minimum, for the entire protection scheme to work. commands from being executed within the code. used as data pointers here but to store write protection data. Figure 96. Flash Protection in Page 31

1. Set up the EADRH, EADRL, PROTB1, and PROTB0 SFRs

memory. The default protection setting is for no protection. the pages that should be protected. T o enable the protection key, write to the PROTKY SFR. value every time the protection functionality is accessed. Reset the chip to activate the new protection. protection bits in the flash.

reserved emulator commands available only in download mode. Protocol, available at www.analog.com.

• Command with ASCII Code I or 0x49 writes the data into R0.
• Command with ASCII Code F or 0x46 writes R0 into the SFR address defined in the data of this command. Omitting the protocol defined in uC004, the sequence to load protections is similar to the sequence mentioned in the Enabling Flash Protection by Code section, except that two emulator commands are necessary to replace one assembly command. For example, to write the protection value in EADRH (Address 0xC7), the following two commands must be executed: Command I with data = value of Protection Byte 0x3FFF.
• Command F with data = 0xC7. With this protocol, the protection can be written to the flash memory using the same sequence as described in the Enabling Flash Protection by Code section. When the part is reset, the protection is effective. Notes on Flash Protection The flash protection scheme is disabled by default so that none of the pages of the flash are protected from reading or writing/ erasing. The last page must be write/erase protected for the protection scheme to work. To activate the protection settings, the ADE7116/ADE7156/ ADE7166/ADE7169/ADE7566/ADE7569 must be reset after configuring the protection. After configuring protection on the last page and resetting the part, protections that have been enabled can be removed only by mass erasing the flash memory. The protection bits are read and erase protected by enabling read and write/erase protection on the last page, but the protection bits are never truly write protected. Protection bits can be modified from a 1 to a 0, even after the last page has been protected. In this way, more protection can be added but none can be removed. When the last page is read protected, the protection bits can still be read by the user code. All other bits on this page are not available for reading. The protection scheme is intended to protect the end system. Pro- tection should be disabled while developing and emulating code. Flash Memory Timing Typical program and erase times for the flash memory are shown in Table 111.

Table 111. Flash Memory Program and Erase Times configured throughout this period. device is in-circuit in its target application hardware. cannot be written or erased.

to operate as timers or as event counters. clock period, the maximum count rate is the core clock frequency. transition, the maximum count rate is half the core clock frequency. operating modes is achieved via the SFRs listed in Table 112. Table 112. Timer SFRs TCON 0x88 Yes Timer/Counter 0 and Timer/Counter 1 control (see Table 114). TMOD 0x89 No Timer/Counter 0 and Timer./Counter 1 mode (see Table 113). TL0 0x8A No Timer 0 low byte (see Table 117). TL1 0x8B No Timer 1 low byte (see Table 119). TH0 0x8C No Timer 0 high byte (see Table 116). TH1 0x8D No Timer 1 high byte (see Table 118). T2CON 0xC8 Yes Timer/Counter 2 control (see Table 115). RCAP2L 0xCA No Timer 2 reload/capture low byte (see Table 123). RCAP2H 0xCB No Timer 2 reload/capture high byte (see Table 122). TL2 0xCC No Timer 2 low byte (Table 121). TH2 0xCD No Timer 2 high byte (see Table 120). Table 113. Timer/Counter 0 and Timer/Counter 1 Mode SFR (TMOD, Address 0x89) TR1 control is set. Cleared by software to enable Timer 1 whenever the TR1 control bit is set. by software to select the timer operation (input from internal system clock). 00 Timer 1 mode select bits. 01 16-bit timer/counter. TH1 and TL1 are cascaded; there is no prescaler. 10 8-bit autoreload timer/counter. TH1 holds a value to reload into TL1 each time it overflows. 2 C/T0 0 Timer 0 timer or counter select bit. Set by software to the select counter operation (input from T0 pin). Cleared by software to the select timer operation (input from internal system clock). 00 Timer 0 mode select bits. 00 TH0 operates as an 8-bit timer/counter. TL0 serves as a 5-bit prescaler. 01 16-bit timer/counter. TH0 and TL0 are cascaded; there is no prescaler. 10 8-bit autoreload timer/counter. TH0 holds a value to reload into TL0 each time it overflows. 8-bit timer only, controlled by Timer 1 control bits.

Table 114. Timer/Counter 0 and Timer/Counter 1 Control SFR (TCON, Address 0x88) when the program counter (PC) vectors to the interrupt service routine. when the PC vectors to the interrupt service routine. when the PC vectors to the interrupt service routine only if the interrupt was transition activated. hardware, controls the request flag. 1-to-0 transition. Cleared by software to specify level sensitive detection, that is, zero level. 1 These bits are not used to control Timer/Counter 0 and Timer/Counter 1 but are instead used to control and monitor the external INT0 and INT1 interrupt pins. Table 115. Timer/Counter 2 Control SFR (T2CON, Address 0xC8) either RCLK = 1 or TCLK = 1. Cleared by user software. negative transition on T2EX pin and EXEN2 = 1. Cleared by user software. to enable Timer 1 overflow to be used for the receive clock. to enable Timer 1 overflow to be used for the transmit clock. port. Cleared by the user for Timer 2 to ignore events at T2EX. 2 0xCA TR2 0 Timer 2 start/stop control bit. Set by the user to start Timer 2. Cleared by the user to stop Timer 2. ignored and the timer is forced to autoreload on Timer 2 overflow.

which is preset by software. The reload leaves TH0 unchanged. Figure 99. Timer/Counter 0, Mode 2 separate counters. This configuration is shown in Figure 100. an extra 8-bit timer or counter. Figure 100. Timer/Counter 0, Mode 3 registers (see Table 120 to Table 123). shown in Table 115 and Table 124. Table 124. T2CON Operating Modes

1 X 1 Baud rate

input, T2EX, which triggers the 16-bit reload and sets EXF2. Autoreload mode is shown in Figure 101. by RCLK = 1 and/or TCLK = 1.

ADE7569 are intended for use with a 32.768 kHz watch crystal. the POWCON SFR, a key is required to modify the register. key, 0xA7, and then a new value is written to the POWCON SFR. is set in the peripheral configuration SFR (PERIPH, Address 0xF4). Table 125. Power Control SFR (POWCON, Address 0xC5) metering functions are not needed in PSM0. 5 Reserved 0 This bit should be kept at 0 for proper operation. 4 COREOFF 0 Set this bit to 1 to shut down the core if in the PSM1 operating mode. [2:0] CD 010 Controls the core clock frequency (f CORE). fCORE = 4.096 MHz/2CD. Table 126. Key SFR (KYREG, Address 0xC1) [7:0] KYREG 0 Write 0xA7 to the KYREG SFR before writing to the POWCON SFR to unlock it.

Table 128. RTC Configuration SFR (TIMECON, Address 0xA1) RTC interrupt must be serviced and the flag cleared to be allowed to enter PSM2 mode. 0 256-hour mode. The HOUR register rolls over from 255 to 0. 1 24-hour mode. The HOUR register rolls over from 23 to 0. [5:4] ITS 0 Interval timer time base selection. 3 SIT 0 Interval Timer 1 alarm. 0 The ALARM flag is set after INTVAL counts, and then another interval count starts. 1 The ALARM flag is set after one time interval. by the user to indicate that the alarm event has been serviced. This bit cannot be set to 1 by user code. 1 ITEN 0 Interval timer enable. 0 The interval timer is disabled. The 8-bit interval timer counter is reset. 1 Set this bit to enable the interval timer. 0 Reserved 1 This bit must be left set for proper operation. Table 129. Hundredths of a Second Counter SFR (HTHSEC, Address 0xA2) reset or an external reset. It is reset after a POR. Table 130. Seconds Counter SFR (SEC, Address 0xA3) external reset. It is reset after a POR. Table 131. Minutes Counter SFR (MIN, Address 0xA4) external reset. It is reset after a POR. Table 132. Hours Counter SFR (HOUR, Address 0xA5) a watchdog reset or an external reset. It is reset after a POR.

Table 133. RTC Alarm Interval SFR (INTVAL, Address 0xA6) Table 134. RTC Nominal Compensation SFR (RTCCOMP, Address 0xF6) or an external reset. It is reset after a POR. Table 135. RTC Temperature Compensation SFR (TEMPCAL, Address 0xF7) register is retained during a watchdog reset or an external reset. It is reset after a POR. Table 136. Interrupt Pins Configuration SFR (INTPR, Address 0xFF) is output on the P0.2/CF1/RTCCAL pin. [6:5] FSEL Sets RTC calibration output frequency and calibration window.

4 Reserved

[3:1] INT1PRG 000 Controls the function of the INT1 pin. 0 INT0PRG 0 Controls the function of the INT0 pin. Table 137. Key SFR (KYREG, Address 0xC1) [7:0] KYREG 0 Write 0xA7 to this SFR before writing to the POWCON SFR, which unlocks KYREG.

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Rev. B | Page 124 of 152 READ AND WRITE OPERATIONS Writing to the RTC Registers The RTC circuitry runs off a 32.768 kHz clock. The timekeeping registers, the hundredths of a second counter SFR (HTHSEC, Address 0xA2), seconds counter SFR (SEC, Address 0xA3), minutes counter SFR (MIN, Address 0xA4), and hours counter SFR (HOUR, Address 0xA5), are updated with a 32.768 kHz clock. However, the RTC configuration SFR (TIMECON, Address 0xA1) and alarm interval SFR (INTV AL, Address 0xA6) are updated with a 128 Hz clock. It takes up to two 128 Hz clock cycles from when the MCU writes to the TIMECON SFR or INTV AL SFR until there is a successful update in the RTC. To protect the RTC timekeeping registers from runaway code, a key must be written to the Key SFR (KYREG, Address 0xC1), which is described in Table 126, to obtain write access to the HTHSEC, SEC, MIN and HOUR SFRs. KYREG should be set to 0xEA to unlock the timekeeping registers and reset to 0 after a timekeeping register is written to. The RTC registers can be written to using the following 8052 assembly code: MOV RTCKey,#0EAh CALL UpdateRTC UpdateRTC: MOV KYREG,RTCKey MOV SEC,#30 MOV KYREG,RTCKey MOV MIN,#05 MOV KYREG,RTCKey MOV HOUR,#04 MOV KYREG,#00h RET Reading the RTC Counter SFRs The RTC cannot be stopped to read the current time because stopping the RTC introduces an error in its timekeeping. Therefore, the RTC is read on the fly, and the counter registers must be checked for overflow. This can be accomplished through the following 8052 assembly code: ReadAgain: MOV R0,HTHSEC ; using Bank 0 MOV R1,SEC MOV R2,MIN MOV R3,HOUR MOV A,HTHSEC CJNE A, 00h, ReadAgain ; 00h is R0 in Bank 0 RTC MODES The RTC can be configured in a 24-hour mode or a 256-hour mode. A midnight event is generated when the RTC hour counter rolls over from 23 to 0 or 255 to 0, depending on whether the TFH bit is set in the RTC Configuration SFR (TIMECON, Address 0xA1). The midnight event sets the MIDNIGHT flag in the TIMECON SFR, and a pending RTC interrupt is created. The RTC midnight event wakes the 8052 MCU core if the MCU is asleep in PSM2 mode when the midnight event occurs. In the 24-hour mode, the midnight event is generated once a day at midnight. The 24-hour mode is useful for updating a software calendar to keep track of the current day. The 256-hour mode results in power savings during extended operation in PSM2 mode because the MCU core wakes up less frequently. RTC INTERRUPTS The RTC midnight interrupt and alarm interrupt are enabled by setting the ETI bit in the Interrupt Enable and Priority 2 SFR (IEIP2, Address 0xA9). When a midnight or alarm event occurs, a pending RTC interrupt is generated. If the RTC interrupt is enabled, the program vectors to the RTC interrupt address and the pending interrupt are cleared. If the RTC interrupt is disabled, the RTC interrupt remains pending until the RTC interrupt is enabled. The program then vectors to the RTC interrupt address. The MIDNIGHT flag and ALARM flag are set when the midnight event and alarm event occur, respectively. The user should manage these flags to keep track of which event caused an RTC interrupt by servicing the event and clearing the appropriate flag in the RTC interrupt servicing routine. Note that if the ADE7116/ADE7156/ADE7166/ADE7169/ ADE7566/ADE7569 are awakened by an RTC event, either by the MIDNIGHT event or an ALARM event, the pending RTC interrupt must be serviced before the device can go back to sleep again. The ADE7116/ADE7156/ADE7166/ADE7169/ ADE7566/ADE7569 keep waking up until this interrupt has been serviced. Interval Timer Alarm The RTC can be used as an interval timer. When the interval timer is enabled by setting the ITEN bit in the RTC Configuration SFR (TIMECON, Address 0xA1), the interval timer clock source selected by the ITS1 and ITS0 bits is passed through an 8-bit counter. This counter increments on every interval timer clock pulse until it is equal to the value in the alarm interval SFR (INTV AL, Address 0xA6). Then, an alarm event is generated, setting the ALARM flag and creating a pending RTC interrupt. If the SIT bit in the RTC configuration SFR (TIMECON, Address 0xA1) is cleared, the 8-bit counter is cleared and starts counting again. If the SIT bit is set, the 8-bit counter is held in reset after the alarm occurs.

1. If the alarm interval SFR (INTV AL, Address 0xA6) is going

64,000 cycles at a 4.096 MHz instruction cycle clock. RTC configuration SFR (TIMECON, Address 0xA1). clear. If it is not, wait for another 128 Hz clock cycle. in PSM2 mode when the alarm event occurs. the crystal frequency and its variation over temperature. adding or subtracting pulses from the crystal clock signal. (RTCCOMP , Address 0xF6) is ±2 ppm/LSB or 0.17 sec/day/LSB. these two registers is limited to ±248 ppm or 42.85 sec/day. precisely 32.768 kHz at 25°C. configuration SFR (INTPR, Address 0xFF). FSEL = 10 and 16 kHz with FSEL = 11 in the INTPR SFR. and hours/125 instead of seconds, minutes, and hours. Therefore, this mode should be used for calibration only. Table 138. RTC Calibration Options calibration window to determine the error in the pulse output. pulses on the P0.2/CF1/RTCCAL pin is sufficient. where 1 sec/day error is equal to 11.57 ppm.

1 Errorsec/dayRTCCOMP ××=

on how to read and write to the RTC timekeeping registers.

ADE7569 UART can be configured in one of four modes.

• Shift register with baud rate fixed at fCORE/12
• 8-bit UART with variable baud rate
• 9-bit UART with baud rate fixed at fCORE/64 or fCORE/32
• 9-bit UART with variable baud rate Variable baud rates are defined by using an internal timer to generate any rate between 300 bauds/sec and 115,200 bauds/sec. The UART serial interface provided in the ADE7166/ADE7169/ ADE7566/ADE7569 is a full-duplex serial interface. It is also receive buffered by storing the first received byte in a receive buffer until the reception of the second byte is complete. The physical interface to the UART is provided via the RxD (P1.0/RxD) and TxD (P1.1/TxD) pins, and the firmware interface is through the SFRs presented in Table 139. Both the serial port receive and transmit registers are accessed through the serial port buffer SFR (SBUF, Address 0x99). Writing to SBUF loads the transmit register, and reading SBUF accesses a physically separate receive register. An enhanced UART mode is offered by using the UART timer and by providing enhanced frame error, break error, and overwrite error detection. This mode is enabled by setting the EXTEN bit in the configuration SFR (CFG, Address 0xAF). See the UART Additional Features section. The enhanced serial baud rate control SFR (SBAUDT, Address 0x9E) and UART timer fractional divider SFR (SBAUDF, Address 0x9D) are used to configure the UART timer and to indicate the enhanced UART errors. UART SFRS

Table 139. Serial Port SFRs SCON 0x98 Yes Serial communications control (see Table 140). SBUF 0x99 No Serial port buffer (see Table 141). SBAUDT 0x9E No Enhanced serial baud rate control (see Table 142). SBAUDF 0x9D No UART timer fractional divider (see Table 143). Table 140. Serial Communications Control SFR (SCON, Address 0x98) [7:6] 0x9F , 0x9E SM0, SM1 00 UART serial mode select bits. These bits select the serial port operating mode. 00 Mode 0, shift register, fixed baud rate (fCORE/12). 01 Mode 1, 8-bit UART, variable baud rate. 10 Mode 2, 9-bit UART, fixed baud rate (fCORE/32) or (fCORE/16). 11 Mode 3, 9-bit UART, variable baud rate. Mode 2 and Mode 3 and framing error detection in Mode 1. In Mode 0, SM2 should be cleared. In Mode 1, if SM2 is set, RI is not activated if a valid stop bit was not received. If SM2 is cleared, RI is set as soon as the byte of data is received. In Mode 2 or Mode 3, if SM2 is set, RI is not activated if the received ninth data bit in RB8 is 0. If SM2 is cleared, RI is set as soon as the byte of data is received. 4 0x9C REN 0 Serial port receive enable bit. Set by user software to enable serial port reception. Cleared by user software to disable serial port reception. into RB8. For Mode 1, the stop bit is latched into RB8. at the beginning of the stop bit in Mode 1, Mode 2, and Mode 3. TI must be cleared by user software. halfway through the stop bit in Mode 1, Mode 2, and Mode 3. RI must be cleared by user software.

Table 141. Serial Port Buffer SFR (SBUF, Address 0x99) [7:0] SBUF 0 Serial port data buffer. Table 142. Enhanced Serial Baud Rate Control SFR (SBAUDT, Address 0x9E) prior SBUF data to be lost. Write a 0 to this bit to clear it. only and updated every time a frame is received. bit is updated every time a frame is received. [4:3] SBTH 0 Extended divider ratio for baud rate setting as shown in Table 144. [2:0] DIV 0 Binary divider. See Table 144. Table 143. UART Timer Fractional Divider SFR (SBAUDF, Address 0x9D) bit (PCON[7]), the TCLK bit (T2CON[4]), and the RCLK bit (T2CON[5]) are ignored. Cleared to let the baud rate be generated as per a standard 8052. 6 Not implemented, write don’t care. [5:0] SBAUDF 0 UART timer fractional divider Bit 5.

Table 144. Common Baud Rates Using UART Timer with a 4.096 MHz PLL Clock

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Rev. B | Page 130 of 152 T o transmit, the eight data bits must be written into the serial port buffer SFR (SBUF, Address 0x99). The ninth bit must be written to TB8 (Bit 3) in the serial communications control Register Bit Description SFR (SCON, 0x98). When transmission is initiated, the eight data bits from SBUF are loaded into the transmit shift register (LSB first). The ninth data bit, held in TB8, is loaded into the ninth bit position of the transmit shift register. The transmission starts at the next valid baud rate clock. The serial port transmit interrupt flag (TI, Bit 1) is set as soon as the transmission completes, when the stop bit appears on TxD. All of the following conditions must be met at the time the final shift pulse is generated to receive a character:

• If the extended UART is disabled (EXTEN = 0 in the CFG SFR), RI must be 0 to receive a character. This ensures that the data in SBUF is not overwritten if the last received character has not been read.
• If multiprocessor communication is enabled by setting SM2, the received ninth bit must be set to receive a character. This ensures that only frames with the ninth bit set, which are frames that contain addresses, generate a receive interrupt. If any of these conditions is not met, the received frame is irretrievably lost, and the receive interrupt flag (RI) is not set. Reception for Mode 2 is similar to that of Mode 1. The eight data bytes are input at the RxD pin (LSB first) and loaded onto the receive shift register. If the received frame has met the previous criteria, the following events occur:
• The eight bits in the receive shift register are latched into the SBUF SFR.
• The ninth data bit is latched into RB8 in the SCON SFR.
• The receiver interrupt flag (RI) is set. Mode 3 (9-Bit UART with Variable Baud Rate) Mode 3 is selected by setting both SM0 and SM1. In this mode, the 8052 UART serial port operates in 9-bit mode with a variable baud rate. The baud rate is set by a timer overflow rate. Timer 1 or Timer 2 can be used to generate baud rates, or both timers can be used simultaneously where one generates the transmit rate and the other generates the receive rate. There is also a dedicated timer for baud rate generation, the UART timer, which has a fractional divisor to precisely generate any baud rate (see the UART Timer Generated Baud Rates section). The operation of the 9-bit UART is the same as for Mode 2, but the baud rate can be varied. In all four modes, transmission is initiated by any instruction that uses SBUF as a destination register. Reception is initiated in Mode 0 when RI = 0 and REN = 1. Reception is initiated in the other modes by the incoming start bit if REN = 1. UART BAUD RATE GENERATION Mode 0 Baud Rate Generation The baud rate in Mode 0 is fixed. ⎛= 12 COREfd RateMode 0 Bau Mode 2 Baud Rate Generation The baud rate in Mode 2 depends on the value of the PCON.7 (SMOD) bit in the program control SFR (PCON, 0x87). If SMOD = 0, the baud rate is 1/32 of the core clock. If SMOD = 1, the baud rate is 1/16 of the core clock. Mode 2 Baud Rate = 32 2SMOD × fCORE Mode 1 and Mode 3 Baud Rate Generation The baud rates in Mode 1 and Mode 3 are determined by the overflow rate of the timer generating the baud rate, that is, Timer 1, Timer 2, or the dedicated baud rate generator, UART timer, which has an integer and a fractional divisor. Timer 1 Generated Baud Rates When Timer 1 is used as the baud rate generator, the baud rates in Mode 1 and Mode 3 are determined by the Timer 1 overflow rate. The value of SMOD is as follows: Mode 1 or Mode 3 Baud Rate = ×32 2SMOD Timer 1 Overflow Rate The Timer 1 interrupt should be disabled in this application. The timer itself can be configured for either timer or counter operation and in any of its three running modes. In the most typical application, it is configured for timer operation in autoreload mode (high nibble of TMOD = 0010 binary). In that case, the baud rate is given by the following formula: Mode 1 or Mode 3 Baud Rate = ) 256 ( 32 TH1 fCORE SMOD Timer 2 Generated Baud Rates Baud rates can also be generated by using Timer 2. Using Timer 2 is similar to using Timer 1 in that the timer must overflow 16 times before a bit is transmitted or received. Because Timer 2 has a 16-bit autoreload mode, a wider range of baud rates is possible. Mode 1 or Mode 3 Baud Rate = 16 1 × Timer 2 Overflow Rate Therefore, when Timer 2 is used to generate baud rates, the timer increments every two clock cycles rather than every core machine cycle as before. It increments six times faster than Timer 1, and, therefore, baud rates six times faster are possible.

are synchronously transmitted and simultaneously received. read the last byte of received data while a new byte is shifted in. The SPI port can be configured for master or slave operation. receive buffer SFR (SPI2CRx, Address 0x9B). Table 145. SPI SFR List 0x9A SPI2CTx W 8 0 SPI/I2C transmit buffer (see Table 146). 0x9B SPI2CRx R 8 0 SPI/I2C receive buffer (see Table 147). 0xE8 SPIMOD1 R/W 8 0x10 SPI Configuration SFR 1 (see Table 148). 0xE9 SPIMOD2 R/W 8 0 SPI Configuration SFR 2 (see Table 149). 0xEA SPISTAT R/W 8 0 SPI/I2C interrupt status (see Table 150). Table 146. SPI/I2C Transmit Buffer SFR (SPI2CTx, Address 0x9A) FIFO input. When a write is requested, the FIFO output is sent on the SPI or I2C bus. Table 147. SPI/I2C Receive Buffer SFR (SPI2CRx, Address 0x9B) transferred to SPI2CRx SFR. A new data byte from the SPI or I2C bus is written to the FIFO input.

Table 148. SPI Configuration SFR 1 (SPIMOD1, Address 0xE8) 5 0xED INTMOD 0 SPI interrupt mode. 0 SPI interrupt is set when the SPI Rx buffer is full. 1 SPI interrupt is set when the SPI Tx buffer is empty. transmission and then returns high. continuous transfer and then returns high. 3 0xEB SS_EN 0 Slave mode, SS input enable. 2 0xEA RxOFW 0 Receive buffer overflow write enable.

0 If the SPI2CRx SFR has not been read when a new data byte is received,

1 If the SPI2CRx SFR has not been read when a new data byte is received,

the new byte overwrites the old data. SPIR 0 Master mode, SPI SCLK frequency.

Table 149. SPI Configuration SFR 2 (SPIMOD2, Address 0xE9) 7 SPICONT 0 Master mode, SPI continuous transfer mode enable bit. can be initiated after a stalled period. 1 The SPI interface continues to transfer data until no valid data is available in the SPI2CTx SFR. SS remains asserted until the SPI2CTx SFR and the transmit shift registers are empty. 6 SPIEN 0 SPI interface enable bit. 0 The SPI interface is disabled. 1 The SPI interface is enabled. 5 SPIODO 0 SPI open-drain output configuration bit. 0 Internal pull-up resistors are connected to the SPI outputs. not exceed the specified operating voltage. 4 SPIMS_b 0 SPI master mode enable bit. 0 The SPI interface is defined as a slave. 1 The SPI interface is defined as a master. 3 SPICPOL 0 SPI clock polarity configuration bit (see Figure 112). sampled on the rising or falling edge of SCLK. input is sampled on the falling or rising edge of SCLK. 2 SPICPHA 0 SPI clock phase configuration bit (see Figure 112).

0 The SPI data output changes state when SS goes low at the second edge of SCLK and then every

1 The SPI data output changes state at the first edge of SCLK and then every two subsequent

1 SPILSBF 0 Master mode, LSB first configuration bit. 0 The MSB of the SPI outputs is transmitted first. 1 The LSB of the SPI outputs is transmitted first. 0 TIMODE 1 Transfer and interrupt mode of the SPI interface. 1 This bit must be set to 1 for proper operation.

Table 150. SPI Interrupt Status SFR (SPISTAT, Address 0xEA) 7 BUSY 0 SPI peripheral busy flag. 0 The SPI peripheral is idle. 1 The SPI peripheral is bu sy transferring data in slave or master mode. 6 MMERR 0 SPI multimaster error flag. 0 A multiple master error has not occurred.

1 If the SS_EN bit (SPIMOD1, Address 0xE8) is set, enabling the slave select input and

raised to indicate the error. Write a 0 to this bit to clear it. 5 SPIRxOF 0 SPI receive overflow error flag. Reading the SPI2CRx SFR clears this bit. 0 X The SPI2CRx SFR (Address 0x9B) contains valid data. occurs, SPI2CRx is overwritten. 4 SPIRxIRQ 0 SPI receive mode interrupt flag . Reading the SPI2CRx SFR clears this bit. 0 X The SPI2CRx register does not contain new data. and the SS pin is deasserted. 1 1 The SPI2CRx register contains new data. 3 SPIRxBF 0 Status bit for SPI Rx buffer. When set, the Rx FIFO is full. A read of th e SPI2CRx clears this flag. (Address 0x9A). Write a 0 to this bit to clear it. 1 SPITxIRQ 0 SPI transmit mode interrupt flag. Writ ing new data to the SPI2CTx SFR clears this bit. 0 X The SPI2CTx SFR is full. 1 0 The SPI2CTx SFR is empty. pin is deasserted. Write a 0 to this bit to clear it. 0 SPITxBF 0 Status bit for the SPI Tx buffer. When set, the SPI Tx buffer is full. Write a 0 to this bit to clear it. (8-bit) serial data, MSB first. byte-wide (8-bit) serial data, MSB first. output in master mode and as an input in slave mode. 0xE8) and SPI Configuration SFR 2 (SPIMOD2, Address 0xE9). of the expected input clock.

interface is implemented as a full hardware master. with the MOSI and SCLK pins of the on-chip SPI interface. until the master issues a stop condition and the bus becomes idle. fast mode (256 kHz) or standard mode (32 kHz).

• I2CMOD
• SPI2CSTAT
• I2CADR
• SPI2CTx
• SPI2CRx Because the SPI and I2C serial interfaces share the same pins, they also share the same SFRs, such as the SPI2CTx and SPI2CRx SFRs. In addition, the I2CMOD, I2CADR, and SPI2CSTAT, and SPI2CTx SFRs are shared with the SPIMOD1, SPIMOD2, and SPISTAT SFRs, respectively.

Table 151. I2C SFR List 0x9A SPI2CTx W 8 SPI/I2C transmit buffer (see Table 146). 0x9B SPI2CRx R 8 0 SPI/I2C receive buffer (see Table 147). 0xE8 I2CMOD R/W 8 0 I2C mode (see Table 152). 0xE9 I2CADR R/W 8 0 I2C slave address (see Table 153). 0xEA SPI2CSTAT R/W 8 0 I2C interrupt status register (see Table 154). Table 152. I2C Mode SFR (I2CMOD, Address 0xE8) I2CADR SFR starts a communication. [6:5] 0xEE to 0xED I2CR 0 I2C SCLK frequency. I2CRCT bits + 1 byte have been read, or if an error occurs. Table 153. I2C Slave Address SFR (I2CADR, Address 0xE9) [7:1] I2CSLVADR 0 Address of the I2C slave being addressed. Writing to this register starts the I2C transmission (read or write). I2C bus. Data from the slave in the SPI2CRx SFR (Address 0x9B) is expected after a command byte.

Table 154. I2C Interrupt Status Register SFR (SPI2CSTAT, Address 0xEA) 7 I2CBUSY 0 This bit is set to Logic 1 when the I2C interface is used. When set, the Tx FIFO is emptied. does not send an acknowledgement. The I2C communication is stopped after this event. Write a 0 to this bit to clear it. 5 I2CRxIRQ 0 I2C receive interrupt. This bit is set to Logic 1 when the receive FIFO is not empty. Write a 0 to this bit to clear it. 4 I2CTxIRQ 0 I2C Transmit Interrupt. This bit is set to Logic 1 when the transmit FIFO is empty. Write a 0 to this bit to clear it. used in I2C communication (receive or transmit) because only one FIFO is active at a time.

00 FIFO empty

01 Reserved

10 FIFO half full

11 FIFO full

1 I2CACC_ERR 0 Set when trying to write and read at the same time. Write a 0 to this bit to clear it. 0 I2CTxWR_ERR 0 Set when a write was attempted when the I2C transmit FIFO was full. Write a 0 to this bit to clear it. Figure 113. I2C Read Operation Figure 114. I2C Write Operation start condition and continues with the next communication. Mov a, spi2crx or Mov R0, spi2crx. does not transfer the right data into RAM Address 0x3D.

I2C receive and transmit FIFOs. needed in the transmit shift register, the communication stops. operation, the Tx FIFO is flushed.

4 BYTE FIFO

Figure 115. I2C FIFO Operation

Table 156. Extended Port Configuration SFR (EPCFG, Address 0x9F) 7 MOD38_FP21 0 This bit enables 38 kHz modulation on the P1.6/FP21 pin. 6 MOD38_FP22 0 This bit enables 38 kHz modulation on the P1.5/FP22 pin. 5 MOD38_FP23 0 This bit enables 38 kHz modulation on the P1.4/T2/FP23 pin. 4 MOD38_TxD 0 This bit enables 38 kHz modulation on the P1.1/TxD pin. 3 MOD38_CF1 0 This bit enables 38 kHz modulation on the P0.2/CF1/RTCCAL pin. 2 MOD38_SSb 0 This bit enables 38 kHz modulation on the P0.7/SS/T1 pin. 1 MOD38_MISO 0 This bit enables 38 kHz modulation on the P0.5/MISO pin. 0 MOD38_CF2 0 This bit enables 38 kHz modulation on the P0.3/CF2 pin. Table 157. Port 0 Weak Pull-Up Enable SFR (PINMAP0, Address 0xB2) 7 PINMAP0.7 0 The weak pull-up on P0.7 is disabled when this bit is set. 6 PINMAP0.6 0 The weak pull-up on P0.6 is disabled when this bit is set. 5 PINMAP0.5 0 The weak pull-up on P0.5 is disabled when this bit is set. 4 PINMAP0.4 0 The weak pull-up on P0.4 is disabled when this bit is set. 3 PINMAP0.3 0 The weak pull-up on P0.3 is disabled when this bit is set. 2 PINMAP0.2 0 The weak pull-up on P0.2 is disabled when this bit is set. 1 PINMAP0.1 0 The weak pull-up on P0.1 is disabled when this bit is set. 0 PINMAP0.0 0 The weak pull-up on P0.0 is disabled when this bit is set. Table 158. Port 1 Weak Pull-Up Enable SFR (PINMAP1, Address 0xB3) 7 PINMAP1.7 0 The weak pull-up on P1.7 is disabled when this bit is set. 6 PINMAP1.6 0 The weak pull-up on P1.6 is disabled when this bit is set. 5 PINMAP1.5 0 The weak pull-up on P1.5 is disabled when this bit is set. 4 PINMAP1.4 0 The weak pull-up on P1.4 is disabled when this bit is set. 3 PINMAP1.3 0 The weak pull-up on P1.3 is disabled when this bit is set. 2 PINMAP1.2 0 The weak pull-up on P1.2 is disabled when this bit is set. 1 PINMAP1.1 0 The weak pull-up on P1.1 is disabled when this bit is set. 0 PINMAP1.0 0 The weak pull-up on P1.0 is disabled when this bit is set. Table 159. Port 2 Weak Pull-Up Enable SFR (PINMAP2, Address 0xB4) [7:6] Reserved 0 Reserved. Should be left cleared. 5 PINMAP2.5 0 The weak pull-up on RESET is disabled when this bit is set. 4 Reserved 0 Reserved. Should be left cleared. 3 PINMAP2.3 0 Reserved. Should be left cleared. 2 PINMAP2.2 0 The weak pull-up on P2.2 is disabled when this bit is set. 1 PINMAP2.1 0 The weak pull-up on P2.1 is disabled when this bit is set. 0 PINMAP2.0 0 The weak pull-up on P2.0 is disabled when this bit is set.

Table 160. Port 0 SFR (P0, Address 0x80) 7 0x87 T1 1 This bit reflects the state of the P0.7/SS/T1 pin. It can be written to or read. 6 0x86 T0 1 This bit reflects the state of the P0.6/SCLK/T0 pin. It can be written to or read. 5 0x85 1 This bit reflects the state of the P0.5/MISO pin. It can be written to or read. 4 0x84 1 This bit reflects the state of the P0.4/MOSI/SDATA pin. It can be written to or read. 3 0x83 CF2 1 This bit reflects the state of the P0.3/CF2 pin. It can be written to or read. 2 0x82 CF1 1 This bit reflects the state of the P0.2/CF1 pin. It can be written to or read. 1 0x81 1 This bit reflects the state of the P0.1/FP19 pin. It can be written to or read. 0 0x80 INT1 1 This bit reflects the state of the BCTRL/INT1/P0.0 pin. It can be written to or read. 1 When an alternate function is chosen for a pin of this port, the bit controlling this pin should always be set. Table 161. Port 1 SFR (P1, Address 0x90) 7 0x97 1 This bit reflects the state of the P1.7/FP20 pin. It can be written to or read. 6 0x96 1 This bit reflects the state of the P1.6/FP21 pin. It can be written to or read. 5 0x95 1 This bit reflects the state of the P1.5/FP22 pin. It can be written to or read. 4 0x94 T2 1 This bit reflects the state of the P1.4/T2/FP23 pin. It can be written to or read. 3 0x93 T2EX 1 This bit reflects the state of the P1.3/T2EX/FP24 pin. It can be written to or read. 2 0x92 1 This bit reflects the state of the P1.2/FP25 pin. It can be written to or read. 1 0x91 TxD 1 This bit reflects the state of the P1.1/TxD pin. It can be written to or read. 0 0x90 RxD 1 This bit reflects the state of the P1.0/RxD pin. It can be written to or read. 1 When an alternate function is chosen for a pin of this port, the bit controlling this pin should always be set. Table 162. Port 2 SFR (P2, Address 0xA0) [7:4] 0x97 to 0x94 0x1F These bits are unused and should remain set. 3 0x93 P2.3 1 This bit reflects the state of the P2.3/SDEN pin. It can be written only. 2 0x92 P2.2 1 This bit reflects the state of the P2.2/FP16 pin. It can be written to or read. 1 0x91 P2.1 1 This bit reflects the state of the P2.1/FP17 pin. It can be written to or read. 0 0x90 P2.0 1 This bit reflects the state of the P2.0/FP18 pin. It can be written to or read. 1 When an alternate function is chosen for a pin of this port, the bit controlling this pin should always be set.

Table 163. Port 0 Alternate Functions INT1 external interrupt Set EX1 in the interrupt enable SFR (IE, Address 0xA8). P0.1 FP19 LCD segment pin Set FP19EN in the LCD Segment Enable 2 SFR (LCDSEGE2, Address 0xED). SPIEN bit in the SPI configuration SFR 2 (SPIMOD2, Address 0xE9). I2CEN bit in the I2C Mode SFR (I2CMOD, Address 0xE8). SPIEN bit in the SPI configuration SFR 2 (SPIMOD2, Address 0xE9). Address 0x89) to enable T0 as an external event counter. P0.7 SS SPI slave select input for SPI in slave mode Set the SS_EN bit in the SPI configuration SFR 1 (SPIMOD1, Address 0xE8). SS SPI slave select output for SPI in master mode Set the SPIMS_b bit in the SPI configuration SFR 2 (SPIMOD2, Address 0xE9). Address 0x89) to enable T1 as an external event counter. Table 164. Port 1 Alternate Functions P1.1 TxD transmitter data output for UART This pin becomes TxD as soon as data is written into SBUF. P1.2 FP25 LCD segment pin Set FP25EN in the LCD segment enable SFR (LCDSEGE, Address 0x97). P1.3 FP24 LCD segment pin Set FP24EN in the LCD segment enable SFR (LCDSEGE, Address 0x97). T2EX Timer 2 control input Set EXEN2 in the timer/counter 2 control SFR (T2CON, Address 0xC8). P1.4 FP23 LCD segment pin Set FP23EN in the LCD segment enable SFR (LCDSEGE, Address 0x97). enable T2 as an external event counter. P1.5 FP22 LCD segment pin Set FP22EN in the LCD segment enable SFR (LCDSEGE, Address 0x97). P1.6 FP21 LCD segment pin Set FP21EN in the LCD segment enable SFR (LCDSEGE, Address 0x97). P1.7 FP20 LCD segment pin Set FP20EN in the LCD segment enable SFR (LCDSEGE, Address 0x97). Table 165. Port 2 Alternate Functions P2.0 FP18 LCD segment pin Set FP18EN in the LCD segment enable 2 SFR (LCDSEGE2, Address 0xED). P2.1 FP17 LCD segment pin Set FP17EN in the LCD Segment enable 2 SFR (LCDSEGE2, Address 0xED). P2.2 FP16 LCD segment pin Set FP16EN in the LCD segment enable 2 SFR (LCDSEGE2, Address 0xED). P2.3 SDEN serial download pin sampled on reset.

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Rev. B | Page 146 of 152 PORT 0 Port 0 is controlled directly through the bit-addressable Port 0 SFR (P0, Address 0x80). The weak internal pull-ups for Port 0 are configured through the Port 0 weak pull-up Enable SFR (PINMAP0, Address 0xB2); they are enabled by default. The weak internal pull-up is disabled by writing a 1 to PINMAP0.x. Port 0 pins also have various secondary functions, as described in Table 163. The alternate functions of Port 0 pins can be activated only if the corresponding bit latch in the Port 0 SFR contains a 1. Otherwise, the port pin remains at 0. PORT 1 Port 1 is an 8-bit bidirectional port controlled directly through the bit-addressable Port 1 SFR (P1, Address 0x90). The weak internal pull-ups for Port 1 are configured through the Port 1 weak pull-up enable SFR (PINMAP1, Address 0xB3); they are enabled by default. The weak internal pull-up is disabled by writing a 1 to PINMAP1.x. Port 1 pins also have various secondary functions as described in Table 164. The alternate functions of Port 1 pins can be activated only if the corresponding bit latch in the Port 1 SFR contains a 1. Otherwise, the port pin remains at 0. PORT 2 Port 2 is a 4-bit bidirectional port controlled directly through the bit-addressable Port 2 SFR (P2, Address 0xA0). Note that P2.3 can be used as an output only. Consequently, any read operation, such as a CPL P2.3, cannot be executed on this I/O. The weak internal pull-ups for Port 2 are configured through the Port 2 weak pull-up enable SFR (PINMAP2, Address 0xB4); they are enabled by default. The weak internal pull-up is disabled by writing a 1 to PINMAP2.x. Port 2 pins also have various secondary functions as described in Table 165. The alternate functions of Port 2 pins can be activated only if the corresponding bit latch in the Port 2 SFR contains a 1. Otherwise, the port pin remains at 0.

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Rev. B | Page 147 of 152 DETERMINING THE VERSION OF THE PART Each ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 holds in its internal flash registers a value that defines its version. This value helps to determine whether users have the latest version of the part. The version of the ADE7116/ADE7156/ ADE7166/ADE7169/ADE7566/ADE7569 that corresponds to this data sheet is ADE7116/ADE7156/ADE7166/ADE7169/ ADE7566/ADE7569 V3.4. This value can be accessed as follows: Launch HyperTerminal with a 9600 baud rate. 2. Put the part in serial download mode by first holding SDEN to logic low, then resetting the part. 3. Hold the SDEN pin. 4. Press and release the RESET pin. A string should appear on the HyperT erminal screen containing the part name and version number, for example, ADE7116V3.4, ADE7156V3.4, ADE7166V3.4, ADE7169V3.4, ADE7566V3.4, or ADE7569V3.4.

Figure 118. 64-Lead Low Profile Quad Flat Package [LQFP]

0.65 TYP

0.05 MAX

0.02 NOM

0.60 MAX

Figure 119. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Rev. B | Page 149 of 152 ORDERING GUIDE Model1 Anti- Tamper di/dt Sensor Interface VAR Flash (kB) Temperature Range Package Description Package Option ADE7116ASTZF162 , 3 , 4 Yes No No 16 −40°C to +85°C 64-Lead LQFP ST-64-2 ADE7116ASTZF16-RL2, 3, 4 No No No 16 −40°C to +85°C 64-Lead LQFP , Reel ST-64-2 ADE7116ASTZF82, 3, 4 Yes No No 8 −40°C to +85°C 64-Lead LQFP ST-64-2 ADE7116ASTZF8-RL2, 3, 4 No No No 8 −40°C to +85°C 64-Lead LQFP , Reel ST-64-2 ADE7156ASTZF162, 4 Yes No No 16 −40°C to +85°C 64-Lead LQFP ST-64-2 ADE7156ASTZF16-RL2, 4 Yes No No 16 −40°C to +85°C 64-Lead LQFP , Reel ST-64-2 ADE7156ASTZF82, 4 Yes No No 8 −40°C to +85°C 64-Lead LQFP ST-64-2 ADE7156ASTZF8-RL2, 4 Yes No No 8 −40°C to +85°C 64-Lead LQFP , Reel ST-64-2 ADE7166ACPZF82 Yes No No 8 −40°C to +85°C 64-Lead LFCSP_VQ CP-64-1 ADE7166ACPZF8-RL2 Yes No No 8 −40°C to +85°C 64-Lead LFCSP_VQ, Reel CP-64-1 ADE7166ACPZF162 Yes No No 16 −40°C to +85°C 64-Lead LFCSP_VQ CP-64-1 ADE7166ACPZF16-RL2 Yes No No 16 −40°C to +85°C 64-Lead LFCSP_VQ, Reel CP-64-1 ADE7166ASTZF82 Yes No No 8 −40°C to +85°C 64-Lead LQFP ST-64-2 ADE7166ASTZF8-RL2 Yes No No 8 −40°C to +85°C 64-Lead LQFP , Reel ST-64-2 ADE7166ASTZF162 Yes No No 16 −40°C to +85°C 64-Lead LQFP ST-64-2 ADE7166ASTZF16-RL2 Yes No No 16 −40°C to +85°C 64-Lead LQFP , Reel ST-64-2 ADE7169ACPZF162 Yes Yes Yes 16 −40°C to +85°C 64-Lead LFCSP_VQ CP-64-1 ADE7169ACPZF16-RL2 Yes Yes Yes 16 −40°C to +85°C 64-Lead LFCSP_VQ, Reel CP-64-1 ADE7169ASTZF82 Yes Yes Yes 8 −40°C to +85°C 64-Lead LQFP ST-64-2 ADE7169ASTZF8-RL2 Yes Yes Yes 8 −40°C to +85°C 64-Lead LQFP , Reel ST-64-2 ADE7169ASTZF162 Yes Yes Yes 16 −40°C to +85°C 64-Lead LQFP ST-64-2 ADE7169ASTZF16-RL2 Yes Yes Yes 16 −40°C to +85°C 64-Lead LQFP , Reel ST-64-2 ADE7566ACPZF82 No No No 8 −40°C to +85°C 64-Lead LFCSP_VQ CP-64-1 ADE7566ACPZF8-RL2 No No No 8 −40°C to +85°C 64-Lead LFCSP_VQ, Reel CP-64-1 ADE7566ACPZF162 No No No 16 −40°C to +85°C 64-Lead LFCSP_VQ CP-64-1 ADE7566ACPZF16-RL2 No No No 16 −40°C to +85°C 64-Lead LFCSP_VQ, Reel CP-64-1 ADE7566ASTZF82 No No No 8 −40°C to +85°C 64-Lead LQFP ST-64-2 ADE7566ASTZF8-RL2 No No No 8 −40°C to +85°C 64-Lead LQFP , Reel ST-64-2 ADE7566ASTZF162 No No No 16 −40°C to +85°C 64-Lead LQFP ST-64-2 ADE7566ASTZF16-RL2 No No No 16 −40°C to +85°C 64-Lead LQFP , Reel ST-64-2 ADE7569ACPZF162 No Yes Yes 16 −40°C to +85°C 64-Lead LFCSP_VQ CP-64-1 ADE7569ACPZF16-RL2 No Yes Yes 16 −40°C to +85°C 64-Lead LFCSP_VQ, Reel CP-64-1 ADE7569ASTZF82 No Yes Yes 8 −40°C to +85°C 64-Lead LQFP ST-64-2 ADE7569ASTZF8-RL2 No Yes Yes 8 −40°C to +85°C 64-Lead LQFP , Reel ST-64-2 ADE7569ASTZF162 No Yes Yes 16 −40°C to +85°C 64-Lead LQFP ST-64-2 ADE7569ASTZF16-RL2 No Yes Yes 16 −40°C to +85°C 64-Lead LQFP , Reel ST-64-2 ADE8052Z-PRG12 ADE Programmer ADE8052Z-DWDL12 ADE Downloader ADE8052Z-EMUL12 ADE Emulator EVAL-ADE7169F16EBZ2 Evaluation Board EVAL-ADE7569F16EBZ2 Evaluation Board 1 All models have W + VA + rms, 5 V LCD, and RTC. 2 Z = RoHS Compliant Part. 3 The ADE7116 does not support battery and temperature ADC measurements. 4 The ADE7116 and the ADE7156 do not have internally adjustable LCD levels.

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Rev. B | Page 150 of 152 NOTES

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Rev. B | Page 151 of 152 NOTES

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Rev. B | Page 152 of 152 NOTES Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. ©2007–2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D06353-0-11/08(B)