ADE5566ASTZF62

ADE5166_09 AD | Alldatasheet

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8052 MCU, RTC, and LCD Driver

license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2008–2009 Analog Devices, Inc. All rights reserved. Table 1. Features Available on Each Part

4 LCD memory banks for screen scrolling

ADE5166/ADE5169/ADE5566/ADE5569 Rev. B | Page 2 of 156 TABLE OF CONTENTS di/dt Current Sensor and Digital Integrator Reactive Energy Calculation (ADE5169/ADE5569 Only) ... 66

ADE5166/ADE5169/ADE5566/ADE5569 Rev. B | Page 3 of 156 Writing to the Watchdog Timer SFR (WDCON, Address Determining the Version of the

REVISION HISTORY

11/09—Rev. A to Rev. B Changes to Fault Detection (ADE5166/ADE5169 2/09—Rev. 0 to Rev. A Changes to Determining the Version of the 10/08—Revision 0: Initial Version

an electronic energy meter with an LCD display in a single part. measurement DSP to simplify energy meter design. driver generates voltages capable of driving LCDs up to 5 V .

256 BYTES

Figure 1. ADE5166/ADE5169 Functional Block Diagram

Figure 2. ADE5566/ADE5569 Functional Block Diagram

ADE5166/ADE5169/ADE5566/ADE5569 Rev. B | Page 6 of 156 SPECIFICATIONS VDD = 3.3 V ± 5%, AGND = DGND = 0 V , on-chip reference XTALx = 32.768 kHz, TMIN to TMAX = −40°C to +85°C, unless otherwise noted. ENERGY METERING Table 2. Parameter Min Typ Max Unit Test Conditions/Comments MEASUREMENT ACCURACY1 Phase Error Between Channels PF = 0.8 Capacitive ±0.05 Degrees Phase lead: 37° PF = 0.5 Inductive ±0.05 Degrees Phase lag: 60° Active Energy Measurement Error2 0.1 % of reading Over a dynamic range of 1000 to 1 at 25°C AC Power Supply Rejection2 VDD = 3.3 V + 100 mV rms/120 Hz Output Frequency Variation 0.01 % IPx = VP = ±100 mV rms DC Power Supply Rejection2 VDD = 3.3 V ± 117 mV dc Output Frequency Variation 0.01 % Active Energy Measurement Bandwidth1 8 kHz Reactive Energy Measurement Error2 0.5 % of reading Over a dynamic range of 1000 to 1 at 25°C Vrms Measurement Error2 0.5 % of reading Over a dynamic range of 100 to 1 at 25°C Vrms Measurement Bandwidth1 3.9 kHz Irms Measurement Error2 0.5 % of reading Over a dynamic range of 500 to 1 at 25°C Irms Measurement Bandwidth1 3.9 kHz ANALOG INPUTS Maximum Signal Levels ±500 mV peak VP − VN differential input ADE5166/ADE5169 ±500 mV peak IPA − IN and IPB − IN differential inputs ADE5566/ADE5569 ±500 mV peak IP − IN Input Impedance (DC) 770 kΩ ADC Offset Error2 ±10 mV PGA1 = PGA2 = 1 ±1 mV PGA1 = 16 Gain Error2 Current Channel ±3 % IPA = IPB = 0.5 V dc or IP = 0.5 V dc Voltage Channel ±3 % VP − VN = 0.5 V dc Gain Error Match ±0.2 % CF1 AND CF2 PULSE OUTPUT Maximum Output Frequency 21.6 kHz VP − VN = 500 mV peak; IPA − IN = 500 mV for the ADE5166/ADE5169; IP − IN = 500 mV for the ADE5566/ADE5569 Duty Cycle 50 % If the CF1 or CF2 frequency > 5.55 Hz Active High Pulse Width 90 ms If the CF1 or CF2 frequency < 5.55 Hz FAULT DETEC TION3 Fault Detection Threshold Inactive Input ≠ Active Input 6.25 % of active IPA or IPB active Input Swap Threshold Inactive Input > Active Input 6.25 % of active IPA or IPB active Accuracy Fault Mode Operation IPA Active, IPB = AGND 0.1 % of reading Over a dynamic range of 500 to 1 IPB Active, IPA = AGND 0.1 % of reading Over a dynamic range of 500 to 1 Fault Detection Delay 3 Seconds Swap Delay 3 Seconds 1 These specifications are not production tested but are guaranteed by design and/or characterization data on production release. 2 See the Terminology section for definition. 3 Available only in the ADE5166/ADE5169.

ADE5166/ADE5169/ADE5566/ADE5569 Rev. B | Page 7 of 156 ANALOG PERIPHERALS Table 3. Parameter Min Typ Max Unit Test Conditions/Comments INTERNAL ADCs (BATTERY, TEMPERATURE, VDCIN) Power Supply Operating Range 2.4 3.7 V Measured on VSWOUT No Missing Codes1 8 Bits Conversion Delay2 38 μs ADC Gain VDCIN Measurement 15.3 mV/LSB VBAT Measurement 14.6 mV/LSB Temperature Measurement 0.83 °C/LSB ADC Offset VDCIN Measurement at 3 V 200 LSB VBAT Measurement at 3.7 V 246 LSB Temperature Measurement at 25°C 123 LSB VDCIN Analog Input Maximum Signal Levels 0 3.3 V Input Impedance (DC) 1 MΩ Low VDCIN Detection Threshold 1.09 1.2 1.27 V POWER-ON RESET (POR) VDD POR Detection Threshold 2.5 2.95 V POR Active Timeout Period 33 ms VSWOUT POR Detection Threshold 1.8 2.2 V POR Active Timeout Period 20 ms VINTD POR Detection Threshold 2.0 2.25 V POR Active Timeout Period 16 ms VINTA POR Detection Threshold 2.0 2.25 V POR Active Timeout Period 120 ms BATTERY SWITCHOVER Voltage Operating Range (VSWOUT) 2.4 3.7 V VDD to VBAT Switching Switching Threshold (VDD) 2.5 2.95 V Switching Delay 10 ns When VDD to VBAT switch is activated by VDD 30 ms When VDD to VBAT switch is activated by VDCIN VBAT to VDD Switching Switching Threshold (VDD) 2.5 2.95 V Switching Delay 30 ms Based on VDD > 2.75 V VSWOUT to VBAT Leakage Current 10 nA VBAT = 0 V, VSWOUT = 3.43 V, TA = 25°C LCD, CHARGE PUMP ACTIVE Charge Pump Capacitance Between LCDVP1 and LCDVP2 100 nF LCDVA, LCDVB, LCDVC Decoupling Capacitance 470 nF LCDVA 0 1.9 V LCDVB 0 3.8 V 1/3 bias mode LCDVC 0 5.8 V 1/3 bias mode V1 Segment Line Voltage LCDVA − 0.1 LCDVA V Current on segment line = −2 μA V2 Segment Line Voltage LCDVB − 0.1 LCDVB V Current on segment line = −2 μA V3 Segment Line Voltage LCDVC − 0.1 LCDVC V Current on segment line = −2 μA DC Voltage Across Segment and COMx Pin 50 mV LCDVC − LCDVB, LCDVC − LCDVA, or LCDVB − LCDVA

ADE5166/ADE5169/ADE5566/ADE5569 Rev. B | Page 8 of 156 Parameter Min Typ Max Unit Test Conditions/Comments LCD, RESISTOR LADDER ACTIVE Leakage Current ±20 nA 1/2 and 1/3 bias modes, no load V1 Segment Line Voltage LCDVA − 0.1 LCDVA V Current on segment line = −2 μA V2 Segment Line Voltage LCDVB − 0.1 LCDVB V Current on segment line = −2 μA V3 Segment Line Voltage LCDVC − 0.1 LCDVC V Current on segment line = −2 μA ON-CHIP REFERENCE Nominal 1.2035 V Reference Error −2.2 +2.2 mV TA = 25°C, fCORE = 1.024 MHz Power Supply Rejection 80 dB Temperature Coefficient1 10 50 ppm/°C fCORE = 1.024 MHz 1 These specifications are not production tested but are guaranteed by design and/or characterization data on production release. 2 Delay between ADC conversion request and interrupt set. DIGITAL INTERFACE Table 4. Parameter Min Typ Max Unit Test Conditions/Comments LOGIC INPUTS1 All Inputs Except XTAL1, XTAL2, BCTRL, INT0, INT1, RESET Input High Voltage, VINH 2.0 V Input Low Voltage, VINL 0.8 V BCTRL, INT0, INT1, RESET Input High Voltage, VINH 1.3 V Input Low Voltage, VINL 0.8 V Input Currents RESET 100 nA RESET = VSWOUT = 3.3 V Port 0, Port 1, Port 2 ±100 nA Internal pull-up disabled, input = 0 V or VSWOUT −3.75 −8.5 μA Internal pull-up enabled, input = 0 V, V SWOUT = 3.3 V Input Capacitance 10 pF All digital inputs FLASH MEMORY Endurance2 20,000 Cycles At 25°C Data Retention3 20 Years TJ = 85°C CRYSTAL OSCILLATOR4 Crystal Equivalent Series Resistance 30 50 kΩ Crystal Frequency 32 32.768 33.5 kHz XTAL1 Input Capacitance 12 pF XTAL2 Output Capacitance 12 pF MCU CLOCK RATE (fCORE) 4.096 MHz Crystal = 32.768 kHz and CD bits = 0b000 32 kHz Crystal = 32.768 kHz and CD bits = 0b111 LOGIC OUTPUTS Output High Voltage, VOH 2.4 V VDD = 3.3 V ± 5% ISOURCE 80 μA Output Low Voltage, VOL5 0.4 V VDD = 3.3 V ± 5% ISINK 2 mA START-UP TIME6 PSM0 Power-On Time 880 ms VDD at 2.75 V to PSM0 code execution From Power Saving Mode 1 (PSM1) PSM1 to PSM0 130 ms VDD at 2.75 V to PSM0 code execution From Power Saving Mode 2 (PSM2) PSM2 to PSM1 48 ms Wake-up event to PSM1 code execution PSM2 to PSM0 186 ms VDD at 2.75 V to PSM0 code execution

ADE5166/ADE5169/ADE5566/ADE5569 Rev. B | Page 9 of 156 Parameter Min Typ Max Unit Test Conditions/Comments POWER SUPPLY INPUTS VDD 3.13 3.3 3.46 V VBAT 2.4 3.3 3.7 V INTERNAL POWER SUPPLY SWITCH (VSWOUT) VBAT to VSWOUT On Resistance 12 Ω VBAT = 2.4 V VDD to VSWOUT On Resistance 9 Ω VDD = 3.13 V VBAT to/from VDD Switching Open Time 40 ns BCTRL State Change and Switch Delay 18 μs VSWOUT Output Current Drive 6 mA POWER SUPPLY OUTPUTS VINTA 2.3 2.70 V VINTD 2.3 2.70 V VINTA Power Supply Rejection 60 dB VINTD Power Supply Rejection 50 dB POWER SUPPLY CURRENTS Current in Normal Mode (PSM0) 4.4 5.3 mA fCORE = 4.096 MHz, LCD and meter active 2.2 mA fCORE = 1.024 MHz, LCD and meter active 1.6 mA fCORE = 32.768 kHz, LCD and meter active 3 3.9 mA fCORE = 4.096 MHz; metering ADC and DSP , powered down Current in Battery Mode (PSM1) 3.3 5.05 mA fCORE = 4.096 MHz, LCD active, VBAT = 3.7 V 1 mA fCORE = 1.024 MHz, LCD active Current in Sleep Mode (PSM2) 38 μA LCD active with charge pump at 3.3 V + RTC, VBAT = 3.3 V 1.7 μA RTC only, TA = 25°C, VBAT = 3.3 V 1 Specifications guaranteed by design. 2 Endurance is qualified as per JEDEC Standard 22 Method A117 and measured at −40°C, +25°C, +85°C, and +125°C. 3 Retention lifetime equivalent at junction temperature (TJ) = 85°C as per JEDEC Standard 22 Method A117. Retention lifetime derates with junction temperature. 4 Recommended crystal specifications. 5 Test carried out with all the I/Os set to a low output level. 6 Delay between power supply valid and execution of first instruction by 8052 core.

Table 7. SPI Master Mode Timing Parameters (SPICPHA = 1) 1 tCORE depends on the clock divider or the CD bits of the POWCON SFR, Address 0xC5[2:0] (see Table 26); tCORE = 2CD/4.096 MHz. Figure 5. SPI Master Mode Timing (SPICPHA = 1)

Table 8. SPI Master Mode Timing Parameters (SPICPHA = 0) 1 tCORE depends on the clock divider or the CD bits of the POWCON SFR, Address 0xC5[2:0] (see Table 26); tCORE = 2CD/4.096 MHz. Figure 6. SPI Master Mode Timing (SPICPHA = 0)

Table 9. SPI Slave Mode Timing Parameters (SPICPHA = 1) 1 tCORE depends on the clock divider or the CD bits of the POWCON SFR, Address 0xC5[2:0] (see Table 26); tCORE = 2CD/4.096 MHz. Figure 7. SPI Slave Mode Timing (SPICPHA = 1)

Table 10. SPI Slave Mode Timing Parameters (SPICPHA = 0) 1 tCORE depends on the clock divider or the CD bits of the POWCON SFR, Address 0xC5[2:0] (see Table 26); tCORE = 2CD/4.096 MHz. Figure 8. SPI Slave Mode Timing (SPICPHA = 0)

TA = 25°C, unless otherwise noted. 1 When used with external resistor divider. soldered in a circuit board for surface-mount packages. Table 12. Thermal Resistance

47 XTAL1

46 XTAL2

48 INT0

35 FP0

34 FP1

33 FP2

Figure 9. ADE5166/ADE5169 Pin Configuration Table 13. Pin Function Descriptions 1 COM3/FP27 Common Output 3/LCD Segment Output 27. COM3 is used for the LCD backplane. 2 COM2/FP28 Common Output 2/LCD Segment Output 28. COM2 is used for the LCD backplane. 3 COM1 Common Output 1. COM1 is used for the LCD backplane. 4 COM0 Common Output 0. COM0 is used for the LCD backplane. 5 P1.2/FP25/ZX General-Purpose Digital I/O Port 1.2/LCD Segment Output 25/ZX Output. 6 P1.3/T2EX/FP24 General-Purpose Digital I/O Port 1.3/Timer 2 Control Input/LCD Segment Output 24. 7 P1.4/T2/FP23 General-Purpose Digital I/O Port 1.4/Timer 2 Input/LCD Segment Output 23. 8 P1.5/FP22 General-Purpose Digital I/O Port 1.5/LCD Segment Output 22. 9 P1.6/FP21 General-Purpose Digital I/O Port 1.6/LCD Segment Output 21. 10 P1.7/FP20 General-Purpose Digital I/O Port 1.7/LCD Segment Output 20. 11 P0.1/FP19 General-Purpose Digital I/O Port 0.1/LCD Segment Output 19. 12 P2.0/FP18 General-Purpose Digital I/O Port 2.0/LCD Segment Output 18. 13 P2.1/FP17 General-Purpose Digital I/O Port 2.1/LCD Segment Output 17. 14 P2.2/FP16 General-Purpose Digital I/O Port 2.2/LCD Segment Output 16. 15 LCDVC Output Port for LCD Levels. This pin should be decoupled with a 470 nF capacitor. 17, 18 LCDVB, LCDVA Output Ports for LCD Levels. These pins should be decoupled with a 470 nF capacitor. 20 to 35 FP15 to FP0 LCD Segment Output 15 to LCD Segment Output 0. 36 P1.1/TxD General-Purpose Digital I/O Port 1.1/Transmitter Data Output (Asynchronous). 37 P1.0/RxD General-Purpose Digital I/O Port 1.0/Receive Data Input (Asynchronous). 39 P0.6/SCLK/T0 General-Purpose Digital I/O Port 0.6/Clock Output for I2C or SPI Port/Timer 0 Input. 40 P0.5/MISO/ZX General-Purpose Digital I/O Port 0.5/Data Input for SPI Port/ZX Output. 41 P0.4/MOSI/SDATA General-Purpose Digital I/O Port 0.4/Data Output for SPI Port/I2C-Compatible Data Line.

ADE5166/ADE5169/ADE5566/ADE5569 Rev. B | Page 17 of 156 Pin No. Mnemonic Description 42 P0.3/CF2 General-Purpose Digital I/O Port 0.3/Calibration Frequency Logic Output 2. The CF2 logic output gives instantaneous active, reactive, or apparent power or Irms information. 43 P0.2/CF1 General-Purpose Digital I/O Port 0.2/Calibration Frequency Logic Output 1. The CF1 logic output gives instantaneous active, reactive, or apparent power or Irms information. 44 SDEN/P2.3/TxD2 Serial Download Mode Enable/General-Purpose Digital Output Port 2.3/Transmitter Data Output 2 (Asynchronous). This pin is used to enable serial download mode through a resistor when pulled low on power-up or reset. On reset, this pin momentarily becomes an input, and the status of the pin is sampled. If there is no pull-down resistor in place, the pin momentarily goes high, and then user code is executed. If the pin is pulled down on reset, the embedded serial download/debug kernel executes, and this pin remains low during the internal program execution. After reset, this pin can be used as a digital output port pin (P2.3) or as Transmitter Data Output 2 (asynchronous). 45 BCTRL/INT1/P0.0 Digital Input for Battery Control/External Interrupt Input 1/General-Purpose Digital I/O Port 0.0. This logic input connects VDD or VBAT to VSWOUT internally when set to logic high or logic low, respectively. When left open, the connection between VDD or VBAT and VSWOUT is selected internally. 46 XTAL2 A crystal can be connected across this pin and XTAL1 (see the XTAL1 pin description) to provide a clock source. The XTAL2 pin can drive one CMOS load when an external clock is supplied at XTAL1 or by the gate oscillator circuit. An internal 6 pF capacitor is connected to this pin. 47 XTAL1 An external clock can be provided at this logic input. Alternatively, a tuning fork crystal can be connected across XTAL1 and XTAL2 to provide a clock source. The clock frequency for specified operation is 32.768 kHz. An internal 6 pF capacitor is connected to this pin. 48 INT0 External Interrupt Input 0. 49, 50 VP, VN Analog Inputs for Voltage Channel. These inputs are fully differential voltage inputs with a maximum differential level of ±500 mV for specified operation. This channel also has an internal PGA. 51 EA Input for Emulation. When held high, this input enables the device to fetch code from internal program memory locations. The ADE5166/ADE5169 do not support external code memory. This pin should not be left floating. 52, 53 IPA, IN Analog Inputs for Current Channel. These inputs are fully differential voltage inputs with a maximum differential level of ±500 mV for specified operation. This channel also has an internal PGA. 54 AGND Ground Reference for Analog Circuitry. 55 I PB Analog Input for Second Current Channel. This input is fully differential with a maximum differential level of ±500 mV, referred to IN for specified operation. This channel also has an internal PGA. 56 RESET Reset Input, Active Low. 57 REF IN/OUT Access to On-Chip Voltage Reference. The on-chip reference has a nominal value of 1.2 V ± 0.1% and a typical temperature coefficient of 50 ppm/°C maximum. This pin should be decoupled with a 1 μF capacitor in parallel with a ceramic 100 nF capacitor. 58 V BAT Power Supply Input from the Battery with a 2.4 V to 3.7 V Range. This pin is connected internally to VDD when the battery is selected as the power supply. 59 V INTA Access to On-Chip 2.5 V Analog LDO. No external active circuitry should be connected to this pin. This pin should be decoupled with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor. 60 V DD 3.3 V Power Supply Input from the Regulator. This pin is connected internally to VSWOUT when the regulator is selected as the power supply. This pin should be decoupled with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor. 61 V SWOUT 3.3 V Power Supply Output. This pin provides the supply voltage for the LDOs and the internal circuitry. This pin should be decoupled with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor. 62 V INTD Access to On-Chip 2.5 V Digital LDO. No external active circuitry should be connected to this pin. This pin should be decoupled with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor. 63 DGND Ground Reference for Digital Circuitry. 64 V DCIN Analog Input for DC Voltage Monitoring. The maximum input voltage on this pin is VSWOUT with respect to AGND. This pin is used to monitor the preregulated dc voltage.

Figure 10. ADE5566/ADE5569 Pin Configuration Table 14. Pin Function Descriptions 1 COM3/FP27 Common Output 3/LCD Segment Output 27. COM3 is used for the LCD backplane. 2 COM2/FP28 Common Output 2/LCD Segment Output 28. COM2 is used for the LCD backplane. 3 COM1 Common Output 1. COM1 is used for the LCD backplane. 4 COM0 Common Output 0. COM0 is used for the LCD backplane. 5 P1.2/FP25/ZX General-Purpose Digital I/O Port 1.2/LCD Segment Output 25/ZX Output. 6 P1.3/T2EX/FP24 General-Purpose Digital I/O Port 1.3/Timer 2 Control Input/LCD Segment Output 24. 7 P1.4/T2/FP23 General-Purpose Digital I/O Port 1.4/Timer 2 Input/LCD Segment Output 23. 8 P1.5/FP22 General-Purpose Digital I/O Port 1.5/LCD Segment Output 22. 9 P1.6/FP21 General-Purpose Digital I/O Port 1.6/LCD Segment Output 21. 10 P1.7/FP20 General-Purpose Digital I/O Port 1.7/LCD Segment Output 20. 11 P0.1/FP19 General-Purpose Digital I/O Port 0.1/LCD Segment Output 19. 12 P2.0/FP18 General-Purpose Digital I/O Port 2.0/LCD Segment Output 18. 13 P2.1/FP17 General-Purpose Digital I/O Port 2.1/LCD Segment Output 17. 14 P2.2/FP16 General-Purpose Digital I/O Port 2.2/LCD Segment Output 16. 15 LCDVC Output Port for LCD Levels. This pin should be decoupled with a 470 nF capacitor. 17, 18 LCDVB, LCDVA Output Ports for LCD Levels. These pins should be decoupled with a 470 nF capacitor. 20 to 35 FP15 to FP0 LCD Segment Output 15 to LCD Segment Output 0. 36 P1.1/TxD General-Purpose Digital I/O Port 1.1/Transmitter Data Output (Asynchronous). 37 P1.0/RxD General-Purpose Digital I/O Port 1.0/Receive Data Input (Asynchronous). 39 P0.6/SCLK/T0 General-Purpose Digital I/O Port 0.6/Clock Output for I2C or SPI Port/Timer 0 Input. 40 P0.5/MISO/ZX General-Purpose Digital I/O Port 0.5/Data Input for SPI Port/ZX Output. 41 P0.4/MOSI/SDATA General-Purpose Digital I/O Port 0.4/Data Output for SPI Port/I2C-Compatible Data Line. instantaneous active, reactive, or apparent power or Irms information.

ADE5166/ADE5169/ADE5566/ADE5569 Rev. B | Page 19 of 156 Pin No. Mnemonic Description 43 P0.2/CF1 General-Purpose Digital I/O Port 0.2/Calibration Frequency Logic Output 1. The CF1 logic output gives instantaneous active, reactive, or apparent power or Irms information. 44 SDEN/P2.3/TxD2 Serial Download Mode Enable/General-Purpose Digital Output Port 2.3/Transmitter Data Output 2 (Asynchronous). This pin is used to enable serial download mode through a resistor when pulled low on power-up or reset. On reset, this pin momentarily becomes an input, and the status of the pin is sampled. If there is no pull-down resistor in place, the pin momentarily goes high, and then user code is executed. If the pin is pulled down on reset, the embedded serial download/debug kernel executes, and this pin remains low during the internal program execution. After reset, this pin can be used as a digital output port pin (P2.3) or as Transmitter Data Output 2 (asynchronous). 45 BCTRL/INT1/P0.0 Digital Input for Battery Control/External Interrupt Input 1/General-Purpose Digital I/O Port 0.0. This logic input connects VDD or VBAT to VSWOUT internally when set to logic high or logic low, respectively. When left open, the connection between VDD or VBAT and VSWOUT is selected internally. 46 XTAL2 A crystal can be connected across this pin and XTAL1 (see the XTAL1 pin description) to provide a clock source. The XTAL2 pin can drive one CMOS load when an external clock is supplied at XTAL1 or by the gate oscillator circuit. An internal 6 pF capacitor is connected to this pin. 47 XTAL1 An external clock can be provided at this logic input. Alternatively, a tuning fork crystal can be connected across XTAL1 and XTAL2 to provide a clock source. The clock frequency for specified operation is 32.768 kHz. An internal 6 pF capacitor is connected to this pin. 48 INT0 External Interrupt Input 0. 49, 50 VP, VN Analog Inputs for Voltage Channel. These inputs are fully differential voltage inputs with a maximum differential level of ±500 mV for specified operation. This channel also has an internal PGA. 51 EA Input for Emulation. When held high, this input enables the device to fetch code from internal program memory locations. The ADE5566/ADE5569 do not support external code memory. This pin should not be left floating. 52, 53 IP, IN Analog Inputs for Current Channel. These inputs are fully differential voltage inputs with a maximum differential level of ±500 mV for specified operation. This channel also has an internal PGA. 54 AGND Ground Reference for Analog Circuitry. 55 FP26 LCD Segment Output 26. 56 RESET Reset Input, Active Low. 57 REF IN/OUT Access to On-Chip Voltage Reference. The on-chip reference has a nominal value of 1.2 V ± 0.1% and a typical temperature coefficient of 50 ppm/°C maximum. This pin should be decoupled with a 1 μF capacitor in parallel with a ceramic 100 nF capacitor. 58 V BAT Power Supply Input from the Battery with a 2.4 V to 3.7 V Range. This pin is connected internally to VDD when the battery is selected as the power supply. 59 V INTA Access to On-Chip 2.5 V Analog LDO. No external active circuitry should be connected to this pin. This pin should be decoupled with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor. 60 V DD 3.3 V Power Supply Input from the Regulator. This pin is connected internally to VSWOUT when the regulator is selected as the power supply. This pin should be decoupled with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor. 61 V SWOUT 3.3 V Power Supply Output. This pin provides the supply voltage for the LDOs and the internal circuitry. This pin should be decoupled with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor. 62 V INTD Access to On-Chip 2.5 V Digital LDO. No external active circuitry should be connected to this pin. This pin should be decoupled with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor. 63 DGND Ground Reference for Digital Circuitry. 64 V DCIN Analog Input for DC Voltage Monitoring. The maximum input voltage on this pin is VSWOUT with respect to AGND. This pin is used to monitor the preregulated dc voltage.

ADE5166/ADE5169/ADE5566/ADE5569 Rev. B | Page 24 of 156 TERMINOLOGY Measurement Error The error associated with the energy measurement made by the ADE5166/ADE5169/ADE5566/ADE5569 is defined by the fol- lowing formula: Measurement Error = % 100×⎟⎟ ⎛ − EnergyTrue EnergyTrueRegisterEnergy Phase Error Between Channels The digital integrator and the high-pass filter (HPF) in the current channel have a nonideal phase response. T o offset this phase response and equalize the phase response between channels, two phase correction networks are placed in the current channel: one for the digital integrator and the other for the HPF. The phase correction networks correct the phase response of the corre- sponding component and ensure a phase match between the current channel and the voltage channel to within ±0.1° over a range of 45 Hz to 65 Hz with the digital integrator off. With the digital integrator on, the phase is corrected to within ±0.4° over a range of 45 Hz to 65 Hz. Power Supply Rejection (PSR) PSR quantifies the ADE5166/ADE5169/ADE5566/ADE5569 measurement error as a percentage of reading when the power supplies are varied. For the ac PSR measurement, a reading at nominal supplies (3.3 V) is taken. A second reading is obtained with the same input signal levels when an ac signal (100 mV rms/ 120 Hz) is introduced onto the supplies. Any error introduced by this ac signal is expressed as a percentage of the reading (see the Measurement Error definition). For the dc PSR measurement, a reading at nominal supplies (3.3 V) is taken. A second reading is obtained with the same input signal levels when the supplies are varied ±5%. Any error introduced is expressed as a percentage of the reading. ADC Offset Error ADC offset error is the dc offset associated with the analog inputs to the ADCs. It means that, with the analog inputs connected to AGND, the ADCs still see a dc analog input signal. The magnitude of the offset depends on the gain and input range selection. However, when HPF1 is switched on, the offset is removed from the current channel, and the power calculation is not affected by this offset. The offsets can be removed by performing an offset calibration (see the Analog Inputs section). Gain Error Gain error is the difference between the measured ADC output code (minus the offset) and the ideal output code (see the Current Channel ADC section and the Voltage Channel ADC section). It is measured for each of the gain settings on the current channel (1, 2, 4, 8, and 16). The difference is expressed as a percentage of the ideal code.

Table 15. SFR Mapping SCRATCH4 0xFE Scratch Pad 4 (see Table 25). SCRATCH3 0xFD Scratch Pad 3 (see Table 24). SCRATCH2 0xFC Scratch Pad 2 (see Table 23). SCRATCH1 0xFB Scratch Pad 1 (see Table 22). B 0xF0 Auxiliary math (see Table 57). VDCINADC 0xEF VDCINADC value (see Table 54). LCDSEGE2 0xED LCD Segment Enable 2 (see Table 101). SBUF2 0xEB Serial Port 2 buffer (see Table 147). SPISTAT 0xEA SPI interrupt status (see Table 155). SPI2CSTAT 0xEA I2C interrupt status (see Table 159). SPIMOD2 0xE9 SPI Configuration SFR 2 (see Table 154). I2CADR 0xE9 I2C slave address (see Table 158). SPIMOD1 0xE8 SPI Configuration SFR 1 (see Table 153). I2CMOD 0xE8 I2C mode (see Table 157). WAV2H 0xE7 Selection 2 sample MSB (see Table 31). WAV2L 0xE5 Selection 2 sample LSB (see Table 31). WAV1H 0xE4 Selection 1 sample MSB (see Table 31). WAV1L 0xE2 Selection 1 sample LSB (see Table 31). ACC 0xE0 Accumulator (see Table 57). BATADC 0xDF Battery ADC value (see Table 55). MIRQSTH 0xDE Interrupt Status 3 (see Table 43). MIRQSTM 0xDD Interrupt Status 2 (see Table 42). MIRQSTL 0xDC Interrupt Status 1 (see Table 41). MIRQENH 0xDB Interrupt Enable 3 (see Table 46). MIRQENM 0xDA Interrupt Enable 2 (see Table 45). MIRQENL 0xD9 Interrupt Enable 1 (see Table 44). ADCGO 0xD8 Start ADC measurement (see Table 52). TEMPADC 0xD7 Temperature ADC value (see Table 56). IRMSH 0xD6 Irms measurement MSB (see Table 31). IRMSL 0xD4 Irms measurement LSB (see Table 31). VRMSH 0xD3 Vrms measurement MSB (see Table 31). VRMSL 0xD1 Vrms measurement LSB (see Table 31). PSW 0xD0 Program status word (see Table 58). TH2 0xCD Timer 2 high byte (see Table 120). TL2 0xCC Timer 2 low byte (see Table 121). T2CON 0xC8 Timer/Counter 2 control (see Table 115). EADRH 0xC7 Flash high byte address (see Table 110). EADRL 0xC6 Flash low byte address (see Table 109). POWCON 0xC5 Power control (see Table 26). KYREG 0xC1 Key (see Table 126). WDCON 0xC0 Watchdog timer (see Table 88). STCON 0xBF Stack boundary (see Table 65). EDATA 0xBC Flash data (see Table 108). PROTKY 0xBB Flash protection key (see Table 107). FLSHKY 0xBA Flash key (see Table 106). ECON 0xB9 Flash control (see Table 105). IP 0xB8 Interrupt priority (see Table 82). SPH 0xB7 Stack pointer high (see Table 64). LCDCONY 0xB1 LCD Configuration Y (see Table 94). CFG 0xAF Configuration (see Table 66). LCDDAT 0xAE LCD data (see Table 100). LCDPTR 0xAC LCD pointer (see Table 99). IE 0xA8 Interrupt enable (see Table 81). DPCON 0xA7 Data pointer control (see Table 79). RTCDAT 0xA4 RTC pointer data (see Table 131). RTCPTR 0xA3 RTC pointer address (see Table 130). TIMECON2 0xA2 RTC Configuration 2 (see Table 129). TIMECON 0xA1 RTC configuration (see Table 128). P2 0xA0 Port 2 (see Table 167).

ADE5166/ADE5169/ADE5566/ADE5569 Rev. B | Page 26 of 156 Mnemonic Address Description SBAUDT 0x9E Enhanced serial baud rate control (see Table 142). SBAUDF 0x9D UART timer fractional divider (see Table 143). LCDCONX 0x9C LCD Configuration X (see Table 92). SPI2CRx 0x9B SPI/I2C receive buffer (see Table 152). SPI2CTx 0x9A SPI/I2C transmit buffer (see Table 151). SBUF 0x99 Serial port buffer (see Table 141). SCON 0x98 Serial communications control (see Table 140). LCDSEGE 0x97 LCD segment enable (see Table 98). LCDCLK 0x96 LCD clock (see Table 95). LCDCON 0x95 LCD configuration (see Table 91). MDATH 0x94 Energy measurement pointer data MSB (see Table 31). MDATM 0x93 Energy measurement pointer data middle byte (see Table 31). MDATL 0x92 Energy measurement pointer data LSB (see Table 31). Mnemonic Address Description MADDPT 0x91 Energy measurement pointer address (see Table 30). P1 0x90 Port 1 (see Table 166). TH1 0x8D Timer 1 high byte (see Table 118). TH0 0x8C Timer 0 high byte (see Table 116). TL1 0x8B Timer 1 low byte (see Table 119). TL0 0x8A Timer 0 low byte (see Table 117). TMOD 0x89 Timer/Counter 0 and Timer/Counter 1 mode (see Table 113). TCON 0x88 Timer/Counter 0 and Timer/Counter 1 control (see Table 114). PCON 0x87 Program control (see Table 59). DPH 0x83 Data pointer high (see Table 61). DPL 0x82 Data pointer low (see Table 60). SP 0x81 Stack pointer (see Table 63). P0 0x80 Port 0 (see Table 165).

supply to battery switchover and power supply failures. through the 8052 power management SFRs (see Table 16). Table 16. Power Management SFRs 0xEC R/W IPSME Power management interrupt enable (see Table 21). 0xF5 R/W BATPR Battery switchover configuration (see Table 19). 0xF8 R/W IPSMF Power management interrupt flag (see Table 18). 0xFF R/W INTPR Interrupt pins configuration (see Table 17). 0xF4 R/W PERIPH Peripheral configuration (see Table 20). 0xC5 R/W POWCON Power control (see Table 26). 0xFB R/W SCRATCH1 Scratch Pad 1 (see Table 22). 0xFC R/W SCRATCH2 Scratch Pad 2 (see Table 23). 0xFD R/W SCRATCH3 Scratch Pad 3 (see Table 24). 0xFE R/W SCRATCH4 Scratch Pad 4 (see Table 25). Table 17. Interrupt Pins Configuration SFR (INTPR, Address 0xFF) [6:5] FSEL 00 Sets RTC calibration output frequency and calibration window. [3:1] INT1PRG 000 Controls the function of INT1. 0 INT0PRG 0 Controls the function of INT0.

0 INT0 input disabled

1 INT0 input enabled

1 X = don’t care

Table 18. Power Management Interrupt Flag SFR (IPSMF, Address 0xF8) 7 0xFF FPSR 0 Power supply restored interrupt flag. Set when the VDD power supply has been restored. This occurs when the source of VSWOUT changes from VBAT to VDD. 6 0xFE FPSM 0 PSM interrupt flag. Set when an enabled PSM interrupt condition occurs. 5 0xFD FSAG 0 Voltage SAG interrupt flag. Set when an ADE energy measurement SAG condition occurs. 4 0xFC Reserved 0 This bit must be kept at 0 for proper operation. 1 0xF9 FBSO 0 Battery switchover interrupt flag. Set when VSWOUT switches from VDD to VBAT. 0 0xF8 FVDCIN 0 VDCIN monitor interrupt flag. Set when VDCIN falls below 1.2 V. Table 19. Battery Switchover Configuration SFR (BATPR, Address 0xF5) [7:2] Reserved 0 These bits must be kept at 0 for proper operation. [1:0] BATPRG 0 Control bits for battery switchover.

00 Battery switchover enabled on low VDD

01 Battery switchover enabled on low VDD and low VDCIN

Table 20. Peripheral Configuration SFR (PERIPH, Address 0xF4) 7 RX2FLAG 0 If set, indicates that an RxD2 edge event has triggered wake-up from PSM2. 6 VSWSOURCE 1 Indicates the power supply that is internally connected to VSWOUT. 0 = VSWOUT is connected to VBAT. 1 = VSWOUT is connected VDD. 5 VDD_OK 1 If set, indicates that the VDD power supply is ready for operation. 2 Reserved 0 This bit must be kept at 0 for proper operation. [1:0] RXPROG 0 Controls the function of the P0.7/SS/T1/RxD2 pin.

00 GPIO

01 RxD2 with wake-up disabled

11 RxD2 with wake-up enabled

Table 21. Power Management Interrupt Enable SFR (IPSME, Address 0xEC) 7 EPSR 0 Enables a PSM interrupt when the power supply restored interrupt flag (FPSR) is set. 5 ESAG 0 Enables a PSM interrupt when the voltage SAG interrupt flag (FSAG) is set. 4 Reserved 0 This bit must be kept at 0 for proper operation. 3 EVADC 0 Enables a PSM interrupt when the VDCINADC monitor interrupt flag (FVADC) is set. 2 EBAT 0 Enables a PSM interrupt when the VBAT monitor interrupt flag (FBAT) is set. 1 EBSO 0 Enables a PSM interrupt when the battery switchover interrupt flag (FBSO) is set. 0 EVDCIN 0 Enables a PSM interrupt when the VDCIN monitor interrupt flag (FVDCIN) is set.

Table 22. Scratch Pad 1 SFR (SCRATCH1, Address 0xFB) [7:0] SCRATCH1 0 Value can be written/read in this register. This value is maintained in all the power saving modes. Table 23. Scratch Pad 2 SFR (SCRATCH2, Address 0xFC) [7:0] SCRATCH2 0 Value can be written/read in this register. This value is maintained in all the power saving modes. Table 24. Scratch Pad 3 SFR (SCRATCH3, Address 0xFD) [7:0] SCRATCH3 0 Value can be written/read in this register. This value is maintained in all the power saving modes. Table 25. Scratch Pad 4 SFR (SCRATCH4, Address 0xFE) [7:0] SCRATCH4 0 Value can be written/read in this register. This value is maintained in all the power saving modes. Note that these scratch pad registers are cleared only when the part loses VDD and VBAT. Table 26. Power Control SFR (POWCON, Address 0xC5) functions are not needed in PSM0 mode. 5 Reserved 0 This bit should be kept at 0 for proper operation. 4 COREOFF 0 Set this bit to shut down the core and enter PSM2 mode if in the PSM1 operating mode. [2:0] CD 010 Controls the core clock frequency, fCORE. fCORE = 4.096 MHz/2CD.

Figure 33. Power Supply Management Interrupt Sources connected to VDD and cleared when VSWOUT is connected to VBAT. 0xEC) enables this event to generate a PSM interrupt. section for details on how VDCIN is measured. to generate a PSM interrupt. Address 0xF8) is set when the VDCIN input level is lower than 1.2 V . initiating a switch from VDD to VBAT.

Figure 37. Power Supply Management Transitions Between Modes

power-on reset or software reset, is 1.024 MHz. In PSM1 mode, or battery mode, VSWOUT is connected to VBAT. a power-on reset or software reset, is 1.024 MHz.

• The RAM in the MCU is no longer valid.
• The program counter for the 8052, also held in volatile memory, becomes invalid when the 2.5 V supply is shut down. Therefore, the program does not resume from where it left off but always starts from the power-on reset vector when the ADE5166/ADE5169/ADE5566/ADE5569 exit PSM2 mode. The 3.3 V peripherals (temperature ADC, V DCINADC, RTC, and LCD) are active in PSM2 mode. They can be enabled or disabled to reduce power consumption and are configured for PSM2 operation when the MCU core is active (see Table 29 for more information about the individual peripherals and their PSM2 configuration). The ADE5166/ADE5169/ADE5566/ADE5569 remain in PSM2 mode until an event occurs to wake them up. In PSM2 mode, the ADE5166/ADE5169/ADE5566/ADE5569 provide four scratch pad RAM SFRs that are maintained during this mode. These SFRs can be used to save data from the PSM0 or PSM1 mode when entering PSM2 mode (see Table 22 to Table 25). In PSM2 mode, the ADE5166/ADE5169/ADE5566/ADE5569 maintain some SFRs (see Table 28). The SFRs that are not listed in this table should be restored when the part enters PSM0 or PSM1 mode from PSM2 mode.

Table 28. SFRs Maintained in PSM2 Mode (RTCCOMP , Address 0xF6); see Table 132. (TEMPCAL, Address 0xF7); see Table 133. Address 0xDF); see Table 55. Address 0xA1); see Table 128. Address 0xA2); see Table 129. in the RTC register list; see Table 134. Address 0x96); see Table 95. Address 0xFB); see Table 22. Address 0xEF); see Table 54. Address 0xFC); see Table 23. Address 0xAC); see Table 99. Address 0xFD); see Table 24. Address 0xAE); see Table 100.

3.3 V PERIPHERALS AND WAKE-UP EVENTS

Table 29. The interrupt flag associated with these events must ADE5169/ADE5566/ADE5569 in PSM2 mode after wake-up. Table 29. 3.3 V Peripherals and Wake-Up Events to the description in the Temperature Measurement section. the description in the External Voltage Measurement section. prior to entering PSM2 mode. Address 0xF4), is set to indicate that VSWOUT is connected to VDD. to be serviced and acknowledged prior to entering PSM2 mode. serviced and acknowledged prior to entering PSM2 mode. and acknowledged prior to entering PSM2 mode. serviced and acknowledged prior to entering PSM2 mode. Scratch Pad N/A N/A N/A N/A The four SCRATCHx registers remain intact in PSM2 mode.

that change the operating mode. over results in a transition from PSM0 to PSM1 operating mode. consumption, user code can initiate a transition to PSM2 mode. (see the 3.3 V Peripherals and Wake-Up Events section). (POWCON, Address 0xC5) to shut down the MCU core. restart. PSM0 code execution begins at the power-on reset vector. used in the ADE energy measurement DSP automatically restarts.

• Enable the battery switchover interrupt (EBSO) if V SWOUT = VDD at power-up.
• Enable the power supply restored interrupt (EPSR) if V SWOUT = VBAT at power-up. An early warning that battery switchover is about to occur is provided by SAG detection and, possibly, by low V DCIN detection (see the Battery Switchover section). For a user-controlled battery switchover, enable automatic battery switchover on low V DD only. Next, enable the low VDCIN event to generate the PSM interrupt. When a low VDCIN event occurs, start data backup. Upon completion of the data backup, enable battery switchover on low VDCIN. Battery switchover occurs 30 ms later. PSM1 BATTERY MODE VSWOUT IS CONNECTED TO VBAT PSM0 NORMAL MODE VSWOUT IS CONNECTED TO VDD PSM2 SLEEP MODE VSWOUT IS CONNECTED TO VBAT POWER SUPPLY RESTORED AUTOMATIC BATTERY SWITCHOVER WAKE-UP EVENT USER CODE DIRECTS MCU TO SHUT DOWN CORE AFTER SERVICING A WAKE-UP EVENT POWER SUPPLY RESTORED 07411-017

Figure 38. Transitioning Between Operating Modes

byte results in reading the data from the previous latched sample. is performed (see Table 30). Table 30. Energy Measurement Pointer Address SFR MDATM SFR and MDATH SFR contents are ignored. write to these registers can take place. the two clock environments is an issue when CD = 0 or CD = 1. SFRs are transferred to another SFR.

Table 31. Energy Measurement SFRs 0x91 R/W MADDPT Energy measurement pointer address. 0x92 R/W MDATL Energy measurement pointer data LSB. 0x93 R/W MDATM Energy measurement pointer data middle byte. 0x94 R/W MDATH Energy measurement pointer data MSB. 0xD1 R VRMSL Vrms measurement LSB. 0xD2 R VRMSM Vrms measurement middle byte. 0xD3 R VRMSH Vrms measurement MSB. 0xD4 R IRMSL Irms measurement LSB. 0xD5 R IRMSM Irms measurement middle byte. 0xD6 R IRMSH Irms measurement MSB. 0xD9 R/W MIRQENL Energy measurement interrupt enable LSB. 0xDA R/W MIRQENM Energy measurement interrupt enable middle byte. 0xDB R/W MIRQENH Energy measurement interrupt enable MSB. 0xDC R/W MIRQSTL Energy measurement interrupt status LSB. 0xDD R/W MIRQSTM Energy measurement interrupt status middle byte. 0xDE R/W MIRQSTH Energy measurement interrupt status MSB. 0xE2 R WAV1L Selection 1 sample LSB. 0xE3 R WAV1M Selection 1 sample middle byte. 0xE4 R WAV1H Selection 1 sample MSB. 0xE5 R WAV2L Selection 2 sample LSB. 0xE6 R WAV2M Selection 2 sample middle byte. 0xE7 R WAV2H Selection 2 sample MSB. Figure 39. ADE5166/ADE5169 Energy Metering Block Diagram

Figure 40. ADE5566/ADE5569 Energy Metering Block Diagram

Table 32. Energy Measurement Register List 0x01 WATTHR R 24 S 0 Reads the Wh accumulator without reset. 0x02 RWATTHR R 24 S 0 Reads the Wh accumulator with reset. 0x03 LWATTHR R 24 S 0 Reads the Wh accumulator synchronous to line cycle. 0x04 VARHR 1 R 24 S 0 Reads the varh accumulator without reset. 0x05 RVARHR 1 R 24 S 0 Reads the varh accumulator with reset. 0x06 LVARHR 1 R 24 S 0 Reads the varh accumulator synchronous to line cycle. MODE2 register (Address 0x0C) is set, this register accumulates Irms. MODE2 register (Address 0x0C) is set, this register accumulates Irms. 0x0A PER_FREQ R 16 U 0 Reads line period or frequency register, depending on MODE2 register. 0x0B MODE1 R/W 8 U 0x06 Sets basic configuration of energy measurement (see Table 33). 0x0C MODE2 R/W 8 U 0x40 Sets basic configuration of energy measurement (see Table 34). 0x0E NLMODE R/W 8 U 0 Sets level of energy no load thresholds (see Table 36). 0x10 PHCAL R/W 8 S 0x40 Sets phase calibration register (see the Phase Compensation section). Voltage SAG Detection section). 0x17 IPEAK R 24 U 0 Reads current peak level without reset (see the Peak Detection section). 0x18 RSTIPEAK R 24 U 0 Reads current peak level with reset (see the Peak Detection section). 0x19 VPEAK R 24 U 0 Reads voltage peak level without reset (see the Peak Detection section). 0x1A RSTVPEAK R 24 U 0 Reads voltage peak level with reset (see the Peak Detection section). 0x1B GAIN R/W 8 U 0 Sets PGA gain of analog inputs (see Table 38). 0x1C IBGAIN 2 R/W 12 S 0 Sets matching gain for IPB current input. 0x1D WGAIN R/W 12 S 0 Sets watt gain register. 0x1E VARGAIN 1 R/W 12 S 0 Sets var gain register. 0x1F VAGAIN R/W 12 S 0 Sets VA gain register. 0x20 WATTOS R/W 16 S 0 Sets watt offset register. 0x21 VAROS 1 R/W 16 S 0 Sets var offset register. 0x22 IRMSOS R/W 12 S 0 Sets current rms offset register. 0x23 VRMSOS R/W 12 S 0 Sets voltage rms offset register. 0x24 WDIV R/W 8 U 0 Sets watt energy scaling register. 0x25 VARDIV 1 R/W 8 U 0 Sets var energy scaling register. 0x26 VADIV R/W 8 U 0 Sets VA energy scaling register. 0x27 CF1NUM R/W 16 U 0 Sets CF1 numerator register. 0x28 CF1DEN R/W 16 U 0x003F Sets CF1 denominator register.

0x29 CF2NUM R/W 16 U 0 Sets CF2 numerator register. 0x2A CF2DEN R/W 16 U 0x003F Sets CF2 denominator register. 0x2B MODE3 R/W 8 U 0 Enables zero-crossing outputs (see Table 39). 0x3B Reserved 0 This register must be set to its default value for proper operation. 0x3C Reserved 0x0300 This register must be set to its default value for proper operation. 0x3D CALMODE 2 R/W 8 U 0 Sets calibration mode (see Table 40). 0x3E Reserved 0 This register must be set to its default value for proper operation. 0x3F Reserved 0 This register must be set to its default value for proper operation. 1 This function is not available in the ADE5166 and ADE5566. 2 This function is not available in the ADE5566 and ADE5569. Table 33. Mode 1 Register (MODE1, Address 0x0B) 7 SWRST 0 Setting this bit resets all of the energy measurement registers to their default values. 6 DISZXLPF 0 Setting this bit disables the zero-crossing low-pass filter. 5 INTE 0 Setting this bit enables the digital integrator for use with a di/dt sensor. 4 SWAPBITS 0 Setting this bit swaps CH1 ADC and CH2 ADC. 3 PWRDN 0 Setting this bit powers down voltage and current ADCs. 2 DISCF2 1 Setting this bit disables Frequency Output CF2. 1 DISCF1 1 Setting this bit disables Frequency Output CF1. 0 DISHPF 0 Setting this bit disables the HPFs in voltage and current channels. Table 34. Mode 2 Register (MODE2, Address 0x0C) [7:6] CF2SEL 01 Configuration bits for CF2 output.

00 CF2 frequency is proportional to active power

01 CF2 frequency is proportional to reactive power1

[5:4] CF1SEL 00 Configuration bits for CF1 output.

00 CF1 frequency is proportional to active power

01 CF1 frequency is proportional to reactive power1

RVAHR, and LVAHR). Note that CF1 cannot be proportional to VA if CF2 is proportional to Irms, and vice versa.

0 If CF1SEL = 1X, CF1 is proportional to VA

1 If CF1SEL = 1X, CF1 is proportional to Irms

2 ZXRMS 0 Logic 1 enables update of rms values synchronously to Voltage ZX. 1 FREQSEL 0 Configuration bit to select period or frequency measurement for the PER_FREQ register (Address 0x0A).

0 The PER_FREQ register holds a period measurement

1 The PER_FREQ register holds a frequency measurement

0 WAVEN 0 When this bit is set, waveform sampling mode is enabled. 1 This function is not available in the ADE5166 and ADE5566.

Table 35. Waveform Mode Register (WAVMODE, Address 0x0D) [7:5] WAV2SEL 000 Waveform Sample 2 selection for samples mode.

000 Current

001 Voltage

010 Active power multiplier output

011 Reactive power multiplier output1

100 VA multiplier output

101 Irms LPF output (low 24-bit)

[4:2] WAV1SEL 000 Waveform Sample 1 selection for samples mode. [1:0] DTRT 00 Waveform samples output data rate. 1 This function is not available in the ADE5166 and ADE5566. Table 36. No Load Configuration Register (NLMODE, Address 0x0E) 7 DISVARCMP 1 0 Setting this bit disables fundamental var gain compensation over line frequency. [5:4] VANOLOAD 00 Apparent power no load threshold.

00 No load detection disabled

[3:2] VARNOLOAD 1 00 Reactive power no load threshold. [1:0] APNOLOAD 00 Active power no load threshold. 1 This function is not available in the ADE5166 and ADE5566.

Table 37. Accumulation Mode Register (ACCMODE, Address 0x0F) 7 ICHANNEL 1 0 This bit indicates the current channel used to measure energy in antitampering mode. 6 FAULTSIGN 1 0 Configuration bit to select the event that triggers a fault interrupt. 0 = FAULTSIGN interrupt occurs when the part enters fault mode. 1 = FAULTSIGN interrupt occurs when the part enters normal mode. 5 VARSIGN 2 0 Configuration bit to select the event that triggers a reactive power sign interrupt. If cleared to 0, a VARSIGN interrupt occurs when reactive power changes from positive to negative. If set to 1, a VARSIGN interrupt occurs when reactive power changes from negative to positive. 4 APSIGN 0 Configuration bit to select the event that triggers an active power sign interrupt. If cleared to 0, an APSIGN interrupt occurs when active power changes from positive to negative. If set to 1, an APSIGN interrupt occurs when active power changes from negative to positive. 3 ABSVARM 2 0 Logic 1 enables absolute value accumulation of reactive power in energy register and pulse output. 2 SAVARM 2 0 Logic 1 enables reactive power accumulation depending on the sign of the active power. If active power is positive, var is accumulated as it is. If active power is negative, the sign of the var is reversed for the accumulation. 1 POAM 0 Logic 1 enables positive-only accumulation of active power in energy register and pulse output. 0 ABSAM 0 Logic 1 enables absolute value accumulation of active power in energy register and pulse output. 1 This function is not available in the ADE5566 and ADE5569. 2 This function is not available in the ADE5166 and ADE5566. Table 38. Gain Register (GAIN, Address 0x1B) [7:5] PGA2 000 These bits define the voltage channel input gain.

000 Gain = 1

001 Gain = 2

010 Gain = 4

011 Gain = 8

100 Gain = 16

3 CFSIGN_OPT 0 This bit defines where the CF change of sign detection (APSIGN or VARSIGN) is implemented.

0 Filtered power signal

1 On a per CF pulse basis

[2:0] PGA1 000 These bits define the current channel input gain. Table 39. Mode 3 Register (MODE3, Address 0x2B) 1 ZX1 0 Setting this bit enables the zero-crossing output signal on P1.2. 0 ZX2 0 Setting this bit enables the zero-crossing output signal on P0.5.

Table 40. Calibration Mode Register (CALMODE, Address 0x3D) 1 [7:6] Reserved 00 These bits must be kept at 0 for proper operation. [5:4] SEL_I_CH 00 These bits define the current channel used for energy measurements.

00 Current channel automatically selected by the tampering condition

01 Current channel connected to IPA

10 Current channel connected to IPB

11 Current channel automatically selected by the tampering condition

3 V_CH_SHORT 0 Logic 1 shorts the voltage channel to ground. 2 I_CH_SHORT 0 Logic 1 shorts the current channel to ground. [1:0] Reserved 00 These bits must be kept at 0 for proper operation. 1 This register is not available in the ADE5566 and ADE5569. Table 41. Interrupt Status 1 SFR (MIRQSTL, Address 0xDC) automatically cleared when all of the enabled ADE status flags are cleared. 5 FAULTSIGN 1 Logic 1 indicates that the fault mode has changed according to the configuration of the ACCMODE register. 4 VARSIGN 2 Logic 1 indicates that the reactive power sign has changed according to the configuration of the ACCMODE register. 3 APSIGN Logic 1 indicates that the active power sign has changed according to the configuration of the ACCMODE register. used to reflect that the part is entering the Irms no load mode. 1 RNOLOAD 2 Logic 1 indicates that an interrupt has been caused by reactive power no load detection. 0 APNOLOAD Logic 1 indicates that an interrupt has been caused by active power no load detection. 1 This function is not available in the ADE5566 and ADE5569. 2 This function is not available in the ADE5166 and ADE5566. Table 42. Interrupt Status 2 SFR (MIRQSTM, Address 0xDD) enabled by clearing Bit 2 of the MODE1 register. enabled by clearing Bit 1 of the MODE1 register. 5 VAEOF Logic 1 indicates that the VAHR register has overflowed. 4 REOF 1 Logic 1 indicates that the VARHR register has overflowed. 3 AEOF Logic 1 indicates that the WATTHR register has overflowed. 2 VAEHF Logic 1 indicates that the VAHR register is half full. 1 REHF 1 Logic 1 indicates that the VARHR register is half full. 0 AEHF Logic 1 indicates that the WATTHR register is half full. 1 This function is not available in the ADE5166 or ADE5566. Table 43. Interrupt Status 3 SFR (MIRQSTH, Address 0xDE) 7 RESET Indicates the end of a reset (for both software and hardware reset). 5 WFSM Logic 1 indicates that new data is present in the waveform registers (Address 0xE2 to Address 0xE7). 4 PKI Logic 1 indicates that the current channel has exceeded the IPKLVL value. 3 PKV Logic 1 indicates that the voltage channel has exceeded the VPKLVL value. 2 CYCEND Logic 1 indicates the end of the energy accumulation over an integer number of half-line cycles. 1 ZXTO Logic 1 indicates that no zero crossing on the line voltage occurred for the last ZXTOUT half-line cycles. 0 ZX Logic 1 indicates detection of a zero crossing in the voltage channel.

eliminates false detection of a fault due to noise at light loads. transducers be closely matched. The current channel selected for measurement can also be forced. ment is selected automatically, based on the fault detection. entering a fault condition or a normal condition. the 8052 core has a pending ADE interrupt. in the Interrupt Status 1 SFR (MIRQSTL, Address 0xDC) is set. input occurs. IPA remains the active input. between IPA and IPB, in this order, becomes greater than 6.25% of IPB. potential chatter between IPA and IPB calibration. power-up. The phase circuit, CT, is connected to IPA in the diagram. Figure 49. Fault Conditions for Inactive Input Greater Than Active Input

than MCLK/160 × ZXTOUT seconds. Figure 56. Zero-Crossing Timeout Detection 60 Hz, the value of the period register is approximately 0d6827. when the line is established and the measurement does not change. line frequency is 60 Hz, the value of the frequency register is 0d960. lished and the measurement does not change. cycles. This condition is illustrated in Figure 57.

3 LINE CYCLES

Figure 57. SAG Detection contents of the SAG level register.

ADE5166/ADE5169/ADE5566/ADE5569 Rev. B | Page 60 of 156 Active Power Gain Calibration Figure 66 shows the signal processing chain for the active power calculation in the ADE5166/ADE5169/ADE5566/ADE5569. As explained previously, the active power is calculated by filtering the output of the multiplier with a low-pass filter. Note that, when reading the waveform samples from the output of LPF2, the gain of the active energy can be adjusted by using the multiplier and writing a twos complement, 12-bit word to the the watt gain reg- ister (WGAIN, Address 0x1D[11:0]). Equation 10 shows how the gain adjustment is related to the contents of the watt gain register. ⎧ + ×= 122

1 WGAINPowerActiveWGAINOutput (10)

For example, when 0x7FF is written to the watt gain register, the power output is scaled up by 50% (0x7FF = 2047d, 2047/212 = 0.5). Similarly, 0x800 = −2048d (signed, twos complement), and power output is scaled by −50%. Each LSB scales the power output by 0.0244%. The minimum output range is given when the watt gain register contents are equal to 0x800, and the maximum output range is given by writing 0x7FF to the watt gain register. This register can be used to calibrate the active power (or energy) calculation in the ADE5166/ADE5169/ADE5566/ADE5569. Active Power Offset Calibration The ADE5166/ADE5169/ADE5566/ADE5569 also incorporate an active power offset register (W ATTOS, Address 0x20[15:0]). It is a signed, twos complement, 16-bit register that can be used to remove offsets in the active power calculation (see Figure 66). An offset can exist in the power calculation due to crosstalk between channels on the PCB or in the IC itself. The offset calibration allows the contents of the active power register to be maintained at 0 when no power is being consumed. The 256 LSBs (W ATTOS = 0x0100) written to the active power offset register are equivalent to 1 LSB in the waveform sample register. Assuming the average value, output from LPF2 is 0xCCCCD (838,861d) when inputs on the voltage and current channels are both at full scale. At −60 dB down on the current channel (1/1000 of the current channel full-scale input), the average word value output from LPF2 is 838.861 (838,861/1000). One LSB in the LPF2 output has a measurement error of 1/838.861 × 100% = 0.119% of the average value. The active power offset register has a resolution equal to 1/256 LSB of the waveform register. Therefore, the power offset correction resolution is 0.000464%/LSB (0.119%/256) at −60 dB. Active Power Sign Detection The ADE5166/ADE5169/ADE5566/ADE5569 can detect a change of sign in the active power. The APSIGN flag (Bit 3) in the Interrupt Status 1 SFR (MIRQSTL, Address 0xDC) records that a change of sign has occurred according to the APSIGN bit (Bit 4) in the ACCMODE register (Address 0x0F). If the APSIGN flag (Bit 3) is set in the Interrupt Enable 1 SFR (MIRQENL, Address 0xD9), the 8052 core has a pending ADE interrupt. The ADE interrupt stays active until the APSIGN status bit is cleared (see the Energy Measurement Interrupts section). When the APSIGN bit (Bit 4) in the ACCMODE register (Address 0x0F) is cleared (default), a transition from positive to negative active power sets the APSIGN flag (Bit 3) in the Interrupt Status 1 SFR (MIRQSTL, Address 0xDC). When the APSIGN bit (Bit 4) in the ACCMODE register (Address 0x0F) is set, the APSIGN flag (Bit 3) in the MIRQSTL SFR (Address 0xDC) is set when a transition from negative to positive active power occurs. Active Power No Load Detection The ADE5166/ADE5169/ADE5566/ADE5569 include a no load threshold feature on the active power that eliminates any creep effects in the meter. The part accomplishes this by not accumu- lating energy if the multiplier output is below the no load threshold. When the active power is below the no load threshold, the APNOLOAD flag (Bit 0) in the Interrupt Status 1 SFR (MIRQSTL, Address 0xDC) is set. If the APNOLOAD bit (Bit 0) is set in the Interrupt Enable 1 SFR (MIRQENL, Address 0xD9), the 8052 core has a pending ADE interrupt. The ADE interrupt stays active until the APNOLOAD status bit is cleared (see the Energy Measurement Interrupts section). The no load threshold level can be selected by setting the APNOLOAD bits (Bits[1:0]) in the NLMODE register (Address 0x0E). Setting these bits to 0b00 disables the no load detection; setting them to 0b01, 0b10, or 0b11 sets the no load detection threshold to 0.015%, 0.0075%, or 0.0037% of the multi- plier full-scale output frequency, respectively. The IEC 62053-21 specification states that the meter must start up with a load of ≤0.4% I PB, which translates to 0.0167% of the full-scale output frequency of the multiplier.

expressed mathematically, as shown in Equation 11. Conversely, energy is given as the integral of power. continuous time. Equation 13 expresses the relationship. n is the discrete time sample number. T is the discrete time sample period. is continuously added to the internal active energy register. positive-only accumulation mode. is accumulated in a 49-bit internal energy accumulation register. to the active energy register (W ATTHR, Address 0x01[23:0]). power signal is accumulated in an internal 49-bit, signed register. Figure 66. Active Energy Calculation

ment is related to the contents of the var gain register. Interrupt Status 1 SFR (MIRQSTL, Address 0xDC). reactive power (or energy) calculation in the ADE5169/ADE5569. energy when the multiplier output is below the no load threshold. Measurement Interrupts section). the full-scale output frequency of the multiplier, respectively. Note that the average reactive power is a signed calculation. is enabled and +90° phase shift when the integrator is disabled. Table 47. Sign of Reactive Power Calculation

Line Cycle Active Energy Accumulation Mode section. can accumulate active power for up to 65,535 half-line cycles. LV ARHR register is overwritten by a new value. LSB size of these two registers is equivalent. Figure 75. Line Cycle Reactive Energy Accumulation Mode

cycle apparent energy accumulation mode is always active. register (Address 0x12), which is an unsigned 16-bit register. in the Interrupt Status 3 SFR (MIRQSTH, Address 0xDE) is set. half-line cycles is then counted until LINCYC is reached. Interrupt Status 1 SFR (MIRQSTL, Address 0xDC) is set. full-scale output frequency of the multiplier, respectively. threshold is the same as for the apparent energy. (Address 0x28 and Address 0x2A) registers. Figure 78. Line Cycle Apparent Energy Accumulation Mode

ADE5166/ADE5169/ADE5566/ADE5569 Rev. B | Page 73 of 156 ENERGY MEASUREMENT INTERRUPTS The energy measurement part of the ADE5166/ADE5169/ ADE5566/ADE5569 has its own interrupt vector for the 8052 core, Vector Address 0x004B (see the Interrupt Vectors section). The bits set in the Interrupt Enable 1 SFR (MIRQENL, Address 0xD9), Interrupt Enable 2 SFR (MIRQENM, Address 0xDA), and Interrupt Enable 3 SFR (MIRQENH, Address 0xDB) enable the energy measurement interrupts that are allowed to interrupt the 8052 core. If an event is not enabled, it cannot create a system interrupt. The ADE interrupt stays active until the status bit that created the interrupt is cleared. The status bit is cleared when a 0 is written to this register bit.

be configured to continue functioning in PSM1 and PSM2 modes. before using it for compensation. Table 49. Temperature, Battery, and Supply Voltage Measurement SFRs 0xF9 R/W STRBPER Peripheral ADC strobe period (see Table 50). 0xF3 R/W DIFFPROG Temperature and supply delta (see Table 51). 0xD8 R/W ADCGO Start ADC measurement (see Table 52). 0xFA R/W BATVTH Battery detection threshold (see Table 53). 0xEF R/W VDCINADC VDCINADC value (see Table 54). 0xDF R/W BATADC Battery ADC value (see Table 55). 0xD7 R/W TEMPADC Temperature ADC value (see Table 56). Table 50. Peripheral ADC Strobe Period SFR (STRBPER, Address 0xF9) [7:6] Reserved 00 These bits must be kept at 0 for proper operation. [5:4] VDCIN_PERIOD 00 Period for background external voltage measurements.

00 No VDCIN measurement

[3:2] BATT_PERIOD 00 Period for background battery level measurements.

00 No battery measurement

[1:0] TEMP_PERIOD 00 Period for background temperature measurements.

00 No temperature measurement

Table 51. Temperature and Supply Delta SFR (DIFFPROG, Address 0xF3) temperature measurement that should interrupt 8052.

000 No interrupt

111 Every temperature measurement

external voltage measurement that should interrupt 8052.

111 Every VDCIN measurement

Table 52. Start ADC Measurement SFR (ADCGO, Address 0xD8) 7 0xDF PLLACK 0 Set this bit to clear the PLL fault bit, PLL_FLT (Bit 4), in the PERIPH SFR (Address 0xF4). A PLL fault is generated if a reset is caused because the PLL lost lock. [6:3] 0xDE to 0xDB Reserved 0000 Reserved. the measurement request is received by the ADC. measurement request is received by the ADC. measurement request is received by the ADC. Table 53. Battery Detection Threshold SFR (BATVTH, Address 0xFA) [7:0] BATVTH 0 The battery ADC value is compared to this register, the battery detection threshold register. If BATADC is lower than the threshold, an interrupt is generated. Table 54. VDCINADC Value SFR (VDCINADC, Address 0xEF) [7:0] VDCINADC 0 The VDCINADC value in this register is updated when an ADC interrupt occurs. Table 55. Battery ADC Value SFR (BATADC, Address 0xDF) [7:0] BATADC 0 The battery ADC value in this register is updated when an ADC interrupt occurs. Table 56. Temperature ADC Value SFR (TEMPADC, Address 0xD7) [7:0] TEMPADC 0 The temperature ADC value in this register is updated when an ADC interrupt occurs.

ADE5166/ADE5169/ADE5566/ADE5569 Rev. B | Page 76 of 156 TEMPERATURE MEASUREMENT To provide a digital temperature measurement, each ADE5166/ ADE5169/ADE5566/ADE5569 includes a dedicated ADC. The 8-bit temperature ADC value SFR (TEMPADC, Address 0xD7) holds the results of the temperature conversion. The resolution of the temperature measurement is 0.83°C/LSB. There are two ways to initiate a temperature conversion: a single temperature measure- ment or background temperature measurements. Single Temperature Measurement Set the TEMP_ADC_GO bit (Bit 1) in the start ADC measure- ment SFR (ADCGO, Address 0xD8) to obtain a temperature measurement (see Table 52). An interrupt is generated when the conversion is complete and when the temperature measurement is available in the temperature ADC value SFR (TEMPADC, Address 0xD7). Background Temperature Measurements Background temperature measurements are disabled by default. To configure the background temperature measurement mode, set a temperature measurement interval in the peripheral ADC strobe period SFR (STRBPER, Address 0xF9). Temperature mea- surements are then performed periodically in the background (see Table 50). When a temperature conversion completes, the new temperature ADC value is compared to the last temperature ADC value that created an interrupt. If the absolute difference between the two values is greater than the setting of the TEMP_DIFF bits in the temperature and supply delta SFR (DIFFPROG, Address 0xF3[5:3]), a TEMPADC interrupt is generated (see Table 51). This allows temperature measurements to take place completely in the back- ground, requiring MCU activity only if the temperature changes more than a configurable delta. To set up background temperature measurement Initiate a single temperature measurement by setting the TEMP_ADC_GO bit in the start ADC measurement SFR (ADCGO, Address 0xD8[1]). Upon completion of this measurement, configure the TEMP_DIFF bits in the temperature and supppy delta SFR (DIFFPROG, Address 0xF3[5:3]) to establish the change in temperature that triggers an interrupt. Set up the interval for background temperature measurements by configuring the TEMP_PERIOD bits in the peripheral ADC strobe period SFR (STRBPER, Address 0xF9[1:0]). Temperature ADC in PSM0, PSM1, and PSM2 Modes Depending on the operating mode of the ADE5166/ADE5169/ ADE5566/ADE5569, a temperature conversion is initiated only by certain actions.

• In PSM0 operating mode, the 8052 is active. Temperature measurements are available in the background measurement mode and by initiating a single measurement.
• In PSM1 operating mode, the 8052 is active, and the part is battery powered. Single temperature measurements can be initiated by setting the TEMP_ADC_GO bit in the start ADC measurement SFR (ADCGO, Address 0xD8[1]). Background temperature measurements are not available. In PSM2 operating mode, the 8052 is not active. Temperature conversions are available through the background measure- ment mode only. The temperature ADC value SFR (TEMPADC, Address 0xD7) is updated with a new value only when a temperature ADC interrupt occurs. Temperature ADC Interrupt The temperature ADC can generate an ADC interrupt when at least one of the following conditions occurs:
• The difference between the new temperature ADC value and the last temperature ADC value generating an ADC interrupt is larger than the value set in the TEMP_DIFF bits. The temperature ADC conversion, initiated by setting start ADC measurement SFR (ADCGO, Address 0xD8), finishes. When the ADC interrupt occurs, a new value is available in the temperature ADC value SFR (TEMPADC, Address 0xD7). Note that there is no flag associated with this interrupt. BATTERY MEASUREMENT To provide a digital battery measurement, each ADE5166/ ADE5169/ADE5566/ADE5569 includes a dedicated ADC. The battery measurement is available in the 8-bit battery ADC value SFR (BATADC, Address 0xDF). The battery measurement has a resolution of 14.6 mV/LSB. A battery conversion can be initiated by two methods: a single battery measurement or background battery measurements. Single Battery Measurement To obtain a battery measurement, set the BATT_ADC_GO bit in the start ADC measurement SFR (ADCGO, Address 0xD8[0]). An interrupt is generated when the conversion is done and when the battery measurement is available in the battery ADC value SFR (BATADC, Address 0xDF). Background Battery Measurements To configure background measurements for the battery, establish a measurement interval in the peripheral ADC strobe period SFR (STRBPER, Address 0xF9). Battery measurements are then performed periodically in the background (see Table 50). When a battery conversion completes, the battery ADC value is compared to the low battery threshold, established in the battery detection threshold SFR (BATVTH, Address 0xFA). If the battery ADC value is below this threshold, a low battery flag is set. This low battery flag is the FBAT bit (Bit 2) in the power management interrupt flag SFR (IPSMF, Address 0xF8), used for power supply management. This low battery flag can be enabled to generate the PSM interrupt by setting the EBAT bit (Bit 2) in the power management interrupt enable SFR (IPSME, Address 0xEC).

ADE5166/ADE5169/ADE5566/ADE5569 Rev. B | Page 77 of 156 This method allows battery measurement to take place completely in the background, requiring MCU activity only if the battery drops below a user-specified threshold. To set up background battery measurements, follow these steps: Configure the battery detection threshold SFR (BATVTH, Address 0xFA) to establish a low battery threshold. If the BATADC measurement is below this threshold, the FBAT bit (Bit 2) in the power management interrupt flag SFR (IPSMF, Address 0xF8) is set. Set up the interval for background battery measurements by configuring the BATT_PERIOD bits in the peripheral ADC strobe period SFR (STRBPER, Adress 0xF9[3:2]). Battery ADC in PSM0, PSM1, and PSM2 Modes Depending on the operating mode, a battery conversion is initiated only by certain actions.

• In PSM0 operating mode, the 8052 is active. Battery mea- surements are available in the background measurement mode and by initiating a single measurement.
• In PSM1 operating mode, the 8052 is active, and the part is battery powered. Single battery measurements can be initiated by setting the BATT_ADC_GO bit in the start ADC measurement SFR (ADCGO, Address 0xD8[0]). Background battery measurements are not available. In PSM2 operating mode, the 8052 is not active. Unlike temperature and VDCIN measurements, the battery conversions are not available in this mode. Battery ADC Interrupt The battery ADC can generate an ADC interrupt when at least one of the following conditions occurs: The new battery ADC value is smaller than the value set in the battery detection threshold SFR (BATVTH, Address 0xFA), indicating a battery voltage loss. A single battery measurement, initiated by setting the BATT_ADC_GO bit in the start ADC measurement SFR (ADCGO, Address 0xD8[0]), finishes. When the battery flag (FBAT, Bit 2) is set in the power manage- ment interrupt flag SFR (IPSMF, Address 0xF8), a new ADC value is available in the battery ADC value SFR (BATADC, Address 0xDF). This battery flag can be enabled as a source of the PSM interrupt to generate a PSM interrupt every time the battery drops below a set voltage threshold or after a single conversion initiated by setting the BATT_ADC_GO bit in the start ADC measurement SFR (ADCGO, Address 0xD8[0]) is ready. The battery ADC value SFR (BATADC, Address 0xDF) is updated with a new value only when the battery flag (FBAT) is set in the power management interrupt flag SFR (IPSMF, Address 0xF8). EXTERNAL VOLTAGE MEASUREMENT The ADE5166/ADE5169/ADE5566/ADE5569 include a dedicated ADC to provide a digital measurement of an external voltage on the VDCIN pin. The 8-bit VDCINADC value SFR (VDCINADC, Address 0xEF) holds the results of the conversion. The resolution of the external voltage measurement is 15.3 mV/LSB. There are two ways to initiate an external voltage conversion: by using a single external voltage measurement or through background external voltage measurements. Single External Voltage Measurement To obtain an external voltage measurement, set the VDCIN_ ADC_GO bit in the start ADC measurement SFR (ADCGO, Address 0xD8[2]). An interrupt is generated when the conversion is done and when the external voltage measurement is available in the V DCINADC value SFR (VDCINADC, Address 0xEF). Background External Voltage Measurements Background external voltage measurements are disabled by default. To configure the background external voltage measure- ment mode, set an external voltage measurement interval in the peripheral ADC strobe period SFR (STRBPER, Address 0xF9). External voltage measurements are performed periodically in the background (see Table 50). When an external voltage conversion is complete, the new external voltage ADC value is compared to the last external voltage ADC value that created an interrupt. If the absolute difference between the two values is greater than the setting of the VDCIN_DIFF bits in the temperature and supply delta SFR (DIFFPROG, Address 0xF3[2:0]), a V DCINADC flag is set. This VDCINADC flag is FV ADC (Bit 3) in the power management interrupt flag SFR (IPSMF, Address 0xF8), which is used for power supply management. This V DCINADC flag can be enabled to generate a PSM interrupt by setting the EV ADC bit (Bit 3) in the power management interrupt enable SFR (IPSME, Address 0xEC). This method allows external voltage measurements to take place completely in the background, requiring MCU activity only if the external voltage has changed more than a confi- gurable delta. To set up background external voltage measurements Initiate a single external voltage measurement by setting the VDCIN_ADC_GO bit in the start ADC measurement SFR (ADCGO, Address 0xD8[2]). 2. Upon completion of this measurement, configure the VDCIN_DIFF bits in the temperature and supply delta SFR (DIFFPROG, Address 0xF3[2:0]) to establish the change in voltage that sets the FV ADC bit in the power manage-ment interrupt flag SFR (IPSMF, Address 0xF8[3]). Set up the interval for the background external voltage measurements by configuring the VDCIN_PERIOD bits in the peripheral ADC strobe period SFR (STRBPER, Address 0xF9[5:4]).

ADE5166/ADE5169/ADE5566/ADE5569 Rev. B | Page 78 of 156 External Voltage ADC in PSM1 and PSM2 Modes An external voltage conversion is initiated only by certain actions that depend on the operating mode of the ADE5166/ADE5169/ ADE5566/ADE5569. In PSM0 operating mode, the 8052 is active. External voltage measurements are available in the background measurement mode and by initiating a single measurement. In PSM1 operating mode, the 8052 is active and the part is powered from battery. Single external voltage measurements can be initiated by setting VDCIN_ADC_GO in the start ADC measurement SFR (ADCGO, Address 0xD8[2]). Background external voltage measurements are not available. In PSM2 operating mode, the 8052 is not active. External voltage conversions are available through the background measurement mode only. The external voltage ADC in the V DCINADC value SFR (VDCINADC, Address 0xEF) is updated with a new value only when an external voltage ADC interrupt occurs. External Voltage ADC Interrupt The external voltage ADC can generate an ADC interrupt when at least one of the following conditions occurs: The difference between the new external voltage ADC value and the last external voltage ADC value generating an ADC interrupt is larger than the value set in the VDCIN_DIFF bits in the temperature and supply delta SFR (DIFFPROG, Address 0xF3[2:0]). The external voltage ADC conversion, initiated by setting the VDCIN_ADC_GO bit in the start ADC measurement SFR (ADCGO, Address 0xD8[2]), finishes. When the ADC interrupt occurs, a new value is available in the V DCINADC value SFR (VDCINADC, Address 0xEF). Note that there is no flag associated with this interrupt.

8052 MCU CORE ARCHITECTURE

been made to it in the ADE5166/ADE5169/ADE5566/ADE5569. Figure 81. Block Diagram Showing Programming Model via the SFRs The registers used by the MCU are summarized in Table 57. Table 57. 8051 SFRs Table 58. Program Status Word SFR (PSW, Address 0xD0) 7 0xD7 CY Carry flag. Modified by ADD, ADDC, SUBB, MUL, and DIV instructions. 6 0xD6 AC Auxiliary carry flag. Modified by ADD and ADDC instructions. 5 0xD5 F0 General-purpose flag available to the user. [4:3] 0xD4, 0xD3 RS1, RS0 Register bank select bits. 2 0xD2 OV Overflow flag. Modified by ADD, ADDC, SUBB, MUL, and DIV instructions. 1 0xD1 F1 General-purpose flag available to the user. PSW 0xD0 Yes Program status word (see Table 58). PCON 0x87 No Program control (see Table 59). DPL 0x82 No Data pointer low (see Table 60). DPH 0x83 No Data pointer high (see Table 61). DPTR 0x82 and 0x83 No Data pointer (see Table 62). SP 0x81 No Stack pointer (see Table 63). SPH 0xB7 No Stack pointer high (see Table 64). STCON 0xBF No Stack boundary (see Table 65). CFG 0xAF No Configuration (see Table 66).

Table 59. Program Control SFR (PCON, Address 0x87) 7 SMOD 0 Double baud rate control. [6:0] Reserved 0 Reserved. These bits must be kept at 0 for proper operation. Table 60. Data Pointer Low SFR (DPL, Address 0x82) [7:0] DPL 0 These bits contain the low byte of the data pointer. Table 61. Data Pointer High SFR (DPH, Address 0x83) [7:0] DPH 0 These bits contain the high byte of the data pointer. Table 62. Data Pointer SFR (DPTR, Address 0x82 and Address 0x83) [15:0] DP 0 These bits contain the 2-byte address of the data pointer. DPTR is a combination of the DPH and DPL SFRs. Table 63. Stack Pointer SFR (SP, Address 0x81) [7:0] SP 0 These bits contain the eight LSBs of the pointer for the stack. Table 64. Stack Pointer High SFR (SPH, Address 0xB7) 7 Reserved 1 Reserved. This bit must be set to 1 for proper operation. 6 SBFLG 0 Stack bottom flag. 5 SSA[10] 0 Stack Starting Address Bit 10. 4 SSA[9] 0 Stack Starting Address Bit 9. 3 SSA[8] 1 Stack Starting Address Bit 8. 2 SP[10] 0 Stack Address Bit 10. 1 SP[9] 0 Stack Address Bit 9. 0 SP[8] 1 Stack Address Bit 8. Table 65. Stack Boundary SFR (STCON, Address 0xBF) [7:3] WTRLINE 0 Contains the stack waterline setting bits. 2 INT_RST 0 Interrupt/reset selection bit.

0 An interrupt is issued when a stack violation occurs

1 A reset is issued when a stack violation occurs

1 SBE 0 Stack boundary enable bit. Table 66. Configuration SFR (CFG, Address 0xAF) 7 Reserved 1 Reserved. This bit should be left set for proper operation. 6 EXTEN 0 Enhanced UART enable bit.

0 Standard 8052 UART without enhanced error checking features

1 Enhanced UART with enhanced error checking (see the UART Additional Features section)

5 SCPS 0 Synchronous communication selection bit.

0 I2C port is selected for control of the shared I2C/SPI (MOSI, MISO, SCLK, and SS) pins and SFRs

1 SPI port is selected for control of the shared I2C/SPI (MOSI, MISO, SCLK, and SS) pins and SFRs

ADE5166/ADE5169/ADE5566/ADE5569 Rev. B | Page 81 of 156 Bit Mnemonic Default Description 4 MOD38EN 0 38 kHz modulation enable bit. MOD38EN Result 0 38 kHz modulation is disabled 1 38 kHz modulation is enabled on the pins selected by the MOD38 bits in the EPCFG SFR (Address 0x9F[7:0]) [3:2] Reserved 00 Reserved. These bits should be kept at 0 for proper operation. [1:0] XREN1, XREN0

01 XREN1, XREN0 Result

XREN1 or XREN0 = 1 Enable MOVX instruction to use 256 bytes of extended RAM XREN1 and XREN0 = 0 Disable MOVX instruction BASIC 8052 REGISTERS Program Counter (PC) The program counter holds the 2-byte address of the next instruc- tion to be fetched. The PC is initialized with 0x00 at reset and is incremented after each instruction is performed. Note that the amount that is added to the PC depends on the number of bytes in the instruction; therefore, the increment can range from one to three bytes. The program counter is not directly accessible to the user but can be directly modified by CALL and JMP instruc- tions that change which part of the program is active. Instruction Register (IR) The instruction register holds the opcode of the instruction being executed. The opcode is the binary code that results from assem- bling an instruction. This register is not directly accessible to the user. Register Banks There are four banks, each containing an 8-byte-wide register, for a total of 32 bytes of registers. These registers are convenient for temporary storage of mathematical operands. An instruction in- volving the accumulator and a register can be executed in one clock cycle, as opposed to two clock cycles, to perform an instruction involving the accumulator and a literal or a byte of general-purpose RAM. The register banks are located in the first 32 bytes of RAM. The active register bank is selected by RS0 and RS1 in the program status word SFR (PSW , Address 0xD0[4:3]). Accumulator The accumulator is a working register, storing the results of many arithmetic or logical operations. The accumulator is used in more than half of the 8052 instructions, where it is usually referred to as A. The program status word SFR (PSW) constantly monitors the number of bits that are set in the accumulator to determine if it has even or odd parity. The accumulator is stored in the SFR space (see Table 57). B Register The B register is used by the multiply and divide instructions, MUL AB and DIV AB, to hold one of the operands. Because it is not used for many instructions, it can be used as a scratch pad register like those in the register banks. The B register is stored in the SFR space (see Table 57). Program Status Word (PSW) The PSW SFR (PSW , Address 0xD0) reflects the status of arithmetic and logical operations through carry, auxiliary carry, and overflow flags. The parity flag reflects the parity of the contents of the accumulator, which can be helpful for communication protocols. The program status word SFR is bit addressable (see Table 58). Data Pointer (DPTR) The data pointer SFR (DPTR, Address 0x82 and Address 0x83) is made up of two 8-bit registers: DPL (low byte, Address 0x82), and DPH (high byte, Address 0x83). These SFRs provide memory addresses for internal code and data access. The DPTR can be manipulated as a 16-bit register (DPTR = DPH, DPL) or as two independent 8-bit registers (DPH and DPL) (see Table 60 and Table 61). The 8052 MCU core architecture supports dual data pointers (see the 8052 MCU Core Architecture section). Stack Pointer (SP) The stack pointer SFR (SP , Address 0x81) keeps track of the current address of the top of the stack. To push a byte of data onto the stack, the stack pointer is incremented, and the data is moved to the new top of the stack. To pop a byte of data off the stack, the top byte of data is moved into the awaiting address, and the stack pointer is decremented. The stack uses a last in, first out (LIFO) method of data storage because the most recent addition to the stack is the first to come off it. The stack is used during CALL and RET instructions to keep track of the address to move into the PC when returning from the function call. The stack is also manipulated when vectoring for interrupts, to keep track of the prior state of the PC.

ADE5166/ADE5169/ADE5566/ADE5569 Rev. B | Page 82 of 156 The stack resides in the upper part of the extended internal RAM. The SP bits in the stack pointer SFR (SP , Address 0x81[7:0]) and the SP bits in the stack pointer high SFR (SPH, Address 0xB7[2:0]) hold the address of the stack in the extended RAM. The advantage of this solution is that the use of the general-purpose RAM can be limited to data storage. The use of the extended internal RAM can be limited to the stack or, alternatively, split between the stack and data storage if more space is required. This separation limits the chance of data corruption because the stack can be contained in the upper section of the XRAM and does not overflow into the lower section containing data. Data can still be stored in extended RAM by using the MOVX command. The default starting address for the stack is 0x100, electing the upper 1792 bytes of XRAM for the stack operation. The starting address can be reconfigured to reduce the stack by writing to the SSA bits in the stack pointer high SFR (SPH, Address 0xB7[5:3]). These three bits set the value of the three most significant bits of the stack pointer. For example, setting the SSA bits to a value of 110b moves the default starting address of the stack to 0x600, allowing the highest 512 bytes of the XRAM to be used for stack operation. If the stack reaches the top of the XRAM and overflows, the stack pointer rolls over to the default starting address that is written in the SSA bits (Address 0xB7[5:3]). Care should be taken if altering the default starting address of the stack because, should the stack overflow or underflow, unwanted overwrite operations may occur. Stack Boundary Protection As a warning signal that the stack pointer is extending outside the specified range, a stack boundary protection feature is included. This feature is controlled through the stack boundary SFR (STCON, Address 0xBF) and is disabled by default. To enable this feature, set the boundary protection enable bit (SBE, Bit 1) in the STCON SFR. The stack boundary protection works in two ways to protect the remainder of the XRAM from being corrupted. The waterline detection feature monitors the top of the stack and warns the user when the stack pointer is reaching the overflow point. By setting the WTRLINE bits in the STCON SFR (Address 0xBF[7:3]), the level of the waterline below the top of the XRAM can be set. For example, by setting STCON[7:3] to the maximum value of 0x1F , the waterline is set to its minimum value of 0x7FF − 0x1F = 0x7F0. Similarly, by setting STCON[7:3] to 0x1, the waterline is set at the top of the RAM space, Address 0x7FE. Note that if STCON[7:3] are set to 000b, the feature is effectively disabled and no interrupt or reset is generated. The bottom of the stack is also preserved by the stack boundary feature. Should the stack pointer be written to a value lower than the default stack starting address defined in Bits[5:3] of the SPH SFR, a warning is issued and the perpetrating command is ignored. The protection for both the waterline and the stack starting addresses are enabled simultaneously by setting the SBE bit in the STCON SFR (Address 0xBF[1]). When enabled, the stack boundary protection can be configured to either reset the part or trigger an interrupt when a stack viola- tion occurs. The value of the INT_RST bit of the STCON SFR (Address 0xBF[2]) determines the response of the part. When STCON[2] is set to 0x1 and the stack pointer exceeds the waterline, the part resets immediately, no matter what other routines are in progress. If an attempt is made to move the stack pointer below the default stack starting address when STCON[2] is high, a reset also occurs. If an interrupt response is selected, the watchdog interrupt service routine is entered, assuming that there is no higher level interrupt currently being serviced. Note that when STCON[1] (SBE) is enabled, an interrupt (or reset) is triggered if the stack boundary is violated, regardless of the status of the EA bit in the interrupt enable SFR (IE, Address 0xA8[7]). This is because the watchdog interrupt is automatically configured as a high priority interrupt and, therefore, is not disabled by clearing EA. When STCON[1] is low, the feature is completely disabled, and no pending interrupts are generated. There are two separate flags associated with the stack boundary protection, allowing the cause of the violation to be determined. When the waterline is exceeded, a flag is set in WTRLFG of the stack boundary SFR (STCON, Address 0xBF[0]), indicating that the reset/interrupt was initiated by the stack waterline monitor. This flag remains high until the stack pointer falls below the water- line and the user clears the flag in software. A waterline or watchdog reset alone does not clear the flag. To successfully clear the flag, the software clear must occur while the stack pointer is below the waterline. Note that the stack pointer should never be altered while in the interrupt service routine. Doing so causes the program to return to a different section of the program and, therefore, malfunction. An external reset also causes the waterline flag to reset. When an attempt is made to move the stack pointer below the stack starting address, a flag (SBFLG) is set in the stack pointer high SFR (SPH, Address 0xB7[6]), indicating that the reset/interrupt was initiated by the stack bottom monitor. Once again, a boundary or watchdog reset alone does not clear this flag, and the user must clear the flag in software to successfully acknowledge the event. Note that if SPH[5:3] and SPH[2:0] are altered simultaneously to reduce the default stack starting address, a stack violation condition occurs when the stack boundary condition is enabled, and SPH[6] (the stack bottom flag, SBFLG) is initiated. To avoid this condition, it is recommended that the default stack starting address remain at 0x100 or be increased to further up the XRAM.

to the estimated stack maximum and the interrupt enabled. maximum stack level is determined. Figure 82. Extended Stack Pointer Operation faces, interrupts, I/O ports, and power-down modes. assertion of an external input signal (see the Timers section). parameters, and another register for the transmit/receive buffer. interrupt, PSM (see the Interrupt System section). flash memory so that an external code space is unnecessary. allow access to external code and data spaces. (see the I/O Ports section). not bit addressable (see the Power Management section).

• Full RTC
• LCD driver
• Battery switchover/power management
• Temperature ADC
• Battery ADC
• SPI/I2C communication
• Flash memory controller
• Watchdog timer
• Secondary UART port

memory, code indirect addressing is used. addressing modes, as shown in Table 67. Table 67. 8052 Addressing Modes an arithmetic expression; the value is computed by the assembler. 0xFF is referring to a special function memory location. useful for indexing into data arrays stored in RAM. referring to internal RAM, not to an SFR. four bytes of storage in the program memory. supported on the ADE5166/ADE5169/ADE5566/ADE5569. access before moving to extended RAM.

of flash memory located at DPTR. resulting in a 4-MIPS peak performance. Note that, throughout this section, A represents the accumulator. Table 68. Instruction Set

ADE5166/ADE5169/ADE5566/ADE5569 Rev. B | Page 87 of 156 Mnemonic Description Bytes Cycles XRL A, dir Exclusive-OR indirect memory to A 2 2 XRL dir, #data Exclusive-OR immediate data to direct 3 3 CLR A Clear A 1 1 CPL A Complement A 1 1 SWAP A Swap nibbles of A 1 1 RL A Rotate A left 1 1 RLC A Rotate A left through carry 1 1 RR A Rotate A right 1 1 RRC A Rotate A right through carry 1 1 Data Transfer MOV A, Rn Move register to A 1 1 MOV A, @Ri Move indirect memory to A 1 2 MOV Rn, A Move A to register 1 1 MOV @Ri, A Move A to indirect memory 1 2 MOV A, dir Move direct byte to A 2 2 MOV A, #data Move immediate to A 2 2 MOV Rn, #data Move register to immediate 2 2 MOV dir, A Move A to direct byte 2 2 MOV Rn, dir Move register to direct byte 2 2 MOV dir, Rn Move direct to register 2 2 MOV @Ri, #data Move immediate to indirect memory 2 2 MOV dir, @Ri Move indirect to direct memory 2 2 MOV @Ri, dir Move direct to indirect memory 2 2 MOV dir, dir Move direct byte to direct byte 3 3 MOV dir, #data Move immediate to direct byte 3 3 MOV DPTR, #data Move immediate to data pointer 3 3 MOVC A, @A+DPTR Move code byte relative DPTR to A 1 4 MOVC A, @A+PC Move code byte relative PC to A 1 4 MOVX A, @Ri Move external (A8) data to A 1 4 MOVX A, @DPTR Move external (A16) data to A 1 4 MOVX @Ri, A Move A to external data (A8) 1 4 MOVX @DPTR, A Move A to external data (A16) 1 4 PUSH dir Push direct byte onto stack 2 2 POP dir Pop direct byte from stack 2 2 XCH A, Rn Exchange A and register 1 1 XCH A, @Ri Exchange A and indirect memory 1 2 XCHD A, @Ri Exchange A and indirect memory nibble 1 2 XCH A, dir Exchange A and direct byte 2 2 Boolean CLR C Clear carry 1 1 CLR bit Clear direct bit 2 2 SETB C Set carry 1 1 SETB bit Set direct bit 2 2 CPL C Complement carry 1 1 CPL bit Complement direct bit 2 2 ANL C, bit AND direct bit and carry 2 2 ANL C, /bit AND direct bit inverse to carry 2 2 ORL C, bit OR direct bit and carry 2 2 ORL C, /bit OR Direct bit inverse to carry 2 2 MOV C, bit Move direct bit to carry 2 2 MOV bit, C Move carry to direct bit 2 2

Some 8052 instructions read the latch and others read the pin. The state of the pin is read for instructions that input a port bit. that read a value, possibly change it, and rewrite it to the latch. rather than the pin returns the correct value of 1. read the latch rather than the pin. Table 69. Read-Modify-Write Instructions

1 These instructions read the port byte (all eight bits), modify the addressed

bit, and write the new byte back to the latch.

affect status flags are listed in this section. flags are referenced by the instruction. Table 70. ADD A (Source) Affected Status Flags to indicate an overflow if the operands are unsigned. AC Set if there is a carry out of Bit 3. Cleared otherwise. mulator. The carry status flag is referenced by the instruction. Table 71. ADDC A (Source) Affected Status Flags to indicate an overflow if the operands are unsigned. AC Set if there is a carry out of Bit 3. Cleared otherwise. Table 72. SUBB A (Source) Affected Status Flags AC Set if a borrow is needed for Bit 3. Cleared otherwise. register. No status flags are referenced by the instruction. Table 73. MUL AB Affected Status Flags OV Set if the result is greater than 255. Cleared otherwise. in the accumulator and the remainder goes into the B register. No status flags are referenced by the instruction. Table 74. DIV AB Affected Status Flags is added to the accumulator to correct the higher four bits. The carry and AC status flags are referenced by this instruction. Table 75. DA A Affected Status Flag C Set if the result is greater than 0x99. Cleared otherwise. The carry status flag is referenced by this instruction. Table 76. RRC A Affected Status Flag

The carry status flag is referenced by this instruction. Table 77. RLC A Affected Status Flag continues with the instruction after the CJNE instruction. No status flags are referenced by this instruction. Table 78. CJNE Destination (Source, Relative Jump) Affected

automatically postincrement and postdecrement the DPTR. postincrement and postdecrement. Table 79. Data Pointer Control SFR (DPCON, Address 0xA7) 7 0 Not implemented. Write don’t care. 6 DPT 0 Data pointer automatic toggle enable. Cleared by the user to disable autoswapping of the DPTR. Set in user software to enable automatic toggling of the DPTR after each MOVX or MOVC instruction. allowing more compact and more efficient code size and execution. 0 1 DPTR is postincremented after a MOVX or MOVC instruction. 1 0 DPTR is postdecremented after a MOVX or MOVC instruction. useful for moving 8-bit blocks to/from 16-bit devices. more compact and more efficient code size and execution. 0 1 DPTR is postincremented after a MOVX or MOVC instruction. 1 0 DPTR is postdecremented after a MOVX or MOVC instruction. for moving 8-bit blocks to/from 16-bit devices. 1 0 Not implemented. Write don’t care. pointer, meaning that the contents of a separate 16-bit register appear in the DPL SFR and DPH SFR.

Table 82. Interrupt Priority SFR (IP, Address 0xB8) 7 0xBF PADE ADE energy measurement interrupt priority (1 = high, 0 = low). 6 0xBE PTEMP Temperature ADC interrupt priority (1 = high, 0 = low). 5 0xBD PT2 Timer 2 interrupt priority (1 = high, 0 = low). 4 0xBC PS UART serial port interrupt priority (1 = high, 0 = low). 3 0xBB PT1 Timer 1 interrupt priority (1 = high, 0 = low). 2 0xBA PX1 INT1 (External Interrupt 1) priority (1 = high, 0 = low). 1 0xB9 PT0 Timer 0 interrupt priority (1 = high, 0 = low). 0 0xB8 PX0 INT0 (External Interrupt 0) priority (1 = high, 0 = low). Table 83. Interrupt Enable and Priority 2 SFR (IEIP2, Address 0xA9) 7 PS2 UART2 serial port interrupt priority (1 = high, 0 = low). 6 PTI RTC interrupt priority (1 = high, 0 = low). 5 ES2 Enables the UART2 serial port interrupt. Set by the user. 4 PSI SPI/I2C interrupt priority (1 = high, 0 = low). 3 EADE Enables the energy metering interrupt (ADE). Set by the user. 2 ETI Enables the RTC interval timer interrupt. Set by the user. 1 EPSM Enables the PSM power supply management interrupt. Set by the user. 0 ESI Enables the SPI/I2C interrupt. Set by the user. If two interrupts of the same priority level occur simultaneously, the polling sequence is observed as shown in Table 84. Table 84. Priority Within Interrupt Level IPSM 0 (highest) Power supply management interrupt. IRTC 1 RTC interval timer interrupt. IADE 2 ADE energy measurement interrupt. WDT 3 Watchdog timer overflow interrupt. ITEMP 4 Temperature ADC interrupt. TF0 6 Timer/Counter 0 interrupt. TF1 8 Timer/Counter 1 interrupt. ISPI/I2CI 9 SPI/I2C interrupt. RI/TI 10 UART serial port interrupt. TF2/EXF2 11 Timer/Counter 2 interrupt. RI2/TI2 12 (lowest) UART2 serial port interrupt.

Figure 89. Interrupt System Functional Block Diagram

Table 87. Interrupt Vector Addresses a RETI instruction or an access of the IP and IE SFRs. instruction cycles, 4 μs with a clock of 4.096 MHz.

determined amount of time (set by the PRE bits, Bits[7:4]). crystal connected between the XTAL1 and XTAL2 pins. write access to the WDCON SFR. Protecting the Flash Memory section). Table 88. Watchdog Timer SFR (WDCON, Address 0xC0) interrupt when the watchdog timeout period has expired. interrupt, depending on the WDIR bit.

Table 89. Watchdog and Flash Protection Byte in Flash (Flash Address = 0xF7FF) 7 WDPROT_PROTKY7 1 This bit holds the protection for the watchdog timer and the seventh bit of the flash protection key. timeout set using the PRE bits (Bits[7:4]) can still be modified by user code. Protecting the Flash Memory section for more information on how to clear this bit). values match, the new protection is written to the Flash Address 0x3FFF to Flash Address 0x3FFB. See the Protecting the Flash Memory section for more information on how to configure these bits. instruction must be a write instruction to the WDCON SFR. to the consecutive instruction cycles. is located in the watchdog timer SFR (WDCON, Address 0xC0). the watchdog to be used as a long interval timer. in the interrupt enable SFR (IE, Address 0xA8; see Table 81). kept active to watch over the program.

waveform voltage generation is also supported. memory for scrolling purposes. Table 90. LCD Driver SFRs 0x95 R/W LCDCON LCD configuration (see Table 91). 0x96 R/W LCDCLK LCD clock (see Table 95). 0x97 R/W LCDSEGE LCD segment enable (see Table 98). 0x9C R/W LCDCONX LCD Configuration X (see Table 92). 0xAC R/W LCDPTR LCD pointer (see Table 99). 0xAE R/W LCDDAT LCD data (see Table 100). 0xB1 R/W LCDCONY LCD Configuration Y (see Table 94). 0xED R/W LCDSEGE2 LCD Segment Enable 2 (see Table 101). Table 91. LCD Configuration SFR (LCDCON, Address 0x95) 7 LCDEN 0 LCD enable. If this bit is set, the LCD driver is enabled. 6 LCDRST 0 LCD data registers reset. If this bit is set, the LCD data registers are reset to 0. BLKMOD (Bits[7:6]) and BLKFREQ (Bits[5:4]) in the LCD clock SFR (LCDCLK, Address 0x96).

0 The LCD is disabled or enabled in PSM2 by LCDEN (Bit 7)

1 The LCD is disabled in PSM2 regardless of LCDEN setting

3 CLKSEL 0 LCD clock selection. [1:0] LMUX 01 LCD multiplex level.

00 Reserved

Table 92. LCD Configuration X SFR (LCDCONX, Address 0x9C) 6 EXTRES 0 External resistor ladder selection bit. [5:0] BIASLVL 0 Bias level selection bits (see Table 93). Table 93. LCD Bias Voltage When Contrast Control Is Enabled Table 94. LCD Configuration Y SFR (LCDCONY, Address 0xB1) AUTOSCREENSCROLL are set, this bit preempts the blinking mode. frame. If this bit is cleared, frames are not inverted. [5:4] Reserved 00 These bits should be kept cleared to 0 for proper operation. and 3 select Screen 0, Screen 1, Screen 2, and Screen 3, respectively. indicates that the LCD memory has been updated and a new frame has begun. LCD driver does not use the data in the LCD data registers to update the display. uses the data in the LCD data registers to update the display at the next frame. Table 95. LCD Clock SFR (LCDCLK, Address 0x96) [7:6] BLKMOD 00 Blink mode clock source configuration bits.

00 The blink rate is controlled by software; the display is off

01 The blink rate is controlled by software; the display is on

10 The blink rate is 2 Hz

11 The blink rate is set by the BLKFREQ bits

[5:4] BLKFREQ 00 Blink rate configuration bits. These bits control the LCD blink rate if BLKMOD (Bits[7:6]) = 11. [3:0] FD 0000 LCD frame rate selection bits (see Table 96 and Table 97).

Table 96. LCD Frame Rate Selection for fLCDCLK = 2048 Hz (LCDCON[3] = 0) 1 Not within the range of typical LCD frame rates. Table 97. LCD Frame Rate Selection for fLCDCLK = 128 Hz (LCDCON[3] = 1) 1 Not within the range of typical LCD frame rates. Table 98. LCD Segment Enable SFR (LCDSEGE, Address 0x97) 7 FP25EN 0 FP25 function select bit. 0 = general-purpose I/O, 1 = LCD function. 6 FP24EN 0 FP24 function select bit. 0 = general-purpose I/O, 1 = LCD function. 5 FP23EN 0 FP23 function select bit. 0 = general-purpose I/O, 1 = LCD function. 4 FP22EN 0 FP22 function select bit. 0 = general-purpose I/O, 1 = LCD function. 3 FP21EN 0 FP21 function select bit. 0 = general-purpose I/O, 1 = LCD function. 2 FP20EN 0 FP20 function select bit. 0 = general-purpose I/O, 1 = LCD function. [1:0] Reserved 0 These bits must be kept at 0 for proper operation.

Table 99. LCD Pointer SFR (LCDPTR, Address 0xAC) is written to the address indicated by the ADDRESS bits (LCDPTR[3:0]). [5:4] RAM2SCREEN 0 These bits select the screen recipient of the data memory action. [3:0] ADDRESS 0 LCD memory address (see Table 102). Table 100. LCD Data SFR (LCDDAT, Address 0xAE) [7:0] LCDDATA 0 Data to be written into or read out of the LCD memory SFRs. Table 101. LCD Segment Enable 2 SFR (LCDSEGE2, Address 0xED) 3 FP19EN 0 FP19 function select bit. 0 = general-purpose I/O, 1 = LCD function. 2 FP18EN 0 FP18 function select bit. 0 = general-purpose I/O, 1 = LCD function. 1 FP17EN 0 FP17 function select bit. 0 = general-purpose I/O, 1 = LCD function. 0 FP16EN 0 FP16 function select bit. 0 = general-purpose I/O, 1 = LCD function. the LCD module to drive the type of LCD in the user end system. should be set according to the LCD specifications. ality to COM2 and the FP27 pin functionality to COM3. addition, a faster refresh rate consumes more power. (LCDCLK, Address 0x96[3:0]).

2048 Hz, ranging from 8 Hz to 128 Hz for an LCD with 4×

128 Hz clock is beneficial for battery operation because it consumes

LCD. This way, each frame has an average dc offset of 0. ADC offset degrades the lifetime and performance of the LCD.

the LCD clock SFR (LCDCLK, Address 0x96); see Table 95. of the screens can then be achieved by a one-command instruction. scrolling between the screens using the five available blink rates. the LCD clock SFR (LCDCLK, Address 0x96); see Table 95. Automatic scrolling mode is available in all operating modes. Each byte configures the on and off states of two segment lines. and the MSBs store the state of the odd numbered segment lines. maintained in the PSM2 operating mode. a read or write operation (see Table 99). Table 102. LCD Data Memory Accessed Indirectly Through LCD Pointer SFR (LCDPTR, Address 0xAC) and LCD Data SFR 1 COMx designates the common lines. 2 FPx designates the segment lines.

ADE5166/ADE5169/ADE5566/ADE5569 Rev. B | Page 104 of 156 Writing to LCD Data Registers To update the LCD data memory, first set the LSB of the LCD Configuration Y SFR (LCDCONY , Address 0xB1) to freeze the data being displayed on the LCD while updating it. This operation ensures that the data displayed on the screen does not change while the data is being changed. Then, move the data to the LCD data SFR (LCDDAT, Address 0xAE) prior to accessing the LCD pointer SFR (LCDPTR, Address 0xAC). The address of the LCD screen should be consistent with the data changed. When the MSB of the LCD pointer SFR (LCDPTR, Address 0xAC) is set, the contents of the LCD data SFR (LCDDAT, Address 0xAE) are transferred to the internal LCD data memory designated by the address in the LCD pointer SFR (LCDPTR, Address 0xAC) and the screen designator. Clear the LSB of the LCD Configuration Y SFR (LCDCONY , Address 0xB1) when all of the data memory has been updated to allow the use of the new LCD setup for display. Sample 8052 code to update the segments attached to Pin FP10 and Pin FP11 on Screen 1 is as follows: ORL LCDCONY,#01h ;start updating the data MOV LCDDAT,#FFh MOV LCDPTR,#80h OR 05h ANL LCDCONY,#0FEh ;update finished Reading LCD Data Registers When the MSB of the LCD pointer SFR (LCDPTR, Address 0xAC) is cleared, the contents of the LCD data memory of the correspond- ing screen designated by LCDPTR are transferred to the LCD data SFR (LCDDAT, Address 0xAE). Sample 8052 code to read the contents of LCD Data Memory Address 0x07 on Screen 1, which holds the on and off state of the segments attached to FP14 and FP15, is as follows: MOV LCDPTR,#07h MOV R1, LCDDAT VOLTAGE GENERATION The ADE5166/ADE5169/ADE5566/ADE5569 provide two ways to generate the LCD waveform voltage levels. The on-chip charge pump option can generate 5 V . This makes it possible to use 5 V LCDs with the 3.3 V ADE5166/ADE5169/ADE5566/ADE5569. There is also an option to use an external resistor ladder with a 3.3 V LCD. The EXTRES bit (Bit 6) in the LCD Configuration X SFR (LCDCONX, Address 0x9C) selects the resistor ladder or charge pump option. When selecting how to generate the LCD waveform voltages, the following should be considered: Lifetime performance power consumption

• Contrast control Lifetime Performance Power Consumption In most LCDs, a high amount of current is required when the LCD waveforms change state. The external resistor ladder option draws a constant amount of current, whereas the charge pump circuitry allows dynamic current consumption. If the LCD module is used with the internal charge pump option when the display is disabled, the voltage generation is disabled so that no power is consumed by the LCD function. This feature results in significant power savings if the display is turned off during battery operation. Contrast Control The electrical characteristics of the liquid in the LCD change over temperature. This requires adjustments in the LCD waveform voltages to ensure a readable display. An added benefit of the internal charge pump voltage generation is a configurable bias voltage that can be compensated over temperature and supply to maintain contrast on the LCD. These compensations can be performed based on the ADE5166/ADE5169/ADE5566/ ADE5569 temperature and supply voltage measurements (see the Temperature, Battery, and Supply Voltage Measurements section). This dynamic contrast control is not easily imple- mented with external resistor ladder voltage generation. The LCD bias voltage sets the contrast of the display when the charge pump provides the LCD waveform voltages. The ADE5166/ ADE5169/ADE5566/ADE5569 provide 64 bias levels selected by the BIASLVL bits (Bits[5:0]) in the LCD Configuration X SFR (LCDCONX, Address 0x9C). The voltage level on LCDV A, LCDVB, and LCDVC depends on the internal voltage reference value (V REF), BIASLVL selection, and the biasing selected, as described in Table 93. Lifetime Performance DC offset on a segment degrades its performance over time. The voltages generated through the internal charge pump switch faster than those generated by the external resistor ladder, reducing the likelihood of a dc voltage being applied to a segment and increasing the lifetime of the LCD. LCD EXTERNAL CIRCUITRY The voltage generation selection is made by the EXTRES bit (Bit 6) in the LCD Configuration X SFR (LCDCONX, Address 0x9C). This bit is cleared by default for charge pump voltage generation, but it can be set to enable an external resistor ladder.

update a byte of data memory. The flash memory can be protected from read or write/erase access. that do not require modification during emulation or debug. flash memory protection and are, therefore, unavailable to the user. byte address SFR (EADRL, Address 0xC6). Table 104. Flash SFRs demonstrates the steps required for access to the flash memory. Figure 94. Flash Memory Read/Write/Erase Protection Block Diagram

Figure 95. Flash Memory Organization

Address 0xBA) to initiate any user access to the flash memory. data being overwritten by a runaway program. throughout the flash memory access. Table 105. Flash Control SFR (ECON, Address 0xB9) being addressed must be pre-erased. EADRL to select it for erasure. during serial mode and parallel download mode but should not be executed by user code. 4 Read byte. The byte in the flash memory, addressed by EADRH and EADRL, is read into EDATA. 8 Protect code (see the Protecting the Flash Memory section). Table 106. Flash Key SFR (FLSHKY, Address 0xBA) operation is allowed (see the Protecting the Flash Memory section). Table 107. Flash Protection Key SFR (PROTKY, Address 0xBB) If the protection key in the flash is 0xFF, the PROTKY SFR value is not used for comparison. value in PROTKY and writing 0x08 in the ECON SFR. This operation can be done only once. Table 108. Flash Data SFR (EDATA, Address 0xBC) [7:0] EDATA 0 Flash pointer data. Table 109. Flash Low Byte Address SFR (EADRL, Address 0xC6) [7:0] EADRL 0 Flash pointer low byte address. Table 110. Flash High Byte Address SFR (EADRH, Address 0xC7) [7:0] EADRH 0 Flash pointer high byte address.

ADE5166/ADE5169/ADE5566/ADE5569 Rev. B | Page 110 of 156 Flash Functions The following sample 8052 code is provided to demonstrate how to use the the flash functions. For these examples, Flash Memory Byte 0x3C00 is accessed. Write By te Write 0xF3 into Flash Memory Byte 0x3C00. MOV EDATA, #F3h ; Data to be written MOV EADRH, #3Ch ; Set up byte address MOV EADRL, #00h MOV FLSHKY, #3Bh ; Write flash security key. MOV ECON, #01H ; Write byte Erase Page Erase the page containing Flash Memory Byte 0x3C00. MOV EADRH, #3Ch ; Select page through byte address MOV EADRL, #00h MOV FLSHKY, #3Bh ; Write flash security key. MOV ECON, #02H ; Erase Page Erase All Erase all of the 62 kB flash memory. MOV FLSHKY, #3Bh ; Write flash security key. MOV ECON, #03H ; Erase all Read Byte Read Flash Memory Byte 0x3C00. MOV EADRH, #3Ch ; Set up byte address MOV EADRL, #00h MOV FLSHKY, #3Bh ; Write flash security key. MOV ECON, #04H ; Read byte ; Data is ready in EDATA register Note that the read byte command can be used to view the status of the protection bytes located in the upper 21 bytes, Page 123. The write byte command is not valid for this area. PROTECTING THE FLASH MEMORY Two forms of protection are offered for this flash memory: read protection and write/erase protection. The read protection ensures that any pages that are read protected cannot be read by the end user. The write protection ensures that the flash memory cannot be erased or written over. This protects the final product from tampering and can prevent the code from being overwritten in the event of a runaway program. Write/erase protection is individually selectable for all 124 pages. Read protection is selected in groups of four pages (see Figure 95 for the groupings). The protection bits are stored in the last flash memory locations, Address 0xF7EB through Address 0xF7FF (see Figure 96). Sixteen bytes are reserved for write/erase pro- tection, four bytes for read protection, and another byte to set the flash protection key (PROTKY , Address 0xBB). The user must enable write/erase protection for the last page, at a minimum, for the entire protection scheme to work. Note that the read protection does not prevent MOVC commands from being executed within the code. There is an additional layer of protection offered by a flash pro- tection security key (PROTKY) that can be set up by the user so that the protection scheme cannot be changed without this key. After the protection key has been configured, it cannot be modified. Enabling Flash Protection by Code The protection bytes in the flash can be programmed by using the flash controller command and programming the ECON SFR to 0x08. Issuing the ECON protection command initiates the programming of one byte of protection data. The EADRL (Address 0xC6) and EDATA (Address 0xBC) data pointer SFRs are used to store the least significant address and data bytes, respectively. Note that the EADRH data pointer SFR is not used in this command. The following sequence should be followed to enable the flash protection: Set the EDATA flash data pointer with the write/erase or read protection data. When erased, the protection bits default to 1, like any other bit of flash memory. The default protection setting is for no protection. To enable protection, write a 0 to the bits corresponding to the pages that should be pro- tected. Note that when setting the read protection, each protection bit protects four pages. Set the EADRL flash data pointer with the least significant byte of the protection address. For example, to access the protection on Page 112 through Page 119 (Address 0xF7FE), EADRL should be written to 0xFE. Enable access to the flash by writing 0x3B to the FLSHKY SFR (Address 0xBA). Issue the protection command by writing 0x08 to the ECON SFR (Address 0xB9). Step 1 to Step 3 should be repeated for each byte that requires protection. While configuring the final byte of write/read pro- tection, the PROTKY SFR (Address 0xBB) can be enabled for a further level of code security. If enabled, the flash protection key is required to modify the protection scheme. To enable the flash protection key, the Flash Location 0xF7EB where the PROTKY is located should be written to using the flash control SFR (ECON, Address 0xB9). The PROTKY can be written to any 8-bit value; once configured, it cannot be modified. To enable the PROTKY and activate the flash protection, the part must be reset.

each time that the protection scheme is changed. prior to issuing the ECON protection command. Figure 96. Flash Protection in Page 124

available at www.analog.com. Command with ASCII Code I or 0x49 writes the data into R0.

• Command with ASCII Code F or 0x46 writes R0 into the SFR address defined in the data of this command. Omitting the protocol defined in the uC004 Application Note, the sequence to load protections is similar to the sequence men- tioned in the Enabling Flash Protection by Code section, except that two emulator commands are necessary to replace one assembly command. For example, to write the protection value in the EADRH SFR (Address 0xC7), the following two commands must be executed: Command I with data = value of Protection Byte 0x3FFF
• Command F with data = 0xC7 With this protocol, the protection can be written to the flash memory using the same sequence described in the Enabling Flash Protection by Code section. When the part is reset, the protection is effective. Notes on Flash Protection The flash protection scheme is disabled by default so that none of the pages of the flash are protected from reading or writing/ erasing. The last page must be write-/erase-protected for the protection scheme to work. To activate the protection settings, the ADE5166/ADE5169/ ADE5566/ADE5569 must be reset after configuring the pro- tection. After configuring protection on the last page and resetting the part, protections that have been enabled can be removed only by mass erasing the flash memory. The protection bits are never truly write protected. Protection bits can be program modified from a 1 to a 0, even after the last page has been protected. In this way, more protection can be added, but none can be removed. When the last page is read protected, the protection bits can still be read by the user code. All other bits on this page are not available for reading. The protection scheme is intended to protect the end system. Pro- tection should be disabled while developing and emulating code. Flash Memory Timing Typical program and erase times for the flash memory are shown in Table 111.

Table 111. Flash Memory Program and Erase Times in serial download mode. Read protected pages cannot be read. figuration bits cannot be programmed in serial download mode.

timers can be configured to operate as timers or as event counters. transition, the maximum count rate is half the core clock frequency. operating modes is achieved via the SFRs listed in Table 112. Table 112. Timer SFRs TCON 0x88 Yes Timer/Counter 0 and Timer/Counter 1 control (see Table 114). TMOD 0x89 No Timer/Counter 0 and Timer/Counter 1 mode (see Table 113). TL0 0x8A No Timer 0 low byte (see Table 117). TL1 0x8B No Timer 1 low byte (see Table 119). TH0 0x8C No Timer 0 high byte (see Table 116). TH1 0x8D No Timer 1 high byte (see Table 118). T2CON 0xC8 Yes Timer/Counter 2 control (see Table 115). RCAP2L 0xCA No Timer 2 reload/capture low byte (see Table 123). RCAP2H 0xCB No Timer 2 reload/capture high byte (see Table 122). TL2 0xCC No Timer 2 low byte (see Table 121). TH2 0xCD No Timer 2 high byte (see Table 120). Table 113. Timer/Counter 0 and Timer/Counter 1 Mode SFR (TMOD, Address 0x89) control bit (Address 0x88[6]) is set. Cleared by software to enable Timer 1 whenever the TR1 control bit is set. 6 C/T1 0 Timer 1 timer or counter select bit. Set by software to select counter operation (input from the T1 pin). Cleared by software to select the timer operation (input from the internal system clock). 00 Timer 1 mode select bits. 01 16-bit timer/counter. TH1 and TL1 are cascaded; there is no prescaler. 10 8-bit autoreload timer/counter. TH1 holds a value to reload into TL1 each time TL1 overflows. control bit (Address 0x88[4]) is set. Cleared by software to enable Timer 0 whenever the TR0 control bit is set. 2 C/T0 0 Timer 0 timer or counter select bit. Set by software to the select counter operation (input from the T0 pin). Cleared by software to select the timer operation (input from the internal system clock). 00 Timer 0 mode select bits. 01 16-bit timer/counter. TH0 and TL0 are cascaded; there is no prescaler. 10 8-bit autoreload timer/counter. TH0 holds a value to reload into TL0 each time TL0 overflows. 8-bit timer only, controlled by the Timer 1 control bits.

Table 114. Timer/Counter 0 and Timer/Counter 1 Control SFR (TCON, Address 0x88) when the program counter (PC) vectors to the interrupt service routine. when the PC vectors to the interrupt service routine. a 1-to-0 transition. Cleared by software to specify level sensitive detection, that is, zero level. a 1-to-0 transition. Cleared by software to specify level sensitive detection, that is, zero level. 1 These bits are not used to control Timer/Counter 0 and Timer/Counter 1 but are, instead, used to control and monitor the external INT0 and INT1 interrupt pins. Table 115. Timer/Counter 2 Control SFR (T2CON, Address 0xC8) RCLK = 1 or TCLK = 1. Cleared by user software. transition on the T2EX pin and EXEN2 = 1. Cleared by user software. Timer 1 overflow to be used for the receive clock. Timer 1 overflow to be used for the transmit clock. by the user for Timer 2 to ignore events at T2EX. 2 0xCA TR2 0 Timer 2 start/stop control bit. Set by the user to start Timer 2. Cleared by the user to stop Timer 2. ignored and the timer is forced to autoreload on Timer 2 overflow.

Figure 99. Overflow from TL0 not only sets TF0 (Address 0x88[5]) software. The reload leaves TH0 unchanged. Figure 99. Timer/Counter 0, Mode 2 separate counters. This configuration is shown in Figure 100. an extra 8-bit timer or counter. Figure 100. Timer/Counter 0, Mode 3 reload registers (see Table 120 to Table 123). Table 124. T2CON Operating Modes

1 X 1 Baud rate

mode is shown in Figure 101. that, upon overflowing, sets the Timer 2 overflow bit (TF2, Bit 7). generator mode is selected by RCLK = 1 and/or TCLK = 1.

5 MHz (or 819.2 kHz) across all CD settings. to the POWCON SFR, a key is required to modify the register. key, 0xA7, and then a new value is written to the POWCON SFR. Table 125. Power Control SFR (POWCON, Address 0xC5) metering functions are not needed in PSM0. 5 Reserved 0 This bit should be kept at 0 for proper operation. 4 COREOFF 0 Set this bit to 1 to shut down the core if in the PSM1 operating mode. [2:0] CD 010 Controls the core clock frequency (fCORE). fCORE = 4.096 MHz/2CD. Table 126. Key SFR (KYREG, Address 0xC1) [7:0] KYREG 0 Write 0xA7 to the KYREG SFR before writing to the POWCON SFR to unlock it. registers to unlock them (see the RTC Registers section).

ADE5166/ADE5169/ADE5566/ADE5569 Rev. B | Page 119 of 156 REAL-TIME CLOCK (RTC) The ADE5166/ADE5169/ADE5566/ADE5569 have an embedded RTC (see Figure 103). The external 32.768 kHz crystal is used as the clock source for the RTC. Calibration is provided to com- pensate the nominal crystal frequency and for variations in the external crystal frequency over temperature. By default, the RTC is active in all the power saving modes. The RTC counters retain their values through watchdog resets and external resets and are reset only during a power-on reset. The ADE5166/ADE5169/ADE5566/ADE5569 provide two ways to access the RTC data: by direct access through SFRs for configu- ration and by indirect access through address and data SFRs for the timekeeping registers and some other configurations. The address and data SFRs act as pointers to the RTC internal registers. ACCESS TO RTC SFRs Access to the RTC SFRs is achieved by reading or writing to the SFR addresses that are detailed in the Access to Internal RTC Registers section. Writing to the indirect registers is protected by a key, as explained in the Writing to Internal RTC Registers section. Reading is not protected. ACCESS TO INTERNAL RTC REGISTERS Access to the internal RTC measurement registers is achieved by writing to the RTC pointer address SFR (RTCPTR, Address 0xA3). The RTCPTR register selects the RTC register to be accessed and determines if a read or a write is performed (see Table 130). Writing to Internal RTC Registers The RTC circuitry runs off a 32.768 kHz clock. The timekeeping registers, HTHSEC, SEC, MIN, HOUR, DAY , DATE, MONTH, and YEAR are updated with a 32.768 kHz clock. However, the TIMECON (Address 0xA1) and TIMECON2 (Address 0xA2) SFRs and the INTV AL register (Address 0x09) are updated with a 128 Hz clock. It takes up to two 128 Hz clock cycles from when the MCU writes to the TIMECON or TIMECON2 SFR, or the INTV AL register until it is successfully updated in the RTC. When the RTCW_RB bit in the RTCPTR SFR (Address 0xA3[7]) is set, the contents of the RTCDAT SFR (Address 0xA4) are transferred to the internal RTC register designated by the address in the RTCPTR SFR. To protect the RTC timekeeping registers from runaway code, a key must be written to the KYREG SFR (Address 0xC1) to obtain write access to any of the RTC indirect registers. The KYREG SFR should be set to 0xEA to unlock the timekeeping registers and is reset to 0 after a timekeeping register is written. The RTC registers can be written using the following 8052 assembly code: MOV RTCKey, #0EAh CALL UpdateRTC UpdateRTC: MOV KYREG, RTCKey MOV RTCDAT, #30 MOV RTCPTR, #82h MOV KYREG, RTCKey MOV RTCDAT, #05 MOV RTCPTR, #83h MOV KYREG, RTCKey MOV RTCDAT, #04 MOV RTCPTR, #84h MOV RTCKey, #00h RET Reading Internal RTC Registers When Bit 7 of the RTCPTR SFR is cleared, the contents of the internal RTC data register designated by the address in RTCPTR are transferred to the RTCDAT SFR. The RTC cannot be stopped to read the current time because stopping the RTC introduces an error in its timekeeping. Therefore, the RTC is read on-the-fly, and the counter registers must be checked for overflow. This can be accomplished using the following 8052 assembly code: ReadAgain: MOV RTCPTR #01 ; Read HTHSEC using Bank MOV R0, RTCDAT MOV RTCPTR, #02 ; Read SEC MOV R1, RTCDAT MOV RTCPTR, #03 ; Read MIN MOV R2, RTCDAT MOV RTCPTR, #04 ; Read HOUR MOV R3, RTCDAT MOV RTCPTR, #01 ; Read HTHSEC MOV A, RTCDAT CJNE A, 00h, ReadAgain ; 00h is R0 in Bank 0

Figure 103. RTC Implementation Table 127. List of RTC SFRs TIMECON 0xA1 No RTC configuration (see Table 128). TIMECON2 0xA2 No RTC Configuration 2 (see Table 129). RTCPTR 0xA3 No RTC pointer address (see Table 130). RTCDAT 0xA4 No RTC pointer data (see Table 131). KYREG 0xC1 No Key (see Table 126). RTCCOMP 0xF6 No RTC nominal compensation (see Table 132). TEMPCAL 0xF7 No RTC temperature compensation (see Table 133). This is a read only register.

Table 128. RTC Configuration SFR (TIMECON, Address 0xA1) the user to indicate that the alarm has been serviced. [5:4] ITS1, ITS0 0 INTVAL timebase select bits.

01 Second

10 Minute

11 Hour

3 SIT 0 Interval timer one-time alarm.

0 The ITFLAG flag is set after INTVAL counts, and then another interval count starts

1 The ITFLAG flag is set after one time interval

user to indicate that the alarm event has been serviced. 1 ITEN 0 Interval timer enable.

0 The interval timer is disabled, and the 8-bit interval timer counter is reset

1 Set this bit to 1 to enable the interval timer

Table 129. RTC Configuration 2 SFR (TIMECON2, Address 0xA2) [7:5] Reserved N/A Reserved. alarms also match, the ALFLAG in the TIMECON SFR (Address 0xA1[6]) is set. If enabled, an RTC interrupt occurs. also match, the ALFLAG in the TIMECON SFR (Address 0xA1[6]) is set. If enabled, an RTC interrupt occurs. alarms also match, the ALFLAG in the TIMECON SFR (Address 0xA1[6]) is set. If enabled, an RTC interrupt occurs. match, the ALFLAG in the TIMECON SFR (Address 0xA1[6]) is set. If enabled, an RTC interrupt occurs. also match, the ALFLAG in the TIMECON SFR (Address 0xA1[6]) is set. If enabled, an RTC interrupt occurs.

Table 130. RTC Pointer Address SFR (RTCPTR, Address 0xA3) 7 RTCW_RB 0 Read/write selection.

0 The RTC register at RTC_ADDRESS (Bits[4:0]) is read into the RTCDAT SFR

1 The data in the RTCDAT SFR is written in the RTC register at RTC_ADDRESS

is set to 0xEA, the instruction before writing to the RTCDAT SFR. [6:5] Reserved N/A Reserved. [4:0] RTC_ADDRESS 0 Target address for read/write operation. Table 131. RTC Pointer Data SFR (RTCDAT, Address 0xA4) [7:0] RTC_DATA 0 Location of data for read/write RTC operation. Table 132. RTC Nominal Compensation SFR (RTCCOMP, Address 0xF6) watchdog reset, an external reset, or a power-on reset (POR). Table 133. RTC Temperature Compensation SFR (TEMPCAL, Address 0xF7)

Table 134. RTC Register List 0x00 Reserved N/A N/A N/A N/A Reserved. incrementing the seconds counter, SEC. clock. It overflows from 6 to 0. incrementing the month counter, MONTH. ITS bits of the RTC configuration SFR (TIMECON, Address 0xA1[5:4]). 0x0F RTC_CAL R/W 8 U 0 Configuration of the RTC calibration output (see Table 135).

Table 135. RTC Calibration Configuration Register (RTC_CAL, Address 0x0F) mode. The RTC output is disabled on all other pins in PSM2 mode. 6 CAL_EN 0 RTC calibration enable output.

0 The RTC calibration output signal is disabled

1 The RTC calibration output signal is enabled and present on the pins selected by

the RTC_P2P3, RTC_P1P2, RTC_P0P7, and RTC_P0P5 bits (Bits[3:0]). [5:4] FSEL[1:0] 00 RTC calibration output frequency selection. 3 RTC_P2P3 0 When this bit is set and the CAL_EN bit is set, the RTC output is present on the P2.3/SDEN/TxD2 pin. 2 RTC_P1P2 0 When this bit is set and the CAL_EN bit is set, the RTC output is present on the P1.2/FP25/ZX pin. 1 RTC_P0P7 0 When this bit is set and the CAL_EN bit is set, the RTC output is present on the P0.7/SS/T1/RxD2 pin. 0 RTC_P0P5 0 When this bit is set and the CAL_EN bit is set, the RTC output is present on the P0.5/MISO/ZX pin. parameters shown in Table 136. Table 136. Month Rollover

Table 137. Leap Years—Rollover After 29 Days by the user to keep track of the RTC events. bit is set, the 8-bit counter is held in reset after the alarm occurs. Disable the interval timer by clearing ITEN (TIMECON[1]). RTC, 64,000 cycles at a 4.096 MHz instruction cycle clock.

1. Read the TIMECON SFR to ensure that the ITEN bit is

cleared. If it is not, wait for another 128 Hz clock cycle. and the program vectors to the RTC interrupt address.

Table 138. RTC Calibration Options by adding or subtracting pulses from the crystal clock signal. (RTCCOMP , Address 0xF6) is ±2 ppm/LSB, or 0.17 sec/day/LSB. of these two registers is limited to ±248 ppm, or 42.85 sec/day. calibration window to determine the error in the pulse output. pulses on the RTC calibration pin is sufficient. precisely 32.768 kHz at 25°C. the CAL_EN bit (RTC_CAL[6]). 1 sec/day error is equal to 11.57 ppm.

configured in one of four modes.

• Shift register with baud rate fixed at fCORE/12
• 8-bit UART with variable baud rate
• 9-bit UART with baud rate fixed at fCORE/64 or fCORE/32
• 9-bit UART with variable baud rate Variable baud rates are defined by using an internal timer to generate any rate between 300 bauds/sec and 115,200 bauds/sec. The UART serial interface provided in the ADE5166/ADE5169/ ADE5566/ADE5569 is a full-duplex serial interface. It is also receive buffered by storing the first received byte in a receive buffer until the reception of the second byte is complete. The physical interface to the UART is provided via the RxD (P1.0/RxD) and TxD (P1.1/TxD) pins, and the firmware interface is through the SFRs, as presented in Table 139. Both the serial port receive and transmit registers are accessed through the serial port buffer SFR (SBUF, Address 0x99). Writing to SBUF loads the transmit register, and reading SBUF accesses a physically separate receive register. An enhanced UART mode is offered by using the UART timer and by providing enhanced frame error, break error, and overwrite error detection. This mode is enabled by setting the EXTEN bit in the configuration SFR (CFG, Address 0xAF[6]) (see the UART Additional Features section). The enhanced serial baud rate control SFR (SBAUDT, Address 0x9E) and UART timer fractional divider SFR (SBAUDF, Address 0x9D) are used to configure the UART timer and to indicate the enhanced UART errors. UART SFRs

Table 139. Serial Port SFRs SCON 0x98 Yes Serial communications control (see Table 140). SBUF 0x99 No Serial port buffer (see Table 141). SBAUDT 0x9E No Enhanced serial baud rate control (see Table 142). SBAUDF 0x9D No UART timer fractional divider (see Table 143). Table 140. Serial Communications Control SFR (SCON, Address 0x98) [7:6] 0x9F , 0x9E SM0, SM1 00 UART serial mode select bits. These bits select the serial port operating mode.

00 Mode 0, shift register, fixed baud rate (fCORE/12)

01 Mode 1, 8-bit UART, variable baud rate

10 Mode 2, 9-bit UART, fixed baud rate (fCORE/32) or (fCORE/16)

11 Mode 3, 9-bit UART, variable baud rate

Mode 2 and Mode 3, and framing error detection in Mode 1. In Mode 0, SM2 should be cleared. In Mode 1, if SM2 is set, RI is not activated if a valid stop bit was not received. If SM2 is cleared, RI is set as soon as the byte of data is received. In Mode 2 or Mode 3, if SM2 is set, RI is not activated if the received ninth data bit in RB8 is 0. If SM2 is cleared, RI is set as soon as the byte of data is received. 4 0x9C REN 0 Serial port receive enable bit. Set by user software to enable serial port reception. Cleared by user software to disable serial port reception. into RB8. For Mode 1, the stop bit is latched into RB8. at the beginning of the stop bit in Mode 1, Mode 2, and Mode 3. TI must be cleared by user software. halfway through the stop bit in Mode 1, Mode 2, and Mode 3. RI must be cleared by user software.

Table 141. Serial Port Buffer SFR (SBUF, Address 0x99) [7:0] SBUF 0 Serial port data buffer. Table 142. Enhanced Serial Baud Rate Control SFR (SBAUDT, Address 0x9E) prior SBUF data to be lost. Write a 0 to this bit to clear it. only and is updated every time a frame is received. bit is updated every time a frame is received. [4:3] SBTH 00 Extended divider ratio for baud rate setting, as shown in Table 144. [2:0] DIV 000 Binary divider (see Table 144).

000 Divide by 1

001 Divide by 2

010 Divide by 4

011 Divide by 8

100 Divide by 16

101 Divide by 32

110 Divide by 64

111 Divide by 128

Table 143. UART Timer Fractional Divider SFR (SBAUDF, Address 0x9D) 7 UARTBAUDEN 0 UART baud rate enable. Set to enable UART timer to generate the baud rate. RCLK bit (T2CON, Address 0xC8[5]) are ignored. Cleared to let the baud rate be generated as per a standard 8052. 6 Not implemented Not implemented, write don’t care. [5:0] SBAUDF 0 UART timer fractional divider.

Table 144. Common Baud Rates Using the UART Timer with a 4.096 MHz PLL Clock

ADE5166/ADE5169/ADE5566/ADE5569 Rev. B | Page 131 of 156 To transmit, the eight data bits must be written into the serial port buffer SFR (SBUF, Address 0x99). The ninth bit must be written to TB8 in the serial communications control SFR (SCON, Address 0x98[3]). When transmission is initiated, the eight data bits from SBUF are loaded into the transmit shift register (LSB first). The ninth data bit, held in TB8, is loaded into the ninth bit position of the transmit shift register. The transmission starts at the next valid baud rate clock. The serial port transmit interrupt flag (TI, SCON[1]) is set as soon as the transmission completes, when the stop bit appears on TxD. All of the following conditions must be met at the time the final shift pulse is generated to receive a character: If the extended UART is disabled (EXTEN = 0 in the CFG SFR, Address 0xAF[6]), RI (SCON[0]) must be 0 to receive a character. This ensures that the data in SBUF is not over- written if the last received character has not been read. If multiprocessor communication is enabled by setting SM2 (SCON[5]), the received ninth bit must be set to receive a character. This ensures that only frames with the ninth bit set, which are frames that contain addresses, generate a receive interrupt. If any of these conditions is not met, the received frame is irre- trievably lost, and the receive interrupt flag (RI in the SCON SFR) is not set. Reception for Mode 2 is similar to that of Mode 1. The eight data bytes are input at RxD (LSB first) and loaded onto the receive shift register. If the received frame meets the previous criteria, the following events occur: The eight bits in the receive shift register are latched into the SBUF SFR.

• The ninth data bit is latched into RB8 in the SCON SFR.
• The receiver interrupt flag (RI in the SCON SFR) is set. Mode 3 (9-Bit UART with Variable Baud Rate) Mode 3 is selected by setting both SM0 and SM1 in the SCON SFR. In this mode, the 8052 UART serial port operates in 9-bit mode with a variable baud rate. The baud rate is set by a timer overflow rate. Timer 1 or Timer 2 can be used to generate baud rates, or both timers can be used simultaneously where one generates the transmit rate and the other generates the receive rate. There is also a dedicated timer for baud rate generation, the UART timer, which has a fractional divisor to precisely generate any baud rate (see the UART Timer Generated Baud Rates section). The operation of the 9-bit UART is the same as for Mode 2, but the baud rate can be varied. In all four modes, transmission is initiated by any instruction that uses SBUF as a destination register. Reception is initiated in Mode 0 when RI = 0 and REN = 1 in the SCON SFR. Reception is initiated in the other modes by the incoming start bit if REN = 1. UART BAUD RATE GENERATION Mode 0 Baud Rate Generation The baud rate in Mode 0 is fixed. Mode 0 Baud Rate = ⎟ COREf Mode 2 Baud Rate Generation The baud rate in Mode 2 depends on the value of the SMOD bit in the program control SFR (PCON, Address 0x87[7]). If SMOD = 0, the baud rate is 1/32 of the core clock. If SMOD = 1, the baud rate is 1/16 of the core clock. Mode 2 Baud Rate = 32 2SMOD × fCORE Mode 1 and Mode 3 Baud Rate Generation The baud rates in Mode 1 and Mode 3 are determined by the overflow rate of the timer generating the baud rate, that is, Timer 1, Timer 2, or the dedicated baud rate generator, the UART timer, which has an integer and a fractional divisor. Timer 1 Generated Baud Rates When Timer 1 is used as the baud rate generator, the baud rates in Mode 1 and Mode 3 are determined by the Timer 1 overflow rate. The value of SMOD (PCON[7]) is as follows: Mode 1 or Mode 3 Baud Rate = ×32 2SMOD Timer 1 Overflow Rate The Timer 1 interrupt should be disabled in this application. The timer itself can be configured for either timer or counter operation and in any of its three running modes. In the most typical application, it is configured for timer operation in auto- reload mode (high nibble of TMOD = 0010 binary, see Table 113). In that case, the baud rate is given by the following formula: Mode 1 or Mode 3 Baud Rate = ) 256 ( 32 TH1 fCORE SMOD Timer 2 Generated Baud Rates Baud rates can also be generated by using Timer 2. Using Timer 2 is similar to using Timer 1 in that the timer must overflow 16 times before a bit is transmitted or received. Because Timer 2 has a 16-bit autoreload mode, a wider range of baud rates is possible. Mode 1 or Mode 3 Baud Rate = 16 1 × Timer 2 Overflow Rate Therefore, when Timer 2 is used to generate baud rates, the timer increments every two clock cycles rather than every core machine cycle, as before. It increments six times faster than Timer 1, and, therefore, baud rates six times faster are possible.

or 9-bit UART with variable baud rate. generate any rate between 300 bauds/sec and 115,200 bauds/sec. physically separate receive register. Table 145. Serial Port 2 SFRs SCON2 0xE1 No Serial Communications Control 2 (see Table 146). SBUF2 0xEB No Serial Port 2 buffer (see Table 147). SBAUD2 0xEE No Enhanced Serial Baud Rate Control 2 (see Table 148). Table 146. Serial Communications Control 2 SFR (SCON2, Address 0xE1) 6 EN-T8 0 9-bit UART, variable baud rate enable bit. When set, the UART2 is in 9-bit mode. data to be lost. Write a 0 to this bit to clear it. only and is updated every time a frame is received. bit. This bit is updated every time a frame is received. user software to disable serial port reception. Table 147. Serial Port 2 Buffer SFR (SBUF2, Address 0xEB) [7:0] SBUF2 0 Serial Port 2 data buffer. Table 148. Enhanced Serial Baud Rate Control 2 SFR (SBAUD2, Address 0xEE) 7 TB8_2 0 Serial port transmit (Bit 9). The data loaded into TB8_2 is the ninth data bit transmitted in 9-bit mode. 8-bit mode, the stop bit is latched into RB8_2. 5 SBF2 Fractional divider Boolean. When set, SBAUDF2 = 0x2B. When cleared, SBAUDF2 = 0x07. [4:3] SBTH2 0 Extended divider ratio for baud rate setting (see Table 149).

[2:0] DIV2 000 Binary divider.

000 Divide by 1 (see Table 149)

001 Divide by 2 (see Table 149)

010 Divide by 4 (see Table 149)

011 Divide by 8 (see Table 149)

100 Divide by 16 (see Table 149)

101 Divide by 32 (see Table 149)

110 Divide by 164 (see Table 149)

111 Divide by 128 (see Table 149)

Table 149. Common Baud Rates Using the UART2 Timer with a 4.096 MHz PLL Clock

TxD2 pin or received on the RxD2 pin. matically set, as shown in Figure 110. Figure 110. 8-Bit Variable Baud Rate

• If the extended UART is disabled (EXTEN = 0, CFG[6]), RI2 (SCON2[0]) must be 0 to receive a character. This ensures that the data in the SBUF2 SFR is not overwritten if the last received character has not been read. If frame error checking is enabled by setting FE2 (SCON2[4]), the received stop bit must be set to receive a character. This ensures that every character received comes from a valid frame, with both a start bit and a stop bit. If any of these conditions is not met, the received frame is irre- trievably lost, and the Serial Port 2 receive interrupt flag, RI2 (SCON2[0]), is not set. If the received frame meets the preceding conditions, the fol- lowing events occur: The eight bits in the receive shift register are latched into SBUF2.
• The Serial Port 2 receiver interrupt flag (RI2) is set. Transmission is initiated by any instruction that uses SBUF2 as a destination register. Reception is initiated by the incoming start bit if REN2 = 1 in the SCON2 SFR, Address0xE1[2]. 9-Bit UART2 with Variable Baud Rate Setting EN-T8 (SCON2[6]) selects the 9-bit mode. In this mode, the UART2 serial port operates in 9-bit mode with a variable baud rate. The baud rate is set by a dedicated timer for baud rate gen- eration, the UART2 timer, which has a fractional divisor to precisely generate any baud rate (see the UART2 Timer Generated Baud Rates section). The operation of the 9-bit UART2 is the same as for the 9-bit mode of the UART. In both modes, transmission is initiated by any instruction that uses SBUF2 as a destination register. Reception is initiated in 8-bit mode when RI2 = 0 and REN2 = 1 in the SCON2 SFR. Recep- tion is initiated in the 9-bit mode by the incoming start bit if REN2 = 1. UART2 BAUD RATE GENERATION The baud rate is determined by the overflow rate of the dedicated baud rate generator, the UART2 timer, which has an integer and fractional divisor. UART2 Timer Generated Baud Rates The enhanced Serial Baud Rate Control 2 SFR (SBAUD2, Address 0xEE) is used to control the UART2 timer. SBAUD2 is the baud rate control SFR; it sets up the integer divider (DIV2, SBAUD2[2:0]) and the extended divider (SBTH2, SBAUD2[4:3]) for the UART2 timer. The desired value to write to DIV2 and to SBTH2 can be cal- culated using the following formula, where fcore is defined in the POWCON SFR. Note that the DIV2 value must be rounded down to the nearest integer. DIV2 + SBTH2 = ()2 log 16log ⎟⎟ × Rate Baud fcore SBAUDF2 is the fractional divider ratio required to achieve the required baud rate. The appropriate value for SBAUDF2 can be calculated with the following formula: SBAUDF2 = ⎟⎟ −××× + 12 1664 2 2 Rate Baud f SBTHDIV core Note that SBAUDF2 can take only two values, 0x2B or 0x07, by clearing or by setting the SBF2 bit (SBAUD2[5]), respectively. These values were chosen to provide an accurate baud rate for 300, 2400, 4800, 9600, 19,200, 38,400, 57,600, and 115,200 bps. When DIV2 and SBAUDF2 are calculated, the actual baud rate can be calculated, using the following formula: Actual Baud Rate = ⎞⎜⎝ ⎛ + ×× + 212 16 2 2 SBAUDF f SBTHDIV core

ADE5166/ADE5169/ADE5566/ADE5569 Rev. B | Page 137 of 156 For example, to get a baud rate of 9600 while operating at a core clock frequency of 4.096 MHz, with the PLL CD bits (POWCON[2:0]) equal to 0 DIV2 + SBTH2 = log(4,096,000/(16 × 9600))/log2 = 4.74 = 4 Note that the DIV result is rounded down. 42.67 = 0x2B Therefore, the actual baud rate is 9570 bps, which gives an error of 0.31%. UART2 ADDITIONAL FEATURES Enhanced Error Checking The extended UART2 provides frame error, break error, and overwrite error detection. Framing errors occur when a stop bit is not present at the end of the frame. A missing stop bit implies that the data in the frame may not have been received properly. Break error detection indicates whether the RxD2 line is low for longer than a 9-bit frame. It indicates that the data just received, a 0 or NULL character, is not valid because the master has discon- nected. Overwrite error detection indicates whether the received data is not read fast enough and, as result, a byte of data is lost. UART2 TxD2 Signal Modulation There is an internal 38 kHz signal that can be read with the UART2 transmit signal for use in remote control applications. One of the events that can wake the MCU from sleep mode is activity on the RxD2 (P0.7/SS/T1/RxD2) pin. See the section for more information. 3.3 V Peripherals and Wake-Up Events

while the current byte is shifted out. The SPI port can be configured for master or slave operation. Table 150. SPI SFR List 0x9A SPI2CTx W 8 0 SPI/I2C transmit buffer (see Table 151). 0x9B SPI2CRx R 8 0 SPI/I2C receive buffer (see Table 152). 0xE8 SPIMOD1 R/W 8 0x10 SPI Configuration SFR 1 (see Table 153). 0xE9 SPIMOD2 R/W 8 0 SPI Configuration SFR 2 (see Table 154). 0xEA SPISTAT R/W 8 0 SPI interrupt status (see Table 155). Table 151. SPI/I2C Transmit Buffer SFR (SPI2CTx, Address 0x9A) FIFO input. When a write is requested, the FIFO output is sent on the SPI or I2C bus. Table 152. SPI/I2C Receive Buffer SFR (SPI2CRx, Address 0x9B) transferred to the SPI2CRx SFR. A new data byte from the SPI or I2C bus is written to the FIFO input.

Table 153. SPI Configuration SFR 1 (SPIMOD1, Address 0xE8) [7:6] 0xEF to 0xEE Reserved 00 Reserved. 5 0xED INTMOD 0 SPI interrupt mode.

0 SPI interrupt is set when the SPI Rx buffer is full

1 SPI interrupt is set when the SPI Tx buffer is empty

0 The SS pin is held low while this bit is cleared, allowing manual chip select

1 Single byte read or write; the SS pin goes low during a single byte

3 0xEB SS_EN 0 Slave mode, SS input enable. 2 0xEA RxOFW 0 Receive buffer overflow write enable.

0 If the SPI2CRx SFR has not been read when a new data byte is received,

1 If the SPI2CRx SFR has not been read when a new data byte is received,

[1:0] 0xE9 to 0xE8 SPIR 00 Master mode, SPI SCLK frequency.

Table 154. SPI Configuration SFR 2 (SPIMOD2, Address 0xE9) 7 SPICONT 0 Master mode, SPI continuous transfer mode enable bit. be initiated after a stalled period. 1 The SPI interface continues to transfer data until no valid data is available in the SPI2CTx SFR. SS remains asserted until the SPI2CTx SFR and the transmit shift registers are empty. 6 SPIEN 0 SPI interface enable bit. 0 The SPI interface is disabled. 1 The SPI interface is enabled. 5 SPIODO 0 SPI open-drain output configuration bit. 0 Internal pull-up resistors are connected to the SPI outputs. not exceed the specified operating voltage. 4 SPIMS_b 0 SPI master mode enable bit. 0 The SPI interface is defined as a slave. 1 The SPI interface is defined as a master. 3 SPICPOL 0 SPI clock polarity configuration bit (see Figure 113). is sampled on the rising or falling edge of SCLK. input is sampled on the falling or rising edge of SCLK. 2 SPICPHA 0 SPI clock phase configuration bit (see Figure 113).

0 The SPI data output changes state when SS goes low at the second edge of SCLK and then every

1 The SPI data output changes state at the first edge of SCLK and then every two subsequent

1 SPILSBF 0 Master mode, LSB first configuration bit. 0 The MSB of the SPI outputs is transmitted first. 1 The LSB of the SPI outputs is transmitted first. 0 TIMODE 1 Transfer and interrupt mode of the SPI interface. 1 See Bit 5, Bit 4, and Bit 1 of Table 155 for mode selection.

Table 155. SPI Interrupt Status SFR (SPISTAT, Address 0xEA) 7 BUSY 0 SPI peripheral busy flag. 0 The SPI peripheral is idle. 1 The SPI peripheral is busy transferring data in slave or master mode. 6 MMERR 0 SPI multimaster error flag. 0 A multiple master error has not occurred.

1 If the SS_EN bit (SPIMOD1, Address 0xE8[3]) is set, enabling the slave select input and asserting

the error. Write a 0 to this bit to clear it. 5 SPIRxOF 0 SPI receive overflow error flag. Reading the SPI2CRx SFR clears this bit. 0 X 1 The SPI2CRx SFR (Address 0x9B) contains valid data. bit (SPIMOD1, Address 0xE8[2]) is set and this condition occurs, SPI2CRx is overwritten. 4 SPIRxIRQ 0 SPI receive mode interrupt flag. Reading the SPI2CRx SFR clears this bit. 0 X 1 The SPI2CRx SFR does not contain new data. end of the current byte transfer, the transfer stops and the SS pin is deasserted. 1 1 The SPI2CRx SFR contains new data. 3 SPIRxBF 0 Status bit for the SPI Rx buffer. When set, the Rx FIFO is full. A read of the SPI2CRx SFR clears this flag. (Address 0x9A). Write a 0 to this bit to clear it. 1 SPITxIRQ 0 SPI transmit mode interrupt flag. Writing new data to the SPI2CTx SFR clears this bit. 0 X 1 The SPI2CTx SFR is full. 1 0 The SPI2CTx SFR is empty. end of the current byte transfer, the transfer stops and the SS pin is deasserted. Write a 0 to this bit to clear it. 0 SPITxBF 0 Status bit for the SPI Tx buffer. When set, the SPI Tx buffer is full. Write a 0 to this bit to clear it. byte-wide (8-bit) serial data, MSB first. wide (8-bit) serial data, MSB first. output in master mode and as an input in slave mode. and SPI Configuration SFR 2 (SPIMOD2, Address 0xE9). figured with the phase and polarity of the expected input clock. be configured the same for the master and slave devices.

until the master issues a stop condition and the bus becomes idle. fast mode (256 kHz) or in standard mode (32 kHz). request. A write to this SFR starts the I2C communication. The I2C peripheral interface consists of five SFRs.

• I2CMOD
• SPI2CSTAT
• I2CADR
• SPI2CTx
• SPI2CRx Because the SPI and I2C serial interfaces share the same pins, they also share the same SFRs, such as the SPI2CTx and SPI2CRx SFRs. In addition, the I2CMOD, I2CADR, and SPI2CSTAT SFRs are shared with the SPIMOD1, SPIMOD2, and SPISTAT SFRs, respectively.

Table 156. I2C SFR List 0x9A SPI2CTx W 8 SPI/I2C transmit buffer (see Table 151). 0x9B SPI2CRx R 8 0 SPI/I2C receive buffer (see Table 152). 0xE8 I2CMOD R/W 8 0 I2C mode (see Table 157). 0xE9 I2CADR R/W 8 0 I2C slave address (see Table 158). 0xEA SPI2CSTAT R/W 8 0 I2C interrupt status (see Table 159). Table 157. I2C Mode SFR (I2CMOD, Address 0xE8) I2CADR SFR (Address 0xE9) starts a communication. [6:5] 0xEE to 0xED I2CR 00 I2C SCLK frequency. I2CRCT[4:0] + 1 byte have been read, or if an error occurs. Table 158. I2C Slave Address SFR (I2CADR, Address 0xE9) [7:1] I2CSLVADR 0 Address of the I2C slave being addressed. Writing to this register starts the I2C transmission (read or write). I2C bus. Data from the slave in the SPI2CRx SFR (Address 0x9B) is expected after a command byte. expected in the SPI2CTx SFR.

Table 159. I2C Interrupt Status SFR (SPI2CSTAT, Address 0xEA) 7 I2CBUSY 0 This bit is set to Logic 1 when the I2C interface is used. When set, the Tx FIFO is emptied. does not send an acknowledgement. The I2C communication is stopped after this event. Write a 0 to this bit to clear it. 5 I2CRxIRQ 0 I2C receive interrupt. This bit is set to Logic 1 when the receive FIFO is not empty. Write a 0 to this bit to clear it. 4 I2CTxIRQ 0 I2C transmit interrupt. This bit is set to Logic 1 when the transmit FIFO is empty. Write a 0 to this bit to clear it. used in I2C communication (receive or transmit) because only one FIFO is active at a time.

00 FIFO empty

01 Reserved

10 FIFO half full

11 FIFO full

1 I2CACC_ERR 0 Set when trying to write and read at the same time. Write a 0 to this bit to clear it. 0 I2CTxWR_ERR 0 Set when a write is attempted when the I2C transmit FIFO is full. Write a 0 to this bit to clear it. Figure 114. I2C Read Operation Figure 115. I2C Write Operation Mov a, spi2crx or Mov R0, spi2crx. does not transfer the right data into RAM Address 0x3D.

needed in the transmit shift register, the communication stops. write operation, the Tx FIFO is flushed. set in the I2CRCT bits in the I2CMOD SFR (Address 0xE8[4:0]). the communication to terminate. Figure 116. I2C FIFO Operation

Table 161. Extended Port Configuration SFR (EPCFG, Address 0x9F) 7 MOD38_FP21 0 This bit enables 38 kHz modulation on the P1.6/FP21 pin. 6 MOD38_FP22 0 This bit enables 38 kHz modulation on the P1.5/FP22 pin. 5 MOD38_FP23 0 This bit enables 38 kHz modulation on the P1.4/T2/FP23 pin. 4 MOD38_TxD 0 This bit enables 38 kHz modulation on the P1.1/TxD pin. 3 MOD38_CF1 0 This bit enables 38 kHz modulation on the P0.2/CF1 pin. 2 MOD38_SSb 0 This bit enables 38 kHz modulation on the P0.7/SS/T1/RxD2 pin. 1 MOD38_MISO 0 This bit enables 38 kHz modulation on the P0.5/MISO/ZX pin. 0 MOD38_CF2 0 This bit enables 38 kHz modulation on the P0.3/CF2 pin. Table 162. Port 0 Weak Pull-Up Enable SFR (PINMAP0, Address 0xB2) 7 PINMAP0.7 0 The weak pull-up on P0.7 is disabled when this bit is set. 6 PINMAP0.6 0 The weak pull-up on P0.6 is disabled when this bit is set. 5 PINMAP0.5 0 The weak pull-up on P0.5 is disabled when this bit is set. 4 PINMAP0.4 0 The weak pull-up on P0.4 is disabled when this bit is set. 3 PINMAP0.3 0 The weak pull-up on P0.3 is disabled when this bit is set. 2 PINMAP0.2 0 The weak pull-up on P0.2 is disabled when this bit is set. 1 PINMAP0.1 0 The weak pull-up on P0.1 is disabled when this bit is set. 0 PINMAP0.0 0 The weak pull-up on P0.0 is disabled when this bit is set. Table 163. Port 1 Weak Pull-Up Enable SFR (PINMAP1, Address 0xB3) 7 PINMAP1.7 0 The weak pull-up on P1.7 is disabled when this bit is set. 6 PINMAP1.6 0 The weak pull-up on P1.6 is disabled when this bit is set. 5 PINMAP1.5 0 The weak pull-up on P1.5 is disabled when this bit is set. 4 PINMAP1.4 0 The weak pull-up on P1.4 is disabled when this bit is set. 3 PINMAP1.3 0 The weak pull-up on P1.3 is disabled when this bit is set. 2 PINMAP1.2 0 The weak pull-up on P1.2 is disabled when this bit is set. 1 PINMAP1.1 0 The weak pull-up on P1.1 is disabled when this bit is set. 0 PINMAP1.0 0 The weak pull-up on P1.0 is disabled when this bit is set. Table 164. Port 2 Weak Pull-Up Enable SFR (PINMAP2, Address 0xB4) [7:6] Reserved 0 Reserved. Should be left cleared. 5 PINMAP2.5 0 The weak pull-up on RESET is disabled when this bit is set. 4 Reserved 0 Reserved. Should be left cleared. 3 PINMAP2.3 0 Reserved. Should be left cleared. 2 PINMAP2.2 0 The weak pull-up on P2.2 is disabled when this bit is set. 1 PINMAP2.1 0 The weak pull-up on P2.1 is disabled when this bit is set. 0 PINMAP2.0 0 The weak pull-up on P2.0 is disabled when this bit is set.

Table 165. Port 0 SFR (P0, Address 0x80) 7 0x87 T1 1 This bit reflects the state of the P0.7/SS/T1/RxD2 pin. It can be written to or read. 6 0x86 T0 1 This bit reflects the state of the P0.6/SCLK/T0 pin. It can be written to or read. 5 0x85 ZX 1 This bit reflects the state of the P0.5/MISO/ZX pin. It can be written to or read. 4 0x84 1 This bit reflects the state of the P0.4/MOSI/SDATA pin. It can be written to or read. 3 0x83 CF2 1 This bit reflects the state of the P0.3/CF2 pin. It can be written to or read. 2 0x82 CF1 1 This bit reflects the state of the P0.2/CF1 pin. It can be written to or read. 1 0x81 1 This bit reflects the state of the P0.1/FP19 pin. It can be written to or read. 0 0x80 INT1 1 This bit reflects the state of the BCTRL/INT1/P0.0 pin. It can be written to or read. 1 When an alternate function is chosen for a pin of this port, the bit controlling this pin should always be set. Table 166. Port 1 SFR (P1, Address 0x90) 7 0x97 1 This bit reflects the state of the P1.7/FP20 pin. It can be written to or read. 6 0x96 1 This bit reflects the state of the P1.6/FP21 pin. It can be written to or read. 5 0x95 1 This bit reflects the state of the P1.5/FP22 pin. It can be written to or read. 4 0x94 T2 1 This bit reflects the state of the P1.4/T2/FP23 pin. It can be written to or read. 3 0x93 T2EX 1 This bit reflects the state of the P1.3/T2EX/FP24 pin. It can be written to or read. 2 0x92 ZX1 1 This bit reflects the state of the P1.2/FP25/ZX pin. It can be written to or read. 1 0x91 TxD 1 This bit reflects the state of the P1.1/TxD pin. It can be written to or read. 0 0x90 RxD 1 This bit reflects the state of the P1.0/RxD pin. It can be written to or read. 1 When an alternate function is chosen for a pin of this port, the bit controlling this pin should always be set. Table 167. Port 2 SFR (P2, Address 0xA0) [7:4] 0x97 to 0x94 0x1F These bits are unused and should remain set. 3 0x93 P2.3 1 This bit reflects the state of the SDEN/P2.3/TxD2 pin. It can be written only. 2 0x92 P2.2 1 This bit reflects the state of the P2.2/FP16 pin. It can be written to or read. 1 0x91 P2.1 1 This bit reflects the state of the P2.1/FP17 pin. It can be written to or read. 0 0x90 P2.0 1 This bit reflects the state of the P2.0/FP18 pin. It can be written to or read. 1 When an alternate function is chosen for a pin of this port, the bit controlling this pin should always be set.

Table 168. Port 0 Alternate Functions P0.0 BCTRL external battery control input Set INT1PRG = X01 in the interrupt pins configuration SFR (INTPR, Address 0xFF[3:1]). INT1 external interrupt Set EX1 in the interrupt enable SFR (IE, Address 0xA8[2]). INT1 wake-up from PSM2 operating mode Set INT1PRG = 11X in the interrupt pins configuration SFR (INTPR, Address 0xFF[3:1]). P0.1 FP19 LCD segment pin Set FP19EN in the LCD Segment Enable 2 SFR (LCDSEGE2, Address 0xED[3]). SPIEN bit in SPI Configuration SFR 2 (SPIMOD2, Address 0xE9[6]). I2CEN bit in the I2C mode SFR (I2CMOD, Address 0xE8[7]). SPIEN bit in SPI Configuration SFR 2 (SPIMOD2, Address 0xE9[6]). Zero-Crossing Detection 2 Set the ZX2 bit in the MODE3 energy measurement SFR (MODE3, Address 0x2B[0]). SPI Configuration SFR 2 (SPIMOD2, Address 0xE9[6]) to enable the I2C or SPI interface. Address 0x89[2]) to enable T0 as an external event counter. P0.7 SS SPI slave select input for SPI in slave mode Set the SS_EN bit in SPI Configuration SFR 1 (SPIMOD1, Address 0xE8[3]). SS SPI slave select output for SPI in master mode Set the SPIMS_b bit in SPI Configuration SFR 2 (SPIMOD2, Address 0xE9[4]). Address 0x89[6]) to enable T1 as an external event counter. Set the REN2 bit in the Serial Communications Control 2 SFR (SCON2, Address 0xE1[2]). Set RXPROG bits = 11 in the peripheral configuration SFR (PERIPH, Address 0xF4[1:0]). Table 169. Port 1 Alternate Functions P1.0 RxD receiver data input for UART Set the REN bit in the serial communications control SFR (SCON, Address 0x98[4]). P1.1 TxD transmitter data output for UART This pin becomes TxD as soon as data is written into SBUF. P1.2 FP25 LCD segment pin Set the FP25EN bit in the LCD segment enable SFR (LCDSEGE, Address 0x97[7]). Zero-Crossing Detection 1 Set the ZX1 bit in the MODE3 energy measurement register (MODE3, Address 0x2B[1]). P1.3 FP24 LCD segment pin Set the FP24EN bit in the LCD segment enable SFR (LCDSEGE, Address 0x97[6]). T2EX Timer 2 control input Set the EXEN2 bit in the Timer/Counter 2 control SFR (T2CON, Address 0xC8[3]). P1.4 FP23 LCD segment pin Set the FP23EN bit in the LCD segment enable SFR (LCDSEGE, Address 0x97[5]). enable T2 as an external event counter. P1.5 FP22 LCD segment pin Set the FP22EN bit in the LCD segment enable SFR (LCDSEGE, Address 0x97[4]). P1.6 FP21 LCD segment pin Set the FP21EN bit in the LCD segment enable SFR (LCDSEGE, Address 0x97[3]). P1.7 FP20 LCD segment pin Set the FP20EN bit in the LCD segment enable SFR (LCDSEGE, Address 0x97[2]). Table 170. Port 2 Alternate Functions P2.0 FP18 LCD segment pin Set the FP18EN bit in the LCD Segment Enable 2 SFR (LCDSEGE2, Address 0xED[2]). P2.1 FP17 LCD segment pin Set the FP17EN bit in the LCD Segment Enable 2 SFR (LCDSEGE2, Address 0xED[1]). P2.2 FP16 LCD segment pin Set the FP16EN bit in the LCD Segment Enable 2 SFR (LCDSEGE2, Address 0xED[0]). Enabled by default. This pin becomes TxD2 as soon as data is written into SBUF2.

weak internal pull-up is disabled by writing a 1 to PINMAP0[x]. only if the corresponding bit latch in the Port 0 SFR contains a 1. Table 169. The alternate functions of Port 1 pins can be activated only if the corresponding bit latch in the Port 1 SFR contains a 1. operation, such as a CPL P2.3, cannot be executed on this I/O. disabled by writing a 1 to PINMAP2[x]. only if the corresponding bit latch in the Port 2 SFR contains a 1.

ADE5166/ADE5169/ADE5566/ADE5569 Rev. B | Page 152 of 156 DETERMINING THE VERSION OF THE ADE5166/ADE5169/ADE5566/ADE5569 Each ADE5166/ADE5169/ADE5566/ADE5569 holds in its internal flash registers a value that defines its version. This value helps to determine if users have the latest version of the part. The version of the ADE5166/ADE5169/ADE5566/ADE5569 that corresponds to this data sheet is ADE5166/ADE5169/ADE5566/ADE5569 V2.3. This value can be accessed as follows: Launch HyperTerminal with a 9600 baud rate. 2. Put the part in serial download mode by first holding SDEN to logic low, then resetting the part. 3. Hold the SDEN pin. 4. Press and release the RESET pin. A string should appear on the HyperT erminal containing the part name and version number, for example, ADE5166V2.3, ADE5169V2.3, ADE5566V2.3, or ADE5569V2.3.

ADE5166/ADE5169/ADE5566/ADE5569 Rev. B | Page 153 of 156 OUTLINE DIMENSIONS COMPLIANT TO JEDEC STANDARDS MS-026-BCD 051706-A TOP VIEW (PINS DOWN) 4964 0.27 0.22 0.17 0.50 BSC LEAD PITCH 12.20 12.00 SQ 11.80 PIN 1 1.60 MAX 0.75 0.60 0.45 10.20 10.00 SQ 9.80 VIEW A 0.20 0.09 1.45 1.40 1.35 0.08 COPLANARITY VIEW A ROTATED 90° CCW SEATING PLANE 0.15 0.05 3.5° Figure 119. 64-Lead Low Profile Quad Flat Package [LQFP]

Description

ADE5166ASTZF622 Yes No No 62 −40°C to +85°C 64-Lead LQFP ST-64-2 ADE5166ASTZF62-RL2 Yes No No 62 −40°C to +85°C 64-Lead LQFP , 13” Tape & Reel ST-64-2 ADE5169ASTZF622 Yes Yes Yes 62 −40°C to +85°C 64-Lead LQFP ST-64-2 ADE5169ASTZF62-RL2 Yes Yes Yes 62 −40°C to +85°C 64-Lead LQFP , 13” Tape & Reel ST-64-2 ADE5566ASTZF622 No No No 62 −40°C to +85°C 64-Lead LQFP ST-64-2 ADE5566ASTZF62-RL2 No No No 62 −40°C to +85°C 64-Lead LQFP , 13” Tape & Reel ST-64-2 ADE5569ASTZF622 No Yes Yes 62 −40°C to +85°C 64-Lead LQFP ST-64-2 ADE5569ASTZF62-RL2 No Yes Yes 62 −40°C to +85°C 64-Lead LQFP , 13” Tape & Reel ST-64-2 ADE8052Z-PRG12 ADE Programmer ADE8052Z-DWDL12 ADE Downloader ADE8052Z-EMUL12 ADE Emulator EVAL-ADE5169F62EBZ2 Evaluation Board EVAL-ADE5569F62EBZ2 Evaluation Board 1 All models have W + VA + rms, 5 V LCD, and RTC. 2 Z = RoHS Compliant Part.

ADE5166/ADE5169/ADE5566/ADE5569 Rev. B | Page 154 of 156 NOTES

ADE5166/ADE5169/ADE5566/ADE5569 Rev. B | Page 155 of 156 NOTES

ADE5166/ADE5169/ADE5566/ADE5569 Rev. B | Page 156 of 156 NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2008–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D07411-0-11/09(B)