ADE1201 (Rev. 0)
Document overview
- Manufacturer or author: Analog Devices, Inc.
- PDF pages: 40
Technical content
Single Channel, Configurable, Isolated Digital Input Data Sheet ADE1201 Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2019 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
FEATURES
Single channel, configurable, isolated digital input Programmable trip threshold On-chip debounce filter On-chip data and power isolation Application circuit monitors wide voltage range ±10 V dc to ±300 V dc
8 V rms to 240 V rms ac
Programmable wetting current Pulse up to 205 mA Constant current up to 6.3 mA Safety and regulatory approvals UL recognition
3750 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice 5A (pending) CSA 61010-1: 300 V rms VDE certificate of conformity (pending) DIN V VDE V 0884-11 (VDE V 0884-11):2017-1 V IORM = 565 V peak EMC robust solution supports relay protection system level requirements ADC samples available for system diagnostics Internal SAR ADC with PGA Single 3.3 V supply Integrated isoPower, isolated dc-to-dc converter Interfaces SPI DOUT1 output reflects state of digital input IRQ interrupt pin Operating temperature: −40°C to +125°C 20-lead, LGA package with 6.8 mm creepage
APPLICATIONS
Energy transmission and distribution Multifunction relay protection Substation battery monitoring Bay or substation interlocking Merge unit Circuit breaker status indication Remote terminal unit Building automation GENERAL DESCRIPTION The ADE12011 is a single channel, configurable, isolated digital input monitoring solution for energy transmission and distribution applications. The ADE1201 is configured through the serial port interface (SPI) to perform an isolated measurement of the digital input that is also called binary input or contact input. The ADE1201 digital output signal on the DOUT1 pin reflects the state of the input signal after user configurable signal conditioning. The SPI protocol supports addressing to allow up to eight devices sharing one 4-wire SPI port. The ADE1201 application circuit accepts a wide range of input voltages from ±10 V dc to ±300 V dc, or 8 V rms to 240 V rms. The programmable wetting current and robust application circuit enable the device to meet stringent, system level electromagnetic capability (EMC) requirements. The ADE1201 includes an isoPower® integrated, isolated dc-to-dc converter that eliminates the need for an external isolated power supply. The iCoupler® chip scale transformer technology is used to isolate the logic signals between the high voltage, isolated side and the low voltage, nonisolated side of the digital input monitor. This technology creates a small form factor design that includes data and power isolation. An integrated successive approximation register (SAR) analog-to-digital converter (ADC) and a programmable gain amplifier (PGA) from 1× to 10× measure the analog inputs. The ADC waveforms are available through the SPI port to allow system level diagnostics. PRODUCT HIGHLIGHTS 1. Single channel, configurable, isolated digital input. 2. Single hardware design supports 24 V to 300 V systems. 3. Robust architecture. 4. Enables system level diagnostics. 1 Protected by U.S. Patent Number 2017/0250043. Other patents pending.
Rev. 0 | Page 2 of 40 TABLE OF CONTENTS DIN V VDE V 0884-11 (VDE V 0884-11) Insulation
REVISION HISTORY
12/2019—Revision 0: Initial Version
Rev. 0 | Page 3 of 40 FUNCTIONAL BLOCK DIAGRAM DECIMATION COMPARATOR FILTERING OUTPUT CONTROL SPI PORT PROGRAMMABLE LOAD GATE DRIVE LDO VDD GND VLDO DOUT1 IRQ ADDR CS SCLK MOSI MISO GNDF VDDI VDDL GATE LOAD1 GNDF RECTIFIER ADE1201 LDO PGAIN1 DATA ISOLATION POWER ISOLATION ADC 22801-001 Figure 1.
Rev. 0 | Page 4 of 40 SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VDD = 3.3 V ± 10%, GND = 0 V , on-chip reference, and all specifications at TA = −40°C to +125°C, unless otherwise noted. Table 1. Static Characteristics
1 Guaranteed by design and characterization. Table 2. SAR, ADC, and PGA Characteristics
Figure 3. SPI Timing For additional information, see www.analog.com/icouplersafety. 1 The device is considered a 2-terminal device. Pin 1 through Pin 10 are shorted together, and Pin 11 through Pin 20 are shorted together.
The ADE1201 is pending approval by the organizations listed in Table 8. Table 8. Approvals
320 V secondary (452 V peak)
1 In accordance with UL 1577, each product is proof tested by applying an insulation test voltage of ≥4500 V rms for 1 sec. 2 In accordance with DIN V VDE V 0884-11, each product is proof tested by applying an insulation test voltage of ≥1059 V peak for 1 sec.
An asterisk (*) on a package denotes VDE 0884 approval for a 707 V peak working voltage.
1060 V peak
848 V peak
678 V peak
8000 V peak
1 This is the maximum power dissipation to guarantee insulation integrity. Figure 4. Thermal Derating Curve, Dependence of Safety Limiting Values with Ambient Temperature, per DIN V VDE V 0884-11
TA = 25°C, unless otherwise noted. JEDEC for the latest revision of this standard. 2 Applicable standard: ANSI/ESDA/JEDEC JS-001-2014. 3 Applicable standard: JESD22-C101F (ESD FICDM standard of JEDEC). Table 11. Thermal Resistance1
1 Based on simulated data using a JEDEC 2s2p thermal test board in a JEDEC
natural convection environment. See JEDEC specification JESD-51 for details. Table 12. Maximum Continuous Working Voltage1 1 The maximum continuous working voltage refers to the continuous voltage magnitude imposed across the isolation barrier. See the Insulation Wear Out section for more details. 2 Insulation lifetime for the specified test condition is greater than 50 years.
- NC = NO CONNECT. THESE PINS ARE INTERNALLY CONNECTED AND
IT IS RECOMMENDED TO TIE THESE PINS TO GNDF EXTE RNALLY.
- NIC = NOT INTERNALLY CONNECTED.
Figure 5. Pin Configuration Table 13. Pin Function Descriptions circuits together if ac or negative dc inputs are applied. 2 GATE Use this pin to drive the gate pin of an enhancement mode field effect transistor (FET). 3 LOAD1 Programmable Load. Use this pin to command a preset current required for loading the relay contacts. 4 NIC Not Internally Connected. 5 IN1 Digital Input Pin. The scaled input signal is applied at this pin. 6, 8 NC No Connect. These pins are internally connected and it is recommended to tie these pins to GNDF externally. 7 VDDL 1.8 V Output of the Analog Low Dropout (LDO) Regulator. Do not connect external load circuitry to this pin. Guidelines section for recommendations on how to connect this pin. 10 GNDF The GNDF pin located at Pin 10 is used as a reference for the internal, isolated power supply and the LDO regulator. circuits together if ac or negative dc inputs are applied. 11 GND GND Pin. This pin is the system controller side ground pin. shown in Table 16, and see the Layout Guidelines section for recommendations on how to connect this pin. connect external load circuitry to this pin. low, VOL, replicating the digital input signal at the IN1 pin. 15 IRQ Interrupt Pin. This pin is open-drain and a 10 kΩ pull-up resistor to the VDD supply voltage is recommended. to ground. The address divider requires 1% resistors, as described in the SPI ADE1201 Addressing section. 17 CS Chip Select for SPI Port. 18 SCLK Serial Clock Input for SPI Port. All serial data transfers are synchronized to this clock. 19 MOSI Data Input for SPI Port. 20 MISO Data Output for SPI Port.
The typical ADE1201 application circuit is shown in Figure 20. Figure 20. Typical Application Circuit
and a nonisolated side (see Figure 21). Only a single 3.3 V supply is required to power the ADE1201. programmable load, and a gate drive. from the isolated side and creates the DOUT1 digital output. monitor status and ADC waveforms during operation. recommendations on how to make these connections. method is described in the Layout Guidelines section. Guidelines section for recommendations. VDDI and GNDF isolated power supply outputs.
- Supply 3.3 V to the VDD pin. The dc-to-dc converter
powers up and supplies the isolated side of the ADE1201.
- To determine when the ADE1201 devices are ready to
device until Bit 14 (RSTDONE) is set to 1.
- Use the SPI to initialize the configuration registers
(BIN_FILTER, PL_EN, and PGA_GAIN) of each ADE1201.
- Write 0xADE1 to the LOCK register to complete the
Figure 21. ADE1201 Nonisolated and Isolated Sides
Table 15. Decimation Settings
00 Bypass the decimator
Figure 24. Decimation Filter Topology including comparators and debounce filtering. output of the warning datapaths can be read over the SPI. the comparator and debounce filters. W ARNB_THR, and W ARNC_THR control registers. THRESHOLD is the desired threshold level expressed in V. PGA is the PGA gain selected by the PGA_GAIN register. DOUT1 datapath, which can be output on the DOUT1 pin. registers contain the configuration for the warning channels. hysteretic output mode is shown in Figure 25. Figure 25. Comparator Behavior in Hysteretic Output Mode in the midrange output mode is shown in Figure 26. Figure 26. Comparator Behavior in Midrange Output Mode
nominal VGATENOM voltage (see Figure 34). LOAD1 pin (VGS) is at 0.6 V. Figure 34. FET Gate Control
voltage applicable to tracking is specified in most standards.
60 Hz sinusoidal stress because this value reflects isolation from
determines the product lifetime. VRMS is the total rms working voltage. VAC RMS is the time varying portion of the working voltage. VDC is the dc offset of the working voltage. Figure 44. Critical Voltage Example In this example, VRMS = 466 V . creepage required by a system standard. In this example, VAC RMS = 240 V rms. sine wave, and is well within the limit for a 50-year service life. can differ for specific system level standards.
Table 16 lists the external components in the recommended ADE1201 application circuit, as shown in Figure 20. Table 16. External Components conditions, maximum VGS of 6 V.
275 V ac/
350 V dc
1 Use recommended components or ones that are similar.
Table 17. Address Map Register Summary
can always read registers even when the device is locked. Table 18. Bit Descriptions for LOCK 0xADE0 to the LOCK register. To lock the device, write 0xADE1 to the LOCK register. ADDR_RELOAD bits and INT_STATUS register, which can all be written when LOCK = 1. The control register allows the user to change several operating modes and also read model and revision information. Table 19. Bit Descriptions for CTRL value is determined based on the voltage on the ADDR pin at power-up. latched from the voltage on the ADDR pin. clocking for 16 cycles, a 16-bit CRC is appended to the read operation.
Binary channel and warning controls for decimation and filter modes. Table 20. Bit Descriptions for BIN_CTRL standby current instead of the ADC voltage values. output drops below the low threshold level. greater than the low threshold level, the comparator output is set high. comparator output is set high. level, the comparator output is set high. output drops below the low threshold level. greater than the low threshold level, the comparator output is set high. comparator output is set high. level, the comparator output is set high. output drops below the low threshold level. greater than the low threshold level, the comparator output is set high. comparator output is set high. level, the comparator output is set high. output drops below the low threshold level. greater than the low threshold level, the comparator output is set high. comparator output is set high. level, the comparator output is set high. 00: DOUT1 equals the FORCEVAL bit value. 01: DOUT1 equals the binary filter output. 10: DOUT1 toggles value on entering invalid mode. 11: DOUT1 holds current value.
0: decimation filter is bypassed. 1: decimation rate equals 2. 10: decimation rate equals 4. 11: decimation rate equals 8. Binary channel high and low threshold values. Table 21. Bit Descriptions for BIN_THR Warning A high and low threshold values. Table 22. Bit Descriptions for WARNA_THR Warning B high and low threshold values. Table 23. Bit Descriptions for WARNB_THR Warning C high and low threshold values. Table 24. Bit Descriptions for WARNC_THR
Binary channel configuration register. Table 25. Bit Descriptions for BIN_FILTER that this bit defaults to zero so that the datapath is disabled. bypassed so the output equals the input with no latency. Warning A datapath configuration register. Table 26. Bit Descriptions for WARNA_FILTER filter is bypassed so the output equals the input with no latency. Warning B datapath configuration register. Table 27. Bit Descriptions for WARNB_FILTER filter is bypassed so the output equals the input with no latency. Warning C datapath configuration register. Table 28. Bit Descriptions for WARNC_FILTER filter is bypassed so the output equals the input with no latency.
Table 29. Bit Descriptions for MASK be disabled with MASK register, Bits[14:0] equal to zero. when the programmable load has been disabled due to thermal protection. COMFLT bit in the INT_STATUS register, then reconfigure the register settings in the device. registers must be reconfigured. output goes from logic low to logic high. output goes from logic low to logic high. output goes from logic low to logic high. to acknowledge the event and then clear the bit. This register can be written while the device is locked. Table 30. Bit Descriptions for INT_STATUS
The bits in this register are not latched and can be polled to determine the current status of the desired event. Table 31. Bit Descriptions for STATUS
14 RSTBUSY RSTBUSY goes from 0 to 1 to indicate that the device has reset and is ready to be programmed
between a bad read (0xFFFF) and an initialized device. ADC sample updates at 100 kHz. Table 32. Bit Descriptions for ADC Table 33. Bit Descriptions for ADCDEC
Configures the programmable load into low idle mode or high idle mode. Table 34. Bit Descriptions for PL_CTRL ADC value rises above the PL_RISE_THR, the load current is set to PL_HIGH_CODE. enough voltage headroom on the LOAD1 pin. Sets programmable load rising edge ADC sample threshold. Table 35. Bit Descriptions for PL_RISE_THR enforced by the hardware such that a write of 0x00 becomes 0x01 and 0xFF becomes 0xFE. Table 36. Bit Descriptions for PL_LOW_CODE value is 0x1. If 0x0 is written, LOW_CODE = 0x1. Programmable load high code. Table 37. Bit Descriptions for PL_HIGH_CODE
High current timer duration. Table 38. Bit Descriptions for PL_HIGH_TIME minimum HIGH_TIME is 10 µs. If 0 is written, HIGH_TIME = 1. Energy meter control register. Table 39. Bit Descriptions for EGY_MTR_CTRL is decremented by the COOLDOWN_DECR value every COOLDOWN_TIMESTEP . decremented by the COOLDOWN_DECR value every COOLDOWN_TIMESTEP . Energy meter maximum energy threshold. Table 40. Bit Descriptions for EGY_MTR_THR ADC values every 10 µs when the device is not in cool down mode. Table 41. Bit Descriptions for EGY_MTR1
The programmable load enable. Table 42. Bit Descriptions for PL_EN the programmable load. Disabled after power-on reset. the programmable load. Disabled after power-on reset. Gain value, as shown in Table 43. Table 43. Bit Descriptions for PGA_GAIN
0.75 REF
7.35 BSC
3.675 BSC
4.50 BSC
0.32 REF
Figure 50. 20-Lead Land Grid Array [LGA] 2 The EVAL-SDP-CB1Z is the controller board that manages the EVAL-ADE1201EBZ evaluation board. Both boards must be ordered together. registered trademarks are the property of their respective owners.