ADDAC85C-CBI-I

ADDAC80_15 AD | Alldatasheet

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REV.B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a ADDAC80/ADDAC85/ADDAC87 Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002 Complete Low Cost 12-Bit D/A Converters FUNCTIONAL BLOCK DIAGRAM *NC = CBI VERSIONS 5V – CCD VERSIONS (MSB) BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 BIT 9 BIT 10 BIT 11 (LSB) BIT 12 V REF OUT GAIN ADJUST +VS COMMON SUMMING JUNCTION 20V RANGE 10V RANGE BIPOLAR OFFSET REF INPUT V OUT –VS NC/+VL* 12-BIT RESISTOR LADDER NETWORK AND CURRENT SWITCHES REF CONTROL CIRCUIT 6.3k/H9024 5k/H9024 5k/H9024 ADDAC80 *NC = CBI VERSIONS 5V – CCD VERSIONS (MSB) BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 BIT 9 BIT 10 BIT 11 (LSB) BIT 12 V REF OUT GAIN ADJUST +VS COMMON SCALING NETWORK SCALING NETWORK SCALING NETWORK BIPOLAR OFFSET REF INPUT I OUT –VS NC/+VL* 12-BIT RESISTOR LADDER NETWORK AND CURRENT SWITCHES REF CONTROL CIRCUIT 6.3k/H9024 2k/H9024 5k/H9024 5k/H9024

FEATURES

Low Power Dissipation: 300 mW Monotonicity Guaranteed over Temperature Guaranteed for Operation with 12 V Supplies Improved Replacement for Standard DAC80, DAC800 Hl-5680 High Stability, High Current Output Buried Zener Reference Laser Trimmed to High Accuracy 1/2 LSB Max Nonlinearity Low Cost Plastic Packaging PRODUCT DESCRIPTION The ADDAC80 Series is a family of low cost 12-bit digital-to- analog converters with both a high stability voltage reference and output amplifier combined on a single monolithic chip. The ADDAC80 Series is recommended for all low cost 12-bit D/A converter applications where reliability and cost are of paramount importance. Advanced circuit design and precision processing techniques result in significant performance advantages over conventional DAC80 devices. Innovative circuit design reduces the total power consumption to 300 mW, which not only improves reli- ability, but also improves long term stability. The ADDAC80 incorporates a fully differential, nonsaturating precision current switching cell structure which provides greatly increased immunity to supply voltage variation. This same struc- ture also reduces nonlinearities due to thermal transients as the various bits are switched; nearly all critical components operate at constant power dissipation. High stability, SiCr thin film resistors are trimmed with a fine resolution laser, resulting in lower differential nonlinearity errors. A low noise, high stability, subsurface Zener diode is used to produce a reference voltage with excellent long term stability, high external current capabil- ity and temperature drift characteristics which challenge the best discrete Zener references. The ADDAC80 Series is available in three performance grades and three package types. The ADDAC80 is specified for use over the 0 °C to 70 °C temperature range and is available in both plastic and ceramic DIP packages. The ADDAC85 and ADDAC87 are av ailable in hermetically sealed ceramic packages and are specified for the –25°C to +85°C and –55°C to +125°C temperature ranges. PRODUCT HIGHLIGHTS 1. The ADDAC80 series of D/A converters directly replaces all other devices of this type with significant increases in performance. 2. Single chip construction and low power consumption pro- vides the optimum choice for applications where low cost and high reliability are major considerations. 3. The high speed output amplifier has been designed to settle within 1/2 LSB for a 10 V full scale transition in 2.0 µs, when properly compensated. The precision buried Zener reference can supply up to 2.5 mA for use elsewhere in the application. 5. The low TC binary ladder guarantees that all units are mono- tonic over the specified temperature range. 6. System performance upgrading is possible without redesign.

REV. B–2– ADDAC80/ADDAC85/ADDAC87–SPECIFICATIONS ADDAC80 ADDAC85 ADDAC87 Model Min Typ Max Min Typ Max Min Typ Max Unit TECHNOLOGY Monolithic Monolithic Monolithic DIGITAL INPUT Binary–CBI 12 12 12 Bits BCD–CCD Digits Logic Levels (TTL Compatible) V VIL (Logic “0”) 0 0.8 0 0.8 0 0.8 V IIH (VIH = 5.5 V) 250 250 250 µA IIL (VIL = 0.8 V) 100 100 100 µA TRANSFER CHARACTERISTICS ACCURACY Linearity Error @ 25 °C CBI ± 1/2 ± 1/2 ± 1/2 LSB 1 CCD LSB TA @ TMIN to TMAX ± 1/4 ±1/2 ± 1/4 ±1/2 ± 1/2 ±3/4 LSB Differential Linearity Error @ 25 °C CBI ±3/4 ±3/4 ±3/4 LSB CCD LSB TA @ TMIN to TMAX ±3/4 ±1 ±1 LSB Temperature Range for Guaranteed Monotonicity 0 +70 –25 +85 –55 +125 °C DRIFT (TMIN to TMAX) Total Bipolar Drift, max (includes gain, offset, and linearity drifts) ± 20 ± 20 ± 30 ppm of FSR/ °C Total Error (T MIN to TMAX)4 Gain Including Internal Reference ± 15 ±30 ±20 ±20 ppm of FSR/°C Gain Excluding Internal Reference ± 4 ± 7 ± 10 ± 10 ppm of FSR/ °C Unipolar Offset ± 1 ±3 ±3 ±3 ppm of FSR/°C Bipolar Offset ± 5 ±10 ±10 ±10 ppm of FSR/°C CONVERSION SPEED Voltage Model (V) 5 Settling Time to ± 0.01% of FSR for FSR Change (2 k Ω/H20648500 pF load) with 10 kΩ Feedback 3 4 3 4 3 4 µs with 5 kΩ Feedback 2 3 2 3 2 3 µs For LSB Change 1 1 1 µs Slew Rate 10 10 10 V/ µs ANALOG OUTPUT Voltage Models 10 10 10 V –CCD V Output Current ± 5 ± 5 ± 5m A Output Impedance (dc) 0.05 0.05 0.05 Ω Short Circuit Current 40 40 40 mA Output Impedance 1.5 1.5 1.5 Ω Max External Current 6 2.5 2.5 2.5 mA Tempco of Drift ± 10 ± 20 ± 10 ± 20 ± 10 ppm of V R/°C POWER SUPPLY SENSITIVITY ±15 V ± 10%, 5 V supply when applicable /H115500.002 /H115500.002 /H115500.002 % of FSR/%VS ± 12 V ± 5% /H115500.002 /H115500.002 /H115500.002 % of FSR/%VS POWER SUPPLY REQUIREMENTS Rated Voltages ± 15 ± 15 ± 15 V Range Logic Supplies V Supply Drain +12 V, +15 V 5 10 5 10 5 10 mA –12 V, –15 V 14 20 14 20 14 20 mA (TA = 25 /H11543C, rated power supplies unless otherwise noted.)

REV. B –3– ADDAC80/ADDAC85/ADDAC87 ADDAC80 ADDAC85 ADDAC87 Model Min Typ Max Min Typ Max Min Typ Max Unit TEMPERATURE RANGE Specifications 0 +70 –25 +85 –55 +125 °C Operating –25 +85 –55 +125 –55 +125 °C Storage –25 +125 –65 +150 –65 +150 °C NOTES 1Least Significant Bit. 2Adjustable to zero with external trim potentiometer. 3FSR means “Full Scale Range” and is 20 V for the ± 10 V range and 10 V for the ± 5 V range. 4Gain and offset errors adjusted to zero at 25 °C. 5CF = 0, see Figure 3a. 6Maximum with no degradation of specification, must be a constant load. 7A minimum of ± 12.3 V is required for a ± 10 V full scale output and ± 11.4 V is required for all other voltage ranges. Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality l evels. All min and max specifications are guaranteed, although only those shown in boldface are tested on all production units. Specifications subject to change without notice. ADDAC80 ADDAC85 ADDAC87 Model Min Typ Max Min Typ Max Min Typ Max Unit TECHNOLOGY Hybrid Hybrid Hybrid DIGITAL INPUT Binary–CBI 12 12 12 Bits BCD–CCD 3 3 3 Digits Logic Levels (TTL Compatible) V VIL (Logic “0”) 0 0.8 0 0.8 0 0.8 V IIH (VIH = 5.5 V) 250 250 250 µA IIL (VIL = 0.8 V) –100 –100 –100 µA TRANSFER CHARACTERISTICS ACCURACY Linearity Error @ 25 °C CBI ± 1/4 ± 1/2 ± 1/2 ± 1/2 LSB 1 TA @ TMIN to TMAX ± 1/4 ± 1/2 ± 1/4 ± 1/2 ± 1/2 ± 1/2 LSB Differential Linearity Error @ 25 °C TA @ TMIN to TMAX ± 1 ± 1 ± 1 LSB Gain Error2 ± 0.1 ± 0.3 ± 0.1 ± 0.1 %FSR 3 Offset Error 2 ± 0.05 ± 0.15 ± 0.05 ± 0.05 %FSR 3 Temperature Range for Guaranteed Monotonicity 0 +70 0 +70 –25 +85 °C DRIFT (TMIN to TMAX) Total Bipolar Drift, max (includes gain, offset, and linearity drifts) ± 20 ppm of FSR/ °C Total Error (T MIN to TMAX)4 Unipolar ± 0.08 ± 0.15 % of FSR Bipolar ± 0.06 ± 0.10 % of FSR Gain Including Internal Reference ± 15 ± 30 ± 20 ± 20 ppm of FSR/ °C Excluding Internal Reference ± 5 ± 7 ± 10 ± 10 ppm of FSR/ °C Unipolar Offset ± 1 ± 3 ± 1 ± 1 ppm of FSR/ °C Bipolar Offset ± 5 ± 10 ± 10 ± 10 ppm of FSR/ °C CONVERSION SPEED Voltage Model (V) 5 Settling Time to ± 0.01% of FSR for FSR Change (2 k Ω/H20648500 pF load) with 10 kΩ Feedback 5 5 5 µs with 5 kΩ Feedback 3 3 3 µs For LSB Change 1.5 1.5 1.5 µs Slew Rate 10 15 20 20 V/ µs Current Model (I) Settling time to ± 0.01% of FSR for FSR Change 10 Ω to 100 Ω Load 300 300 300 ns for 1 kΩ 111 µs

REV. B–4– ADDAC80/ADDAC85/ADDAC87–SPECIFICATIONS ADDAC80 ADDAC85 ADDAC87 Model Min Typ Max Min Typ Max Min Typ Max Unit ANALOG OUTPUT Voltage Models +10 +10 +10 V Ranges–CCD ± 10 +10 +10 V Output Current ± 5 ± 5 ± 5m A Output Impedance (dc) 0.05 0.05 0.05 Ω Short Circuit Duration Indefinite to Common Indefinite to Common Indefinite to Common Current Models Ranges–Unipolar –2.0 –2.0 –2.0 mA Ranges–Bipolar ± 1.0 ± 1.0 ± 1.0 mA Output Impedance Bipolar 3.2 3.2 3.2 k Ω Unipolar 6.6 6.6 6.6 k Ω Compliance –1.5, +10 –2.5, +10 –2.5, +10 V Internal Reference Voltage (V Output Impedance 1.5 1.5 1.5 Ω Max External Current 6 2.5 2.5 2.5 mA Tempco of Drift ± 10 ± 20 ± 10 ± 20 ± 10 ± 20 ppm of V R/°C POWER SUPPLY SENSITIVITY ±15 V ± 10%, 5 V Supply When Applicable ± 0.002 ± 0.002 ± 0.002 % of FSR/%V S POWER SUPPLY REQUIREMENTS Rated Voltages ± 15, +5 ± 15, +5 ± 15, +5 V Range Analog Supplies ± 14 ± 16 ± 14.5 ± 15.5 ± 14.5 ± 15.5 V Supply Drain7 +15 V 10 20 15 20 15 20 mA –15 V 20 35 25 30 25 30 mA +5 V8 8 2 01 5 2 01 5 2 0 m A TEMPERATURE RANGE Specifications 0 +70 0 +70 –25 +85 °C Operating –25 +85 –25 +85 –55 +125 °C Storage –55 +130 –65 +150 –65 +150 °C NOTES 1Least Significant Bit. 2Adjustable to zero with external trim potentiometer. 3FSR means “Full Scale Range” and is 20 V for the ± 10 V range and 10 V for the ± 5 V range. 4Gain and offset errors adjusted to zero at 25 °C. 5CF = 0, see Figure 3a. 6Maximum with no degradation of specification, must be a constant load. 7Including 5 mA load. 85 V supply required only for CCD versions. Specifications subject to change without notice. (continued)

REV. B –5– ADDAC80/ADDAC85/ADDAC87 ADDAC85LD ADDAC85MIL ADDAC87 Model Min Typ Max Min Typ Max Min Typ Max Unit TECHNOLOGY Hybrid Hybrid Hybrid DIGITAL INPUT Binary–CBI 12 12 12 Bits BCD–CCD Digits Logic Levels (TTL Compatible) V VIL (Logic “0”) 0 0.8 0 0.8 0 0.8 V IIH (VIH = 5.5 V) 250 250 250 µA IIL (VIL = 0.8 V) –100 –100 –100 µA TRANSFER CHARACTERISTICS ACCURACY Linearity Error @ 25 °C CBI ± 1/2 ± 1/2 ± 1/4 ± 1/2 LSB 1 CCD LSB TA @ TMIN to TMAX ± 1/2 ± 3/4 ± 3/4 LSB Differential Linearity Error @ 25 °C CBI ± 1/2 ± 1/2 ± 1/2 LSB CCD LSB TA @ TMIN to TMAX ± 1 ± 1 ± 1 LSB Gain Error2 ± 0.1 ± 0.1 ± 0.1 ± 0.2 %FSR 3 Offset Error2 ± 0.05 ± 0.05 ± 0.05 ± 0.1 %FSR 3 Temperature Range for Guaranteed Monotonicity –25 +85 –55 +125 –55 +125 °C DRIFT (TMIN to TMAX) Total Bipolar Drift, max (includes gain, offset, and linearity drifts) ± 15 ± 30 ppm of FSR/ °C Total Error (T MIN to TMAX)4 Unipolar ± 0.13 ± 0.30 % of FSR Bipolar ± 0.12 ± 0.24 % of FSR Gain Including Internal Reference ± 10 ± 20 ± 10 ± 25 ppm of FSR/ °C Excluding Internal Reference ± 5 ± 10 ppm of FSR/ °C Unipolar Offset ± 1 ± 2 ± 1 ± 3 ppm of FSR/ °C Bipolar Offset ± 5 ± 10 ± 5 ± 10 ppm of FSR/ °C CONVERSION SPEED Voltage Model (V) 5 Settling Time to ± 0.01% of FSR for FSR change (2 k Ω/H20648500 pF load) with 10 kΩ Feedback 5 5 5 µs with 5 kΩ Feedback 3 3 3 µs For LSB Change 1.5 1.5 1.5 µs Slew Rate 20 20 20 V/ µs Current Model (I) Settling Time to ± 0.01% of FSR for FSR Change 10 Ω to 100 Ω Load 300 300 300 ns for 1 kΩ 111 µs ANALOG OUTPUT Voltage Models +10 +10 +10 V Ranges–CCD V Output Current ± 5 ± 5 ± 5m A Output Impedance (dc) 0.05 0.05 0.05 Ω Short Circuit Duration Indefinite to Common Indefinite to Common Indefinite to Common Current Models Ranges–Unipolar –2.0 –2.0 –2.0 mA Ranges–Bipolar ± 1.0 ± 1.0 ± 1.0 mA Output Impedance Compliance –2.5, +10 –2.5, +10 –1.5, +10 V Internal Reference Voltage (V Output Impedance 1.5 1.5 1.5 Ω Max External Current 6 2.5 2.5 2.5 mA Tempco of Drift ± 10 ± 20 ± 10 ± 20 ± 5 ± 10 ppm of V R/°C POWER SUPPLY SENSITIVITY ±15 V ± 10%, 5 V supply when applicable ± 0.002 ± 0.002 ± 0.002 ± 0.003 % of FSR/%VS

REV. B ADDAC80/ADDAC85/ADDAC87 –7– ORDERING GUIDE Input Output Temperature Linearity Package Model Code Mode Technology Range Error Option 1 ADDAC80N-CBI-V Binary Voltage Monolithic 0 °C to 70°C ± 1/2 LSB N-24A ADDAC80D-CBI-V Binary Voltage Monolithic 0 °C to 70°C ± 1/2 LSB D-24 ADDAC85D-CBI-V Binary Voltage Monolithic –25 °C to +85°C ± 1/2 LSB D-24 ADDAC87D-CBI-V Binary Voltage Monolithic –55 °Cto +125°C ± 1/2 LSB D-24 ADDAC80-CBI-V Binary Voltage Hybrid 0 °C to 70°C ± 1/2 LSB DH-24A ADDAC80-CBI-I Binary Current Hybrid 0 °C to 70°C ± 1/2 LSB DH-24A ADDAC80-CCD-V Binary Coded Decimal Voltage Hybrid 0 °C to 70°C ± 1/4 LSB DH-24A ADDAC80-CCD-I Binary Coded Decimal Current Hybrid 0 °C to 70°C ± 1/4 LSB DH-24A ADDAC80Z-CBI-V2 Binary Voltage Hybrid 0 °C to 70°C ± 1/2 LSB DH-24A ADDAC80Z-CBI-I2 Binary Current Hybrid 0 °C to 70°C ± 1/2 LSB DH-24A ADDAC80Z-CCD-V2 Binary Coded Decimal Voltage Hybrid 0 °C to 70°C ± 1/4 LSB DH-24A ADDAC80Z-CCD-I2 Binary Coded Decimal Current Hybrid 0 °C to 70°C ± 1/4 LSB DH-24A ADDAC85C-CBI-V3 Binary Voltage Hybrid 0 °C to 70°C ± 1/2 LSB DH-24A ADDAC85C-CBI-I Binary Current Hybrid 0 °C to 70°C ± 1/2 LSB DH-24A ADDAC85-CBI-V3 Binary Voltage Hybrid –25 °C to +85°C ± 1/2 LSB DH-24A ADDAC85-CBI-I3 Binary Current Hybrid –25 °C to +85°C ± 1/2 LSB DH-24A ADDAC85LD-CBI-V3 Binary Voltage Hybrid –25 °C to +85°C ± 1/2 LSB DH-24A ADDAC85LD-CBI-I3 Binary Current Hybrid –25 °C to +85°C ± 1/2 LSB DH-24A ADDAC85MIL-CBI-V3 Binary Voltage Hybrid –55 °C to +125°C ± 1/2 LSB DH-24A ADDAC85MIL-CBI-I3 Binary Current Hybrid –55 °C to +125°C ± 1/2 LSB DH-24A ADDAC85C-CCD-V3 Binary Coded Decimal Voltage Hybrid 0 °C to 70°C ± 1/4 LSB DH-24A ADDAC85C-CCD-I3 Binary Coded Decimal Current Hybrid 0 °C to 70°C ± 1/4 LSB DH-24A ADDAC85-CCD-V3 Binary Coded Decimal Voltage Hybrid –25 °C to +85°C ± 1/4 LSB DH-24A ADDAC85-CCD-I3 Binary Coded Decimal Current Hybrid –25 °C to +85°C ± 1/4 LSB DH-24A ADDAC85MILCBII8 Binary Current Hybrid –55 °C to +125°C ± 1/2 LSB DH-24A ADDAC85MILCBIV8 Binary Voltage Hybrid –55 °C to +125°C ± 1/2 LSB DH-24A ADDAC87-CBI-V3 Binary Voltage Hybrid –55 °C to +125°C ± 1/2 LSB DH-24A ADDAC87-CBI-I3 Binary Current Hybrid –55 °C to +125°C ± 1/2 LSB DH-24A ADDAC87-CBII883 Binary Current Hybrid –55 °C to +125°C ± 1/2 LSB DH-24A ADDAC87-CBIV883 Binary Voltage Hybrid –55 °C to +125°C ± 1/2 LSB DH-24A NOTES 1For outline information see Package Information section. 2Z-Suffix devices guarantee performance of 0 V to +5 V and ± 5 V spans with minimum supply voltages of ± 11.4 V. 3These models have been discontinued. This is for historical information only. PRODUCT OFFERING Analog Devices has developed a number of technologies to support products within the data acquisition market. In serving the market new products are implemented with the technology best suited to the application. The DAC80 series of products was first implemented in hybrid form and now it is available in a single monolithic chip. We will provide both the hybrid and mono- lithic versions of the family so that in existing designs changes to documentation or product qualification will not have to be done. Specifications and ordering information for both versions are delineated in this data sheet. DIGITAL INPUT CODES The ADDAC80 Series accepts complementary digital input code in binary (CBI) format. The CBI model may be connected by the user for anyone of three complementary codes: CSB, COB or CTC. Table I. Digital Input Codes Digital Input Analog Input CSB COB CTC * Compl. Compl. Compl. Straight Offset Two’s MSB LSB Binary Binary Compl. 000000000000 +Full-Scale +Full-Scale –1 LSB 011111111111 +1/2 Full-Scale Zero –Full-Scale

100000000000 Midscale –1 LSB +Full-Scale

111111111111 Zero –Full-Scale Zero

*Invert the MSB of the COB code with an external inverter to obtain CTC code.

or 0 V to +10 V (see Figure 9). Figure 9. Output Amplifier Voltage Range Scaling Circuit ranges are not required, the external resistors are not needed. Figure 10. Internal Scaling Resistors

0 TO 2mA

Figure 11. ADDAC80 Current Model Equivalent Output Circuit TCR of RL (or RF) to the total drift.

0 V to 10 V CSB 18 21 NC 24

0 V to 5 V CSB 18 21 20 24

0 V to 10 V CCD 19 NC 15 24

(RLS) to provide full scale output voltage range of 0 V to –2 V. Figure 12. Equivalent Circuit ADDAC80-CBI-I Connected

zero, the full scale range will be ± 0.874 V. Figure 13. ADDAC80-CBI-I Connected for Bipolar Figure 14. External Op Amp Using Internal when a high voltage op amp is used. typically add 50 ppm/°C + RF drift to total drift. Figure 15. External Op Amp Using External

REV. B ADDAC80/ADDAC85/ADDAC87 –13– OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 24-Lead Plastic DIP (N-24A) 11 2 PIN 1 0.580 (14.73) 0.485 (12.32) 1.290 (32.70) 1.150 (29.30) 0.195 (4.95) 0.125 (3.18) 0.015 (0.381) 0.008 (0.204) 0.625 (15.87) 0.600 (15.24)SEATING PLANE 0.060 (1.52) 0.015 (0.38) 0.250 (6.35) MAX 0.022 (0.558) 0.014 (0.356) 0.200 (5.05) 0.125 (3.18) 0.150 (3.81) MIN 0.100 (2.54) BSC 0.070 (1.77) 0.030 (0.77) CONTROLLING DIMENSIONS ARE IN MILLIMETERS: INCH DIMENSIONS ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN24-Lead Ceramic DIP (D-24) SEATING PLANE0.023 (0.58) 0.014 (0.36) 0.075 (1.91) 0.015 (0.38) 0.225 (5.72) MAX 0.200 (5.08) 0.120 (3.05) 0.070 (1.78) 0.030 (0.76) 0.150 (3.81) MIN 1.290 (32.77) MAX 11 2 0.610 (15.49) 0.500 (12.70) PIN 1 0.098 (2.49) MAX0.005 (0.13) MIN 0.620 (15.75) 0.590 (14.99) 0.015 (0.38) 0.008 (0.20) NOTES 1. INDEX AREA; A NOTCH OR A LEAD ONE IDENTIFICATION MARK IS LOCATED ADJACENT TO LEAD ONE. 2. THE MINIMUM LIMIT FOR DIMENSION MAY BE 0.023" (0.58 mm) FOR ALL FOUR CORNER LEADS ONLY. 3. DIMENSION SHALL BE MEASURED FROM THE SEATING PLANE TO THE BASE PLANE. 4. THIS DIMENSION ALLOWS FOR OFF-CENTER LID, MENISCUS AND GLASS OVERRUN. 5. APPLIES TO ALL FOUR CORNERS. 6. ALL LEADS — INCREASE MAXIMUM LIMIT BY 0.003" (0.08 mm) MEASURED AT THE CENTER OF THE FLAT, WHEN HOT SOLDER DIP LEAD FINISH IS APPLIED. 7. TWENTY TWO SPACES. 8. CONTROLLING DIMENSIONS ARE IN MILLIMETERS. INCH DIMENSIONS ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN SEE NOTE 5 SEE NOTE 1 SEE NOTE 7 SEE NOTE 3 SEE NOTE 2, 6 SEE NOTE 4 0.110 (2.79) 0.090 (2.29) SEE NOTE 4 SEE NOTE 6 Table V. External Op Amp Voltage Mode Connections Output Digital Connect Connect Connect Connect Range Input Codes A to Pin 17 to Pin 19 to Pin 16 to ±10 V COB or CTC 19 15 A 24 ±5 V COB or CTC 18 15 NC 24 ±2.5 V COB or CTC 18 15 15 24

0 V to 5 V CSB 18 21 15 24

REV. B ADDAC80/ADDAC85/ADDAC87 –14– OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 24-Lead Side Brazed Ceramic DIP for Hybrid (DH-24A) SEATING PLANE0.023 (0.58) 0.014 (0.36) 0.075 (1.91) 0.015 (0.38) 0.225 (5.72) MAX 0.200 (5.08) 0.120 (3.05) 0.070 (1.78) 0.030 (0.76) 0.180 (4.57) MIN 1.212 (29.69) MAX 0.100 (2.54) BSC 0.098 (2.49) MAX0.005 (0.13) MIN 0.620 (15.75) 0.590 (14.99) 0.015 (0.38) 0.008 (0.20) PIN 1 NOTES 1. INDEX AREA; A NOTCH OR A LEAD ONE IDENTIFICATION MARK IS LOCATED ADJACENT TO LEAD ONE. 2. THE MINIMUM LIMIT FOR DIMENSION MAY BE 0.023" (0.58 mm) FOR ALL FOUR CORNER LEADS ONLY. 3. DIMENSION SHALL BE MEASURED FROM THE SEATING PLANE TO THE BASE PLANE. 4. THE BASIC PIN SPACING IS 0.100" (2.54 mm) BETWEEN CENTERLINES. 5. APPLIES TO ALL FOUR CORNERS. 6. SHALL BE MEASURED AT THE CENTERLINE OF THE LEADS. 7. TWENTY TWO SPACES. 8. CONTROLLING DIMENSIONS ARE IN MILLIMETERS: INCH DIMENSIONS ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. SEE NOTE 5 SEE NOTE 1 SEE NOTE 2 SEE NOTE 6 SEE NOTE 3 SEE NOTE 4, 7 0.600 (14.70) 0.580 (14.21)

REV. B ADDAC80/ADDAC85/ADDAC87 –15–

Revision History

Data Sheet changed from REV. A to REV. B.

–16– C00381–0–1/02(B) PRINTED IN U.S.A.