ADD8754

ADD8754 LCD Panel Power, VCOM, and Gate Modulation Data Sheet (Rev. 0)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 28

Technical content

LCD Panel Power, VCOM, and Gate Modulation ADD8754 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent ri ghts of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2005 Analog Devices, Inc. All rights reserved.

FEATURES

Step-up switching regulator with 2 A power switch 650 kHz or 1.2 MHz switching frequency Output adjustable to 20 V 350 mA logic voltage regulator Selectable output voltages: 2.5 V, 2.85 V, 3.3 V VCOM amplifier with 300 mA drive Gate pulse modulation circuitry Independently adjustable delay and falling slope General 3 V to 5.5 V input Undervoltage lockout Thermal shutdown 24-lead, Pb-free LFCSP package

APPLICATIONS

TFT LCD panels for monitors, TVs, and notebooks FUNCTIONAL BLOCK DIAGRAM ADD8754 VGH VGH_M VDD_1 CE RE VFLK VDPM 05110-001 GATE PULSE MODULATION VCOM AMPLIFIER LOGIC VOLTAGE REGULATOR UNDER VOLTAGE LOCKOUT AND THERMAL PROTECTION FB FREQ SHDN VDD_2 OUT STEP-UP SWITCHING REGULATOR VIN_2VIN_1SSCOMP LDO_OUT ADJ LX POS NEG Figure 1. GENERAL DESCRIPTION The ADD8754 is optimized for use in TFT LCD applications, requiring only external charge pump components to provide all the requirements for panel power, VCOM, and gate modulation. Included in a single chip are a high frequency step-up dc-to-dc switching regulator, logic voltage regulator, V COM amplifier, and gate pulse modulation circuitry. The step-up dc-to-dc converter provides up to 20 V output and includes a 2 A internal switch. Either a 650 kHz or 1.2 MHz step- up switching regulator frequency can be chosen, allowing easy filtering and low noise operation. It achieves 93% efficiency and features soft start to limit the inrush current at startup. The internal voltage regulator operates with an input voltage range of 3 V to 5.5 V and delivers a load current of up to 350 mA. Three selectable output voltages are available: 2.5 V , 2.85 V , and 3.3 V . The proprietary VCOM amplifier can deliver a peak output current of 300 mA and is specifically designed to drive TFT panel loads. The gate pulse modulator allows shaping of the TFT gate high voltage to improve image quality. The integrated switches provide the ability to independently control the delay and slope for the gate drive voltage. The ADD8754 is offered in a 24-lead, Pb-free LFCSP package and is specified over the industrial temperature range of −40 to +85°C.

Rev. 0 | Page 2 of 28 TABLE OF CONTENTS

REVISION HISTORY

4/05—Revision 0: Initial Version

Rev. 0 | Page 3 of 28 SPECIFICATIONS STEP-UP SWITCHING REGULATOR SPECIFICATIONS VIN_1 = VIN_2 = SHDN = 5 V , VOUT1 = VDD_1 = VDD_2 = 14 V , TA = 25°C, FREQ = GND, unless otherwise noted. Table 1. Parameter Symbol Conditions Min Typ Max Unit SUPPLY Input Voltage Range VIN 3.0 5.5 V OUTPUT1 Output Voltage Range VOUT1 20 V Load Regulation 10 mA ≤ ILOAD ≤ 150 mA, VOUT1 = 10 V 200 μV/mA Line Regulation ILOAD = 350 mA, 4.5 V ≤ VIN_1 ≤ 5.5 V mV Load Regulation 10 mA ≤ ILOAD ≤ 150 mA, VOUT1 = 10 V 200 μV/mA Line Regulation ILOAD = 150 mA, 3.0 V ≤ VIN_1 ≤ 5.5 V mV Overall Regulation Line, load, temperature (−40°C ≤ TA ≤ +85°C) −3 +3 % REFERENCE Feedback Voltage VFB 1.200 1.211 1.220 V ERROR AMPLIFIER Transconductance GMEA 100 μA/V Gain AV 1000 V/V Input Bias Current IB 225 nA SWITCH On Resistance RDS (ON) 170 mΩ Leakage Current ILKG VLX = 14 V, SHDN = GND 0.5 μA Peak Current Limit ICL 2.6 A OSCILLATOR Oscillator Frequency FOSC FREQ = GND 650 kHz FREQ = VIN_1 1.2 MHz Maximum Duty Cycle DMAX VFB = 1 V 90 95 % SOFT START Peak Current SS = GND 2.5 μA 1 Refer to the Figure 23.

Rev. 0 | Page 4 of 28 LDO REGULATOR SPECIFICATIONS VIN_1 = VIN_2 = SHDN = 5 V , ADJ = LDO_OUT,1 CLDO = 2.2 μF, TA = 25°C, unless otherwise noted. Table 2. Parameter Symbol Conditions Min Typ Max Unit INPUT Input Voltage Range VIN2 ADJ = LDO_OUT1 3.0 5.5 V ADJ = OPEN3 3.35 5.5 V ADJ = GND4 3.8 5.5 V OUTPUT Output Voltage LDO_OUT ILDO = 1 mA, ADJ = GND 3.31 V ILDO = 350 mA, ADJ = GND 3.29 V ILDO = 1 mA, ADJ = OPEN 2.86 V ILDO = 350 mA, ADJ = OPEN 2.84 V ILDO = 1 mA, ADJ = LDO_OUT 2.51 V ILDO = 350 mA, ADJ = LDO_OUT 2.49 V Voltage Accuracy ILDO = 1 mA to 350 mA, −40°C ≤ TA ≤ +85°C −3 +3 % Line Regulation ILDO = 1 mA 3 mV/V Load Regulation ILDO = 1 mA to 350 mA 20 mV Dropout Voltage VDROP LDO_OUT = 98% of LDO_OUT(NOM), ILDO = 350 mA 300 500 mV Current Limit ILDPK 350 mA 1 Sets LDO_OUT(NOM) to 2.5 V. 2 VIN = VIN_1 = VIN_2. 3 Sets LDO_OUT(NOM) to 2.85 V. 4 Sets LDO_OUT(NOM) to 3.3 V.

Rev. 0 | Page 5 of 28 VCOM AMPLIFIER SPECIFICATIONS VIN_1 = VIN_2 = SHDN = 5 V , VDD_2 = 14 V , POS = 4.0 V , NEG = OUT, TA = 25°C, unless otherwise noted. Table 3. Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage VOS 19 mV Noninverting Input Bias Current IB 50 300 nA Input Voltage Range 2 VDD_2 − 3 V Common-Mode Rejection Ratio CMRR VCM = 2 V to (VDD_2 − 3) V 60 dB OUTPUT CHARACTERISTICS Output Voltage Swing VOH IOUT (source) = 50 mA VDD_2 − 0.5 V V OL IOUT (sink) = 50 mA 50 mV Output Current1 IOUT ±300 mA POWER SUPPLY Supply Voltage VDD_2 8 18 V Power Supply Rejection Ratio PSRR 7.5 V ≤ VDD_2 ≤ 18.5 V 65 70 dB Supply Current ISY No load, POS = VDD_2 /2 2 mA DYNAMIC PERFORMANCE Slew Rate2 SR RL = 10 kΩ, CL = 10 pF 105 V/μs Gain Bandwidth GBW −3 dB, RL = 10 kΩ, CL = 10 pF 1.95 MHz 1 Not short-circuit protected. 2 Slew rate is the average of the rising and the falling slew rates.

Rev. 0 | Page 6 of 28 GATE PULSE MODULATOR SPECIFICATIONS VIN_1 = VIN_2 = SHDN = 5 V , VGH = 20 V , VDD_1 = 14 V , TA = 25°C, unless otherwise noted. Table 4. Parameter Symbol Condition Min Typ Max Unit INPUT CHARACTERISTICS VGH Voltage VGH 7 30 V VGH Input Current IVGH VFLK = GND, VDPM = LDO_OUT 95 μA VDD_1 Voltage 7 VGH V VDD_1 Input Current IVDD_1 VFLK = VDPM = LDO_OUT 0.02 μA CONTROL INPUT CHARACTERISTICS VFLK Voltage Low VLOWFLK 0.8 V VFLK Voltage High VHIGHFLK 2.2 V VFLK Input Current IFLK 0.9 ≤ VFLK ≤ LDO_OUT −1 +1 μA VDPM Voltage Low VLOWDPM 0.8 V VDPM Voltage High VHIGHDPM 2.2 V VDPM Input Current IVDPM 0.9 ≤ VDPM ≤ LDO_OUT −1 +1 μA SWITCHING CHARACTERISTICS VGH to VGH_M On Resistance RVGH VDPM = VFLK = LDO_OUT 60 Ω VGH_M Discharge Current1 IVGH_M VFLK < 0.8 V, RE = 33 kΩ 8.0 mA DELAY CHARACTERISTICS Delay Time2 TDELAY CE = 470 pF, RE = 33 kΩ 1.88 μs 1 Discharge current = 302.5/(RE + 5000). 2 Delay time = CE × 4200. GENERAL SPECIFICATIONS VIN_1 = VIN_2 = SHDN = 5 V , TA = 25°C, unless otherwise noted. Table 5. Parameter Symbol Conditions Min Typ Max Unit SHUTDOWN Input Voltage Low VIL 0.8 V Input Voltage High VIH 2.2 V Shutdown Pin Input Current GND ≤ SHDN ≤ 5.5 V −1 +1 μA Total Ground Current SHDN = GND 2.0 μA Total VIN Current (IVIN_1 + IVIN_2) SHDN = GND −1 +1 μA UNDERVOLTAGE LOCKOUT UVLO Rising Threshold VUVLOR VIN_1 rising 2.8 V UVLO Falling Threshold VUVLOF VIN_1 falling 2.6 V QUIESCENT CURRENT Step-Up Regulator in Nonswitching State IQ 300 500 μA Step-Up Regulator in Switching State IQSW 2 3 mA

Rev. 0 | Page 7 of 28 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 6. Parameter Symbol Rating Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RE, CE, FB, SHDN , VIN_2, FREQ, COMP, SS, VIN_1, LDO_OUT, ADJ, VDPM, VFLK to GND, PGND, and AGND −0.5 V to +6.5 V −0.5 V to +16 V OUT, NEG and POS to GND, PGND, and AGND LX to GND, PGND, and AGND −0.5 V to +22 V VDD_2 and OUT to GND, PGND, and AGND −0.5 V to +18.5 V Absolute maximum ratings apply individually only, not in combination. ±0.5 V Voltage Between GND and AGND, GND and PGND, and AGND and PGND −0.5 V to +32 V VDD_1, VGH, and VGH_M to GND, PGND, and AGND ±5 V Differential Voltage Between POS and NEG Package Power Dissipation PD (TJ max − TA)/θJA Thermal Resistance θJA 38°C/W Maximum Junction Temperature TJ max 125°C Operating Temperature Range TA −40°C to +85°C Storage Temperature Range TS −65°C to +150°C 250°C Reflow Peak Temperature (20 sec to 40 sec) ESD CAUTION ESD (electrostatic discharge) sensit ive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge wi thout detection. Although this product features proprietary ESD protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Figure 2. Pin Configuration Table 7. Pin Function Descriptions 2 VGH_M Gate Pulse Modulator Output. This pin supplies the gate drive signal. 3 VFLK Gate Pulse Modulator Control Input. GND when this pin is connected to GND. 5 VDD_1 Gate Pulse Modulator Low Voltage Input. 11 ADJ LDO Output Voltage Select. Refer to Table 13 for details. 13 VIN_1 Supply Input. This pin supplies power to the LDO and step-up switching regulator. Typically connected to VIN_2. 14 SS Soft Start. A capacitor must be connected between GND and this pin to set the soft start time. when this pin is connected to GND and at 1.2 MHz when connected to VIN_1. 18 LX Step-Up Switching Regulator Switch Node. mode is to pull this pin to VIN_1. 20 FB Feedback Voltage Sense to Set the Output Voltage of the Step-Up Switching Regulator. 21 PGND Step-Up Switching Regulator Power Ground. 22 CE GPM Time Delay. A capacitor must be connected between GND and this pin to set the delay time. 23 RE GPM Negative Ramp Rate. A resistor must be connected between GND and this pin to set the negative ramp rate. 24 VGH Gate Pulse Modulator High Voltage Input.

2.45 OUTPUT VOLTAGE (V)

2.8 OUTPUT VOLTAGE (V)

Figure 7. LDO Output Voltage vs. Load Current, VIN = 5 V Figure 4. Start-Up Response from Shutdown, CSS = 0 F Figure 8. LDO Power-Up Response from Shutdown Figure 5. Start-Up Response from Shutdown, CSS = 10 F

Rev. 0 | Page 11 of 28 50kΩ 25kΩ 10kΩ 5kΩ 0kΩ 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0

0.5 DELAY TIME (μs)

0 100 200 300 400 500 600 700 CAPACITANCE CE (pF) 05110-0610 T 05110-0591 Ch1 2.00 V A Ch1 12.0 VM 40.0ns Δ: 8.00V @: 5.04V Δ: 102ns @: –83.2ns Rising Slew Rate, VDD_2 = 14 V Figure 15. V Figure 17. GPM Delay Time vs. CE Capacitance COM T 05110-060 Ch1 2.00 V A Ch1 5.16 VM 40.0ns Δ: 8.08V @: 9.08V Δ: 60.8ns @: 1.88μs Falling Slew Rate, VDD_2 = 14 V Figure 16. VCOM

switch-off time. Use inductance in the range of 1 μH to 22 μH. current and lower series resistance for a given physical size. required to maintain stability of the current-mode regulator. Table 9. Inductor Manufacturers

use an ultrafast junction diode. ripple current due to the capacitance is calculated as follows. where VIN_MAX is the maximum input voltage. COUT is the output capacitance. IL is the average inductor current. Table 10. Capacitor Manufacturers Table 11. Schottky Diode Manufacturers allows optimization of the loop dynamics for a given application. FZ(RHP) is the right-half plane zero. divided by the load current.

VFB is the feedback regulation voltage, 1.210 V . VOUT is the regulated output voltage. GMEA is the error amplifier transconductance gain. ZOUT is the impedance of the load and output capacitor. fC is the crossover frequency. RC is the compensation resistor. where CC is the compensation capacitor. Figure 19. Compensation Components Table 12. Recommended External Components for Various Input/Output Voltage Conditions

the best combination of low ESR and small size. Figure 22. Power-Up Sequence Timing Diagram better capacitor is recommended. ADJ as an open circuit, a nominal voltage of 2.85 V is selected. mode, quiescent current is reduced to a typical value of 300 μA. Table 13. LDO Output Voltage Selection

2.5 V LDO_OUT UVLO

2.85 V No connection An undervoltage lockout (UVLO) circuit is included with a

2.8 V and shuts down when VIN_1 falls below 2.6 V .

3.3 V GND

Rev. 0 | Page 18 of 28 POWER DISSIPATION The ADD8754’s maximum power dissipation depends on the thermal resistance from the IC die to the ambient environment and the ambient temperature. The thermal resistance depends on the IC package, PC board copper area, other thermal mass, and airflow. The ADD8754, with the exposed backside pad soldered to a 2-layer PC board with nine 12 mil-diameter thermal vias, can dissipate about 1.5 W into 65°C still air before the die exceeds 125°C. More PC board copper, cooler ambient air, and more airflow increase the dissipation capability, whereas less copper or warmer air decreases the IC’s dissipation capability. The major contributors to the power dissipation are the LDO regulator and the V COM amplifier. Step-Up Converter The largest portions of power dissipation in the step-up converter are the internal MOSFET, the inductor, and the output diode. For a 90% efficiency step-up converter, about 3% to 5% of the power is lost in the internal MOSFET, about 3% to 4% in the inductor, and about 1% in the output diode. The rest of the 1% to 3% is distributed among the input and output capacitors and the PC board traces. For an input power of about 3 W , the power lost in the internal MOSFET is about 90 mW to 150 mW . LDO The power dissipated in the LDO depends on the output current, the output voltage, and the supply voltage: PDLDO = (VIN_1 − LDO_OUT) × ILDO_OUT VCOM Amplifier The power dissipated in the VCOM amplifier depends on the output current, the output voltage, and the supply voltage: PDSOURCE = IOUT (source) × (VDD_2 − VOUT) PDSINK = IOUT (sink) × VOUT where: IOUT (source) is the output current sourced by the VCOM amplifier. I OUT (sink) is the output current that the VCOM amplifier sinks to AGND. In a typical case where the supply voltage is 12 V and the output voltage is 6 V with an output source current of 20 mA, the power dissipated is 120 mW . Thermal Overload Protection Thermal overload protection prevents excessive power dissipation from overheating the ADD8754. When the junction temperature exceeds TJ = 145°C, a thermal sensor immediately activates the fault protection, which shuts down the device, allowing the IC to cool. The device self-starts once the die temperature falls below T J = 105°C. Thermal overload protection protects the controller in the event of fault conditions. For continuous operation, do not exceed the absolute maximum junction temperature rating of TJ = 125°C.

Rev. 0 | Page 19 of 28 LAYOUT GUIDELINES When designing a high frequency, switching, regulated power supply, layout is very important. Using a good layout can solve many problems associated with these types of supplies. Some of the main problems are loss of regulation at high output current and/or large input-to-output voltage differentials, excessive noise on the output and switch waveforms, and instability. Using the following guidelines can help minimize these problems. Make all power (high current) traces as short, direct, and thick as possible. It is good practice on a standard PCB board to make the traces an absolute minimum of 15 mil (0.381 mm) per Ampere. The inductor, output capacitors, and output diode should be as close to each other as possible. This helps reduce the EMI radiated by the power traces that is due to the high switching currents through them. This also reduces lead inductance and resistance, which in turn reduce noise spikes, ringing, and resistive losses that produce voltage errors. The grounds of the IC, input capacitors, output capacitors, and output diode (if applicable), should be connected close together, directly to a ground plane. It is also a good idea to have a ground plane on both sides of the printed circuit board (PCB). This reduces noise by reducing ground-loop errors and absorbing more of the EMI radiated by the inductor. For multilayer boards of more than two layers, a ground plane can be used to separate the power plane (power traces and components) and the signal plane (feedback, compensation, and components) for improved performance. On multilayer boards, the use of vias is required to connect traces and different planes. If a trace needs to conduct a significant amount of current from one plane to the other, it is good practice to use one standard via per 200 mA of current. Arrange the components so that the switching current loops curl in the same direction. Due to the how switching regulators operate, there are two power states: one state when the switch is on, and one when the switch is off. During each state, there is a current loop made by the power components currently conducting. Place the power components so that the current loop is conducting in the same direction during each of the two states. This prevents magnetic field reversal caused by the traces between the two half cycles and reduces radiated EMI. Layout Procedure To achieve high efficiency, good regulation, and stability, a good PCB layout is required. It is recommended that the reference board layout be followed as closely as possible because it is already optimized for high efficiency and low noise. Use the following general guidelines when designing PCBs: 1. Keep CIN close to the IN and GND leads of the ADD8754. 2. Keep the high current path from CIN (through L1) to the SW and PGND leads as short as possible. 3. Keep the high current path from CIN (through L1), D1, and COUT as short as possible. 4. Keep high current traces as short and wide as possible. 5. Keep nodes connected to SW away from sensitive traces such as FB or COMP to prevent coupling of the traces. If these traces need to be run near each other, place a ground trace between the two as a shield. 6. Place the feedback resistors as close as possible to the FB pin to prevent noise pickup. 7. Place the compensation components as close as possible to the COMP pin. 8. Avoid routing noise-sensitive traces near the high current traces and components. 9. Use a thermal pad size that is the same as the dimension of the exposed pad on the bottom of the package. Heat Sinking When using a surface-mount power IC or external power switches, the PCB can often be used as the heat sink. This is done by simply using the copper area of the PCB to transfer heat from the device.

Figure 23. 1.2 MHz Application Circuit for TFT LCD Panel with Charge Pumps for VGH and VGL

Figure 24. 1.2 MHz Application Circuit for TFT LCD Display with Transformer for VGH and VGL

Figure 25. 1.2 MHz Application Circuit for TFT LCD Display with Charge Pumps with Input Power Disconnect Switch

Figure 26. 1.2 MHz Application Circuit for TFT LCD Display with LDO_ALWAYS_ ON

0.60 MAX

2.50 REF

0.80 MAX

0.65 TYP

0.05 MAX

0.02 NOM

0.080.20 REF

0.25 MIN

Figure 28. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

Rev. 0 | Page 26 of 28 NOTES

Rev. 0 | Page 27 of 28 NOTES

Rev. 0 | Page 28 of 28 NOTES ©2005 Analog Devices, Inc. All ri ghts reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D05110–0–4/05(0)