ADD8707 AD | Alldatasheet
Document overview
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Technical content
Rev. A Information furn ished by An alog D evices is believed to be accurate and reliable. However, n o resp onsibility is assume d b y A nalog De vices fo r its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or p atent rights of Analog De vices. Trademarks an d registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
FEATURES
12 precision gamma reference outputs Mask-programmable gamma resistors: 0.2% resolution and 0.1% accuracy Mask programmable voltage regulator: 0.4% accuracy Upper 6 buffers swing to VDD Lower 6 buffers swing to GND Single-supply operation: 7.5 V to 16 V Gamma current drive: 15 mA per channel VCOM peak output current: 250 mA Outputs stable under load conditions 48-lead, Pb-free LFCSP package
APPLICATIONS
The ADD8707 is a 12-channel integrated gamma reference with VCOM for use in LCD TV and monitor panels. The output buffers feature high current drive and low offset voltage to provide an accurate and stable gamma curve. The top six channels swing to VDD and the lower six channels swing to GND. Integrating the gamma setup resistors drastically reduces the external component count while increasing the gamma curve accuracy. To accommodate multiple column drivers and panel architectures, the ADD8707 is mask-programmable to a 0.2% resolution using the on-chip 500 resistor string. An on-board voltage regulator provides a fixed input for the resistor string, isolating the gamma curve from supply ripple. The ADD8707 is specified over the temperature range of –40°C to +105°C and comes in a 48-lead, Pb-free, lead frame chip-scale package. FUNCTIONAL BLOCK DIAGRAM 04712-001 VCOM IN+ VOUT12 GAMMA BUFFERS GND 1.2V + MASK-PROGRAMMABLE REGULATOR RESISTORS MASK- PROGRAMMABLE GAMMA RESISTORS VOUT11VIN11 VOUT10VIN10 VOUT9 VOUT8VIN8 VOUT7VIN7 VOUT6VIN6 VOUT5VIN5 VOUT4 VOUT3VIN3 VOUT2VIN2 VOUT1VIN1 FB VREG OUT VCOM OUTVCOM VCOM IN– 700Ω* 700Ω* 700Ω* 700Ω* 700Ω* 700Ω* 700Ω* 700Ω* 700Ω* *ESD PROTECTION RESISTORS 700Ω* Figure 1. 48-Lead LFCSP
Rev. A | Page 2 of 20 TABLE OF CONTENTS
REVISION HISTORY
10/04—Data Sheet Changed from Rev. 0 to Rev. A 7/04—Revision 0: Initial Version
Rev. A | Page 3 of 20
ELECTRICAL CHARACTERISTICS
VDD = 16 V , TA @ +25oC, unless otherwise noted. Table 1. Parameter Symbol Condition Min Typ Max Unit GAMMA CURVE CHARACTERISTICS Accuracy RACC1 0.1 0.4 % Programming Resolution RRES 500 segments 0.2 % Total Resistor String Value RTOTAL 15 kΩ BUFFER CHARACTERISTICS OUTPUTS Output Voltage Range (Ch12 to Ch7) VOUT IL = 100 µA 1.4 VDD V Output Voltage Range (Ch6 to Ch1) VOUT IL = 100 µA 0 VDD − 1.4 V Output vs. Load (Ch12, Ch11, Ch2, Ch1) ∆VOUT2 IL = 20 mA 15 mV Output vs. Load (Ch10 to Ch3) ∆VOUT2 IL = 5 mA 5 mV INPUTS Offset Voltage VOS 5 15 mV Offset Voltage Drift ∆VOS/∆T −40°C ≤ TA ≤ +105°C 20 µV/°C Input Bias Current IB −40°C ≤ TA ≤ +105°C 0.5 1.5 µA Input Voltage Range (Ch12 to Ch7) VIN 1.4 VDD V Input Voltage Range (Ch6 to Ch1) VIN 0 VDD − 1.4 V VCOM CHARACTERISTICS Offset Voltage VOS 5 15 mV Input Range VIN 1.4 VDD − 1.4 V Peak Output Current IPK 250 mA Continuous Output Current IOUT 50 mA Output vs. Load ∆VCOM2 IL = 30 mA 10 mV BUFFER AND VCOM DYNAMIC PERFORMANCE Slew Rate SR RL = 10 kΩ, CL = 200 pF 4 6 V/µs Bandwidth BW −3dB, RL = 10 kΩ, CL = 200 pF 4.5 MHz Settling Time to 0.1% tS 1V step, RL = 10 kΩ, CL = 200 pF 1.1 µs Phase Margin φo RL = 10 kΩ, CL = 200 pF 55 Degrees Power Supply Rejection Ratio PSRR VDD = 7 V to 17 V, −40°C ≤ TA ≤ +105°C 68 90 dB VOLTAGE REGULATOR Programmable Range VREG OUT 5 VDD − 0.6 V Initial Regulator Accuracy VACC No Load. VREG OUT = 14.4V 0.4 1.5 % Dropout Voltage VDO IL = 100 µA 100 150 mV IL = 5 mA 310 350 mV Line Regulation REGLINE VIN = 8.5 V to 16.5 V, VOUT = 8V 0.01 0.20 %/V Load Regulation REGLOAD IO = 100 µA to 5 mA 0.02 0.10 %/mA Maximum Load Current IO −40°C ≤ TA ≤ +105°C 5 mA Feedback Reference Voltage VREF 1.2 V Feedback Input Bias Current IB FB −40°C ≤ TA ≤ +105°C −150 10 150 nA
Rev. A | Page 4 of 20 Parameter Symbol Condition Min Typ Max Unit SYSTEM ACCURACY 10 Total Error3, 4 VTOTAL ERROR –40°C ≤ TA ≤ +105°C 0.5 3 % POWER SUPPLY Supply Voltage VDD 7.5 16 V Supply Current ISY No load, –40°C ≤ TA ≤ +105°C 8.3 15 mA 1 Gamma curve accuracy includes resistor matching and buffer errors, but excludes the regulator error. 2 ∆VCOM is the shift from the desired output voltage under the specified current load. 3 Total error is defined as the difference between the designed and actual output voltage divided by the actual regulator output voltage or full-scale voltage. 4 Total error includes regulator error, resistor string error, bias current effects, and buffer offset voltage.
Table 3. Thermal Resistance 1 See the Applications Information section. 2 θJA for exposed pad soldered to JEDEC 4-layer board. 3 θJA for exposed pad not soldered down. degradation or loss of functionality.
Figure 2. 48-Lead LFCSP Table 4. Pin Function Descriptions 3 VDD Supply voltage. Normally 16 V. 5 FB Regulator feedback pin. Compares a percentage of the regulator output to the internal 1.2V voltage reference. Internal resistors are used to program the desired regulator output voltage.
8 VIN11
14 VIN7
15 VIN6
16 VIN5
18 VIN3
19 VIN2
20 VIN1
21 VCOM IN- VCOM amplifier inverting input. 22 VCOM IN+ VCOM amplifier non-inverting input. 1 External resistors can be added to modify the internal resistor string to change the gamma voltage. An external resistor calculator is available upon request.
Rev. A | Page 7 of 20 Pin No. Name Description 25 NC 26 NC 27 VCOM OUT VCOM amplifier output. 28 GND Ground. Normally 0 V. 29 VDD Supply voltage. Normally 16 V.
30 VOUT1
31 VOUT2
32 VOUT3
33 VOUT4
Buffer outputs. These buffers can swing to ground. 34 NC 35 NC 36 NC 37 NC
38 VOUT5
39 VOUT6 Buffer outputs. These buffers can swing to ground. 40 GND Ground. Normally 0 V. 41 VDD Supply voltage. Normally 16 V.
42 VOUT7
43 VOUT8
44 VOUT9
45 VOUT10
46 VOUT11
47 VOUT12
Buffer outputs. These buffers can swing to VDD. 48 NC
Rev. A | Page 14 of 20 OPERATING TEMPERATURE RANGE The junction temperature is as follows: TJ = TAMB + θJA × PDIS where: TAMB = ambient temperature specified on the data sheet. θJA = junction-to-ambient thermal resistance, in °C/watt. PDIS = power dissipated in the device, in watts. For the ADD8707, PDIS can be calculated by PDIS = VDD × IDQ + Σ(IOUT X(+) × (VDD − VOUT X)) + Σ(−IOUT X(-) × VOUTX) + (VDD – VREG OUT) × ILOAD where: VDD × IDQ = nominal system power requirements. IOUT X(+) × (VDD − VOUT X) = positive-current amplifier load power dissipation (current comes from VDD). −IOU XT(-) × VOUT X = negative-current amplifier load power dissipation (current goes to GND). (VDD – VREG OUT) × ILOAD = regulator load power dissipation. In this example, TAMB = 95°C. To calculate PDIS, assume the values in Table 6. Table 6. V OUT X (V) IOUT X (mA) P (W) VOUT12 14.400 8.3 0.0133 VOUT11 12.067 7.9 0.0311 VOUT10 10.512 −4.5 0.0473 VOUT9 10.051 −4.2 0.0422 VOUT8 9.878 5.6 0.0343 VOUT7 8.554 −3.3 0.0282 VOUT6 6.134 −6.9 0.0423 VOUT5 4.982 5.7 0.0628 VOUT4 4.694 3.5 0.0396 VOUT3 4.205 9.6 0.113 VOUT2 2.736 9.5 0.126 VOUT1 0.202 −7.2 0.00145 Σ(IOUT X(+) × (VDD − VOUT X)) + Σ(−IOUT X(-) × VOUT X) 0.582 VDD × IDQ = 16 V × 15 mA = 0.240 W . (VDD – VREG OUT) × ILOAD = (16 V – 14.4 V) × 5 mA = 0.008 W . Example 1 Exposed pad soldered down with via θJA = 28.3°C/W: The maximum junction temperature that is guaranteed before the part breaks down is 150°C. is The maximum process limit is 125°C. Because TJ is < 150°C and < 125°C, this example demonstrates a condition where the part should perform within process limits. Example 2 Exposed pad not soldered down θJA = 47.7°C/W: In this example, TJ is < 150°C but > 125°C. Although the part should not exhibit any damage here, the process limits have been exceeded. The part may no longer operate as intended. These examples show that soldering down the exposed pad is important for proper heat dissipation. Under the same power- up and loading conditions, the unsoldered part has a higher temperature than the soldered part. Therefore, it is strongly advised that the exposed pad be soldered down.
Figure 27. 48-Lead LFCSP (CP-48) Land Pattern—Dimensions shown in millimeters
- Gray area represents the board metallization.
- White area represents the solder mask and vias.
- Hatched area is for the heat sink solder paste.
- The thermal pad is electrically active. The solder mask opening should be 0.150 mm larger than the pad size, resulting in
0.075 mm of clearance between the copper pad and solder mask.
Figure 28. Typical Applications Circuit
circuit for this part is shown in Figure 30. To order this version, refer to the Ordering Guide. The model listed is the development version. Figure 29. Block Diagram for ADD8707 Development Version (with No Tap Points)
Figure 30. Typical Applications Circuit for ADD8707 Development Version (with No Tap Points)
Rev. A | Page 19 of 20 TAP POINT AND REGULATOR VOLTAGE REQUEST FORM REGULATOR SECTION—VREG OUT To ensure correct regulator operation VDD must exceed VREG by 600 mV minimum—that is, a VREG = 14.4 V requires a minimum VDD = 15.0 V. Parameter Value (6.9 V – 15.4 V) VREG OUT TAP POINT SECTION Gamma output voltages are calculated using the following formula: 500 OUTREG OUT VTPV ×= A Microsoft® Excel spreadsheet is available which automatically calculates the best tap point based on VREG OUT and the desired output voltages for each gamma output. Output Tap Point VOUT18 VOUT17 VOUT16 VOUT15 VOUT14 VOUT13 VOUT12 VOUT11 VOUT10 VOUT9 VOUT8 VOUT7 VOUT6 VOUT5 VOUT4 VOUT3 VOUT2 VOUT1 CUSTOMER INFORMATION Please return this form to your local sales office.
0.50 BSC
0.20 REF
0.80 MAX
0.05 MAX
0.02 NOM
0.60 MAX
0.60 MAX PIN 1
0.25 MIN
Figure 31. 48-Lead Lead Frame Chip Scale Package [LFCSP] registered tra demarks are the prop erty of their respective owners .