ADD8701 AD | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 8
Technical content
REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved. ADD8701 12-Channel Gamma Buffers with VCOM Buffer PANEL TIMING CONTROLLER TIMING AND CONTROL SCAN DRIVER CONTROL GAMMA REFERENCE VOLTAGES V12 VCOM IN VCOM OUT V1 GND VDD VDD RESISTOR LADDER R 384 SOURCE DRIVER NO. 1 768SCAN DRIVERS TFT COLOR PANEL 1024 /H11547 768 384 SOURCE DRIVER NO. 2 384 SOURCE DRIVER NO. 8 ADD8701 G B Figure 1. Typical SVGA TFT-LCD Application
FEATURES
Single-Supply Operation: 7 V to 16 V Dual-Supply Operation: /H115503.5 V to /H115508 V Supply Current: 13 mA Max Upper/Lower Buffers Swing to V DD/GND Continuous Output Current: 10 mA VCOM Peak Output Current: 250 mA Offset Voltage: 15 mV Max Slew Rate: 6 V/ /H9262s Fast Settling Time with Large C-Load
APPLICATIONS
The ADD8701 is a low cost, 12-channel buffer amplifier and VCOM driver that operates from a single supply. The part is designed for high resolution TFT LCD panels, and is built on an advanced, high voltage, CBCMOS process. The buffers have high slew rate, 10 mA continuous output current, and high capacitive load drive capability. The VCOM buffer has increased drive of 35 mA and can drive large capacitive loads. The ADD8701 offers wide supply range and offset voltages below 15 mV. The ADD8701 is specified over the –40ºC to +85ºC tempera- ture range and is available in a 32-lead lead frame chip scale package (LFCSP). All inputs and outputs incorporate internal ESD protection circuits.
REV. 0–2– ADD8701–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Parameter Symbol Condition Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage V OS 41 5 m V Offset Voltage Drift ∆VOS/∆T –40°C ≤ TA ≤ +85°C 5 µV/°C Input Bias Current I B 0.5 1.1 µA Input Voltage Range –0.5 V DD + 0.5 V Input Impedance Z IN 400 k Ω Input Capacitance C IN 1p F OUTPUT CHARACTERISTICS Output Voltage High (V11, V12) V OUT IL = 100 µA 15.995 V VDD = 16 V, IL = 5 mA 15.85 15.9 V VDD = 7 V, IL = 5 mA 6.75 6.85 V Output Swing (V3 to V10) V OUT IL = 5 mA, VDD = 16 V 14.6 V Output Swing (V3 to V10) V OUT IL = 5 mA, VDD = 7 V 5.6 V Output Voltage Low (V1, V2) V OUT IL = 100 µA 5 mV VDD = 16 V, IL = 5 mA 85 150 mV –40°C ≤ TA ≤ +85°C 250 mV VDD = 7 V, IL = 5 mA 140 300 mV –40°C ≤ TA ≤ +85°C 400 mV Continuous Output Current I OUT 10 mA Peak Output Current I PK VDD = 16 V 150 mA VCOM CHARACTERISTICS Continuous Output Current I OUT 35 mA Peak Output Current I PK VDD = 16 V 250 mA TRANSFER CHARACTERISTICS Gain A VCL RL = 2 kΩ 0.995 0.9985 1.005 V/V –40°C ≤ TA ≤ +85°C 0.995 0.9980 1.005 V/V Gain Linearity NL R L = 10 kΩ VO = 0.5 to (VDD – 0.5 V) 0.01 % SUPPLY CHARACTERISTICS Supply Voltage V DD 71 6 V Power Supply Rejection Ratio PSRR V DD = 6 V to 17 V –40°C ≤ TA ≤ +85°C 70 90 dB Supply Current I SYS No Load 10 13 mA –40°C ≤ TA ≤ +85°C 15 mA DYNAMIC PERFORMANCE Slew Rate SR R L = 10 kΩ, CL = 200 pF 4 6 V/µs Bandwidth BW –3 dB, R L = 10 kΩ, CL = 200 pF 4.5 MHz Settling Time to 0.1% (Buffers) t S 1 V, RL = 10 kΩ, CL = 200 pF 1.1 µs Settling Time to 0.1% (VCOM) t S 1 V, RL = 10 kΩ, CL = 200 pF 0.7 µs Phase Margin fo R L = 10 kΩ, CL = 200 pF 55 Degrees Channel Separation 75 dB NOISE PERFORMANCE Voltage Noise Density e n f = 1 kHz 26 nV/ √Hz en f = 10 kHz 25 nV/ √Hz Current Noise Density i n f = 10 kHz 0.8 pA/ √Hz Specifications subject to change without notice. (7 V ≤ VDD ≤ 16 V, TA = 25°C, unless otherwise specified.)
REV. 0 ADD8701 –3– CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADD8701 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. PIN CONFIGURATION PIN 1 INDICATOR TOP VIEW
24 GND
23 VDD
32 VCOM OUT
V DD 15 GND 16 IN11 4 IN10 5 IN9 6 IN8 7 IN7 8
31 GND
30 V12
29 V11
28 V10
ABSOLUTE MAXIMUM RATINGS * *Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ORDERING GUIDE Model Temperature Package Package Range Description Option ADD8701ACP –40°C to +85°C 32-Lead LFCSP CP-32 Package Type /H9258JA 1 /H9023JB
2 Unit
32-Lead LFCSP (CP) 35 13 °C/W NOTES 1θJA is specified for worst-case conditions, i.e., θJA is specified for device soldered in circuit board for surface-mount packages. 2ψJB is applied for calculating the junction temperature by reference to the board temperature. PIN FUNCTION DESCRIPTION Pin No. Mnemonic Description 1, 15, 23 V DD Power (+)
2 VCOM IN VCOM Buffer Input
3–14 IN12–IN1 Gamma Buffer Inputs 16, 24, 31 GND Power (–) 17–22, 25–30 V1–V12 Gamma Buffer Outputs
32 VCOM OUT VCOM Buffer Output
REV. 0–4– ADD8701–Typical Performance Characteristics INPUT OFFSET VOL T AGE – mV NUMBER OF AMPLIFIERS 1,400 600 –7 9 –5 –3 –1 1 3 5 1,200 1,000 400 200 800 TA = 25/H11543C 7V < VDD < 16V TPC 1. Input Offset Voltage Distribution COMMON-MODE VOL T AGE – V –8 –6 8 –4 –2 0 4 6 2 OFFSET VOL T AGE – mV –10 VDD = /H115508V BUFFERS 10 TO 12 TPC 4. Offset Voltage vs. Common-Mode Voltage TEMPERATURE – /H11543C INPUT BIAS CURRENT – nA 350 –40 85 25 200 150 100 300 250 BUFFERS 10 TO 12 VDD = 16V VDD = 7V TPC 7. Input Bias Current vs. Temperature 4051 0 1 52 02 53 03 5 TCVOS – /H9262V//H11543C NUMBER OF AMPLIFIERS 7,000 6,000 4,000 3,000 2,000 1,000 5,000 7V < VDD < 16V TPC 2. TCVOS Distribution COMMON-MODE VOL T AGE – V –8 –6 8 –4 –2 0 4 6 2 OFFSET VOL T AGE – mV –10 VDD = /H115508V VCOM, BUFFERS 1 TO 9 TPC 5. Offset Voltage vs. Common-Mode Voltage LOAD CURRENT – mA ∆OUTPUT VOL T AGE – V 100 0.001 0.01 0.1 100 11 0 0.1 0.01 SOURCE SINK VDD = 16V BUFFERS 1, 2 TPC 8. Output Voltage to Supply Rail vs. Load Current TEMPERATURE – /H11543C INPUT OFFSET VOL T AGE – mV –20 –40 85 25 –15 –10 7V < VDD < 16V BUFFER 1 BUFFER 12 VCOM TPC 3. Input Offset Voltage vs. Temperature TEMPERATURE – /H11543C INPUT BIAS CURRENT – nA –200 –900 –40 85 25 –500 –600 –800 –700 –300 –400 VCOM AND BUFFERS 1 TO 9 –100 VDD = 16V VDD = 7V TPC 6. Input Bias Current vs. Temperature LOAD CURRENT – mA ∆OUTPUT VOL T AGE – V 100 0.001 0.01 0.1 100 11 0 0.1 0.01 VDD = 16V BUFFERS 3 TO 9 SOURCE SINK TPC 9. Output Voltage to Supply Rail vs. Load Current
REV. 0 ADD8701 –5– LOAD CURRENT – mA ∆OUTPUT VOL T AGE – V 100 0.001 0.01 0.1 100 11 0 0.1 0.01 VDD = 16V BUFFERS 11, 12 SOURCE SINK TPC 11. Output Voltage to Supply Rail vs. Load Current TEMPERATURE – /H11543C SUPPL Y CURRENT – mA –40 85 25 VDD = 7V VDD = 16V TPC 14. Supply Current vs. Temperature FREQUENCY – Hz POWER SUPPL Y REJECTION RA TIO – dB 100 1k 10M 10k 100k 1M –120 –20 –40 –60 –80 –100 PSRR ALL CHANNELS VDD = 8V TA = +25/H11543C TPC 17. Power Supply Rejection Ratio vs. Frequency LOAD CURRENT – mA ∆OUTPUT VOL T AGE – V 0.0001 0.01 0.1 100 11 0 0.1 0.01 0.001 VDD = 16V VCOM SOURCE SINK TPC 12. Output Voltage to Supply Rail vs. Load Current FREQUENCY – Hz GAIN – dB –30 100k 1M 30M 10M –10 –20 VDD = 16V VCOM AND BUFFERS 1 TO 9 10k/H9024 2k/H9024 1k/H9024 560/H9024 150/H9024 TPC 15. Frequency Response vs. Resistive Loading FREQUENCY – Hz GAIN – dB –30 100k 1M 30M 10M –10 –20 VDD = 16V VCOM, BUFFERS 1 TO 9 50pF 1040pF –40 –50 540pF 100pF TPC 18. Frequency Response vs. Capacitive Loading LOAD CURRENT – mA ∆OUTPUT VOL T AGE – V 100 0.001 0.01 0.1 100 11 0 0.1 0.01 VDD = 16V BUFFER 10 SOURCE SINK TPC 10. Output Voltage to Supply Rail vs. Load Current SUPPL Y VOL T AGE – V SUPPL Y CURRENT – mA 04 1 6 81 2 VCM = 1/2 VDD TPC 13. Supply Current vs. Supply Voltage FREQUENCY – Hz GAIN – dB –30 100k 1M 30M 10M –10 –20 VDD = 16V BUFFERS 10 TO 12 10k/H9024 2k/H9024 1k/H9024 560/H9024 150/H9024 TPC 16. Frequency Response vs. Resistive Loading
REV. 0–6– ADD8701 CAP ACITIVE LOAD – pF PHASE SHIFT – Degrees 180 0 200 1,200400 600 800 1,000 160 140 120 100 VCOM CHANNELS 1 AND 2 CHANNELS 3 TO 9 CHANNELS 11 AND 12VDD = 7V RL = 2k/H9024 TPC 20. Input-Output Phase Shift vs. Capacitive Load TEMPERATURE – /H11543C SLEW RA TE – V//H9262s –40 85 25 VDD = 16V RNULL = 33/H9024 CL = 100pF VCOM SLEW RA TE RISING VCOM SLEW RA TE FALLING TPC 23. Slew Rate vs. Temperature SETTLING TIME – ns STEP SIZE – V –12 400 1,400600 800 1,000 1,200 +tS (0.1%) VCOM VDD = 8V RL = 5k/H9024 CL = 100pF RNULL = 33/H9024 TA = 25/H11543C –tS (0.1%) TPC 26. Settling Time vs. Step Size CAP ACITIVE LOAD – pF PHASE SHIFT – Degrees 180 0 200 1,200400 600 800 1,000 160 140 120 100 VCOM CHANNEL 1 CHANNEL 3 CHANNEL 11VDD = 16V RL = 2k/H9024 TPC 21. Input-Output Phase Shift vs. Capacitive Load 7V < VDD < 16V ROUT SERIES = 33/H9024 CLOAD = 0.1/H9262F TIME – 20/H9262s/DIV VOLTAGE – 20mV/DIV TPC 24. Small Signal Transient Response TIME – 40/H9262s/DIV VOLTAGE – 3V/DIV TPC 27. No Phase Reversal FREQUENCY – Hz GAIN – dB –30 100k 1M 30M 10M –10 –20 50pF 1040pF –40 –50 540pF 100pF VDD = 16V BUFFERS 10 TO 12 TPC 19. Frequency Response vs. Capacitive Loading TIME – 2/H9262s/DIV VOLTAGE – 2V/DIV VDD = 16V TPC 22. Large-Signal Transient Response CAP ACITIVE LOAD – pF OVERSHOOT – % 10 100 10k 1k 100 +OS–OS VDD = 8V VIN = 50mV RL = 2k/H9024 TA = 25/H11543C TPC 25. Small-Signal Overshoot vs. Capacitive Load
REV. 0 ADD8701 –7– VOLTAG E NOISE DENSITY – nV/ Hz VDD = 16V BUFFERS 10 TO 12 MARKER SET @ 10kHz MARKER READING = 36.6nV/ Hz FREQUENCY – Hz 05 1 0 15 20 25 –10 TPC 29. Voltage Noise Density vs. Frequency VOLTAG E NOISE DENSITY – nV/ Hz VDD = 16V VCOM AND BUFFERS 1 TO 9 MARKER SET @ 10kHz MARKER READING = 25.7nV/ Hz FREQUENCY – Hz 05 1 0 15 20 25 –10 TPC 28. Voltage Noise Density vs. Frequency LCD Gamma Reference Buffers In high resolution TFT-LCD displays, gamma correction must be performed to correct the nonlinearity in the LCD panel’s transmission characteristics. A typical TFT-LCD panel consisting of 256 grayscale levels takes an 8-bit digital word to select an appropriate gamma reference voltage. An 8-bit source driver may use 12 analog voltages that match the characteristic gamma curve for optimum panel picture quality. The ADD8701 is specifically designed to generate analog reference voltages to meet the gamma characteristics of an LCD panel used by the source driver. The gamma reference buffers offer 10 mA drive capability. The ADD8701 is designed to meet the rail-to-rail capability needed by the application and yet offers a low cost-per-channel solution. The design maximizes the die area by offering channels to swing to the positive and negative rails. It is imperative that the channels swinging close to the supply rail be used for the positive gamma references and that the channels swinging close to GND be used for the negative gamma references. See Figure 2 for an example of the application circuit. LCD VCOM Buffer The output of the VCOM buffer is designed to control the voltage on the back plate of the LCD display. The buffer must be capable of sinking and sourcing capacitive pulse current. The amplifier stability is designed for high load capacitance. A high quality ceramic capacitor is recommended to supply short duration current pulses at the output. The VCOM buffer of the ADD8701 can handle up to 35 mA of continuous output current and can drive up to 1,000 nF of pure capacitive load. Unused Buffers Inputs of any unused buffer should be tied to the ground plane. POSITIVE GAMMA REFERENCES GMAA12 GMAA11 GMAA10 GMAA9 GMAA8 GMAA7 GMAA6 GMAA5 GMAA4 GMAA3 GMAA2 GMAA1 ADD8701 LCD SOURCE DRIVER NEGATIVE GAMMA REFERENCES Figure 2. Application Circuit
REV. 0 C03599–0–4/03(0) –8– ADD8701 32-Lead Lead Frame Chip Scale Package [LFCSP] (CP-32) Dimensions shown in millimeters COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 0.30 0.23 0.18
0.20 REF
0.80 MAX
0.65 NOM
0.05 MAX
0.02 NOM
1.00 0.90 0.80 SEATING PLANE COPLANARITY 0.08 132 1617 BOTTOM VIEW 0.50 0.40 0.30 3.50 REF 0.50 BSC PIN 1 INDICATOR TOP VIEW 5.00 BSC SQ 4.75 BSC SQ SQ 3.25 3.10 2.95 PIN 1 INDICATOR