ADD8502 Integrated LCD Grayscale Generator Data Sheet (REV.0)
Document overview
- Manufacturer or author: Analog Devices
- PDF pages: 16
Technical content
REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a ADD8502 Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002 Integrated LCD Grayscale Generator FUNCTIONAL BLOCK DIAGRAMFEATURES Two Mask Programmable Sets of Five Reference Levels Dual 10-Bit DACs for Flicker Offset and Range Adjustment Integrated V COM Switching Single-Supply Operation: 5.0 V Low Supply Current: 300 /H9262A Global Power Save Mode: 1 /H9262A Max Fast Settling Time for Load Change: 20 /H9262s Stable with 20 nF/100 /H9024 Loads CMOS/TTL Input Levels
APPLICATIONS
The ADD8502 is an integrated, high accuracy, programmable grayscale generator. Two sets of five output reference voltages are mask programmed to 0.2% resolution. The outputs switch between the two sets of five levels. The reference levels are selected from a 512 tap resistor network using a via mask. ADD8502 includes two serially addressable, 10-bit digital-to- analog converters (DACs) and five fast, low current buffers. The dual DACs set the endpoint voltages applied to the resistor network to adjust for flicker and range. The two power save modes can reduce the total current to less than 1 µA and feature fast recovery time from Shutdown/Sleep Mode. The ADD8502 accepts CMOS or TTL inputs for all controls, including the common drive circuit levels. ADD8502 operates over the industrial temperature range from –40°C to +85°C and is available in a space-saving 24-lead 4 mm /H11003 4 mm frame chip scale package. REV2 VDD GND COM VP0R R R VN4 POWER SAVE LOGIC VREF+ VREF– VDD CS-LD DIN GS1 GS2 SCK PSK CV4CMREV1COM_M VP4 R R VN0 R DIGIT AL CORE VCOM LOGIC MUX R VP4 VN4 VP0 VN0 INTERFACE LOGIC 10-BIT DAC A VREF+ VREF– VDD/2 10-BIT DAC B VDD/2 A0 VDD VL
Figure 1. Slew Rate Diagram
512 Resistor String
1Swing error is a comparison of measured V OUT step versus theoretical V OUT step. Theoretical values can be found on the Mask Tap Point Option sheet. 2Mean error is measured V OUT mean versus theoretical V OUT mean (see Figure 3 ). 3Mean errors between two adjacent channels versus theoretical (see Figure 3 ). 4Mean errors between V0 and V4 versus theoretical (see Figure 3 ). 5Slew rate and settling time are measured between the output resistor and the capacitor (see Figure 1) . Specifications subject to change without notice.
REV. 0 ADD8502 –4– ABSOLUTE MAXIMUM RATINGS * Lead Temperature Range (Soldering, 10 sec) *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Package Type /H9258JA 1 /H9023JB
2 Unit
24-Lead LFCSP (ACP) 34.8 13 °C/W NOTES 1θJA is specified for worst-case conditions, i.e., θJA is specified for device soldered in circuit board for surface-mount packages. 2ψJB is applied for calculating the junction temperature by reference to the board temperature. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADD8502 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE ORDERING GUIDE Temperature Package Package Model Range Description Option ADD8502ACP –40 °C to +85°C2 4-Lead LFCSP CP-24 Available in 7 ” reel only.
REV. 0 ADD8502 –5– PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Name I/O Description 1V L Logic Select Pin I Logic Supply Voltage. Connect to supply used for system logic. Can accept 2.7 V to VDD. 2D IN Serial Data Input I When CS is LOW, the input on this pin is shifted into the internal shift register on the rising edge of SCK. 3 SCK Serial Clock I Accepts up to 10 MHz input. The rising edge on this clock will shift the data on DIN Pin into the internal shift registers.
4 CS-LD Load I When CS-LD is LOW, SCK is enabled for shifting data on the D IN input into the
internal shift register on the rising edge of SCK. Data is loaded MSB first. 5C ML ogic Control 2 I When CM is LOW, COM will output the voltage level input on COM_M. for VCOM When CM is HIGH, COM levels will be determined by the input on REV1. 6 CV4 Logic Control V4 I If CV4 is HIGH, V4 output is the output of the op amp A4. If CV4 is LOW, V4 is connected to COM and op amp A4 is shut down. Refer to Table II.
7 REV1 Logic Control 1 I With CM HIGH, a HIGH on REV1 will cause COM to output the voltage level
for VCOM input at VDD. A LOW on REV1 will cause COM to output the voltage level input at GND. 8N CN o Connect Unused Pin 9N CN o Connect Unused Pin 10 COM Common Output O If CM is LOW, COM will output the voltage input at COM_M. If CM is HIGH, COM will output the voltage input at V DD when REV1 is HIGH and will output the voltage input at GND when REV1 is LOW. Refer to Table II. 11 COM_M Common System I COM_M is a system voltage reference input between 2.5 V and 3.5 V. This may VREF be the system 3.3 V supply.
12 NC No Connect Unused Pin
13 GND Ground I Ground. Nominally 0 V. 14 V4 Output O Buffers are rail-to-rail buffers that can drive high capacitive loads (>16.5 nF). When PSK is LOW, these outputs will be Hi-Z. 15 V3 Output O Buffers are rail-to-rail buffers that can drive high capacitive loads (>16.5 nF). When PSK is LOW or GS1 and GS2 = HIGH, these outputs will be Hi-Z. 16 V2 Output O Buffers are rail-to-rail buffers that can drive high capacitive loads (>16.5 nF). When PSK is LOW or GS1 and GS2 = HIGH, these outputs will be Hi-Z. 17 V1 Output O Buffers are rail-to-rail buffers that can drive high capacitive loads (>16.5 nF). When PSK is LOW or GS1 and GS2 = HIGH, these outputs will be Hi-Z. 18 V0 Output O Buffers are rail-to-rail buffers that can drive high capacitive loads (>16.5 nF). When PSK is LOW, these outputs will be Hi-Z. 19 V DD Supply I Supply Voltage. Nominally 5 V.
20 NC No Connect Unused Pin
(Not to Scale) VL DIN SCK CS-LD CM CV4 PSK GS1 GS2 REV2 NC VDD REV1 NC NC COM COM_M NC NC = NO CONNECT ADD8502 23 22 21 20 19 789 1 0 1 1 1 2
REV. 0 ADD8502 –6– Pin No. Mnemonic Name I/O Description
21 REV2 Reference Output I When PSK is HIGH and GS1 or GS2 is LOW, then INVERT selects the output
Select levels on V0 to V4. If INVERT is HIGH, outputs V0 to V4 are connected to reference levels VP0 to VP4, respectively. If INVERT is LOW, outputs V0 to V4 are connected to reference levels VN0 to VN4, respectively. When PSK is HIGH and GS1 and GS2 are HIGH, V1–V3 are, Hi-Z state, but V0 and V4 are still connected to reference levels VP0 and VP4 when INVERT is HIGH. Outputs V0 and V4 switch to VN0 and VN4 when REV is LOW.
22 GS2 Sleep Mode I When GS1 and GS2 are HIGH, the middle three output buffers are shut down
Select and V1, V2, and V3 are put into Hi-Z states. Other combinations of GS1 and GS2 leave the outputs of A1 to A3 fully active.
23 GS1 Sleep Mode I When GS1 and GS2 are HIGH, the middle three output buffers are shut down
Select and V1, V2, and V3 are Hi-Z. Other combinations of GS1 and GS2 leave the outputs of A1 to A3 fully active. 24 PSK Global Power I When PSK is pulled LOW, the chip will be put into the full Power-Down Mode. Shutdown The DACs, resistor ladder network preamps, and output buffers will all be shut down, and A0 to A4 will be in Hi-Z states. Recovery from full power-down to normal operation is within 30 µs. All digital inputs accept CMOS or TTL logic levels.
REV. 0 –7– ADD8502 DAC A DAC B CODE – LSB 0 1025128 INTEGRAL NONLINEARITY – %LSB 256 384 512 640 768 896 VDD = 5V TPC 1. DAC Integral Nonlinearity CODE – LSB /H1154650 1024128 DIFFERENTIAL NONLINEARITY – %LSB 256 384 512 640 768 896 /H115461 /H115463 DAC A DAC B VDD = 5V TPC 2. DAC Differential Nonlinearity TEMPERATURE – /H11543C 0.5 /H115460 /H115463.0 /H1154640 OFFSET ERROR – LSB 25 85 /H115461.0 /H115461.5 /H115462.0 /H115462.5 DAC B /H115460.5 VDD = 5V DAC A TPC 3. Offset Error vs. Temperature TEMPERATURE – /H11543C 250 200 /H1154640 SHUTDOWN CURRENT – /H9262A 25 85 100 150 VDD = 5V TPC 4. Shutdown Current vs. Temperature TEMPERATURE – /H11543C 190 175 155 /H1154640 SLEEP SUPPLY CURRENT – /H9262A 25 85 165 160 170 VDD = 5V 180 185 TPC 5. Sleep Supply Current vs. Temperature TEMPERATURE – /H11543C 350 200 /H1154640 SUPPLY CURRENT – /H9262A 25 85 100 150 VDD = 5V 250 300 TPC 6. Supply Current vs. Temperature Typical Performance Characteristics–
REV. 0 ADD8502 –8– VDD – V 350 300 100 27 3 SYSTEM SUPPL Y CURRENT – /H9262A 45 6 250 200 150 TPC 7. System Supply Current at Full Power VDD –V 400 200 2.0 7.02.5 SYSTEM SUPPL Y CURRENT – nA 350 300 100 250 150 TPC 8. System Supply Current at Shutdown TEMPERATURE – /H11543C /H1154640 SHUTDOWN RECOVERY TIME – /H9262s 25 85 VDD = 5V TPC 9. Shutdown Recovery Time vs. Temperature TEMPERATURE – /H11543C 10.0 7.0 /H1154640 SLEEP RECOVERY TIME – /H9262s 25 85 9.0 8.0 9.5 VDD = 5V 7.5 8.5 TPC 10. Sleep Recovery Time vs. Temperature TEMPERATURE – /H11543C /H115462 /H1154640 LEAKAGE – nA 25 85 VDD = 5V TPC 11. Output Leakage TIME – 10/H9262s/DIV 00 0 VOLTAGE – 2V/DIV 00000000 REV2 VDD = 5V TPC 12. V0 Output Swing Response to REV2
REV. 0 –9– ADD8502 TEMPERATURE – /H11543C /H1154640 RON – /H9024 25 85 VDD = 5V TPC 13. V COM Switch-On-Resistance vs. Temperature OUTPUT VOL T AGE – mV 800 –23 22 –18 FREQUNECY –13 –8 –3 2 7 12 17 700 400 300 200 100 600 500 TPC 14. V OUT Error Distribution TEMPERATURE – /H11543C 1.5 –2.5 /H1154640 SWING ERROR – mV 25 85 –0.5 –1.5 0.5 2.0 –2.0 –1.0 1.0 TPC 15. Swing Error vs. Temperature OUTPUT VOL T AGE MEAN ERROR 400 150 –15 15–13 FREQUENCY –9 –5 –3 –1 13579 1 1 1 3 350 200 100 300 250 –11 –7 TPC 16. V OUT Swing Mean vs. Distribution TEMPERATURE – /H11543C 1.5 /H1154640 MEAN ERROR BETWEEN ADJACENT CHANNEL – mV25 85 –0.5 0.5 2.0 –1.0 1.0 VP3–VP4 VP0–VP1 VP2–VP3 VP1–VP2 TPC 17. Mean Error between Adjacent Channel vs. Temperature TEMPERATURE – /H11543C 0.6 /H115461.4 /H1154640 MEAN ERROR CHANNEL-TO-CHANNEL – mV 25 85 0.4 /H115461.0 /H115460.8 /H115460.6 /H115460.4 /H115460.2 VN2–VN3 VN3–VN4 VN0–VN1 VN1–VN2 0.2 /H115461.2 TPC 18. Mean Error between Adjacent Channel vs. Temperature
REV. 0 ADD8502 –10– TEMPERATURE – /H11543C 2.0 /H115462.5 /H1154640 MEAN ERROR V0–V4 – mV 25 85 1.5 /H115461.5 /H115460.5 0.5 VP0–VP4 VN0–VN4 1.0 /H115462.0 /H115461.0 TPC 19. Mean Error between V0 and V4 vs. Temperature TIME – 500mV/DIV 00 0 VOLTAGE – 500mV/DIV 00000000 VTH LOW VTH HIGH VL = 2.5V TPC 20. REV1 Hysteresis TEMPERATURE – /H11543C 1.40 1.00 /H1154640 SLEW RATE – V//H9262s 25 85 1.30 1.05 1.10 1.15 1.20 1.25 SLEW RATE RISING SLEW RATE FALLING 1.35 VDD = 5V TPC 21. Slew Rate vs. Temperature TEMPERATURE – /H11543C /H1154640 TIME – /H9262s 45 125 RISING EDGE FALLING EDGE VDD = 5V TPC 22. Settling Time at V OUT vs. Temperature OUTPUT CURRENT – mA 08 0 20 OUTPUT VOL T AGE – V 40 60 SOURCE SINK TPC 23. Output Current Source and Sink
- Digital-to-analog transfer function for DAC A. An output can
- Digital-to-analog transfer function for DAC B. An output can
that are loaded to the DAC Register from 0 to 1023.
- Using any programmed tap point from the 512 resistor string,
Figure 4. Input Register Contents puts. The actual will vary with load, process, and architecture. ters and the operation mode is dependent upon the control bits. that is transferred to the DAC register on the rising edge of CS-LD. th rising edge, this acts as an interrupt to the write sequence. The shift register is reset and the write sequence is seen as invalid.
REV. 0 ADD8502 –12– Table II. DAC Control Function Control Code Input Register DAC Register Power-Down Status C3 C2 C1 C0 Status Status (Sleep/Wake) Comments 0 000 No Change No Update No Change No operation; power-down status unchanged (part stays in Wake or Sleep Mode). 0 001 Load DAC A No Update No C hange Load input Register A with data. DAC outputs unchanged. Power-down status unchanged. 0 010 Load DAC B No Update No Change Load input Register B with data. DAC outputs unchanged. Power-down status unchanged. 0 011 N o t Used 0 100 N o t Used 0 101 N o t Used 0 110 N o t Used 0 111 N o t Used 1 000 No Change Update Outputs Wake Load both DAC registers with existing contents of input registers. Update DAC outputs. Part wakes up. 1 001 Load DAC A Update Outputs Wake Load input Register A. Load DAC registers with new contents of input register A and existing contents of Register B. Update DAC outputs. Part wakes up. 1 010 Load DAC B Update Outputs Wake Load input Register B. Load DAC registers with new contents of input Register B and existing contents of Register A. Update DAC outputs. Part wakes up. 1 011 N o t Used 1 100 N o t Used 1 101 No Change No Update Wake Part wakes up. Input and DAC registers unchanged. DAC outputs reflect existing contents of DAC registers. 1 110 No Change No Update Sleep Power down the IC, put in into Sleep Mode. 1 111 Load DACs Update Wake Load both input registers. Load both DAC A, B with Same Outputs registers with new contents of input registers. 10-Bit Code Update DAC outputs. Part wakes up. Modes of Operation The ADD8502 has various modes of operation, such as updating both DACs simultaneously or changing the power-down status (Sleep/Wake). These are selected by writing the appropriate 4-bit control code (C0–C3). The details for each mode are summarized in Table II. Low Power Serial Interface To reduce the power consumption of the device ever further, the interface only powers up fully when the device is being written to. As soon as the 16-bit control word has been written to the part, the SCK and D IN input buffers are powered down. They only power up again following a falling edge of CS-LD. Double-Buffered Interface The ADD8502 has double-buffered interfaces consisting of two banks of registers: input and DAC. The input register is con- nected directly to the input shift register, and the digital code is transferred to the relevant input register on completion of a valid write sequence. The DAC register contains the digital code used by the resistor string. Access to the DAC register is controlled by the control codes, C0 to C3. The user can update both DACs simultaneously as well as individually. It depends on the selected control codes to update individual output or both outputs simultaneously. Initial Power-Up Condition The ADD8502 has preset DAC conditions when its initially powered on. The DACs are loaded with 1110 1011 11 for the upper DAC and 0000 1010 00 for the lower DAC. The part is powered up in a normal operation mode (Wake Status). Power-Down Modes The ADD8502 has two shutdown modes. One mode is to fully shut down the device using PSK or the digital serial control code, and the other mode is to shut down V1 to V3 buffers using GS1 and GS2. See Table III for the priority of the shutdown control functions.
REV. 0 ADD8502 –13– The ADD8502 will have a quiescent current less than 1 µA when it is fully shut down and all output buffers are switched to a high impedance state. The only active circuitries are the digital logics and the latches for the serial control. When the device is brought back from Sleep Mode to normal operation, it will use the last serial word to update the DACs or a new control code or data if any was loaded when the part was in Sleep Mode; i.e., the contents of the input register, DAC register, and power-down status shown in Table II is retained as long as V DD and VL are on. The second power save mode (mid 3 buffers are shut down) is using GS1 and GS2. In a condition where both GS1 and GS2 logics are HIGH, the output buffers (V1, V2, and V3) are shut down and switched into a high impedance state. Table III. Shutdown Control Function Serial Operation PSK Control GS1 GS2 Mode H Wake L L Normal Operation H Wake L H Normal Operation H Wake H L Normal Operation H Wake H H Mid 3 Buffers are Shutdown H Sleep X X Full Shutdown LX XX Full Shutdown X = Don’t Care VCOM Logic VCOM operation is described in Table IV. The V COM logic is always active and its logic inputs are CM, REV1, and CV4. When CM is LOW, COM is connected to COM_M. When CM is HIGH, COM is determined by the logic input of REV1. If REV1 is HIGH, COM is connected to V DD. When REV1 is LOW, COM is connected to GND. CV4 controls the V4 output. If CV4 goes LOW, V4 is connected to COM and A4 is shut down with its output in a Hi-Z state. When CV4 is HIGH, the switch connecting V4 to COM is open and A4 is in normal operation mode. Table IV. VCOM Logic Control Inputs Outputs CM REV1 CV4 V COM V4 LX L COM_M COM LX H COM_M A4 HL L GND COM HH L V DD COM HL H GND A4 HH H V DD A4 X = Don’t Care
Figure 5. CST ESD and Logic Level Translation Scheme
- The ADD8502 uses logic level translators to convert external logic levels to levels suitable for use in the ADD8502 core.
- T he logic level translators are intended to be powered from the same supply voltage as is used to power the external logic driving the ADD8502. DD may be powered down while normal voltages are present on the VL and logic input pins.
- V DD and VL are independent and can be in the range 0 V to 5.5 V.
- N o damage to the digital inputs will occur with applied voltages up to 7 V (see Absolute Maximum Ratings section of data sheet).
- N o current will flow between V DD and VL under normal operating conditions.
- Logic voltages can be present on the logic input pins even if VL is powered down. Inputs are limited by max supply rating of 7 V.
- D igital input pins have ESD protection connected to GND.
- All other input and output pins have ESD protection connected to GND and V DD.
REV. 0 ADD8502 –15– ADD8502-000 MASK OPTION Table V. Default Power-Up Conditions DAC Setpoints (0 ≤ D ≤ 1023) Decimal Code Voltage Unit Upper DAC 943 4.8022 V Lower DAC 40 0.0977 V Resistor Tap Points (0 ≤ X ≤ 512) Tap Point Voltage Unit VP0 450 4.2325 V VP1 271 2.5878 V VP2 203 1.9630 V VP3 137 1.3565 V VP4 3 0.1252 V VN0 31 0.3825 V VN1 215 2.0732 V VN2 290 2.7624 V VN3 367 3.4699 V VN4 509 4.7747 V Supply voltage = 5 V DAC A DAC B VP0 VP1 VP2 VP3 VP4 VN4 VN3 VN2 VN1 VN0 VOUT A VOUTB Figrue 6. Tap Point References Tap point voltages can be derived from the following equation: Vx V X VVOUTB OUTA OUTB=+ − []512 Where VOUTA and VOUTB can be derived from the transfer func- tions under the Operation Section of the datasheet. The ADD8502 uses a single resistor string consisting of 512 individual elements. Both sets of reference voltages (V P0–VP4, VN0–VN4) are generated from this single string. Two separate resistor networks are shown to demonstrate the tap points, which are changeable by mask option and completely independent of each other.
REV. 0–16– C02944–0–8/02(0) PRINTED IN U.S.A. ADD8502 OUTLINE DIMENSIONS 24-Lead Frame Chip Scale Package [LFCSP] 4x4 mm Body (CP-24) 124 713 BOTTOM VIEW 2.25 1.70 0.75
0.60 MAX
0.50 0.40 0.30 0.30 0.23 0.18 2.50 REF 0.50 BSC 12/H11543 MAX
0.70 MAX
0.65 NOM
0.05 MAX
0.02 NOM
1.00 0.90 0.85 SEA TING PLANE PIN 1 INDICA TOR TOP VIEW 3.75 BSC SQ 4.0 BSC SQ 0.25 MIN PIN 1 INDICA TOR 0.25 REF COMPLIANT TO JEDEC ST ANDARDS MO-220-VGGD-2 0.08