ADD3701

ADD3701 NSC | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 10

Technical content

SS = Z A National a rs

2 Semiconductor

ADD3701 3%/, Digit DVM with Multiplexed 7-Segment Output General Description Features The ADD3701 (MM74C936-1) monolithic DVM circuit is ™ Operates from single 5V supply manufactured using standard complementary MOS (CMOS) _—™ Converts 0 to +3999 counts technology. A pulse modulation analog-to-digital conversion Multiplexed 7-segment technique is used and requires no external precision com- i Drives segments directly Ponents. In addition, this technique allows the use of a refer- —@ No extemal precision components necessary ence voltage that is the same polarity as the input voltage. ™ Accuracy specified over temperature ‘One 5V (TTL) power supply is required. Operating with an Medium speed — 400 ms/conversion isolated supply allows the conversion of positive as well as , negative voltages. The sign of the input voltage is automat eral clock set win Re pe ork oF omen onemaly 4 cally determined and output on the sign pin. If the power ™ “ eand DELO ou y +OFL or isplay read- supply is not isolated, only one polarity of voltage may be ing and OFLO output | converted. ™ Analog inputs in applications shown can withstand ‘The conversion rate is set by an internal oscillator. The fre- £200 Volts quency of the oscillator can be set by an external RC net- % ADD3701 equivalent to MM74C936-1 work or the oscillator can be driven from an external fre- quency source. When using the external RC network, a ‘square wave output is available. It is important to note that great care has been taken to synchronize digit multiplexing Applications with the A/D conversion timing to eliminate noise due to ™ Low cost digital power supply readouts power supply transients. 1 Low cost digital multimeters The ADD3701 has been designed to drive 7-segment multi- = Low cost digital panel meters plexed LED displays directly with the aid of external digit m Eliminate analog multiplexing by using remote A/D con- buffers and segment resistors. Under condition of over- verters. range, the overflow output will go high and the display will m Convert analog transducers (temperature, pressure, dis- read +OFL or —OFL, depending on whether the input volt- placement, etc.) to digital transducers age is positive or negative. In addition to this, the most sig- indicators and displays requiri dout up to 3999 nificant digit is blanked when zero. counts haplays requiring readout up A start conversion input and a conversion complete output are included. Connection Diagram Vecmedt aks, ANALOG Vec—d 2 ni ema ahs, Se’ \\e 25) "GND Se 6 24) ‘DIGIT 1 (MSD) Se 6 Es] DIGIT 2 orto—47 nb—o1irs CONVERSION COMPLETE: ' 003701 n DIGIT 4 (LSD) START CONVERSION —4 9 20h—tour SIGN 0 19) ry VFILTER " 18) VREF Vint-) 2 1) Swi Viw(*) 3 18) SWZ Vee: 16) ANALOG GND TUH/5682-1 Order Number ADD3701CCN See NS Package Number N28B. 3-268

i=] Absolute Maximum Ratings (note 1) =] If Military/Aerospace specified devices are required, Operating Temperature Range (Ta) —40°C to +85°C g Please contact the National Semiconductor Sales Package Dissipation at Ta= 25°C 800mW = Ofee/Distrbutore for availability and specifications. Operating Vog Range asvoeDy foltage at Any Pin except Start Conversion =0.8V to Voo+0.3V vee Maximum Voc o second bad Voltage at Start Conversion -0.8V to +15.0V a sre. (Corrina, 10 seconds) eect + cro ESD Susceptibility (Note 5) TeDV forage Temperature Range ~eerCto +1

Electrical Characteristics

4.75V<Voc<5.25V, —40°C<Ta< +85°C, unless otherwise specified. Parameter [conaitions Tm typ? | Max | unite Ving) —_esical"s"inputvowtage [oom | Tv Vout(o) _ Logical “0” Output Voltage v {All Digital Outputs Except Digital Outputs) Vout) Logical “0” Output Voltage lo=0.7 mA Vv {Digit Outputs) Vourit) Logical 1" Output Voltage | Io=50 MA @ Ty=25°C Veg =8V | Voc-1.6 | Voc-1.3 v {All Segment Outputs) Ig=30 mA @ Ty= 100°C Voo-1.6 | Voo-1.3 v Vouri) Logical “1” Output Voltage | Io = 500 pA (Digit Outputs) Voc—0.4 v (All Digital Outputs Except lo =360 nA (Conv. Complete, Segment Outputs) +/—,OFLO Outputs) Isource Output Source Current Vout=1.0V mA (Digital Outputs) nay Logical “1” Input Current Vin= 15V 1.0 pA (Start Conversion) lin(oy Logical “0” Input Current Vin=0V pA (Start Conversion) loc ___ Supply Gurent SegmentsandOigisOpen | | os | 10 | ma fosc__Ossillator Frequency a fy Clock Frequency a te Conversion Rate Po rtzei026 [| conv. ree 3 toianc _InterDigitBlankingtime [Tarzan || secon ‘scpw __StartGonvorsionPusewath | | a0 | oc [ns Note 1: Absolute Maximum Riatings indicate fimits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions. Note 2: All typicals given for T,= 25°C. Note 3: Full scale= 4000 counts; therefore 0.025% of tull scale = 1 count and 0.05% of full scale=2 counts. Note 4: For 2.000 Votts full scale, 1 mV=2 counts, Note 5: Human body model, 100 pF discharged through a 1.5 kf resistor. 3-269

o & | Electrical Characteristics (continued 2 tc=2.5 conversions/second, 0°C<Ta< + 70°C, unless otherwise specified. < Parameter [| conaitions [win typ? [mex [Units Non-Linearity of Output Vin =0—2V Full Scale —0.05 +0.025 £0.05 % full scale Reading Vin= 0-200 mV Full Scale 0.05 +0.025 +0.05 (Note 3) QuantzationEror fT mt 0 courts OtsetEronvw=ov [Tos Ts [a [mv voto Rollover Error Poo 0 courts Analog Input Current Ta=25°C +1 +5 nA (in+, Vin-) Block Diagram ADD3701 3%/,-Digit DVM wort mc “ — pos u — a po * a — START CONV a | om a — seonewsf [> ts 8 — setoot 3 — oe bi — 2 — Do s oS BU = ce eel ws Des oP>o— nen mao o—1 TUT TTT af o-P>o—e outa ao TT TT over ana ——— foe ores rrr | _ eal an * =, = (| | Y ovenrtow erra. vee conv compere var anon Vee _-| ow “vim i: J o va ‘TL/H/5682-2 3-270

OV with a time constant R4C;. When Veg is less than 0.5 V For the ADD3701 N= 4000. FIGURE 1. Analog Loop Schematic Pulse Modulation A/D Converter

SYSTEM DESIGN CONSIDERATIONS a Perhaps the most important thing to consider when design- The most important characteristics of transients on the Voc | ing a system using the ADD3701 is power supply noise on line is the duration of the transient and not its amplitude. the Voc and ground lines. Because a single power supply is Figure 4 shows a DPM system which converts 0 to +3.999 used and currents in the 300 mA range are being switched, counts operating from anon isolated power supply In this good circuit layout techniques cannot be overemphasized. configuration the sign output could be + (logic 1”) or — Great care has been exercised in the design of the (logic ““0”) and it should be ignored. Higher voltages could ADD3701 to minimize these problems but poor printed cir- be converted by placing a fixed divider on the input; lower cuit layout can negate these features. voltages could be converted by placing a fixed divider on Figures 4, 5, and 6 show schematics of DVM systems. An the feedback, as shown in Figure 5. attempt has been made to show, on these schematics, the Figures 5 and 6 show systems operating with an isolated Proper distribution for ground and Vcc. To help isolate digi- supply that will convert positive and negative inputs. 60 Hz {al and analog portions of the circuit, the analog Voc and common mode input becomes a problem in this configura- ground have been separated from the digital Vog_and tion and a transformer with an electrostatic shield between ground. Care must be taken to eliminate high current from Primary and secondary windings is shown. The necessity for flowing in the analog Vcc and ground wires. The most effec- using a shielded transformer depends on the performance tive method of accomplishing this is to use a single ground requirements and the actual application, point and a single Vcc point where all wires are brought 7 . together. In addition to this the conductors must be of suffi- The filter capacitors connected to Veg (pin 14) and Veit " = ie (pin 11) should be tow leakage. In the application examples cient size to prevent significant voltage drops. shown every 1.0 nA of leakage current will cause 0.1 mV To prevent switching noise from causing jitter problems, a error (1.0X10-9A Xx 100 kN=0.1 mV). If the leakage cur- voltage regulator with good high frequency response is nec- rent in both capacitors is exactly the same no error will re- essary. The LM309 and the LM340-5 voltage regulators all sult since the source impedances driving them are matched. function well and are shown in Figures 4, 5, and 6. Adding more fittering than is shown will in general increase the jitter rather than decrease it. 3.273

E—:_—SXXX i $3335333| = ff a ] . vee eb 2 Cee Hn | Pi E re ee PILE ac |i ye oy Bea 3 na Vrer ws FHS ones EB o g od] wn Vim(-) E3 7 Late =H i [eg =) |UL_e x 1 <= eh a I = ee ig /32 4 : i ec) j i i 2 3-274

. 3 SS , P sxaioe ve z fie — HY ne

_ 2 =<=_S=S= = G3! wi B, “Ty 3 8 | o<] Ht owwtt 2 a : g g 3 . t{—4 L : 5

lo OO Oh. | aikeke Ss ee es ee eee All| (= od