ADCMP562BRQ

ADCMP561 AD | Alldatasheet

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Technical content

Dual High Speed PECL Comparators ADCMP561/ADCMP562 Rev. A Information furn ished by An alog D evices is believed to be accurate and reliable. However, n o resp onsibility is assume d b y A nalog De vices fo r its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or p atent rights of Analog De vices. Trademarks an d registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.

FEATURES

Differential PECL compatible outputs 700 ps propagation delay input to output 75 ps propagation delay dispersion Input common-mode range: –2.0 V to +3.0 V Robust input protection Differential latch control Internal latch pull-up resistors Power supply rejection greater than 85 dB 700 ps minimum pulse width

1.5 GHz equivalent input rise time bandwidth

Typical output rise/fall time of 500 ps ESD protection > 4kV HBM, >200V MM Programmable hysteresis

APPLICATIONS

High speed instrumentation Scope and logic analyzer front ends Window comparators High speed line receivers Threshold detection Peak detection High speed triggers Patient diagnostics Disk drive read channel detection Hand-held test instruments Zero-crossing detectors Line receivers and signal restoration Clock drivers FUNCTIONAL BLOCK DIAGRAM 04687-0-001 HYS* *ADCMP562 ONLY NONINVERTING INPUT INVERTING INPUT LATCH ENABLE INPUT Q OUTPUT LATCH ENABLE INPUT Q OUTPUT ADCMP561/ ADCMP562 Figure 1. 04687-0-002 ADCMP561 TOP VIEW (Not to Scale) –INA +INA QA QA VDD VEE LEA LEA –INB +INB QB QB GND VCC LEB LEB 04687-0-003 ADCMP562 TOP VIEW (Not to Scale) –INA QA QA VDD VEE LEA LEA VDD +INA HYSA –INB QB QB GND VCC LEB LEB VDD +INB HYSB Figure 2. ADCMP561 16-Lead QSOP Figure 3. ADCMP562 20-Lead QSOP programmable hysteresis pin is available on the ADCMP562. are fully compatible with PECL 10 K and 10 KH logic families. temperature range (−40°C to +85°C).

Rev. A | Page 2 of 16 TABLE OF CONTENTS

REVISION HISTORY

7/04—Data Sheet Changed from Rev. 0 to Rev. A 4/04—Revision 0: Initial Version

Table 1. Electrical Characteristics

Rev. A | Page 4 of 16 Parameter Symbol Conditions Min Typ Max Unit AC PERFORMANCE (continued) Equivalent Input Rise Time Bandwidth1 BWEQ 0 V to 1 V swing, 2 V/ns 1500 MHz Maximum Toggle Rate >50% output swing 800 MHz Minimum Pulse Width PWMIN ∆tPD < 25 ps 700 ps RMS Random Jitter VOD = 400 mV, 1.3 V/ns, 312 MHz, 50% duty cycle 1.0 ps Unit-to-Unit Propagation Delay Skew 100 ps POWER SUPPLY Positive Supply Current IVCC @ +5.0 V 2 3.2 5 mA Negative Supply Current IVEE @ −5.2 V 10 22 28 mA Logic Supply Current IVDD @ 3.3 V without load 6 9 13 mA Logic Supply Current @ 3.3 V with load 45 60 70 mA Positive Supply Voltage VCC Dual 4.75 5.0 5.25 V Negative Supply Voltage VEE Dual −4.96 −5.2 −5.45 V Logic Supply Voltage VDD Dual 2.5 3.3 5.0 V Power Dissipation PD Dual, without load 130 160 190 mW Power Dissipation Dual, with load 180 220 250 mW DC Power Supply Rejection Ratio—VCC PSRRVCC 85 dB DC Power Supply Rejection Ratio—VEE PSRRVEE 85 dB DC Power Supply Rejection Ratio—VDD PSRRVDD 85 dB HYSTERESIS (ADCMP562 Only) Hysteresis RHYS = 19.5 kΩ 20 mV RHYS = 8.0 kΩ 70 mV 1 Equivalent input rise time bandwidth assumes a first-order input response and is calculated by the following formula: BWEQ = 0.22/√ (trCOMP2 – trIN2), where trIN is the 20/80 input transition time applied to the comparator and trCOMP is the effective transition time as digitized by the comparator input.

Rev. A | Page 5 of 16 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Rating Supply Voltages Positive Supply Voltage (VCC to GND) −0.5 V to +6.0 V Negative Supply Voltage (VEE to GND) −6.0 V to +0.5 V Logic Supply Voltage (VDD to GND) −0.5 V to +6.0 V Ground Voltage Differential −0.5 V to +0.5 V Input Voltages Input Common-Mode Voltage −3.0 V to +4.0 V Differential Input Voltage −7.0 V to +7.0 V Input Voltage, Latch Controls −0.5 V to +5.5 V Output Output Current 30 mA Temperature Operating Temperature, Ambient −40°C to +85°C Operating Temperature, Junction 125°C Storage Temperature Range −65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL CONSIDERATIONS The ADCMP561 QSOP 16-lead package option has a θJA (junction-to-ambient thermal resistance) of 104°C/W in still air. The ADCMP562 QSOP 20-lead package option has a θJA (junction-to-ambient thermal resistance) of 80°C/W in still air. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Figure 4. ADCMP561 16-Lead QSOP Pin Configuration Figure 5. ADCMP562 20-Lead QSOP Pin Configuration Table 3. Pin Function Descriptions 1 VDD Logic Supply Terminal. comparator is in compare mode). See the description of Pin LEA for more information. comparator is in compare mode). See the description of Pin LEA for more information. 3 4 VDD Logic Supply Terminal. output reflects the input state just prior to the comparator’s being placed in the latch mode. output reflects the input state just prior to the comparator’s being placed in the latch mode. 6 7 VEE Negative Supply Terminal. be driven in conjunction with the noninverting A input. A input must be driven in conjunction with the inverting A input. 10 HYSA Programmable Hysteresis Input. 11 HYSB Programmable Hysteresis Input. B input must be driven in conjunction with the inverting B input. be driven in conjunction with the noninverting B input. 11 14 VCC Positive Supply Terminal. driven in conjunction with LEB. If left unconnected, the comparator defaults to compare mode.

Rev. A | Page 7 of 16 Pin No. ADCMP561 ADCMP562 Mnemonic Function 14 17 GND Analog Ground. 15 18 QB One of two complementary outputs for Channel B. QB is logic low if the analog voltage at the noninverting input is greater than the analog voltage at the inverting input (provided the comparator is in compare mode). See the description of PIN LEB for more information. 16 19 QB One of two complementary outputs for Channel B. QB is logic high if the analog voltage at the noninverting input is greater than the analog voltage at the inverting input (provided the comparator is in compare mode). See the description of Pin LEB for more information. 20 VDD Logic Supply Terminal.

Rev. A | Page 11 of 16

APPLICATION INFORMATION

The ADCMP561/ADCMP562 comparators are very high speed devices. Consequently, high speed design techniques must be employed to achieve the best performance. The most critical aspect of any ADCMP561/ADCMP562 design is the use of a low impedance ground plane. A ground plane, as part of a multilayer board, is recommended for proper high speed performance. Using a continuous conductive plane over the surface of the circuit board can create this, allowing breaks in the plane only for necessary signal paths. The ground plane provides a low inductance ground, eliminating any potential differences at different ground points throughout the circuit board caused by ground bounce. A proper ground plane also minimizes the effects of stray capacitance on the circuit board. It is also important to provide bypass capacitors for the power supply in a high speed application. A 1 µF electrolytic bypass capacitor should be placed within 0.5 inches of each power supply pin to ground. These capacitors reduce any potential voltage ripples from the power supply. In addition, a 10 nF ceramic capacitor should be placed as close as possible from the power supply pins on the ADCMP561/ADCMP562 to ground. These capacitors act as a charge reservoir for the device during high frequency switching. The LATCH ENABLE input is active low (latched). If the latching function is not used, the LATCH ENABLE input may be left open or may be attached to VDD (VDD is a PECL logic high). The complementary input, LATCH ENABLE, may be left open or may be tied to VDD − 2.0 V . Leaving the latch inputs unconnected or providing the proper voltages disables the latching function. Occasionally, one of the two comparator stages within the ADCMP561/ADCMP562 is not used. The inputs of the unused comparator should not be allowed to float. The high internal gain may cause the output to oscillate (possibly affecting the comparator that is being used) unless the output is forced into a fixed state. This is easily accomplished by ensuring that the two inputs are at least one diode drop apart, while also appropriately connecting the LATCH ENABLE and LATCH ENABLE inputs as described previously. The best performance is achieved with the use of proper PECL terminations. The open emitter outputs of the ADCMP561/ ADCMP562 are designed to be terminated through 50 Ω resistors to VDD − 2.0 V , or any other equivalent PECL termin- ation. If high speed PECL signals must be routed more than a centimeter, microstrip or stripline techniques may be required to ensure proper transition times and prevent output ringing. CLOCK TIMING RECOVERY Comparators are often used in digital systems to recover clock timing signals. High speed square waves transmitted over a distance, even tens of centimeters, can become distorted due to stray capacitance and inductance. Poor layout or improper termination can also cause reflections on the transmission line, further distorting the signal waveform. A high speed comparator can be used to recover the distorted waveform while maintaining a minimum of delay. OPTIMIZING HIGH SPEED PERFORMANCE As with any high speed comparator amplifier, proper design and layout techniques should be used to ensure optimal perform- ance from the ADCMP561/ADCMP562. The performance limits of high speed circuitry can be a result of stray capaci- tance, improper ground impedance, or other layout issues. Minimizing resistance from source to the input is an important consideration in maximizing the high speed operation of the ADCMP561/ADCMP562. Source resistance in combination with equivalent input capacitance could cause a lagged response at the input, thus delaying the output. The input capacitance of the ADCMP561/ADCMP562, in combination with stray capacitance from an input pin to ground, could result in several picofarads of equivalent capacitance. A combination of 3 kΩ source resistance and 5 pF of input capacitance yields a time constant of 15 ns, which is significantly slower than the 750 ps capability of the ADCMP561/ADCMP562. Source impedances should be significantly less than 100 Ω for best performance. Sockets should be avoided due to stray capacitance and induc- tance. If proper high speed techniques are used, the devices should be free from oscillation when the comparator input signal passes through the switching threshold. COMPARATOR PROPAGATION DELAY DISPERSION The ADCMP561/ADCMP562 have been specifically designed to reduce propagation delay dispersion over an input overdrive range of 100 mV to 1.5 V . Propagation delay overdrive dispersion is the change in propagation delay that results from a change in the degree of overdrive (how far the switching point is exceeded by the input). The overall result is a higher degree of timing accuracy because the ADCMP561/ADCMP562 are far less sensitive to input variations than most comparator designs.

Rev. A | Page 15 of 16 NOTES

Rev. A | Page 16 of 16 NOTES © 2004 Analo g De vices, Inc. All rights reserve d. Tra demarks and registered tra demarks are the prop erty of their respective owners . D04687–0–7/04(A)