ADCMP551

ADCMP551/ADCMP552/ADCMP553 (Rev. B)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 15

Technical content

Single-Supply, High Speed PECL/LVPECL Comparators Data Sheet ADCMP551/ADCMP552/ADCMP553 Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2004–2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

500 ps propagation delay input to output 125 ps overdrive dispersion Differential PECL/LVPECL compatible outputs Differential latch control Internal latch pull-up resistors Power supply rejection greater than 70 dB 700 ps minimum pulse width Equivalent input rise time bandwidth > 750 MHz Typical output rise/fall of 500 ps Programmable hysteresis

APPLICATIONS

High speed instrumentation Scope and logic analyzer front ends Window comparators High speed line receivers Threshold detection Peak detection High speed triggers Patient diagnostics Disk drive read channel detection Hand-held test instruments Zero crossing detectors Line receivers and signal restoration Clock drivers FUNCTIONAL BLOCK DIAGRAM Figure 1. GENERAL DESCRIPTION The ADCMP551/ADCMP552/ADCMP553 are single-supply, high speed comparators fabricated on Analog Devices, Inc., proprietary XFCB process. The devices feature a 500 ps propagation delay with less than 125 ps overdrive dispersion. Overdrive dispersion, a measure of the difference in propagation delay under differing overdrive conditions, is a particularly important characteristic of high speed comparators. A separate programmable hysteresis pin is available on the ADCMP552. A differential input stage permits consistent propagation delay with a common-mode range from −0.2 V to VCCI − 2.0 V . Outputs are complementary digital signals and are fully compatible with PECL and 3.3 V LVPECL logic families. The outputs provide sufficient drive current to directly drive transmission lines terminated in 50 Ω to VCCO − 2 V . A latch input is included and permits tracking, track-and-hold, or sample-and-hold modes of operation. The latch input pins contain internal pull- ups that set the latch in tracking mode when left open. The ADCMP551/ADCMP552/ADCMP553 are specified over the −40°C to +85°C industrial temperature range. The ADCMP551 is available in a 16-lead QSOP package; the ADCMP552 is available in a 20-lead QSOP package; and the ADCMP553 is available in an 8-lead MSOP package. 04722-001 NONINVERTING INPUT INVERTING INPUT LATCH ENABLE INPUT Q OUTPUT LATCH ENABLE INPUT Q OUTPUT ADCMP551/ ADCMP552/ ADCMP553 *ADCMP552 ONLY HYS*

ADCMP551/ADCMP552/ADCMP553 Data Sheet Rev. B | Page 2 of 15 TABLE OF CONTENTS

REVISION HISTORY

3/15—Rev. A to Rev. B Changed ADCMP55x to 6/13—Rev. 0 to Rev. A 10/04—Revision 0: Initial Version

VCCI = 3.3 V , VCCO = 3.3 V , TA = 25°C, unless otherwise noted. Table 1. Electrical Characteristics

ADCMP551/ADCMP552/ADCMP553 Data Sheet Rev. B | Page 4 of 15 Parameter Symbol Conditions Min Typ Max Unit AC PERFORMANCE (continued) Pulse Width Dispersion 700 ps ≤ PW ≤ 10 ns 25 ps Duty Cycle Dispersion 33 MHz, 1 V/ns, VCM = 0.5 V 10 ps Common-Mode Voltage Dispersion 1 V swing, 0.3 V ≤ VCM ≤ 0.8 V 10 ps Equivalent Input Rise Time Bandwidth1 BW EQ 0 V to 1 V swing, 2 V/ns 750 MHz Maximum Toggle Rate >50% output swing 800 MHz Minimum Pulse Width PWMIN ΔtPD < 25 ps 700 ps RMS Random Jitter VOD = 250 mV, 1.3 V/ns,

500 MHz, 50% duty cycle

1.1 ps Unit-to-Unit Propagation Delay Skew 50 ps POWER SUPPLY (ADCMP551/ADCMP552) Input Supply Current IVCCI @ 3.3 V 8 12 17 mA Output Supply Current IVCCO @ 3.3 V without load 3 5 9 mA Output Supply Current @ 3.3 V with load 40 55 70 mA Input Supply Voltage VCCI Dual 3.135 3.3 5.25 V Output Supply Voltage VCCO Dual 3.135 3.3 5.25 V Positive Supply Differential VCCO − VCCI −0.2 +2.3 V Power Dissipation PD Dual, without load 40 55 75 mW Power Dissipation Dual, with load 90 110 130 mW DC Power Supply Rejection Ratio—VCCI PSRR VCCI 75 dB DC Power Supply Rejection Ratio—VCCO PSRR VCCO 85 dB POWER SUPPLY (ADCMP553) Positive Supply Current IVCC @ 3.3 V without load 9 13 mA Positive Supply Current @ 3.3 V with load 35 42 mA Positive Supply Voltage VCC Dual 3.135 3.3 5.25 V Power Dissipation PD Dual, without load 30 42 mW Power Dissipation Dual, with load 60 75 mW DC Power Supply Rejection Ratio—VCC PSRR VCC 70 dB HYSTERESIS (ADCMP552 Only) Programmable Hysteresis 0 40 mV 1 Equivalent input rise time bandwidth assumes a first order input response and is calculated by the following formula: BWEQ = .22/ (trCOMP2 − trIN2), where trIN is the 20/80 input transition time applied to the comparator and trCOMP is the effective transition time as digitized by the comparator input.

Data Sheet ADCMP551/ADCMP552/ADCMP553 Rev. B | Page 5 of 15 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Rating Supply Voltages Input Supply Voltage (VCCI to GND) −0.5 V to +6.0 V Output Supply Voltage (VCCO to GND) −0.5 V to +6.0 V Ground Voltage Differential −0.5 V to +0.5 V Input Voltages Input Common-Mode Voltage −0.5 V to +3.5 V Differential Input Voltage −4.0 V to +4.0 V Input Voltage, Latch Controls −0.5 V to +5.5 V Output Output Current 30 mA Temperature Operating Temperature, Ambient −40°C to +85°C Operating Temperature, Junction 125°C Storage Temperature Range −65°C to +150°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. THERMAL CONSIDERATIONS The ADCMP551 16-lead QSOP package has a θJA (junction-to- ambient thermal resistance) of 104°C/W in still air. The ADCMP552 20-lead QSOP package has a θJA (junction-to- ambient thermal resistance) of 80°C/W in still air. The ADCMP553 8-lead MSOP package has a θ JA (junction-to- ambient thermal resistance) of 130°C/W in still air. ESD CAUTION

Data Sheet ADCMP551/ADCMP552/ADCMP553 Rev. B | Page 7 of 15 Pin No. Mnemonic Description ADCMP551 ADCMP552 ADCMP553 13 16 LEB One of Two Complementary Inputs for Channel B Latch Enable. In compare mode (logic high), the output tracks changes at the input of the comparator. In latch mode (logic low), the output reflects the input state just prior to the comparator being placed into latch mode. LEB must be driven in conjunction with LEB. 15 18 QB One of Two Complementary Outputs for Channel B. QB is logic low if the analog voltage at the noninverting input is greater than the analog voltage at the inverting input (provided the comparator is in the compare mode). See the description of Pin LEB for more information. 16 19 QB One of Two Complementary Outputs for Channel B. QB is logic high if the analog voltage at the noninverting input is greater than the analog voltage at the inverting input (provided the comparator is in the compare mode). See the description of Pin LEB for more information. 7 V CC Positive Supply Terminal.

Data Sheet ADCMP551/ADCMP552/ADCMP553 Rev. B | Page 11 of 15 APPLICATIONS INFORMATION The comparators in the ADCMP551/ADCMP552/ADCMP553 are very high speed devices. Consequently, high speed design techniques must be employed to achieve the best performance. The most critical aspect of any ADCMP551/ADCMP552/ ADCMP553 design is the use of a low impedance ground plane. A ground plane, as part of a multilayer board, is recommended for proper high speed performance. Using a continuous conductive plane over the surface of the circuit board can create this, allowing breaks in the plane only for necessary signal paths. The ground plane provides a low inductance ground, eliminating any potential differences at different ground points throughout the circuit board caused by ground bounce. A proper ground plane also minimizes the effects of stray capacitance on the circuit board. It is also important to provide bypass capacitors for the power supply in a high speed application. A 1 μF electrolytic bypass capacitor should be placed within 0.5 inches of each power supply pin to ground. These capacitors reduce any potential voltage ripples from the power supply. In addition, a 10 nF ceramic capacitor should be placed as close to the power supply pins as possible on the ADCMP551/ADCMP552/ADCMP553 to ground. These capacitors act as a charge reservoir for the device during high frequency switching. The LATCH ENABLE input is active low (latched). If the latching function is not used, the LATCH ENABLE input pins may be left open. The internal pull-ups on the latch pins set the latch to transparent mode. If the latch is to be used, valid PECL voltages are required on the inputs for proper operation. The PECL voltages should be referenced to V CCI. Occasionally, one of the two comparator stages within the ADCMP551/ADCMP552 is not used. The inputs of the unused comparator should not be allowed to float. The high internal gain may cause the output to oscillate (possibly affecting the comparator that is being used) unless the output is forced into a fixed state. This is easily accomplished by ensuring that the two inputs are at least one diode drop apart, while also appropriately connecting the LATCH ENABLE and LATCH ENABLE inputs as described previously. The best performance is achieved with the use of proper PECL terminations. The open-emitter outputs of the ADCMP551/ ADCMP552/ADCMP553 are designed to be terminated through 50 Ω resistors to VCCO − 2.0 V or any other equivalent PECL termination. If high speed PECL signals must be routed more than a centimeter, microstrip or stripline techniques may be required to ensure proper transition times and prevent output ringing. CLOCK TIMING RECOVERY Comparators are often used in digital systems to recover clock timing signals. High speed square waves transmitted over a dist- ance, even tens of centimeters, can become distorted due to stray capacitance and inductance. Poor layout or improper termination can also cause reflections on the transmission line, further dis- torting the signal waveform. A high speed comparator can be used to recover the distorted waveform while maintaining a minimum of delay. OPTIMIZING HIGH SPEED PERFORMANCE As with any high speed comparator amplifier, proper design and layout techniques should be used to ensure optimal performance from the ADCMP551/ADCMP552/ADCMP553. The performance limits of high speed circuitry can easily be a result of stray capacitance, improper ground impedance, or other layout issues. Minimizing resistance from source to the input is an important consideration in maximizing the high speed operation of the ADCMP551/ADCMP552/ADCMP553. Source resistance in combination with equivalent input capacitance can cause a lagged response at the input, thus delaying the output. The input capacitance of the ADCMP551/ADCMP552/ADCMP553, in combination with stray capacitance from an input pin to ground, could result in several picofarads of equivalent capacitance. A combination of 3 kΩ source resistance and 5 pF input capacitance yields a time constant of 15 ns, which is significantly slower than the 500 ps capability of the ADCMP551/ADCMP552/ADCMP553. Source impedances should be significantly less than 100 Ω for best performance. Sockets should be avoided due to stray capacitance and inductance. If proper high speed techniques are used, the ADCMP551/ ADCMP552/ADCMP553 should be free from oscillation when the comparator input signal passes through the switching threshold. COMPARATOR PROPAGATION DELAY DISPERSION The ADCMP551/ADCMP552/ADCMP553 has been specifically designed to reduce propagation delay dispersion over an input overdrive range of 20 mV to 1 V . Propagation delay overdrive dispersion is the change in propagation delay that results from a change in the degree of overdrive (how far the switching point is exceeded by the input). The overall result is a higher degree of timing accuracy since the ADCMP551/ ADCMP552/ADCMP553 is far less sensitive to input variations than most comparator designs.

Figure 27. 8-Lead Mini Small Outline Package [MSOP]

0.65 BSC

1.10 MAX

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