ADCMB-HSFMCEV1Z

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Document overview

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PDF pages: 38

Technical content

Features

JESD204A/B high-speed data interface -J E S D 2 0 4 A c o m p l i a n t - JESD204B device subclass 0 compliant - JESD204B device subclass 2 compatible - Up to 3 JESD204 output lanes running up to 4.375Gbps - Highly configurable JESD204 transmitter
Multiple chip time alignment and deterministic latency support (JESD204B device subclass 2)
SPI programmable debugging features and test patterns
48-pin QFN 7mmx7mm package Key Specifications
SNR at 250/200/125MSPS 70.6/71.2/71.7 dBFS fIN = 30MHz 70.3/70.7/70.9 dBFS fIN = 190MHz
SFDR at 250/200/125MSPS 87/93/95 dBc fIN = 30MHz 84/93/86 dBc fIN = 190MHz
T o t a l P o w e r C o n s u m p t i on: 989mW at 250MSPS

Applications

Radar and satellite antenna array processing
Broadband communications and microwave receivers
High-performance data acquisition
Communications test equipment
High-speed medical imaging

FIGURE 1. SERDES DATA EYE AT 4.375Gbps CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners.

2 FN8302.1 July 6, 2015 Submit Document Feedback Table of Contents

FIGURE 2. BLOCK DIAGRAM

4 FN8302.1 July 6, 2015 Submit Document Feedback Pin Descriptions PIN NUMBER NAME FUNCTION 2, 11, 14, 15, 46 AVDD 1.8V Analog Supply 12, 20, 47, 48 DNC Do Not Connect 3, 6, 7, 10 AVSS Analog Ground 4, 5 BINP, BINN B-Channel Analog Input Positive, Negative 8, 9 AINN, AINP A-Channel Analog Input Negative, Positive

1 VCM Common Mode Output

44 CLKDIV Clock Divider Control

16, 17 CLKP, CLKN Clock Input True, Complement

45 NAPSLP Power Control (Nap, Sleep modes)

13 RESETN Power On Reset (Active Low)

26, 29, 32, 35, 37, 38 OVSS Output Ground 25, 36, 39 OVDD 1.8V Digital Supply 22, 24 OVDD (PLL) 1.8V Analog Supply for SERDES PLL 21, 23 OVSS (PLL) Analog Ground Supply for SERDES PLL 18, 19 SYNCP, SYNCN JESD204 SYNC Input 27, 28 LANE0P, LANE0N SERDES Lane 0 30, 31 LANE1P, LANE1N SERDES Lane 1 33, 34 LANE2P, LANE2N SERDES Lane 2

40 SDO SPI Serial Data Output

41 CSB SPI Chip Select (active low)

42 SCLK SPI Clock

43 SDIO SPI Serial Data Input/Output

PAD - Exposed Paddle. Analog Ground (connect to AVSS)

Ordering Information

(Notes 1, 2) PART MARKING TEMP. RANGE (°C) PACKAGE (RoHS Compliant) PKG. DWG. # ISLA222S25IR1Z ISLA222S25 IR1Z -40 to +85 48 Ld QFN L48.7x7G ISLA222S20IR1Z ISLA222S20 IR1Z -40 to +85 48 Ld QFN L48.7x7G ISLA222S12IR1Z ISLA222S12 IR1Z -40 to +85 48 Ld QFN L48.7x7G ISLA224S25IR48EV1Z FMC Based Evaluation Board (Supports 125/200/250 speed grades), Dual 14-bit Evaluation Board, which can be configured for 12-bit operation; Interfaces with ADCMB-HSFMCEV1Z Motherboard and Other FPGA Vendor FMC Based Evaluation Platforms. ADCMB-HSFMCEV1Z FMC Based Motherboard NOTES: 1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate-e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2. For Moisture Sensitivity Level (MSL), please see device information page for ISLA222S12 , ISLA222S20, ISLA222S25. For more information on MSL please see techbrief TB363.

5 FN8302.1 July 6, 2015 Submit Document Feedback Absolute Maximum Ratings Thermal Information Thermal Resistance (Typical)  JA (°C/W) JC (°C/W) Recommended Operating Conditions CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 3. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 4. For JC, the “case temp” location is the center of the exposed metal pad on the package underside. 5. For solder stencil layout and reflow guidelines, please see Tech Brief. TB389 Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V, TA = -40°C to +85°C (typical specifications at +25°C), AIN = -2dBFS, fSAMPLE = Maximum Conversion Rate (per speed grade). Boldface limits apply across the operating temperature range, -40°C to +85°C. PARAMETER SYMBOL TEST CONDITIONS ISLA222S25 ISLA222S20 ISLA222S12 UNIT MIN (Note 6)T Y P MAX (Note 6) MIN (Note 6)T Y P MAX (Note 6) MIN (Note 6)T Y P MAX (Note 6) DC SPECIFICATIONS Analog Input Full Scale Analog Input Range Input Resistance R IN Differential 600 600 600 Ω Input Capacitance C IN Differential 7.4 7.4 7.4 pF Full Scale Range Temp. Drift AVTC Full Temp 115 58 58 ppm/°C Input Offset Voltage V OS ±1 ±1 ±1 mV Gain Error E G 111 % Common-mode Output Voltage VCM 0.94 0.94 0.94 V Common Mode Input Current (per pin) ICM 6.0 6.0 6.0 µA/MSPS Clock Inputs Inputs Common Mode Voltage 0.9 0.9 0.9 V CLKP, CLKN Swing 1.8 1.8 1.8 V Power Requirements 1.8V Analog Supply Voltage AVDD 1.8 1.8 1.8 V 1.8V Digital Supply Voltage OVDD 1.8 1.8 1.8 V 1.8V Analog Supply Current IAVDD 353 397 324 365 282 316 mA 1.8V Digital Supply Current IOVDD Minimum number of lanes active 195 218 179 200 123 173 mA

6 FN8302.1 July 6, 2015 Submit Document Feedback Power Supply Rejection Ratio (Note 7) PSRR 30MHz 200mV P-P 40 40 40 dB 1MHz 200mVP-P 47 47 47 dB Total Power Dissipation Normal Mode P D 989 1107 910 1017 731 843 mW Nap Mode P D 422 484 391 450 290 398 mW Sleep Mode P D CSB at logic high 6 12 6 12 6 12 mW Nap Mode Wakeup Time Sample Clock Running 555 µ s Sleep Mode Wakeup Time Sample Clock Running 111 m s AC SPECIFICATIONS (Note 8) Differential Nonlinearity DNL f IN = 105MHz No Missing Codes Minimum Conversion Rate (Note 9) fS MIN ISLA222S25, ISLA222S20 (3 Lanes, Efficient Packing) ISLA222S12 (2 Lanes, Simple Packing) 100 100 50 MSPS Maximum Conversion Rate f S MAX Efficient Packing 250 200 125 MSPS Simple Packing MSPS Minimum Serdes Lane Data Rate Independent of Packing Mode 1.0 1.0 1.0 GBPS Maximum Serdes Lane Data Rate (See “ Lane data rate” on page 22.) Independent of Packing Mode Signal-to-noise Ratio (Note 10) SNR f IN = 30MHz 70.6 71.2 71.7 dBFS fIN = 190MHz 70.3 70.7 70.9 dBFS fIN = 363MHz 69.4 69.5 69.3 dBFS fIN = 495MHz 68.6 68.5 68.0 dBFS fIN = 605MHz 67.9 67.6 66.9 dBFS Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V, TA = -40°C to +85°C (typical specifications at +25°C), AIN = -2dBFS, fSAMPLE = Maximum Conversion Rate (per speed grade). Boldface limits apply across the operating temperature range, -40°C to +85°C. (Continued) PARAMETER SYMBOL TEST CONDITIONS ISLA222S25 ISLA222S20 ISLA222S12 UNIT MIN (Note 6)T Y P MAX (Note 6) MIN (Note 6)T Y P MAX (Note 6) MIN (Note 6)T Y P MAX (Note 6)

7 FN8302.1 July 6, 2015 Submit Document Feedback Signal-to-noise and Distortion (Note 10) SINAD f IN = 30MHz 70.5 71.1 71.7 dBFS fIN = 190MHz 70.0 70.5 70.7 dBFS fIN = 363MHz 69.0 68.9 67.8 dBFS fIN = 495MHz 65.4 64.0 61.4 dBFS fIN = 605MHz 59.3 58.0 54.1 dBFS Effective Number of Bits (Note 10) ENOB f IN = 30MHz 11.42 11.52 11.61 Bits fIN = 190MHz 11.34 11.42 11.46 Bits fIN = 363MHz 11.16 11.16 10.97 Bits fIN = 495MHz 10.57 10.34 9.91 Bits fIN = 605MHz 9.56 9.35 8.69 Bits Spurious-free Dynamic Range (Note 10) SFDR f IN = 30MHz 87 93 95 dBc fIN = 105MHz 74 83 76 89 76 87 dBc fIN = 190MHz 84 93 86 dBc fIN = 363MHz 79 88 71 dBc fIN = 495MHz 66 85 61 dBc fIN = 605MHz 58 83 52 dBc Spurious-Free Dynamic Range Excluding H2, H3 (Note 10 SFDRX23 f IN = 30MHz 87 93 98 dBc fIN = 105MHz 89 95 96 dBc fIN = 190MHz 88 93 90 dBc fIN = 363MHz 84 88 85 dBc fIN = 495MHz 85 85 82 dBc fIN = 605MHz 88 83 81 dBc Intermodulation Distortion IMD f IN = 70MHz -84 -82 -81 dBFS fIN = 170MHz -92 -99 -100 dBFS Channel-to-channel Isolation fIN = 10MHz 88 90 100 dB fIN = 124MHz 82 87 86 dB Word Error Rate WER 10 -13 10-13 10-13 Full Power Bandwidth FPBW 675 675 675 MHz NOTES: 6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 7. PSRR is calculated by the equation 20*log10(A/B), where B is the amplitude of a disturber sinusoid on AVDD at the device pins, and A is the amplitude of the spur in the captured data at the frequency of the disturber sinusoid. 8. AC Specifications apply after internal calibration of the ADC is invoked at the given sample rate and temperature. Refer to “Power-on Calibration” on page 15 and “User Initiated Reset” on page 16 for more detail. 9. The DLL Range setting must be changed via SPI for ADC core sa mple rates below 80MSPS. The JESD204 transmitter can support ADC sample rates below 100MSPS, as long as the SERDES lane data rate is greater than or equal to 1Gbps. 10. Minimum specification guaran teed when calibrated at +85°C. Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V, TA = -40°C to +85°C (typical specifications at +25°C), AIN = -2dBFS, fSAMPLE = Maximum Conversion Rate (per speed grade). Boldface limits apply across the operating temperature range, -40°C to +85°C. (Continued) PARAMETER SYMBOL TEST CONDITIONS ISLA222S25 ISLA222S20 ISLA222S12 UNIT MIN (Note 6)T Y P MAX (Note 6) MIN (Note 6)T Y P MAX (Note 6) MIN (Note 6)T Y P MAX (Note 6)

8 FN8302.1 July 6, 2015 Submit Document Feedback Digital Specifications Boldface limits apply across the operating temperature range, -40°C to +85°C. PARAMETER SYMBOL TEST CONDITIONS MIN (Note 6)T Y P MAX (Note 6)U N I T CMOS INPUTS Input Current High (RESETN) I IH VIN = 1.8V 1 10 µA Input Current Low (RESETN) I IL VIN = 0V -25 -12 -7 µA Input Current High (SDIO, SCL, SDA SCLK) I IH VIN = 1.8V 4 12 µA Input Current Low (SDIO, SCL, SDA SCLK) I IL VIN = 0V -600 -400 -300 µA Input Current High (CSB) I IH VIN = 1.8V 40 52 70 µA Input Current Low (CSB) I IL VIN = 0V 1 10 µA Input Voltage High (SDIO, RESETN) V IH 1.17 V Input Voltage Low (SDIO, RESETN) V IL 0.63 V Input Current High (NAPSLP, CLKDIV) (Note 11)I IH 19 25 30 µA Input Current Low (NAPSLP, CLKDIV) I IL --30 -25 -19 µA Input Capacitance C DI 4p F LVDS INPUTS (SYNCP, SYNCN) Input Common Mode Range V ICM 825 1575 mV Input Differential Swing (peak-to-peak, single-ended) V ID 250 450 mV Input Pull-up and Pull-down Resistance R Ipu 100 kΩ CML OUTPUTS Output Common Mode Voltage 1.14 V Switching Specifications Boldface limits apply across the operating temperature range, -40°C to +85°C. PARAMETER SYMBOL TEST CONDITION MIN (Note 6)T Y P MAX (Note 6)U N I T ADC OUTPUT Aperture Delay t A 190 ps RMS Aperture Jitter j A 100 fs Synchronous Clock Divider Reset Recovery Time (Note 12)t RSTRT DLL recovery time after Synchronous Reset 250 µs Latency (ADC Pipeline Delay) L 10 cycles Overvoltage Recovery t OVR 1c y c l e s SERDES PLL Lock Time 250 µs PLL Bandwidth 2.2 MHz Added Random Jitter 5p s RMS Added Deterministic Jitter 7p s P - P Maximum Input Sample Clock Total Jitter to Maintain SERDES BER <1E-12 Integrated from 1kHz to 10MHz offset from carrier 5p s r m s

9 FN8302.1 July 6, 2015 Submit Document Feedback LVDS Inputs SYNCP, SYNCN Setup Time (with Respect to the Positive Edge of CLKP) tRSTS AVDD, OVDD = 1.7V to 1.9V, TA = -40°C to +85°C 400 75 ps SYNCP, SYNCN Hold Time (with respect to the positive edge of CLKP) tRSTH AVDD, OVDD = 1.7V to 1.9V, TA = -40°C to +85°C 150 350 ps CML Outputs Output Rise Time t R 165 ps Output Fall Time t F 145 ps Data Output Duty Cycle 50 % Differential Output Resistance 100 Ω Differential Output Voltage (Note 13) 760 mV P-P SPI INTERFACE (Notes 14, 15) SCLK Period tCLK Write Operation 7 cycles tCLK Read Operation 16 cycles CSBto SCLK Setup Time t S Read or Write 2 cycles CSBafter SCLK Hold Time t H Read or Write 5 cycles Data Valid to SCLK Setup Time t DS Read or Write 6 cycles Data Valid after SCLK Hold Time t DH Read or Write 4 cycles Data Valid after SCLK Time t DVR Read 4 cycles NOTES: on desired function. 12. The synchronous clock divider reset function is available as a (SPI-programmable) overload on the SYNC input. 13. The voltage is expressed in peak-to-peak differential swing. The peak-to-peak single-ended swing is 1/2 of the differential swing. 14. The SPI interface timing is directly proportional to the ADC sample period (t S). Values above reflect multiples of a 4ns sample period, and must be scaled proportionally for lower sample rates. ADC sample clock must be running for SPI communication. 15. The SPI may operate asynchronously with respect to the ADC sample clock. Switching Specifications Boldface limits apply across the operating temperature range, -40°C to +85°C. (Continued) PARAMETER SYMBOL TEST CONDITION MIN (Note 6)T Y P MAX (Note 6)U N I T

FIGURE 9. SNR AND SFDR vs f SAMPLE FIGURE 10. HD2 AND HD3 vs f SAMPLE FIGURE 11. POWER vs f SAMPLE FIGURE 12. DIFFERENTIAL NONLINEARITY (250MSPS) FIGURE 13. INTEGRAL NONLINEARITY (250MSPS) FIGURE 14. SNR AND SFDR vs VCM (250MSPS)

3 LANE OPERATION

inversely proportional to the sample rate. page 20 for additional details. then determines the achievable SNR. while taking longer to return to functionality. up code group alignment will be required to reestablish the link. continues to remain stable during the nap period. NAPSLP pin voltage dictates it is to do so. contained in “Serial Peripheral Interface” on page 26. TABLE 1. CLKDIV PIN SETTINGS FIGURE 49. SNR vs CLOCK JITTER

10 BITS

12 BITS

14 BITS

TABLE 2. NAPSLP PIN SETTINGS

generate the frame clock for the receiving device. a full list of downgradeable configurations that are supported. the “Typical Performance Curves” beginning on page 10. FIGURE 52. SERDES TRANSMITTER BLOCK DIAGRAM

found in the JESD204 rev A standard. defined in the JESD204 rev A standard. passes the lane alignment sequence through its descrambler. the self-synchronizing nature of the scrambler used. from more than one ADC device. simultaneously-sampled converters. subclass 2 device definition. patterns than previous ADC families. controlled through SPI register 0xC0. FIGURE 53. LANE DATA RATE AS A FUNCTION OF ADC SAMPLE

4.375 GBPS

3.125 GBPS

3 Lanes (Efficient Packing)

3 Lanes (Simple Packing)

2 Lanes

1 Lane

TABLE 4. JESD204 CONFIGURATIO NS AND CLOCK FREQUENCIES TABLE 5. JESD204 PARAMETERS

The JESD204 parameters are shown as their actual values, with the JESD204 encoded values (i.e., the values that are programmed into the SPI

registers) in the next column over. Typically values that must always be greater than 1 are encoded as value minus 1, and so on.

Frame map format decoder: "CxSy[a:b]" = Converter x, Sample y, bits a through b. For example, "C0S0[13:6]" = Converter 0, Sample 0, bits 13 through

6, etc. "T" = Tail bit (information-less bit packed in the transport layer mapping to form octets).

The topmost lane in the graphical frame map is Lane0, fo llowed by Lane1 and Lane 2 (for 3-lane configurations).

TABLE 5. JESD204 PARAMETERS (Continued)

transfer can be inferred from these diagrams. first) to accommodate various microcontrollers. as arriving in LSB to MSB order. Setting this bit high resets all SPI registers to default values. This bit should always be set high. number of bytes based on the starting and ending addresses. be read from these two registers. multi-channel devices, is used for all Intersil ADC products. by the ADC (see description for 0xFE). ADC (see description for 0xFE). TABLE 6. BYTE TRANSFER SELECTION TABLE 7. OFFSET ADJUSTMENTS TABLE 8. COARSE GAIN ADJUSTMENT

not changed by a soft reset. used by the ADC (see description for 0xFE). and 0x2A to be used by the ADC (see description for 0xFE). one input clock period each time phase_slip is asserted. The clkdivrst feature can work in conjunction with phase_slip. This register is not changed by a soft reset. This bit sets the DLL operating range to fast (default) or slow. allowable sample rate ranges for the slow and fast settings. TABLE 9. MEDIUM AND FINE GAIN ADJUSTMENTS TABLE 10. POWER-DOWN CONTROL

000 Pin Control

001 Normal Operation

010 Nap Mode

001 Divide by 1 (Default)

010 Divide by 2

TABLE 12. OUTPUT FORMAT CONTROL

000 Two’s Complement (Default)

010 Gray Code

100 Offset Binary

functionality of the SYNCP, SYNCN pins is the JESD204 SYNC. chip, which can’t be read until calibration is complete. respectively, of the user-defined pattern 1. respectively, of the user-defined pattern 3. respectively, of the user-defined pattern 4. respectively, of the user-defined pattern 5. respectively, of the user-defined pattern 6. respectively, of the user-defined pattern 7. respectively, of the user-defined pattern 8. contact Intersil sales support for details. TABLE 13. DLL RANGES

30 FN8302.1 July 6, 2015 Submit Document Feedback allows downgrading of the JESD204 link (such as reducing the number of lanes, reducing the converter resolution, etc), but not upgrading. These parameters are communicated on every lane of the link during the 2nd multiframe of the initial lane alignment sequence, and therefore can be used by a generic JESD204 receiver the supports the given configuration. See the JESD204 specification for additional information on how these registers are used in a JESD204 system, including encoding rules. ADDRESS 0XDF: JESD204_UPDATE_CONFIG_START Bit 0 Update_start This self-resetting bit is used to indicate that some or all the JESD204 parameters (addresses 0xE0 through 0xED) are going to be written. Writing a ‘1’ to this bit will hold the JESD204 PLL and transmitter in a reset state while these parameters are written, because these parameters can affect the transmitter’s dynamic behavior (such as modifying the PLL’s frequency multiplication). The bit will automatically reset to a ‘0’ once a ‘1’ is written to address 0xEE Bit[0] “update_config W1TC”. The recommended sequence for modifying the JESD204 transmitter is as follows: 1. Write a ‘1’ to 0xDF Bit[0] 2. Write some or all modified values to 0xE0 through 0xEC 3. Write a ‘1’ to 0xEE Bit[0]. Note: 0xDF Bit[0] and 0xEE Bit[0] will automatically be reset to a ‘0’ once configuration has been applied to the circuitry. ADDRESS 0XE0: JESD204_CONFIG_0 Bits 7:0 “DID”, JESD204 Device ID number. ADDRESS 0XE1: JESD204_CONFIG_1 Bits 3:0 “BID”, JESD204 Bank ID. ADDRESS 0XE2: JESD204_CONFIG_2 Bits 4:0 “LID” JESD204 Lane ID. ADDRESS 0XE3: JESD204_CONFIG_3 Bit 7 “SCR”, JESD204 SCR controls if scrambling across the SERDES lane(s) is enabled (‘1’ means enabled). Bits 4:0 “L”, JESD204 L is the number of SERDES lanes in the link. ADDRESS 0XE4: JESD204_CONFIG_4 Bits 7:0 “F”, JESD204 Number of octets per frame period. ADDRESS 0XE5: JESD204_CONFIG_5 Bits 4:0 “K” JESD204 Number of frame periods per multi-frame period. This product family supports the full programmable range of K (decimal 0 through 31), although note that the JESD204 standard dictates a minimum number for this parameter that is configuration dependent. ADDRESS 0XE6: JESD204_CONFIG_6 Bits 7:0 “M” JESD204 Number of converters per device. ADDRESS 0XE7: JESD204_CONFIG_7 Bits 7:6 “CS”, JESD204 CS is the number of control bits per sample (Always ‘0’ for this product family). Bits 4:0 “N”, JESD204 N is the converter resolution. ADDRESS 0XE8: JESD204_CONFIG_8 Bits 4:0 “N’”, JESD204 N’ is the total number of bits per sample. ADDRESS 0XE9: JESD204_CONFIG_9 Bits 4:0 “S”, JESD204 Number of samples per converter per frame cycle. ADDRESS 0XEA: JESD204_CONFIG_10 Bit 7 “HD”, JESD204 HD indicates if a converter’s sample can be split across multiple lanes in the link (always ‘0’ for this product family). Bits 4:0 “CF”, JESD204 CF is the number of control fames per frame clock (always ‘0’ for this product family). ADDRESS 0XEB: JESD204_CONFIG_11 Bits 7:0 “RES1”, JESD204 reserved for future use. ADDRESS 0XEC: JESD204_CONFIG_12 Bits 7:0 “RES2”, JESD204 reserved for future use. ADDRESS 0XED: JESD204_CONFIG_13 Bits 7:0 “FCHK” JESD204 checksum (unsigned sum MOD 256) of all the other JESD204 parameter register values. This is a read-only register, as the checksum is calculated by the device. ADDRESS 0XEE: JESD204_UPDATE_CONFIG_COMPLETE Bit 0 Update_complete This self-resetting bit is used to indicate that all the modifications to the JESD204 parameters are complete. ADDRESS 0XEF: JESD204_PLL_MONITOR_RESET Bit 0 “pll_lock_mon_rst”, This self resetting register resets the state of the 0xF0 Bit[0] “latched_pll_lockn” bit. The purpose of this pair of bits is as a debugging feature to the system designer. The “latched_pll_lockn” bit indicates if the JESD204 transmitter PLL inside the device has at any time lost lock since the last ‘1’ was written to the “pll_lock_mon_rst” bit. This can be used to help identify the source of intermittent link lost errors in the system. ADDRESS 0XF0: JESD204_STATUS Bit 2 “op_cfg_wrong” indicates if the JESD204 parameters (registers 0xE0 through 0xED) are supported by the JESD204 transmitter (a ‘1’ indicates they are not supported, a ‘0’ indicates they are supported). Bit 1“pll_lockn” indicates if the JESD204 transmitter PLL is currently locked (a ‘1’ indicates it is not locked, a ‘0’ indicates it is locked). Bit 0 “latched_pll_lockn” indicates if the JESD204 transmitter PLL has lost lock since the last assertion of the “pll_lock_mon_rst” (see register 0xEF description for more information).

31 FN8302.1 July 6, 2015 Submit Document Feedback ADDRESS 0XF1: JESD204_SYNC Bit 0 “sync_req” this register provides a SPI-programmable interface that can be used to assert and deassert the JESD204 SYNC~ functionality. Certain systems may benefit from the elimination of SYNC~ as a separate board-level LVDS signal (and the power, PCB space and pins it consumes), and these systems can use this register to functionally assert and deassert SYNC~. For this bit to have any effect, a ‘1’ must have previously been written to the SYNC_FUNCTION (Address 0x77, bit 0). A ‘1’ written to this bit will result in behavior identical to the assertion of SYNC~ (comma character generation) and ‘0’ will result in the behavior identical to the deassertion of SYNC~ (initial lane alignment sequence followed by converter data). Usage of this SPI SYNC~ capability may compromise the system’s ability to perform multi-chip time alignment, as the SYNC~ asserted to deasserted transition using this register is not well timed with respect to sample clock. ADDRESS 0XF2: JESD204_TRANS_PAT_CONFIG Bit 0 “no_mf_lane_sync”, By default, this device family assumes that both sides of the link support lane synchronization. As per the JESD204 rev A standard, in this case continuous frame alignment monitoring via character substitution (section 5.3.3.4) is modified such that a different control character is substituted when the octet reoccurrence happens at the end of a multiframe. This behavior occurs when Bit 0 is ‘0’ (the power on default). Writing a ‘1’ to Bit 0 will inform the JESD204 transmitter than the receiving device does not support lane synchronization, and therefore the transmitter will no longer substitute this different control character when reoccurrence of octets occurs at the end of a multi-frame. Bit 1 “trans_pat_max_len” There is some ambiguity of the proper length of the JESD204 rev A section 5.1.6.2 required transport layer test pattern. Specifically, that the description perhaps should have “max()” in place of “min()” for the equation defining the length of the pattern. Setting Bit 1 in this register to a ‘0’ (also the power-on default) and issuing this test pattern by writing to 0xC0 will cause the pattern to assume a “min()” interpretation of the pattern described in section 5.1.6.2. Setting the bit to a ‘1’ will assume a “max()” interpretation of the described pattern. ADDRESS 0XF3: JESD204_CML_POLARITY 0xF3 Bit[2:0]: “TX polarity flip lane x” This register allows the system designer to invert the sense of the SERDES pins on a per lane basis. For example, writing a ‘1’ to Bit[0] causes LANE0N to functionally become LANE0P and LANE0P to become LANE0N. This feature allows the system designer to avoid having to crossover P and N sides of the CML pair on the board to match pin out and layout of the transmitter and receiver. Typically, a trace crossover would require vias, which can degrade the signal integrity of the high-speed SERDES lanes. ADDRESS 0XFE: OFFSET/GAIN_ADJUST_ENABLE Bit 0 at this register must be set high to enable adjustment of offset coarse and fine adjustments (0x20 and 0x21) and gain medium and gain fine adjustments(0x23 and 0x24). It is recommended that new data be written to the offset and gain adjustment registers (0x20, 0x21, 0x23, 0x24) while Bit 0 is a ‘0’. Subsequently, Bit 0 should be set to ‘1’ to allow the values written to the aforementioned registers to be used by the ADC. Bit 0 should be set to a ‘0’ upon completion. SPI Memory Map ADDR. (HEX) PARAMETER NAME BIT 7 (MSB) BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 (LSB) DEF. VALUE (HEX) SPI Config/Control 00 port_config SDO Active LSB First Soft Reset Mirror (Bit 5) Mirror (Bit 6) Mirror (Bit 7) 00h

01 Reserved Reserved

02 burst_end Burst end address [7:0] 00h 03-07 Reserved Reserved DUT Info 08 chip_id Chip ID # Read only 09 chip_version Chip Version # Read only 0A-0F Reserved Reserved

32 FN8302.1 July 6, 2015 Submit Document Feedback Device Config/Control 10-1F Reserved Reserved 20 offset_coarse_CoreA Coarse Offset cal. value 21 offset_fine_CoreA Fine Offset cal. value 22 gain_coarse_CoreA Reserved Coarse Gain cal. value 23 gain_medium_CoreA Medium Gain cal. value 24 gain_fine_CoreA Fine Gain cal. value 25 modes_CoreA Reserved Power Down Mode CoreA [2:0] 000 = Pin Control 001 = Normal Operation 010 = Nap 100 = Sleep Other codes = Reserved 00h NOT reset by soft reset 26 offset_coarse_CoreB Coarse Offset cal. value 27 offset_fine_CoreB Fine Offset cal. value 28 gain_coarse_CoreB Reserved Coarse Gain cal. value 29 gain_medium_CoreB Medium Gain cal. value 2A gain_fine_CoreB Fine Gain cal. value 2B modes_CoreB Reserved Power Down Mode CoreB [2:0] 000 = Pin Control 001 = Normal Operation 010 = Nap 100 = Sleep Other codes = Reserved 00h NOT reset by soft reset 2C-6F Reserved Reserved 70 skew_diff Differential Skew 80h 71 phase_slip Reserved Next Clock Edge 00h 72 clock_divide Clock Divide [2:0] 000 = Pin Control 001 = divide by 1 010 = divide by 2 100 = divide by 4 Other codes = Reserved 01h NOT reset by soft reset Device Config/Control 73 output_mode_A Output Format [2:0] 000 = Two’s Complement (Default) 010 = Gray Code 100 = Offset Binary Other codes = Reserved 00h NOT reset by soft reset 74 output_mode_B DLL Range 0 = Fast 1 = Slow Default=’0 00h NOT reset by soft reset 75-76 Reserved Reserved

77 SYNC_function Clkdivrst

B6 cal_status Reserved Calibration Done Read only B7-BF Reserved SPI Memory Map (Continued) ADDR. (HEX) PARAMETER NAME BIT 7 (MSB) BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 (LSB) DEF. VALUE (HEX)

33 FN8302.1 July 6, 2015 Submit Document Feedback Device Test C0 test_io Output Test Mode [7:4] JESD Test User Test Mode [2:0] User Test Mode (Single ADC products only) 0 = user pattern 1 only 1 = cycle pattern 1 through 2 2 = cycle pattern 1 through 3 3 = cycle pattern 1 through 4 4 = cycle pattern 1 through 5 5 = cycle pattern 1 through 6 6 = cycle pattern 1 through 7 7 = cycle pattern 1 through 8 User Test Mode (Dual and interleaved ADC products only) 0 = cycle pattern 1 through 2 1 = cycle pattern 1 through 4 2 = cycle pattern 1 through 6 3 = cycle pattern 1 through 8 4 through 7 = NA 00h <7:4> = Output Test, <3> = JESD Test JESD Test = 0 Output Test = 0x0 = Output Test Mode Off. During calibration MSB justified constant output 0xCCCC 0x1 = Midscale adjusted by numeric format 0x2 = Plus full scale, adjusted by numeric format 0x3 = Minus full scale adjusted by numeric format 0x4 = Checkboard output - 0xAAAA, 0x5555 0x5 = reserved 0x6 = reserved 0x7 = 0xFFFF, 0x0000 all on pattern 0x8 = User pattern 8 deep, MSB justified with output 0x9 = reserved 0xA, Count-up ramp 0xB, PRBS-9 0xC, PRBS-15 0xD, PRBS-23 0xE, PRBS-31 0xF = reserved JESD Test=1 Output Test = 0x0 = Link Layer Repeat K28.5+Lane Alignment Sequence 0x1, Link Layer Repeat K28.5 0x2, Link Layer Repeat D21.5 0x3, Link Layer Repeat K28.7 0x4, Link Layer PRBS-7 0x5, Link Layer PRBS-23 0x6, Link Layer All Zeros 0x7, Link Layer All Ones 0x8 - 0xE, reserved 0xF, JESD204 section 5.1.6.2 Transport Layer Test Pattern C1 user_patt1_lsb B7 B6 B5 B4 B3 B2 B1 B0 00h C2 user_patt1_msb B15 B14 B13 B12 B11 B10 B9 B8 00h C3 user_patt2_lsb B7 B6 B5 B4 B3 B2 B1 B0 00h C4 user_patt2_msb B15 B14 B13 B12 B11 B10 B9 B8 00h C5 user_patt3_lsb B7 B6 B5 B4 B3 B2 B1 B0 00h C6 user_patt3_msb B15 B14 B13 B12 B11 B10 B9 B8 00h C7 user_patt4_lsb B7 B6 B5 B4 B3 B2 B1 B0 00h C8 user_patt4_msb B15 B14 B13 B12 B11 B10 B9 B8 00h C9 user_patt5_lsb B7 B6 B5 B4 B3 B2 B1 B0 00h CA user_patt5_msb B15 B14 B13 B12 B11 B10 B9 B8 00h CB user_patt6_lsb B7 B6 B5 B4 B3 B2 B1 B0 00h CC user_patt6_msb B15 B14 B13 B12 B11 B10 B9 B8 00h CD user_patt7_lsb B7 B6 B5 B4 B3 B2 B1 B0 00h CE user_patt7_msb B15 B14 B13 B12 B11 B10 B9 B8 00h CF user_patt8_lsb B7 B6 B5 B4 B3 B2 B1 B0 00h D0 user_patt8_msb B15 B14 B13 B12 B11 B10 B9 B8 00h D1-DE Reserved Reserved SPI Memory Map (Continued) ADDR. (HEX) PARAMETER NAME BIT 7 (MSB) BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 (LSB) DEF. VALUE (HEX)

34 FN8302.1 July 6, 2015 Submit Document Feedback JESD204 Interface DF JESD204_update_config_start update_ start 00h E0 JESD204_config_0 DID (Device ID Number) 00h E1 JESD204_config_1 BID (Bank ID Number) See Description for Default Settings E2 JESD204_config_2 LID (Lane ID Number) E3 JESD204_config_3 SCR L (Number of Lanes per Device) E4 JESD204_config_4 F (Number of Octets per Frame) E5 JESD204_config_5 K (Number of frames per multiframe) E6 JESD204_config_6 M (Number of Converters per Device) E7 JESD204_config_7 CS (Number of Control bits per Sample) N (Converter Resolution in bits) E8 JESD204_config_8 N’ (Total number of bits per Sample) E9 JESD204_config_9 S (Number of Samples per Converter per Frame) EA JESD204_config_10 HD CF (Number of Control Words per Frame per Link) EB JESD204_config_11 RES1 EC JESD204_config_12 RES2 ED JESD204_config_13 FCHK (Checksum) EE JESD204_update_config_ complete update_ complete 00h EF JESD204_PLL_monitor_reset pll_lock_ mon_rst 00h F0 JESD204_status op_confg_ wrong pll_lockn latched_ pll_lockn 00h F1 JESD204_sync sync_req F2 JESD204_trans_pat_config trans_pat_ max_len no_mf_ lane_sync F3 JESD204_CML_polarity lane_2_ polarity lane_1_ polarity lane_0_ polarity 00h F4-FD Reserved Reserved FE Offset/Gain_Adjust_Enable Enable ‘1’=Enable 00h FF Reserved Reserved SPI Memory Map (Continued) ADDR. (HEX) PARAMETER NAME BIT 7 (MSB) BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 (LSB) DEF. VALUE (HEX)

36 FN8302.1 July 6, 2015 Submit Document Feedback ADC Evaluation Platform Intersil offers ADC Evaluation platforms, which can be used to evaluate any of Intersil’s high speed ADC products. Each platform consists of a FPGA based data capture motherboard and a family of ADC daughtercards. The USB interface and evaluation platform control software allow a user to quickly evaluate the ADC’s performance at a user’s specific application frequency requirements. More information is available at http://www.intersil.com/converters/adc_eval_platform/ Layout Considerations Split Ground and Power Planes Data converters operating at high sampling frequencies require extra care in PC board layout. Many complex board designs benefit from isolating the analog and digital sections. Analog supply and ground planes should be laid out under signal and clock inputs. Locate the digital planes under outputs and logic pins. Grounds should be joined under the chip. Clock Input Considerations Use matched transmission lines to the transformer inputs for the analog input and clock signals. Locate transformers and terminations as close to the chip as possible. Exposed Paddle The exposed paddle must be electrically connected to analog ground (AVSS) and should be connected to a large copper plane using numerous vias for optimal thermal performance. Bypass and Filtering Bulk capacitors should have low equivalent series resistance. Tantalum is a good choice. For best performance, keep ceramic bypass capacitors very close to device pins, as longer traces between the ceramic bypass capacitors and the device pins will increase inductance, which can result in diminished dynamic performance. Best practices bypassing is especially important on the AVDD and OVDD(PLL) power supply pins. Whenever possible, each supply pin should have its own 0.1µF bypass capacitor. Make sure that connections to ground are direct and low impedance. Avoid forming ground loops. CML Outputs Output traces and connections must be designed for 50Ω (100Ω differential) characteristic impedance. Keep traces direct and short, and minimize bends and vias where possible. Avoid crossing ground and power-plane breaks with signal traces. Keep good clearance (at least 5 trace widths) between the SERDES traces and other signals. Given the speed of these outputs and importance of maintaining an open eye to achieve low BER, signal integrity simulations are recommended, especially when the data lane rate exceeds 3Gbps and/or the trace or cable length between the ADC and the receiver gets larger than 20cm. Unused Inputs Standard logic inputs (RESETN, CSB, SCLK, SDIO, SDO) which will not be operated, do not require connection to ensure optimal ADC performance. These inputs can be left floating if they are not used. Tri-level inputs (NAPSLP) accept a floating input as a valid state and therefore should be biased according to the desired functionality. Definitions Analog Input Bandwidth is the analog input frequency at which the spectral output power at the fundamental frequency (as determined by FFT analysis) is reduced by 3dB from its full scale low-frequency value. This is also referred to as Full Power Bandwidth. Aperture Delay or Sampling Delay is the time required after the rise of the clock input for the sampling switch to open, at which time the signal is held for conversion. Aperture Jitter is the RMS variation in aperture delay for a set of samples. Clock Duty Cycle is the ratio of the time the clock wave is at logic high to the total time of one clock period. Differential Non-Linearity (DNL) is the deviation of any code width from an ideal 1 LSB step. Effective Number of Bits (ENOB) is an alternate method of specifying Signal to Noise-and-Distortion Ratio (SINAD). In dB, it is calculated as: ENOB = (SINAD - 1.76)/6.02 Gain Error is the ratio of the difference between the voltages that cause the lowest and highest code transitions to the full scale voltage less than 2 LSB. It is typically expressed in percent. I2E The Intersil Interleave Engine. This highly configurable circuitry performs estimates of offset, gain, and sample time skew mismatches between the core converters, and updates analog adjustments for each to minimize interleave spurs. Integral Non-Linearity (INL) is the maximum deviation of the ADC’s transfer function from a best fit line determined by a least squares curve fit of that transfer function, measured in units of LSBs. Least Significant Bit (LSB) is the bit that has the smallest value or weight in a digital word. Its value in terms of input voltage is V FS/(2N - 1) where N is the resolution in bits. Missing Codes are output codes that are skipped and will never appear at the ADC output. These codes cannot be reached with any input value. Most Significant Bit (MSB) is the bit that has the largest value or weight. Pipeline Delay is the number of clock cycles between the initiation of a conversion and the appearance at the output pins of the data. Power Supply Rejection Ratio (PSRR) is the ratio of the observed magnitude of a spur in the ADC FFT, caused by an AC signal superimposed on the power supply voltage. Signal-to-Noise and Distortion (SINAD) is the ratio of the RMS signal amplitude to the RMS sum of all other spectral components below one half the clock frequency, including harmonics but excluding DC.

Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8302.1 July 6, 2015 For additional products, see www.intersil.com/en/products.html Submit Document Feedback Signal-to-Noise Ratio (without Harmonics) is the ratio of the RMS signal amplitude to the RMS sum of all other spectral components below one-half the sampling frequency, excluding harmonics and DC. SNR and SINAD are either given in units of dB when the power of the fundamental is used as the reference, or dBFS (dB to full scale) when the converter’s full scale input power is used as the reference. Spurious-Free-Dynamic Range (SFDR) is the ratio of the RMS signal amplitude to the RMS value of the largest spurious spectral component. The largest spurious spectral component may or may not be a harmonic. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE REVISION CHANGE July 6, 2015 FN8302.1 Removed Product Availability column from “Pin-compatible Family” on page 1. Removed “Coming Soon” from parts in ordering information on page 4 and changed ADCMB-HSFMC-EV1Z to ADCMB-HSFMCEV1Z Changed default value for register 72 from 00h to 01h in “SPI Memory Map” on page 32. Under “Address 0x72: clock_divide” on page 28, replaced the sentence "By default, the tri-level CLKDIV pin selects the divisor." with the sentence "By default, CLOCK_DIVIDE is set to divide by 1. In Table 11 on page 28, added the phrase "(Default)" to the right of "Divide by 1" in the second row. May 1, 2012 FN8302.0 Initial Release

38 FN8302.1 July 6, 2015 Submit Document Feedback Package Outline Drawing L48.7x7G

48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE

Rev 0, 1/10 located within the zone indicated. The pin #1 indentifier may be Unless otherwise specified, tolerance : Decimal ± 0.05 Tiebar shown (if present) is a non-functional feature. The configuration of the pin #1 identifier is optional, but must be between 0.015mm and 0.30mm from the terminal tip. Dimension applies to the metallized terminal and is measured Dimensions in ( ) for Reference Only. Dimensioning and tolerancing conform to ASME Y14.5m-1994. either a mold or mark feature. Dimensions are in millimeters.1. NOTES: BOTTOM VIEW DETAIL "X" SIDE VIEW TYPICAL RECOMMENDED LAND PATTERN TOP VIEW 7.00 B A 7.00 (4X) 0.15 INDEX AREA PIN 1 PIN #1 44X 0.50 4X 5.5 4837 EXP. DAP 136 48X 0.40 1324 50 . 2 REF 0 . 00 MIN. 0 . 05 MAX. C

1.00 MAX SEE DETAIL "X"

C C0.08 SEATING PLANE C0.10 6 .80 SQ 5.70 SQ ( 48X 0 . 60 ) ( 44X 0 . 5 ) ( 48X 0 . 20 ) 48x 0.20 5.70 SQ. INDEX AREA

Summary

Dual 12-bit, 250/200/125 MSPS JESD204B High Speed Serial Output ADC July 6, 2015

Description