ADCLK948_16 AD | Alldatasheet
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Two Selectable Inputs, 8 LVPECL Outputs, SiGe Clock Fanout Buffer Data Sheet ADCLK948 Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2009–2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
FEATURES
2 selectable differential inputs
4.8 GHz operating frequency
75 fs rms broadband random jitter On-chip input terminations
3.3 V power supply
APPLICATIONS
Low jitter clock distribution Clock and data signal restoration Level translation Wireless communications Wired communications Medical and industrial imaging ATE and high performance instrumentation GENERAL DESCRIPTION The ADCLK948 is an ultrafast clock fanout buffer fabricated on the Analog Devices, Inc., proprietary XFCB3 silicon germanium (SiGe) bipolar process. This device is designed for high speed applications requiring low jitter. The device has two selectable differential inputs via the IN_SEL control pin. Both inputs are equipped with center tapped, differential, 100 Ω on-chip termination resistors. The inputs accept dc-coupled LVPECL, CML, 3.3 V CMOS (single-ended), and ac-coupled 1.8 V CMOS, LVDS, and LVPECL inputs. A VREFx pin is available for biasing ac-coupled inputs. The ADCLK948 features eight full-swing emitter coupled logic (ECL) output drivers. For LVPECL (positive ECL) operation, bias VCC to the positive supply and VEE to ground. For ECL operation, bias VCC to ground and VEE to the negative supply. The output stages are designed to directly drive 800 mV each side into 50 Ω terminated to V CC − 2 V for a total differential output swing of 1.6 V . The ADCLK948 is available in a 32-lead LFCSP and specified for operation over the standard industrial temperature range of −40°C to +85°C. FUNCTIONAL BLOCK DIAGRAM VT0 VREF0 VREF1 IN_SEL CLK0 CLK0 VT1 CLK1 CLK1 LVPECL ADCLK948 REFERENCE REFERENCE 08280-001 Figure 1.
Rev. B | Page 2 of 12 TABLE OF CONTENTS
REVISION HISTORY
8/2016— Rev. A to Rev. B 6/2010— Rev. 0 to Rev. A Changed Output Voltage Differential Parameter to Output Changes to Output Voltage, Single Ended Parameter, Table 1 ... 3 7/2009— Revision 0: Initial Version
Rev. B | Page 3 of 12 SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Typical (Typ column) values are given for VCC − VEE = 3.3 V and TA = 25°C, unless otherwise noted. Minimum (Min column) and maximum (Max column) values are given over the full VCC − VEE = 3.3 V ± 10% and TA = −40°C to +85°C variation, unless otherwise noted. Table 1. Clock Inputs and Outputs Table 2. Timing Characteristics Maximum Output Frequency 4.5 4.8 GHz See Figure 4 for differential output voltage vs. 1 The output skew is the difference between any two similar delay paths while operating at the same voltage and temperature. 2 Measured at the rising edge of the clock signal; calculated using the SNR of the ADC method. 3 This is the amount of added jitter measured at the output while two related, asynchronous, differential frequencies are applied to the inputs.
Table 3. Input Select Control Pin Table 4. Power 1 Change in tPD per change in VCC. 2 Change in output swing per change in VCC.
Rev. B | Page 5 of 12 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Rating Supply Voltage VCC − VEE 6 V Input Voltage CLK0, CLK1, CLK0, CLK1, IN_SEL V EE − 0.5 V to VCC + 0.5 V CLK0, CLK1, CLK0, CLK1 to VTx Pin (CML, LVPECL Termination) ±40 mA CLK0, CLK1 to CLK0, CLK1 ±1.8 V Input Termination, VTx to CLK0, CLK1, CLK0, and CLK1 ±2 V Maximum Voltage on Output Pins V CC + 0.5 V Maximum Output Current 35 mA Voltage Reference (VREFx) V CC to VEE Operating Temperature Range Ambient − 40°C to +85°C Junction 150°C Storage Temperature Range − 65°C to +150°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. DETERMINING JUNCTION TEMPERATURE To determine the junction temperature on the application printed circuit board (PCB), use the following equation: TJ = TCASE + (ΨJT × PD) where: TJ is the junction temperature (°C). TCASE is the case temperature (°C) measured by the customer at the top center of the package. ΨJT is from Table 6. PD is the power dissipation. Values of θJA are provided for package comparison and PCB design considerations. θJA can be used for a first-order approxi- mation of TJ by the equation TJ = TA + ( θJA × PD) where TA is the ambient temperature (°C). Values of θJB are provided in Table 6 for package comparison and PCB design considerations. ESD CAUTION THERMAL PERFORMANCE Table 6. Parameter Symbol Description Value1 Unit Junction-to-Ambient Thermal Resistance θJA Still Air Per JEDEC JESD51-2 0 m/sec Air Flow 49.8 °C/W Moving Air θJMA Per JEDEC JESD51-6 1 m/sec Air Flow 4 3.5 °C/W 2.5 m/sec Air Flow 39.0 °C/W Junction-to-Board Thermal Resistance θJB Moving Air Per JEDEC JESD51-8 1 m/sec Air Flow 30.7 °C/W Junction-to-Case Thermal Resistance θJC Moving Air Per MIL-STD 883, Method 1012.1 Die-to-Heatsink 8.8 °C/W Junction-to-Top-of-Package Characterization Parameter ΨJT Still Air Per JEDEC JESD51-2 0 m/sec Air Flow 0.7 °C/W 1 Results are from simulations. The PCB is a JEDEC multilayer type. Thermal performance for actual applications requires careful inspection of the conditions in the application to determine if they are similar to those assumed in these calculations.
- THE EPAD MUST BE SOLDERED TO THE V
Figure 2. Pin Configuration Table 7. Pin Function Descriptions 1 CLK0 Differential Input (Positive) 0. 2 CLK0 Differential Input (Negative) 0. 3 V REF0 Reference Voltage. Reference voltage for biasing ac-coupled CLK0 and CLK0 inputs. 4 V T0 Center Tap. Center tap of a 100 Ω input resistor for CLK0 and CLK0 inputs. 5 CLK1 Differential Input (Positive) 1. 6 CLK1 Differential Input (Negative) 1. 7 V T1 Center Tap. Center tap of a 100 Ω input resistor for CLK1 and CLK1 inputs. 8 V REF1 Reference Voltage. Reference voltage for biasing ac-coupled CLK1 and CLK1 inputs. 11, 12 Q7, Q7 Differential LVPECL Outputs. 13, 14 Q6, Q6 Differential LVPECL Outputs. 17, 18 Q5, Q5 Differential LVPECL Outputs. 19, 20 Q4, Q4 Differential LVPECL Outputs. 21, 22 Q3, Q3 Differential LVPECL Outputs. 23, 24 Q2, Q2 Differential LVPECL Outputs. 27, 28 Q1, Q1 Differential LVPECL Outputs. 29, 30 Q0, Q0 Differential LVPECL Outputs. 32 IN_SEL Input Select. Logic 0 selects CLK0 and CLK0 inputs. Logic 1 selects CLK1 and CLK1 inputs. EPAD Exposed Pad. The EPAD must be soldered to the VEE power plane.
the General Description section for more clock input details. good high frequency characteristics. dent propagation delay dispersion. Figure 13. Simplified Schematic Diagram of the LVPECL Output Stage
1.3 V because there is additional current flowing from the
ADCLK948 LVPECL driver through the pull-down resistor. driving long trace lengths but is usually not an issue. Figure 14. DC-Coupled, 3.3 V LVPECL Figure 15. DC-Coupled, 3.3 V LVPECL Far-End Thevenin Termination Figure 16. DC-Coupled, 3.3 V LVPECL Y-Termination Figure 17. AC-Coupled, LVPECL with Parallel Transmission Line
ECL operation, the VCC power plane becomes the ground plane. that can affect jitter performance. the return side is connected to the reference pin that is provided. the rated input differential and common-mode ranges. voltage and supply the input bias currents. appropriate external diodes be used. attached to the VEE power plane. from the top layer down to the VEE power plane (see Figure 18). vides an example of how to attach the part to the PCB. Figure 18. PCB Land for Attaching Exposed Paddle
0.05 MAX
0.02 NOM
0.20 REF
0.20 MIN
COMPLIANT TO JEDEC STANDARDS MO-220- WHHD-2 . Figure 24. 32-Lead Lead Frame Chip Scale Package [LFCSP] registered trademarks are the property of their respective owners.