ADCLK944 (Rev. 0)
Document overview
- Manufacturer or author: Analog Devices, Inc.
- PDF pages: 12
Technical content
2.5 V/3.3 V, Four LVPECL Outputs, SiGe Clock Fanout Buffer ADCLK944 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved. FEATURES FEATURES Operating frequency: 7.0 GHz Operating frequency: 7.0 GHz Broadband random jitter: 50 fs rms Broadband random jitter: 50 fs rms On-chip input terminations On-chip input terminations Power supply (VCC − VEE): 2.5 V to 3.3 V Power supply (VCC − VEE): 2.5 V to 3.3 V APPLICATIONS APPLICATIONS Low jitter clock distribution Low jitter clock distribution Clock and data signal restoration Clock and data signal restoration Level translation Level translation Wireless communications Wireless communications Wired communications Wired communications Medical and industrial imaging Medical and industrial imaging ATE and high performance instrumentation ATE and high performance instrumentation FUNCTIONAL BLOCK DIAGRAM FUNCTIONAL BLOCK DIAGRAM LVPECLADCLK944 REFERENCEREF VT V CLK CLK 08770-001 Figure 1. GENERAL DESCRIPTION The ADCLK944 is an ultrafast clock fanout buffer fabricated on the Analog Devices, Inc., proprietary XFCB3 silicon germanium (SiGe) bipolar process. This device is designed for high speed applications requiring low jitter. The device has a differential input equipped with center-tapped, differential, 100 Ω on-chip termination resistors. The input can accept dc-coupled LVPECL, CML, 3.3 V CMOS (single-ended), and ac-coupled 1.8 V CMOS, LVDS, and LVPECL inputs. A VREF pin is available for biasing ac-coupled inputs. The ADCLK944 features four full-swing emitter-coupled logic (ECL) output drivers. For LVPECL (positive ECL) operation, bias V CC to the positive supply and VEE to ground. For ECL operation, bias VCC to ground and VEE to the negative supply. The ECL output stages are designed to directly drive 800 mV each side into 50 Ω terminated to V CC − 2 V for a total differen- tial output swing of 1.6 V . The ADCLK944 is available in a 16-lead LFCSP and is specified for operation over the standard industrial temperature range of −40°C to +85°C.
Rev. 0 | Page 2 of 12 TABLE OF CONTENTS
REVISION HISTORY
3/10—Revision 0: Initial Version
Rev. 0 | Page 3 of 12 SPECIFICATIONS Typical values are given for VCC − VEE = 3.3 V and TA = 25°C, unless otherwise noted. Minimum and maximum values are given for the full VCC − VEE = 3.3 V + 10% to 2.5 V − 5% and TA = −40°C to +85°C variation, unless otherwise noted. CLOCK INPUTS AND OUTPUTS Table 1. Parameter Symbol Min Typ Max Unit Test Conditions/Comments DC INPUT CHARACTERISTICS Input Common-Mode Voltage VICM V EE + 1.35 VCC − 0.1 V Input Differential Voltage VID 0.4 3.4 V p-p ±1.7 V between input pins Input Capacitance CIN 0.4 pF Input Resistance RIN Single-Ended Mode 50 Ω Differential Mode 100 Ω Common Mode 50 kΩ VT open Input Bias Current 20 μA DC OUTPUT CHARACTERISTICS Output Voltage High Level VOH V CC − 1.26 VCC − 0.76 V Load = 50 Ω to (VCC − 2.0 V) Output Voltage Low Level VOL V CC − 1.99 VCC − 1.54 V Load = 50 Ω to (VCC − 2.0 V) Output Voltage, Single-Ended VO 600 960 mV VOH − VOL, output static Voltage Reference VREF Output Voltage (VCC + 1)/2 V −500 μA to +500 μA Output Resistance 250 Ω TIMING CHARACTERISTICS Table 2. Parameter Symbol Min Typ Max Unit Test Conditions/Comments AC PERFORMANCE Maximum Output Frequency 6.2 7.0 GHz Differential output voltage swing > 0.8 V (see Figure 4) Output Rise/Fall Time tR 35 50 75 ps 20% to 80%, measured differentially Propagation Delay tPD 70 100 130 ps VID = 1.6 V p-p Temperature Coefficient 75 fs/°C Output-to-Output Skew1 15 ps Part-to-Part Skew 35 ps VID = 1.6 V p-p Additive Time Jitter Integrated Random Jitter 26 fs rms BW = 12 kHz to 20 MHz, CLK = 1 GHz Broadband Random Jitter2 50 fs rms VID = 1.6 V p-p, 8 V/ns, VICM = 2 V CLOCK OUTPUT PHASE NOISE Absolute Phase Noise Input slew rate > 1 V/ns (see Figure 11) fIN = 1 GHz −118 dBc/Hz 100 Hz offset −135 dBc/Hz 1 kHz offset −144 dBc/Hz 10 kHz offset −150 dBc/Hz 100 kHz offset −150 dBc/Hz >1 MHz offset 1 The output-to-output skew is the difference between any two similar delay paths while operating at the same voltage and temperature. 2 Measured at the rising edge of the clock signal; calculated using the SNR of the ADC method.
Rev. 0 | Page 4 of 12 POWER Table 3. Parameter Symbol Min Typ Max Unit Test Conditions/Comments POWER SUPPLY Supply Voltage Requirement VCC − VEE 2.375 3.63 V 3.3 V + 10% to 2.5 V − 5% Power Supply Current S tatic Negative Supply Current IVEE 35 mA VCC − VEE = 2.5 V ± 5% I VEE 37 49 mA VCC − VEE = 3.3 V ± 10% Positive Supply Current IVCC 139 mA VCC − VEE = 2.5 V ± 5% I VCC 138 165 mA VCC − VEE = 3.3 V ± 10% Power Supply Rejection1 PSRVCC −3 ps/V Output Swing Supply Rejection2 PSRVCC 28 dB 1 Change in tPD per change in VCC. 2 Change in output swing per change in VCC.
Rev. 0 | Page 5 of 12 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter Rating Supply Voltage VCC − VEE 6.0 V Input Voltage CLK, CLK VEE − 0.5 V to VCC + 0.5 V CLK to CLK ±1.8 V Input Termination, VT to CLK, CLK ±2 V Input Current, CLK, CLK to VT Pin (CML, LVPECL Termination) ±40 mA Maximum Voltage on Output Pins VCC + 0.5 V Maximum Output Current 35 mA Voltage Reference (VREF) V CC to VEE Operating Temperature Ambient Range −40°C to +85°C Junction 150°C Storage Temperature Range −65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DETERMINING JUNCTION TEMPERATURE To determine the junction temperature on the application printed circuit board (PCB), use the following equation: T J = TCASE + (ΨJT × PD) where: T J is the junction temperature (°C). TCASE is the case temperature (°C) measured by the customer at the top center of the package. Ψ JT is as indicated in Table 5. PD is the power dissipation. Values of θJA are provided for package comparison and PCB design considerations. θJA can be used for a first-order approx- imation of TJ using the following equation: TJ = TA + (θJA × PD) where TA is the ambient temperature (°C). Values of θJB are provided in Table 5 for package comparison and PCB design considerations. ESD CAUTION THERMAL PERFORMANCE Table 5. Parameter Symbol Description Value1 Unit Junction-to-Ambient Thermal Resistance Still Air θJA Per JEDEC JESD51-2 0.0 m/sec Airflow 78 °C/W Moving Air θJMA Per JEDEC JESD51-6 1.0 m/sec Airflow 68 °C/W 2.5 m/sec Airflow 61 °C/W Junction-to-Board Thermal Resistance θJB Per JEDEC JESD51-8 Moving Air 1.0 m/sec Airflow 49 °C/W Junction-to-Case Thermal Resistance (Die-to-Heat Sink) θJC Per MIL-STD-883, Method 1012.1 Still Air 0.0 m/sec Airflow 1.5 °C/W Junction-to-Top-of-Package Characterization Parameter ΨJT Still Air Per JEDEC JESD51-2 0.0 m/sec Airflow 2.0 °C/W 1 Results are from simulations. The PCB is a JEDEC multilayer type. Thermal performance for actual applications requires careful inspection of the conditions in the application to determine whether they are similar to those assumed in these calculations.
- EXPOSED PAD MUST BE CONNECTED
Figure 2. Pin Configuration Table 6. Pin Function Descriptions 1 CLK Differential Input (Positive). 2 V T Center Tap. This pin provides the center tap of a 100 Ω input resistor for the CLK and CLK inputs. 3 V REF Reference Voltage. This pin provides the reference voltage for biasing ac-coupled CLK and CLK inputs. 4 CLK Differential Input (Negative). 5, 16 VEE Negative Supply Pin. 6, 7 Q3, Q3 Differential LVPECL Outputs. 8, 13 VCC Positive Supply Pin. 9, 10 Q2, Q2 Differential LVPECL Outputs. 11, 12 Q1, Q1 Differential LVPECL Outputs. 14, 15 Q0, Q0 Differential LVPECL Outputs. EPAD The exposed pad must be connected to VEE.
VCC = 3.3 V , VEE = 0.0 V , VICM = VREF, TA = 25°C, clock outputs terminated at 50 Ω to VCC − 2 V , unless otherwise noted. Figure 3. LVPECL Differential Output Waveform at 200 MHz Figure 4. Differential Output Voltage Swing vs. Frequency
110 PROPAGATION DELAY (ps)
Figure 5. Propagation Delay vs. Differential Input Voltage Swing Figure 6. LVPECL Differential Output Waveform at 1000 MHz Figure 7. Differential Output Voltage Swing vs. Power Supply Voltage Figure 8. Propagation Delay vs. DC Common-Mode Voltage
0.05 MAX
0.02 NOM
0.20 REF
0.25 MIN
COMPLIANT TOJEDEC STANDARDS MO-220-WEED-6. Figure 22. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] registered trademarks are the prop erty of their respective owners.