ADCLK905_17 AD | Alldatasheet

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Data Sheet ADCLK905/ADCLK907/ADCLK925 Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 © 2007–2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

7.5 GHz toggle rate

60 ps typical output rise/fall 60 fs random jitter (RJ) On-chip terminations at both input pins Extended industrial temperature range: −40°C to +125°C 2.5 V to 3.3 V power supply (VCC − VEE)

APPLICATIONS

Clock and data signal restoration and level shifting Automated test equipment (ATE) High speed instrumentation High speed line receivers Threshold detection Converter clocking GENERAL DESCRIPTION The ADCLK905 (one input, one output), ADCLK907 (dual one input, one output), and ADCLK925 (one input, two outputs) are ultrafast clock/data buffers fabricated on the Analog Devices, Inc., proprietary XFCB3 silicon germanium (SiGe) bipolar process. The ADCLK905/ADCLK907/ADCLK925 feature full-swing emitter coupled logic (ECL) output drivers. For PECL (positive ECL) operation, bias VCC to the positive supply and VEE to ground. For NECL (negative ECL) operation, bias VCC to ground and VEE to the negative supply. The buffers offer 95 ps propagation delay, 7.5 GHz toggle rate, 10 Gbps data rate, and 60 fs random jitter (RJ). The inputs have center tapped, 100 Ω, on-chip termination resistors. A VREF pin is available for biasing ac-coupled inputs. The ECL output stages are designed to directly drive 800 mV each side into 50 Ω terminated to VCC − 2 V for a total differential output swing of 1.6 V . The ADCLK905/ADCLK907/ADCLK925 are available in 16-lead LFCSP packages. TYPICAL APPLICATION CIRCUITS D D Q V CC VEE VT Q VREF 06318-001 Figure 1. ADCLK905 ECL 1:1 Clock/Data Buffer Figure 2. ADCLK907 ECL Dual 1:1 Clock/Data Buffer Figure 3. ADCLK925 ECL 1:2 Clock/Data Fanout Buffer

ADCLK905/ADCLK907/ADCLK925 Data Sheet Rev. B | Page 2 of 16 TABLE OF CONTENTS

REVISION HISTORY

2/2017— Rev. A to Rev. B 8/2016— Rev. 0 to Rev. A 8/2007— Revision 0: Initial Version

Data Sheet ADCLK905/ADCLK907/ADCLK925 Rev. B | Page 3 of 16 SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

Typical (Typ) values are given for VCC − VEE = 3.3 V and TA = 25°C, unless otherwise noted. Minimum (Min) and maximum (Max) values are given over the full VCC − VEE = 3.3 V ± 10% and TA = −40°C to +125°C variation, unless otherwise noted. Table 1. Parameter Symbol Min Typ Max Unit Test Conditions/Comments DC INPUT CHARACTERISTICS Input Voltage High Level V IH V EE + 1.6 V CC V Input Voltage Low Level V IL V EE V CC − 0.7 V Input Differential Range V ID 0.2 3.4 V p-p − 40°C to +85°C (±1.7 V between input pins) VID 0.2 2.8 V p-p 85°C to 125°C (±1.4 V between input pins) Input Capacitance C IN 0.4 pF Input Resistance, Single-Ended Mode 50 Ω Input Resistance, Differential Mode 100 Ω Input Resistance, Common Mode 50 kΩ Open VT Input Bias Current 20 µA DC OUTPUT CHARACTERISTICS Output Voltage High Level VOH VCC − 1.26 VCC − 0.76 V 50 Ω to (VCC − 2.0 V) Output Voltage Low Level V OL V CC − 1.99 V CC − 1.54 V 50 Ω to (VCC − 2.0 V) Output Voltage Differential V OD 610 1040 mV 50 Ω to (VCC − 2.0 V) Reference Voltage V REF Output Voltage (VCC + 1)/2 V − 500 µA to +500 µA Output Resistance 250 Ω AC PERFORMANCE Propagation Delay t PD 70 95 125 ps V CC = 3.3 V ± 10%, VICM = VREF, VID = 0.5 V p-p 70 95 125 ps VCC = 2.5 V ± 5%, VICM = V REF, VID = 0.5 V p-p Propagation Delay Temperature Coefficient 50 f s/°C Propagation Delay Skew (Output to Output) ADCLK907 15 ps V ID = 0.5 V Propagation Delay Skew (Output to Output) ADCLK925 10 ps V ID = 0.5 V Propagation Delay Skew (Device to Device) 35 ps V ID = 0.5 V Toggle Rate 6 7.5 GHz >0.8 V differential output swing, VCC = 3.3 V ± 10% 6.5 GHz >0.8 V differential output swing, VCC = 2.5 V ± 5% Random Jitter RJ 60 fs rms V ID = 1600 mV, 8 V/ns, VICM = 1.85 V Rise/Fall Time t R/tF 30 85 ps 20%/80% Additive Phase Noise

622.08 MHz − 138 dBc/Hz @ 10 Hz offset

− 144 dBc/Hz @ 100 Hz offset − 152 dBc/Hz @ 1 kHz offset −159 dBc/Hz @10 kHz offset − 161 dBc/Hz @ 100 kHz offset − 161 dBc/Hz > 1 MHz offset

122.88 MHz − 135 dBc/Hz @ 10 Hz offset

− 145 dBc/Hz @ 100 Hz offset − 153 dBc/Hz @ 1 kHz offset − 160 dBc/Hz @ 10 kHz offset − 161 dBc/Hz @ 100 kHz offset −161 dBc/Hz >1 MHz offset

ADCLK905/ADCLK907/ADCLK925 Data Sheet Rev. B | Page 4 of 16 Parameter Symbol Min Typ Max Unit Test Conditions/Comments POWER SUPPLY Supply Voltage Requirement V CC − VEE 2.375 3.63 V 2.5 V − 5% to 3.3 V + 10% Power Supply Current Static ADCLK905 Negative Supply Current I VEE 24 mA V CC − VEE = 2.5 V 25 40 mA VCC − VEE = 3.3 V ± 10% Positive Supply Current IVCC 47 mA VCC − VEE = 2.5 V 48 63 mA VCC − VEE = 3.3 V ± 10% ADCLK907 Negative Supply Current I VEE 48 mA V CC − VEE = 2.5 V 50 80 mA VCC − VEE = 3.3 V ± 10% Positive Supply Current I VCC 94 mA V CC − VEE = 2.5 V 96 126 mA VCC − VEE = 3.3 V ± 10% ADCLK925 Negative Supply Current I VEE 29 mA V CC − VEE = 2.5 V 31 51 mA VCC − VEE = 3.3 V ± 10% Positive Supply Current I VCC 76 mA V CC − VEE = 2.5 V 77 97 mA VCC − VEE = 3.3 V ± 10% Power Supply Rejection1 PSRVCC 3 ps/V VCC − VEE = 3.0 V ± 20% Output Swing Supply Rejection2 PSR VCC 26 dB V CC − VEE = 3.0 V ± 20% 1 Change in TPD per change in VCC. 2 Change in output swing per change in VCC.

soldered in a circuit board for surface-mount packages. Table 3. Thermal Resistance

  1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
  2. EXPOSED PAD. THE EXPOSED PAD IS NOT ELECTRICALLY CONNECTED TO ANY PART OF THE CIRCUIT.

IS CONNECTED TO THIS EXPOSED PAD. ALLOW SUFFICIENT CLEARANCE TO VIAS AND OTHER COMPONENTS. Figure 4. ADCLK905 Pin Configuration Table 4. Pin Function Descriptions for 1:1 ADCLK905 Buffer NC No Connect. No physical connection to the die. 7, 14 V EE Negative Supply Voltage. 8, 13 V CC Positive Supply Voltage. 15 V REF Reference Voltage. Reference voltage for biasing ac-coupled inputs. 16 V T Center Tap. Center tap of 100 Ω input resistor. of the package is connected to this exposed pad. Allow sufficient clearance to vias and other components.

  1. EXPOSED PAD. THE EXPOSED PAD IS NOT ELECTRICALLY CONNECTED TO ANY PART OF THE CI RCUIT.

IS CONNECTED TO THIS EXPOSED PAD. ALLOW SUFFICIENT CLE ARANCE TO VIAS AND OTHER COMPONENTS. Figure 5. ADCLK907 Pin Configuration Table 5. Pin Function Descriptions for Dual 1:1 ADCLK907 Buffer 5 V T2 Center Tap 2. Center tap of 100 Ω input resistor, Channel 2. 6 V REF2 Reference Voltage 2. Reference voltage for biasing ac-coupled inputs, Channel 2. 7, 14 V EE Negative Supply Voltage. 8, 13 V CC Positive Supply Voltage. Pin 8 and Pin 13 are not strapped internally. 10 Q2 Noninverting Output 2. 12 Q1 Noninverting Output 1. 15 V REF1 Reference Voltage 1. Reference voltage for biasing ac-coupled inputs, Channel 1. 16 V T1 Center Tap 1. Center tap of 100 Ω input resistor, Channel 1. of the package is connected to this exposed pad. Allow sufficient clearance to vias and other components.

  1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
  2. EXPOSED PAD. THE EXPOSED PAD IS NOT ELECTRICALLY CONNECTED TO ANY PART OF THE CI RCUIT.

IS CONNECTED TO THIS EXPOSED PAD. ALLOW SUFFICIENT CLEARANCE TO VIAS AND OTHER CO MPONENTS. Figure 6. ADCLK925 Pin Configuration Table 6. Pin Function Descriptions for 1:2 ADCLK925 Buffer 3, 4, 5, 6 NC No Connect. No physical connection to the die. 7, 14 V EE Negative Supply Voltage. 8, 13 V CC Positive Supply Voltage. 10 Q2 Noninverting Output 2. 12 Q1 Noninverting Output 1. 15 V REF Reference Voltage. Reference voltage for biasing ac-coupled inputs. 16 V T Center Tap. Center tap of 100 Ω input resistor. of the package is connected to this exposed pad. Allow sufficient clearance to vias and other components.

techniques must be used to achieve the specified performance. performance in the target application. effectiveness of the bypass at high frequencies. dependent propagation delay dispersion. Figure 25. Simplified Schematic Diagram of techniques are essential to obtaining the specified performance. performance by reducing the effective input slew rate. side should normally be connected to the reference pin provided. differential and common-mode ranges. and supply the input bias currents. random jitter is affected most by the slew rate of the input signal.

0Ω resistors are NOT to be installed. Jumpers are NOT to be installed. 0Ω resistors are NOT to be installed. Figure 30. Evaluation Board Schematic

0.05 MAX

0.02 NOM

0.20 REF

0.20 MIN

COMPLIANT TOJEDEC STANDARDS MO-220-WEED-6. Figure 31. 16-Lead Lead Frame Chip Scale Package [LFCSP]

ADCLK905/ADCLK907/ADCLK925 Data Sheet Rev. B | Page 16 of 16 NOTES ©2007–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06318-0-2/17(B)