ADCLK846 AD | Alldatasheet
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Technical content
1.8 V, 6 LVDS/12 CMOS Outputs
Low Power Clock Fanout Buffer ADCLK846 Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved.
FEATURES
Selectable LVDS/CMOS outputs Up to 6 LVDS (1.2 GHz) or 12 CMOS (250 MHz) outputs <16 mW per channel (100 MHz operation) 54 fs integrated jitter (12 kHz to 20 MHz) 100 fs additive broadband jitter 2.0 ns propagation delay (LVDS) 135 ps output rise/fall (LVDS) 65 ps output-to-output skew (LVDS) Sleep mode Pin-programmable control
1.8 V power supply
APPLICATIONS
Low jitter clock distribution Clock and data signal restoration Level translation Wireless communications Wired communications Medical and industrial imaging ATE and high performance instrumentation FUNCTIONAL BLOCK DIAGRAM OUT0 (OUT0A) OUT0 (OUT0B) OUT1 (OUT1A) OUT1 (OUT1B) OUT2 (OUT2A) OUT2 (OUT2B) OUT3 (OUT3A) OUT3 (OUT3B) OUT4 (OUT4A) OUT4 (OUT4B) OUT5 (OUT5A) OUT5 (OUT5B) LVDS/CMOS LVDS/CMOS CLK CTRL_A CTRL_B SLEEP VREF CLK ADCLK846 07226-001 Figure 1. GENERAL DESCRIPTION The ADCLK846 is a 1.2 GHz/250 MHz, LVDS/CMOS, fanout buffer optimized for low jitter and low power operation. Possible configurations range from 6 LVDS to 12 CMOS outputs, including combinations of LVDS and CMOS outputs. Two control lines are used to determine whether fixed blocks of outputs are LVDS or CMOS outputs. The clock input accepts various types of single-ended and differential logic levels including LVPECL, LVDS, HSTL, CML, and CMOS. Table 8 provides interface options for each type of connection. The SLEEP pin enables a sleep mode to power down the device. This device is available in a 24-pin LFCSP package. It is specified for operation over the standard industrial temperature range of −40°C to +85°C.
Rev. A | Page 2 of 16 TABLE OF CONTENTS Using the ADCLK846 Outputs for ADC Clock
REVISION HISTORY
6/09—Rev. 0 to Rev. A 4/09—Revision 0: Initial Version
Rev. A | Page 3 of 16 SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Typical values are given for VS = 1.8 V and TA = 25°C, unless otherwise noted. Minimum and maximum values are given over the full VS = 1.8 V ± 5% and TA = −40°C to +85°C variations, unless otherwise noted. Input slew rate > 1 V/ns, unless otherwise noted. Table 1. Parameter Symbol Min Typ Max Unit Conditions CLOCK INPUTS Differential input Input Frequency 0 1200 MHz Input Sensitivity, Differential 150 mV p-p Jitter performance is improved with higher slew rates (greater voltage swing) Input Level 1.8 V p-p Larger voltage swings can turn on the protection diodes and can degrade jitter performance Input Common-Mode Voltage VCM V S/2 − 0.1 VS/2 + 0.05 V Inputs are self-biased; enables ac coupling Input Common-Mode Range VCMR 0.4 VS − 0.4 V Inputs are dc-coupled with 200 mV p-p signal applied Input Voltage Offset 30 mV Input Sensitivity, Single-Ended 150 mV p-p CLK ac-coupled; CLK ac-bypassed to ground Input Resistance (Differential) 7 kΩ Input Capacitance CIN 2 pF Input Bias Current (Each Pin) −350 +350 μA Full input swing LVDS CLOCK OUTPUTS Termination = 100 Ω; differential (OUTx, OUTx) Output Frequency 1200 MHz See Figure 9 for a swing vs. frequency plot Differential Output Voltage VOD 247 344 454 mV ΔV OD 50 mV Offset Voltage VOS 1.125 1.25 1.375 V ΔV OS 50 mV Short-Circuit Current ISA, ISB 3 6 mA Each pin (output shorted to GND ) CMOS CLOCK OUTPUTS Single-ended; termination = open OUTx and OUTx in phase Output Frequency 250 MHz With 10 pF load each output; see Figure 16 for swing vs. frequency Output Voltage High VOH V S − 0.1 V At 1 mA load VS − 0.35 V At 10 mA load Output Voltage Low VOL 0.1 V At 1 mA load
0.35 V At 10 mA load
Output Voltage VS/2 − 0.1 VS/2 V S/2 + 0.1 V ±500 μA Output Resistance 60 Ω Output Current 500 μA
Rev. A | Page 4 of 16 TIMING CHARACTERISTICS Table 2. Parameter Symbol Min Typ Max Unit Conditions LVDS OUTPUTS Termination = 100 Ω differential; 3.5 mA Output Rise/Fall Time tR, tF 135 235 ps 20% to 80% measured differentially Propagation Delay, CLK-to-LVDS Output tPD 1.5 2.0 2.7 ns VICM = VREF, VID = 0.5 V Temperature Coefficient 2.0 ps/°C Output Skew1 All LVDS Outputs on the Same Part 65 ps All LVDS Outputs Across Multiple Parts 390 ps Additive Time Jitter Integrated Random Jitter 54 fs rms BW = 12 kHz to 20 MHz, CLK = 1000 MHz 74 fs rms BW = 50 kHz to 80 MHz, CLK = 1000 MHz 86 fs rms BW = 12 kHz to 20 MHz, CLK = 1000 MHz Broadband Random Jitter2 150 fs rms Input slew rate = 1 V/ns Crosstalk-Induced Jitter 260 fs rms Calculated from spur energy with an interferer
10 MHz offset from carrier
CMOS OUTPUTS Termination = open Output Rise/Fall Time tR, tF 525 950 ps 20% to 80%; CMOS load = 10 pF Propagation Delay, CLK-to-CMOS Output tPD 2.5 3.2 4.2 ns 10 pF load Temperature Coefficient 2.2 ps/°C Output Skew2 All CMOS Outputs on the Same Part 175 ps All CMOS Outputs Across Multiple Parts 640 ps Additive Time Jitter Integrated Random Jitter 56 fs rms BW = 12 kHz to 20 MHz, CLK = 200 MHz Broadband Random Jitter3 100 fs rms Input slew = 2 V/ns; see Figure 11 Crosstalk-Induced Jitter 260 fs rms Calculated from spur energy with an interferer LVDS Output(s) and CMOS Output(s) on the Same Part 0.8 1.6 ns CMOS load = 10 pF and LVDS load = 100 Ω 1 This is the difference between any two similar delay paths while operating at the same voltage and temperature. 2 Measured at rising edge of clock signal. 3 Calculated from SNR of ADC method.
Table 3. Clock Output Phase Noise
1000 MHz −90 dBc/Hz At 10 Hz offset
200 MHz −100 dBc/Hz At 10 Hz offset
Table 4. Control Pin Characteristics 1 These pins each have a 200 kΩ internal pull-down resistor. 2 Change in TPD per change in VS.
Rev. A | Page 6 of 16 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Rating Supply Voltage VS to GND 2 V Inputs CLK and CLK −0.3 V to +2 V CMOS Inputs −0.3 V to +2 V Outputs Maximum Voltage −0.3 V to +2 V Voltage Reference Voltage (VREF) −0.3 V to +2 V Operating Temperature Range Ambient −40°C to +85°C Junction 150°C Storage Temperature Range −65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DETERMINING JUNCTION TEMPERATURE To determine the junction temperature on the application PCB, use the following formula: TJ = TCASE + (ΨJT × PD) where: T J is the junction temperature (°C). TCASE is the case temperature (°C) measured by the customer at top center of the package. Ψ JT is indicated in Table 6. PD is the power dissipation. Values of θJA are provided for package comparison and PCB design considerations. θJA can be used for a first-order approximation of TJ by the equation TJ = TA + (θJA × PD) where TA is the ambient temperature (°C). Values of θJB are provided for package comparison and PCB design considerations. ESD CAUTION THERMAL PERFORMANCE Table 6. Parameter Symbol Description Value1 Unit Junction-to-Ambient Thermal Resistance θJA Still Air Per JEDEC JESD51-2 0.0 m/sec Airflow 57.0 °C/W Moving Air θJMA Per JEDEC JESD51-6 1.0 m/sec Airflow 49.8 °C/W 2.5 m/sec Airflow 44.7 °C/W Junction-to-Board Thermal Resistance θJB Moving Air Per JEDEC JESD51-8 1.0 m/sec Airflow 35.2 °C/W Junction-to-Case Thermal Resistance θJC Moving Air Per MIL-STD 883, Method 1012.1 Die-to-Heat Sink 2.0 °C/W Junction-to-Top-of-Package Characterization Parameter ΨJT Still Air Per JEDEC JESD51-2 0 m/sec Airflow 1.0 °C/W 1 Results are from simulations. The PCB is a JEDEC multilayer type. Thermal performance for actual applications requires careful inspection of the conditions in the application to determine if they are similar to those assumed in these calculations.
15 OUT3 (OUT3A)
17 OUT2 (OUT2B)
18 OUT2 (OUT2A)
14 OUT3 (OUT3B)
- EXPOSED PADDLE MUST BE CONNECTED TO GND.
Figure 2. Pin Configuration Table 7. Pin Function Descriptions 2 CLK Clock Input (Negative). 3 CLK Clock Input (Positive). 8 OUT5 (OUT5B) Complementary Side of Differential LVDS Output 5, or CMOS Output 5 on Channel B. 9 OUT5 (OUT5A) True Side of Differential LVDS Output 5, or CMOS Output 5 on Channel A. 11 OUT4 (OUT4B) Complementary Side of Differential LVDS Output 4, or CMOS Output 4 on Channel B. 12 OUT4 (OUT4A) True Side of Differential LVDS Output 4, or CMOS Output 4 on Channel A. 14 OUT3 (OUT3B) Complementary Side of Differential LVDS Output 3, or CMOS Output 3 on Channel B. 15 OUT3 (OUT3A) True Side of Differential LVDS Output 3, or CMOS Output 3 on Channel A. 17 OUT2 (OUT2B) Complementary Side of Differential LVDS Output 2, or CMOS Output 2 on Channel B. 18 OUT2 (OUT2A) True Side of Differential LVDS Output 2, or CMOS Output 2 on Channel A. 20 OUT1 (OUT1B) Complementary Side of Differential LVDS Output 1, or CMOS Output 1 on Channel B. 21 OUT1 (OUT1A) True Side of Differential LVDS Output 1, or CMOS Output 1 on Channel A. 23 OUT0 (OUT0B) Complementary Side of Differential LVDS Output 0, or CMOS Output 0 on Channel B. 24 OUT0 (OUT0A) True Side of Differential LVDS Output 0, or CMOS Output 0 on Channel A. (25) EPAD Exposed Paddle. The exposed paddle must be connected to ground.
0.60 MAX
2.50 REF
0.80 MAX
0.65 TYP
0.05 MAX
0.02 NOM
0.080.20 REF
0.23 MIN
Figure 33. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Rev. A | Page 16 of 16 NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D07226-0-6/09(A)