ADCA5191

ADCA5191 (Rev.A)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 24

Technical content

5 MHz to 1800 MHz Broadband CATV Amplifier

Rev. A DOCUMENT FEEDBACK TECHNICAL SUPPORT Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

FEATURES

►Frequency range of 5 MHz to 1800 MHz ►High gain of 25.8 dB at 1800 MHz ►Excellent reverse isolation: −37 dB typical ►Excellent NPR (MER) performance: 51 dB at 67 dBmV TCP ►Excellent return losses: ►−20 dB at 45 MHz to 1218 MHz ►−18 dB at 1218 MHz to 1800 MHz ►VDD operation: 5.0 V to 8.0 V ►Configurable dc current (total) from 250 mA to 530 mA ►32-lead, 5 mm x 5 mm, LFCSP

APPLICATIONS

►45 MHz to 1800 MHz CATV infrastructure amplifier systems ►5 MHz to 700 MHz upstream ►Remote physical layer (PHY) ►DOCSIS 3.1 and DOCSIS 4.0 compliant FUNCTIONAL BLOCK DIAGRAM Figure 1. GENERAL DESCRIPTION The ADCA5191 is a medium power gain block amplifier that pro- vides excellent linearity across a flexible bias range allowing power efficient design implementation for various applications. The device provides 25.8 dB of flat gain up to 1800 MHz, making this ideal for Data Over Cable Service Interface Specification (DOC- SIS) 4.0 downstream applications. The device is also well suited for upstream applications to 700 MHz as the output stage. It is conven- iently packaged in an industry-standard, 5 mm × 5 mm, 32-lead, lead frame chip-scale package (LFCSP) with an exposed pad on the bottom of the package for improved thermal performance.

analog.com Rev. A | 2 of 24 S-Parameters for Downstream Application S-Parameters for Upstream Application DOCSIS 4.0 Downstream Performance DOCSIS 3.1 Downstream Performance DOCSIS Upstream Performance (See Soldering Information and Recommended Downstream Cable Application Circuit Bill of Upstream Cable Applications Circuit Bill of

REVISION HISTORY

8/2022—Rev. 0 to Rev. A 5/2022—Revision 0: Initial Version

source impedance (ZS) = load impedance (ZL) = 75 Ω, unless otherwise noted. Table 1. Downstream Performance 1 The slope is defined as the delta of the gain at the start frequency and the gain at the stop frequency. 2 Flatness is defined as the maximum deviation from a linear best-fit of the gain in the frequency range of operation.

See the application circuit in Figure 40. VDD = 8.0 V, IDD = 470 mA, TPADDLE = 35 °C, and ZS = ZL = 75 Ω, unless otherwise noted. Table 2. Upstream Performance 1 Flatness is defined as the maximum deviation from a linear best-fit of the gain in the frequency range of operation. See the application circuit in Figure 39. VDD = 8.0 V, IDD = 470 mA, TPADDLE = 35°C, and ZS = ZL = 75 Ω, unless otherwise noted. Table 3. Distortion Data 1 The noise power ratio gives an equivalent result to the standard modulation error rate (MER) testing but with improved dynamic range using an industry-accepted method.

See the application circuit in Figure 39. VDD = 8.0 V, IDD = 470 mA, TPADDLE = 35 °C, and ZS = ZL = 75 Ω, unless otherwise noted. Table 4. Distortion Data 1 The noise power ratio gives an equivalent result to the standard MER testing but with improved dynamic range using an industry-accepted method. See the application circuit in Figure 40. VDD = 8.0 V, IDD = 470 mA, TPADDLE = 35°C, and ZS = ZL = 75 Ω, unless otherwise noted. Table 5. Distortion Data 1 The noise power ratio gives an equivalent result to standard MER testing but with improved dynamic range using an industry-accepted method.

Table 6. Absolute Maximum Ratings ing conditions for extended periods may affect product reliability. Considerations section for additional information. Table 7. Thermal Resistance sitive devices in an ESD protected area only. Human body model (HBM) per ANSI/ESDA/JEDEC JS-001. Table 8. ADCA5191, 32-Lead LFCSP damage may occur on devices subjected to high energy ESD. performance degradation or loss of functionality.

Figure 21. NPR vs. TCP Over Frequency, 10 dB Tilt, No Offset at 1026 MHz,

analog.com Rev. A | 17 of 24 The ADCA5191 is a single-die, 1800 MHz differential cascode amplifier fabricated on a linear gallium arsenide (GaAs), pHEMT process. The device provides general-purpose linear gain suitable for a wide range of applications. When used with a recommended balun, the ADCA5191 can ach- ieve a 5.2 dB noise figure at 1800 MHz (3.8 dB noise figure at 1218 MHz) while holding excellent linearity for extended spectrum line extender input stage applications. The device has suitable drive capability to overcome nominal inser- tion losses introduced from automatic gain control and tilt functions. The ADCA5191 can also serve as an output stage for the upstream path at any DOCSIS 4.0 frequency split. Depending on the application, the ADCA5191 can be biased from 5.0 V through 8.0 V with currents from 250 mA to 530 mA. Opti- mized biasing for 5.0 V applications can be achieved with additional bill of material (BOM) changes.

and serves as the ac ground for the RF input signal. Ω outputs (RFON and RFOP) to a single-ended 75 Ω RF output. discussed in detail in the Supply Voltage and Bias Current section. Figure 39. Suggested Downstream Cable TV (CATV) Application Circuit

Table 10. Downstream Bill of Materials

the ac ground for the RF input signal. Ω outputs (RFIN and RFIP) to a single-ended 75 Ω RF output. Figure 40. Suggested Upstream CATV Application Circuit

Table 11. Upstream Bill of Materials

registered trademarks are the property of their respective owners. One Analog Way, Wilmington, MA 01887-2356, U.S.A. Figure 43. 32-Lead Lead Frame Chip Scale Package [LFCSP]