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DOCSIS 3.1 Power Doubler Amplifier,
45 MHz to 1218 MHz
Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2021 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
FEATURES
Drop-in replacement for RFCM3327 and RFCM3328 Total composite power: 73 dBmV High power gain: 25 dB at 1218 MHz Excellent linearity Very low distortion Composite triple beat: −80 dBc typical Composite second-order: −80 dBc typical Carrier to intermodulation noise: 59 dB typical Low noise figure: 3 dB typical at 45 MHz and 4 dB typical at
1218 MHz
Configurable current: 350 mA to 480 mA at 24 V Temperature monitor 9-terminal thermally enhanced chip array small outline no lead cavity [LGA_CAV]
APPLICATIONS
45 MHz to 1218 MHz community access television (CAT V)
infrastructure amplifier systems Remote physical layer (PHY) DOCSIS 3.1 compliant GENERAL DESCRIPTION The Analog Devices, Inc., ADCA3270 is a 24 V power doubler, monolithic microwave IC (MMIC) with 25 dB of power gain. The device achieves high RF output up to 73 dBmV composite power under 18 dB tilt conditions by using advanced circuit design techniques with gallium arsenide (GaAs), pseudomorphic high electron transistor (pHEMT), and gallium nitride (GaN) HEMT technologies. The dc current and supply voltage can be adjusted externally for optimum distortion performance vs. power consumption over a range of output levels. The ADCA3270 provides high gain, simplifying the design and manufacturing of DOCSIS 3.1 infrastructure equipment. The ADCA3270 is packaged in a 9-terminal thermally enhanced chip array small outline no lead cavity [LGA_CAV] with an industry-standard footprint. FUNCTIONAL BLOCK DIAGRAM ADCA3270 OUTPUT GND TEMPERATURE MONITOR TSENVCC NTC DNC 2 3 6 87 INPUT RFIP RFIN RFOP RFON VCC 4 5 24276-001 Figure 1.
Rev. 0 | Page 2 of 14 TABLE OF CONTENTS Soldering Information and Recommended PCB Land Pattern
REVISION HISTORY
7/2021—Revision 0: Initial Version
Rev. 0 | Page 3 of 14 SPECIFICATIONS GENERAL PERFORMANCE Supply voltage (VCC) = 24 V , exposed paddle temperature (TPADDLE) = 35°C, source impedance (ZS) = load impedance (ZL) = 75 Ω, and dc current (ICC) = 480 mA, unless otherwise noted. Table 1. Parameter Symbol Min Typ Max Unit Test Conditions/Comments POWER GAIN S21 22.0 23.6 25.0 dB Frequency = 45 MHz, see Figure 4 23.0 25 26.5 dB Frequency = 1218 MHz, see Figure 4 SLOPE STRAIGHT LINE1 2.0 dB Frequency = 45 MHz to 1218 MHz FLATNESS OF FREQUENCY RESPONSE2 0.75 dB Frequency = 45 MHz to 1218 MHz REVERSE ISOLATION S12 28 dB Frequency = 45 MHz to 1218 MHz, see Figure 5 RETURN LOSS See Figure 3 and Figure 6 Input S11 −20 dB Frequency = 45 MHz to 320 MHz −15 dB Frequency = 320 MHz to 640 MHz −12 dB Frequency = 640 MHz to 870 MHz −12 dB Frequency = 870 MHz to 1000 MHz −12 dB Frequency = 1000 MHz to 1218 MHz Output S22 −20 dB Frequency = 45 MHz to 320 MHz −20 dB Frequency = 320 MHz to 640 MHz −20 dB Frequency = 640 MHz to 870 MHz −20 dB Frequency = 870 MHz to 1000 MHz −18 dB Frequency = 1000 MHz to 1218 MHz NOISE FIGURE 3 dB Frequency = 45 MHz 4 dB Frequency = 1218 MHz SUPPLY Voltage V CC 18 24 26 V Supply voltage can be adjusted for different applications, see the Applications Information section DC Current (Total) I CC (TOTAL) 350 480 500 mA Can be biased between 350 mA and 480 mA (see the Applications Information section) RF Input Bias Voltage V BIAS 1.08 V 1 Slope straight line is defined as the delta between the gain at the start frequency and the gain at the stop frequency. 2 Flatness of frequency response is defined as the delta between the gain at any frequency between the start and stop frequencies and a straight line reference drawn between the gain at the start frequency and the gain at the stop frequency. DISTORTION DATA (ALL DIGITAL CHANNEL PLAN) VCC = 24 V , TPADDLE = 35°C, and ZS = ZL = 75 Ω, unless otherwise noted. Table 2. Parameter Symbol Min Typ Max Unit Test Conditions/Comments TOTAL COMPOSITE POWER TCP 73 dBmV 18 dB tilt, 190 digital (256 QAMs) channels from 57 MHz to
1215 MHz
73 dBmV 9 dB tilt, 190 digital (256 QAMs) channels from 57 MHz to Modulation Error Rate MER 47 dB Bit Error Rate BER <1 × 10 −10 PostViterbi, 18 dB tilt, 190 digital (256 QAMs) channels from
57 MHz to 1215 MHz
<1 × 10 −9 PreViterbi, 9 dB tilt, 190 digital (256 QAMs) channels from
Rev. 0 | Page 4 of 14 DISTORTION DATA (MIXED SIGNAL CHANNEL PLAN) VCC = 24 V, TFLANGE = 35°C, and ZS = ZL = 75 Ω, unless otherwise noted. Table 3. Parameter Symbol Min Typ Max Unit Test Conditions/Comments DISTORTION TCP = 72.4 dBmV, the analog and digital channel plan consists of 18 dB extrapolated tilt, 79 continuous wave channels plus 111 digital channels, a National Television System Committee (NTSC) frequency raster range of 55.25 MHz to 547.25 MHz, and −6 dB offset Composite Triple Beat CTB −80 dBc Defined by the National Cable and Telecommunications Association (NCTA) Composite Second-Order CSO −80 dBc Defined by NC TA Carrier to Intermodulation Noise 59 dB Defined by American National Standard/Society of Cable Telecommunications Engineers (ANSI/SCTE) 17 (test procedure for carrier to noise)
PCB thermal design is required. Table 5. Thermal Resistance
1 Thermal resistance (θJC) is defined as between the TPADDLE and the internal
ESD-sensitive devices in an ESD protected area only. Human body model (HBM) per ANSI/ESDA/JEDEC JS-001. Table 6. ADCA3270, 6-Terminal LGA_CAV
- EXPOSED PAD. SOLDER THE EXPOSED
Figure 2. Pin Configuration Table 7. Pin Function Descriptions 1, 4 RFIP , RFIN RF Differential Inputs. 5, 9 RFON, RFOP RF Differential Outputs. 7 VCC Positive Supply Voltage, 24 V Typical. 8 TSEN Temperature Sensing Pin. Exposed Pad. Solder the exposed paddle to a low impedance electrical and thermal ground plane.
The ADCA3270 is a balanced amplifier packaged in a LGA_CAV. frequency of operation is from 45 MHz to 1218 MHz. systems targeting DOCSIS 3.1 and legacy DOCSIS standards. Figure 15. Simplified Schematic
2.50 MAX
6.80 BSC
7.40 BSC
1.95 REF
Figure 26. 9-Terminal Chip Array Small Outline No Lead Cavity [LGA_CAV] registered trademarks are the property of their respecti ve owners.