ADC912A

ADC912A AD | Alldatasheet

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REV.B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a ADC912A Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001 CMOS Microprocessor-Compatible 12-Bit A/D Converter FUNCTIONAL BLOCK DIAGRAM THREE-STATE OUTPUT DRIVERS THREE-STATE OUTPUT DRIVERS CLOCK OSCILLATOR CONTROL LOGIC MULTIPLEXER 12-BIT LATCH 12-BIT DAC SUCCESSIVE APPROXIMATION REGISTER ADC912A AGND VREFIN AIN VDD VSS CLK OUT CLK IN HBEN CS RD BUSY D11 D7D8 D4 DGND D3/11 D0/8 5k/H9024 ANALOG INPUT DIGITAL OUTPUT 100 TRANSITION NOISE Figure 2. Transition Noise Cross Plot

FEATURES

Low Transition Noise between Code 12-Bit Accurate /H115501/2 LSB Nonlinearity Error over Temperature No Missing Codes at All Temperatures 10 /H9262s Conversion Time Internal or External Clock 8- or 16-Bit Data Bus Compatible Improved ESD Resistant Design Latchup Resistant Epi-CMOS Processing Low 95 mW Power Consumption Space-Saving 24-Lead 0.3" DIP, or 24-Lead SOIC

APPLICATIONS

The ADC912A is a monolithic 12-bit accurate CMOS A/D converter. It contains a complete successive-approximation A/D converter built with a high-accuracy D/A converter, a precision bipolar transistor high-speed comparator, and successive- approximation logic including three-state bus interface for logic compatibility. The accuracy of the ADC912A results from the addition of precision bipolar transistors to Analog Devices’ advanced-oxide isolated silicon-gate CMOS process. Particular attention was paid to the reduction of transition noise between adjacent codes achieving a 1/6 LSB uncertainty. The low noise design produces the same digital output for dc analog inputs not located at a transition voltage, see Figures 1 and 2. NPN digital output transistors provide excellent bus interface timing, 125 ns access and bus disconnect time which results in faster data transfer without the need for wait states. An external 1.25 MHz clock provides a 10 µs conversion time. In stand-alone applications an internal clock can be used with external crystal. An external negative five-volt reference sets the 0 V to 10 V input range. Plus 5 V and minus 12 V power supplies result in 95 mW of total power consumption. 256 128 192 2045 2049 204820472046

256 SUCCESSIVE

AIN = 4.99756V OUTPUT CODE – Decimal NUMBER OF OCCURRENCES Figure 1. Code Repetition

Figure 5. Parallel Read Timing Diagram, Slow-Memory Figure 6. Two-Byte Read Timing Diagram, Slow-Memory

3 CL = 100 pF 65 125 ns

3 CL = 100 pF –30 0 ns

2All input control signals are specified with t R = tF = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. 3t3, t4, and t6 are measured with the load circuits of Figure 3 and timed for and output to cross 0.8 V or 2.4 V. 4t7 is the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 4. Specifications subject to change without notice. Figure 7. Parallel Read Timing Diagram, ROM Mode Figure 8. Two-Byte Read Timing Diagram, ROM Mode

REV. B ADC912A –4– CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADC912A features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE ABSOLUTE MAXIMUM RATINGS (TA = 25°C, unless otherwise noted) Digital Input Voltage to DGND, Digital Output Voltage to DGND, Table I. Analog Input to Digital Output Code Conversion Analog Input Voltage Output Code *

0 V to 10 V –10 V to +10 V DB 11 (MSB) DB0 (LSB)

+FS – 1 LSB 9.9976 9.99951 1111 1111 1111 +FS – 1 1/2 LSB 9.9964 9.9927 1111 1111 1111φ Midscale + 1/2 LSB 5.0012 0.0024 1000 0000 000 φ Midscale 5.0000 0.0000 1000 0000 0000 –FS + 1/2 LSB 0.0012 –9.9976 0000 0000 000 φ –FS 0.0000 –10.000 0000 0000 0000 *The symbol” φ” indicates a 0 or 1 with equal probability. Operating Temperature Range Thermal Resistance θJA ORDERING GUIDE Temperature INL Package Model Range (LSB) Package Description Option ADC912AFP –40 °C to +85°C ±1 24-Lead Narrow-Body Plastic N-24 ADC912AFS –40 °C to +85°C ±1 24-Lead Wide-Body SOIC R-24

for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assem bly and testing. Figure 9. Burn-In Circuit

l AIN Analog Input. 0 V to 10 V. 2 VREFIN Voltage Reference Input. Requires external –5 V reference. *D11 . . . D 0/8 are the ADC data output pins. ceramic resonator may be connected between CLK IN (Pin 17) and CLK OUT (Pin 18). CLK IN (Pin 17) description for crystal (resonator). conversion start when HBEN is high. state drivers and initiates a conversion if CS and HBEN are low. three-state drivers and initiates a conversion if RD and HBEN are low. 22 BUSY BUSY output indicates converter status. BUSY is LOW during conversion. 23 V SS Negative Supply, –12 V or –15 V. 24 V DD Positive Supply, +5 V. Figure 10. Basic Connection Diagram

REV. B –7– Typical Performance Characteristics– ADC912A 0.4 4096 –0.4 –0.2 0.2 20481024 3072 DIGIT AL OUTPUT CODE INL–NONLINEARITY ERROR – LSB TPC 1. Nonlinearity Error vs. Digital Output Code 125 –50 –75 10025 50–25 0 75 TEMPERA TURE – C SUPPL Y CURRENT – mA CS, RD = LOGIC HIGH AIN = 10V CLK = 1MHz XT AL ISS @ VSS = –15.75V VDD @ 5.25V TPC 4. Supply Current vs. Temperature 256 128 192 2045 2049 204820472046 AIN = 4.99756V OUTPUT CODE – Decimal NUMBER OF OCCURRENCES TPC 7. Code Repetition 125 –50 –75 10025 50–25 0 75 TEMPERA TURE – C OFFSET ERROR – LSB TPC 2. Offset Error vs. Temperature 100k10k CLK IN FREQUENCY – Hz COUT = 20pF fCONV = 1/13 fCLK IN TA = 25 C EXT CLK IN PDISS = IDD /H11547 5 + ISS /H11547 12 PDISS – mW TPC 5. Power Dissipation vs. CLK IN Frequency ANALOG INPUT DIGITAL OUTPUT 100 TRANSITION NOISE TPC 8. Transition Noise Cross Plot 125 –50 –75 10025 50–25 0 75 TEMPERA TURE – C GAIN ERROR – LSB TPC 3. Gain Error vs. Temperature –50 –20 –40 –30 –10 5432 VO OUTPUT VOL T AGE – V olts DIGIT AL OUTPUT CURRENT – mA ISINK ISOURCE TPC 6. Digital Output Current vs. Output Voltage 1015 5 CONVERSION TIME – /H9262s LINEARITY ERROR – LSB VDD = +5V VSS = –12V TA = 25/H11543C TPC 9. Linearity Error vs. Conversion Time

and noninverting configurations given in Figures 17 and 18. Figure 17. Noninverting Bipolar Analog Input Operation

3 AGND

Figure 18. Inverting Bipolar Analog Input Figure 19. Ideal Input/Output Transfer Characteristics for

REV. B ADC912A –14– OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 24-Lead Narrow Body Plastic DIP Package (N-24) 11 2 PIN 1 1.275 (32.30) 1.125 (28.60) 0.280 (7.11) 0.240 (6.10) 0.195 (4.95) 0.115 (2.93) 0.015 (0.381) 0.008 (0.204) 0.325 (8.25) 0.300 (7.62) SEATING PLANE 0.060 (1.52) 0.015 (0.38)0.210 (5.33) MAX 0.022 (0.558) 0.014 (0.356) 0.200 (5.05) 0.125 (3.18) 0.150 (3.81) MIN 0.100 (2.54) BSC 0.070 (1.77) 0.045 (1.15) 24-Lead Wide Body SOIC Package (R-24) 0.0125 (0.32) 0.0091 (0.23) 8/H11543 0/H11543 0.0291 (0.74) 0.0098 (0.25)/H11547 45/H11543 0.0500 (1.27) 0.0157 (0.40) SEATING PLANE 0.0118 (0.30) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.1043 (2.65) 0.0926 (2.35) 0.0500 (1.27) BSC 24 13 121 0.4193 (10.65) 0.3937 (10.00) 0.2992 (7.60) 0.2914 (7.40)PIN 1 0.6141 (15.60) 0.5985 (15.20)

REV. B –15– Location Page Data Sheet changed from REV. A to REV. B.

–16– C00384–0–6/01(B) PRINTED IN U.S.A.