ADC-908 ETC1 | Alldatasheet
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CMOS MICROPROCESSOR-COMPATIBLE FAST 8-BIT A/D CONVERTER FEATURES operations. This input structure permits the ADC-808 to be © 8-Bit Resolution and Accuracy used as a memory-mapped input device. Depending on the ¢ No Missing Codes over Full Temperature Range control timing waveforms, the ADC-908 is interfaced like © 6us Conversion Time static RAM, ROM, or slow memory. @ Flexible uP Interface The low power consumption of the ADC-908 is derived from a ¢ 2.5mA Maximum Standby Current single +5V supply. A negative reference voltage must also be ¢ Replaces AD7574 with Improved Speed supplied. Optimum accuracy is achieved when the reference ¢ Available in Die Form is at ~10.00V with a low output resistance. For a low-cost precision ~10V/-10.24V reference, ask your PMI sales repre- ORDERING INFORMATION ' sentative about the REF-08. PACKAGE: 18-PIN DIP AND SO With its on-board comparator, interface logic, optional internal EXTENDED clock, and +5V operation, the ADC-908 is the ideal low-cost MILITARY® INDUSTRIAL COMMERCIAL solution for microprocessor-based 8-bit A/D systems. INL ONL. TEMPERATURE TEMPERATURE TEMPERATURE (188) (LSB) -S8'CTO+I25' aC TOES FC TOLOE PMI's ADC-908 is pin-and-function compatible with the 2 aala” ADOBOBAX ST ADOBDEEX ADGsongr ”SC*«*&R'M-7574, but offers faster conversion time and faster micro- 3/2 3/8 ADCROBAX 109086 : cae ie —«ADGBOBBX AD are Apcs08GP processor bus interface timing. Conversion time has been sis a78 — ADCOOBFP = reduced by 60% and most key timing specifications, including 23/4 27/8 - ADC908FS =- data access time, START command propagation delay * Fordevices processedin total compliance to MiL-STD-683, add /883 ater part (twapo), and reset time, have been improved. ‘number. Consult factory tor 883 data sheet + Burn-in is available on commercial and industrial temperature range parts in CerDIP. plastic DIP, and TO-can packages. For ordering information, see PIN CONNECTIONS PM's Data Book, Section 2 veo C7 [i] oano GENERAL DESCRIPTION vaur Fae 48-PIN CERDIP The ADC-908 is a monolithic CMOS successive-approxima- ors Gy] aes (Suffix) tion analog-to-digital converter. When used with a 1.35MHz Aw (E] [is) ® clock, a conversion time of 6us is achieved, with full accuracy sono Ge [=] sey «18-PIN PLASTIC DIP ‘over the operating temperature range. a7 mse) [of [73) 080 se) (P-Suttix) The ADC-908 outputs use 3-state logic, allowing direct con- 06 [7] [=2}081 wen SOL nection to the data bus or system input port. Active-LOW chip os (24 [aloe (S-Sutfixy select (CS) and read/write (RD) inputs are used to control all poe] felee FUNCTIONAL DIAGRAM Yoo cu 1 | oes cowrmoctéere J] Bors © © wusy v i _ Vv * 12-10 10/89, Rev. B
Exp ADC-908 CMOS MICROPROCESSOR-COMPATIBLE FAST 8-BIT A/D CONVERTER ABSOLUTE MAXIMUM RATINGS (T, = +25°C, unless Storage Temperature ...svnnnnnnissennnee 65°C 10 +150°C oo , PACKAGE TYPE Note2) UNITS Vo 9tODGND vncnnnnnnninnnninnnnnnnas OV,47,0V PACKAGE TYPE @yaN0102)__ je UNITS. AGND to GND... oessesenssenssnnsstssseessssanssnnnntseceeetes “O.3V, Voy 18-Pin Hermetic DIP (X) 79 W “cw GS, RD 0 DGND -...eersssoresernnseretrenssreernnee “O.3V, Voy + =3V 18-Pin Plastic DIP (P) 70 30 “cw CLK, BUSY to DGND oo.cssscnsninnnnninnnnt “0.8, Vpyq NOTES: Boggs Ain cssssssessssessseetssesunsstnsssunssttsessinseseseereerensees #20V 1. Digital pins are zener protected. However, proper ESD handling precautions V, ‘OV, -20V _are recommended, REF nmninnmnnmnninnrinemninninninnesnnnesne OV) 2. ©, specter worst case mounting condtons, i 848 specif for Operating Temperature Range «device in socket for TO, CarDIP, P-DIP, and LCC packages. @,, is specified ADC-90B8AX, BX ooocssescsssssssssnnnneeeeesssssssnnnns “SSC to +125°C. for device soldered to printed circuit board for SO and PLCC packages. ADC-908EX, FX, FP, FS oo nnnnntnnnrnse 40°C to 485°C ELECTRICAL CHARACTERISTICS atV,,, = +5V, Vac, =—10V, Unipolar Configuration, Ro, , = 43k, Co, x = 100pF; 40°C = T, = +85°C for ADC-90BE/F, 0°C =< T, = +70°C for ADC-908G, -55°C = T, = +125°C for ADC-908A/B, unless otherwise noted. ‘ADC-908 PARAMETER sya. CONDITIONS MIN Tye Max units, ‘ACCURACY Resolution N 3 = Z ote Integral ‘NEIG Grades ar =e Nonlinearity INL iF Grades -ae - sa ise Diterentat ‘NEIG Grades ~aie - a Nonlinearity ONL BIF Grades -718 - +718 use AIEIG Grades T, = «25°C = = Ey 1, =FulTemp Range 45 - 445 Gain Error Srse BF Grades Ty= 25°C — - +6 ise Ty =FullTeme Range “65 - 465 EIG Grades T= 425°C “30 = 930 Th=Full Temp Range -50 = 480 Ofset Error Vase BIF Grades Th 125°C -60 - 460 ™ 1, = FullTamp Range 80 - +80 ‘ANALOG INPUTS Resistance Mismatch Cams APs “1 - “ * Input Resistance at Veg (Note 1) Pree . - 6 “° 12 Input Resistance Roors 10 - 30 «a “ a8 org Aw Ban Reterence Voltage Range Vace Specified Conversion Accuracy = 10 = vp Reference Voliage Range Vaee Degraded Conversion Accuracy 3 - 5 vB x revroree Curent ther Conversion Complete Prior to Reset - - 24 om Input Range [o] Unipolar Mode Vinw ~ 010+Vpegl = v2 Bipolar Mode Vine = Wrerlt+Vper! - <x g in 12-11 10/89, Rev.B <
Exp ADC-908 MICROPROCESSOR-COMPATIBLE FAST 8-BIT D/A CONVERTER ELECTRICAL CHARACTERISTICS at V,, = +5V, Vace =—10V, Unipolar Configuration, Roy , = 43k2, Coy, = 100pF; ~40°C ST, $+85°C for ADC-908E/F, 0°C < T, s +70°C for ADC-908G, -55°C < T, < +125°C for ADC-908A/B, unless otherwise noted. Continued aes ‘ADC-908 PARAMETER ‘SYMBOL CONDITIONS MIN Tye MAX UNITS: LOGIC INPUTS Input HIGH Voltage AD, CS inputs Yo 24 = = v Input LOW Voltage RD, CS Inputs Me = os y Input Current j a= 425°C = = 1 MA RD, GS inputs im Ta= Full Temp Range - = 10 Input Capacitance RD, CS Inpute (Note 6) = = s bell Input HIGH Voltage, - - Clock Input Vu 24 v Input LOW Voltage, Clock Input Mu 7 7 08 v Input HIGH Current, _ Clock Input i ~ 7 2 mA Input LOW Current, j Ta = +250 = = 1 wa Clock Input « Ty = Full Temp Range - = 10 Logic oureuts ‘Output HIGH Volta wero YO Isunce = OHA 40 - - v ‘Output LOW Voltage . _ SU, beo-y Vou ‘gnu = 16MA - o« v Floating Leakage j Ta = 425°C - = 1 a Current, DB0-7 Ka Ta = Full Temp Range - - 10 ” Floating State Output Capacitance Coz (Note 6) ~ ~ 7 oF POWER REQUIREMENTS Standby Current 10 Vop = +4.75V to +5.25V = = 25 mA DIGITAL INTERFACE TIMING GS Minimum ‘es Ter tme ° = = . ia = Tan - - ns Pulse With (Note 6) te ° = = FD to 6S Setup Time (Note 6) twses ° 7 i *s BUSY Load = 20pF T= +250 - - 120 GS 10 BUSY = Taw > > Bhed Propagation te TAS Tax - - 150 as olay Note 6 aro BUSY Loas = 100pF Th Tan - - 120 Ta = Tune = - ‘BUSY to RD Setup Time (Notes 2, 6) fash ° - - ne BUSY 10 OS ‘Setup Time (Note 6) teses ° _ ~ ns 12-12 10/89, Rev. B
[PMD ADC-908 CMOS MICROPROCESSOR-COMPATIBLE FAST 8-BIT A/D CONVERTER ELECTRICAL CHARACTERISTICS at V,,,. = +5V, Vac, = —10V, Unipolar Configuration, Ro, x = 43KQ, Coy, = 100pF; 40°C < Ty, ¢+85°C for ADC-908E/F, 0°C < Ty, $+70°C for ADC-908G, -55°C < ty! $+125°C for ADC-908A/B, unless otherwise noted. Continued ADC-908 PARAMETER ecooct__cowommone re wax nme Data Access Time t Ta = Tax - - a0 (Note 6) "aD Oy = 100pF ns Ta = +28°C - - 70 T= Twin - - 150, Ta = Tax _ — 230 i a Ta = Tax 40 - 140 GS to RD Hold t Tan tere = = beg . Requirement (Note 6) weseT Ta = Full Temp. Range 500 - - ns coment te tashnte - - : 2 now Nose (Notes 4, 5, 6) Internal Clock = - 7 RD HIGH to BUSY Cy = 20pF ROM Mode lwaPo Th Tan - - 400 ad (Notes 4, 5, 6) Ta = - 800 NoTEs: Seta BURN-IN CIRCUIT 2ot ZE - : 7 2 fe 5 en Fi RO a g 51 oxo wars [Re E Fee | [| 8 ar een cee ss 2 é Q - 8 g GS 12-13 10/89, Rev.B <
PMD ‘ADC-908 MICROPROCESSOR-COMPATIBLE FAST 6-BIT D/A CONVERTER = SSCA 908 MICROPROCESSOR-COMPATIBLE FAST 8-BIT D/A CONVERTER DICE CHARACTERISTICS he P_ Re my ia pa Sem ay | SN ap ft Loe = oma iy 1. Veo 10, DBS - “CLT — 2. Vrer 11. DB2 3. Bors 12. DBI a a 4. Ay 19. DBO(LSB) |e ee = 5. AGND 14. BUSY SUR anal Sy 6. DB7(MSB) 15. RD Te et Tau) 7 7 DB6 16. CS — —_ = 8. OBS 1 CLK | ETE Ea SESE 9. DB4 18, DGND [ES TE fe Sd Ob Sed Ul tr Ed TE For additional DICE ordering infromation, refer aA WA to PMI's Data Book, Secion 2. DIE SIZE 0.129 X 0.103 inch, 13,287 sq. mils (8.28 X 2.62 mm, 8.58 sq. mm) WAFER TEST LIMITS at Vop = +5V, Vcr = —10.000V, AGND = DGND = OV, T, = +25°C, unless otherwise noted. S———— ee errr ADC-908 PARAMETER syBot CONDITIONS ust units Resolution N _ _ _ 8 Bits MIN Integral Nonlinearity im 204 USB MAX Differential Nonlinearity DNL 278 USB MAX Gain Eror Grae 6B USB MAX. ‘Offset Error Vese_ - __260 . mv MAX Resistance Mismatch CoA Pas Fa % Max ows Ay ee Pree 515 ka MINIMAX Input Resistance ; wena Raors: Fin tw anne DIGITAL INPUTS —— Input HIGH Vortage at AD, CS Inputs Mi 24 vein Input LOW Voltage _at RO, GS inputs _ _ a oe _vax Input Current
7 GS inputs hw 1 A MAX
ae SB npn I“ Input HIGH Voltage Vn oa van Clock input : 7 __ input LOW Voltage Clock Input 7 Me _ _ _ oe Mac Input HIGH Current —— Clock Input ‘na 2 ma MAX ween topne e Input LOW Current Clock Input fhe 7 _ je HAMAX 12-14 10/89, Rev. B
Mp ADC-908 CMOS MICROPROCESSOR-COMPATIBLE FAST 8-BIT A/D CONVERTER WAFER TEST LIMITS at Vop = +5V. Vae¢ = —10.000V, AGND = DGND = OV, Ta = +25°C, unless otherwise noted. (Continued) ‘ADC-908 PARAMETER syMBOL CONDITIONS ust uNtts DIGITAL OUTPUTS Quout HIGH vatage Isounce = 400A ‘ van Floating Leakage Current xe 1 oA POWER REQUIREMENTS oo Standby Current ‘0 Voo = +475V to 625 25 mA MAX TIMING _ Conversion Time convent Static RAM Mode, External Clock, (= 1.36MHE 6 os MAX NOTE: Electrical tests are pectormed at water probe to the limits shown. Due to variations in assembly methods and normal yels toss, yield ater packaging isnot guarantees for stendara product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing. TYPICAL PERFORMANCE CHARACTERISTICS OFFSET ERROR LINEARITY ERROR vs CONVERSION TIME CONVERSION TIME vs vs CONVERSION TIME RAM MODE Rex AND Coix te" ee | | feet we Tee A on . sO ra on Kitt | Ee
1 ZY : pot ye
“ ~ LALA TT att TT aw itl | | eer rr ¢ a 5 es iat ee ds CONVERSION THME CONVERSION TMG) Foun) | GAIN ERROR CONVERSION TIME vs CONVERSION vs TEMPERATURE CONVERSION UNCERTAINTY | . TIME WITH INTERNAL CLOCK AROUND MAJOR CARRY i fet TTT TT Nob] }.Fo le z aaa ee oe . _- toh ae, ee awatoc input a wert TT |) EPEE ETT 3 pee! we a ; CONVERSION THE Us) Tec TEMPERATURE CO) 8 12-15 10/89, Rev.B <
up ADC-908 CMOS MICROPROCESSOR-COMPATIBLE FAST 8-BIT A/D CONVERTER GENERAL CIRCUIT INFORMATION Pin 14. BUSY Conversion status output. BUSY indicates The ADC-908 is an 8-bit analog-to-digital converter which conversion in progress by going LOW at uses a successive approximation technique to convert an start of conversion and returning HIGH at unknown analog input into a digital code output. The contro! end of conversion. May be used to interrupt logic inputs allow easy interface to most microprocessors controlling microprocessor or to gate con- while three-state outputs allow direct connection to the data ___ tol Inpute, bus. Most applications require only passive RC clock com- Pin 15. RD_—_-READ input. Used to read data (on falling ponents, a —10V reference, and a +5V power supply. The edge) and to reset converter (on rising RC-timed internal clock may be used, or an external clock edge). may be applied to the ADC to maximize performance. Pin 16. CS Chip Select input. Asserted to allow ADC When a Start Conversion command is applied to the CS or operation, Starts conversion when converter RD inputs (see Operating Descriptions for details), BUSY is in reset condition. Note: Holding CS goes LOW indicating a conversion in progress. BUSY may be HIGH will not prevent a rising edge on RD used as an interrupt to halt the controlling microprocessor from resetting the converter. during conversion or may be polled to prevent premature 5, 47 CLK External clock input/internal clock RC tim- data reads. ing input. Starting with the most significant bit (MSB), each successive bit in the DAC is turned on (see Figure 1). The comparator ‘then decides if the DAC output is less than or greater than the APPLICATIONS INFORMATION signal being converted, and that bit is latched on or off, The ADC-908 may be interfaced as if it were a static RAM, a respectively, before proceeding to the next lower bit and ROM, or a slow-memory device. Each of these interface repeating the cycle. When all eight bits have been tested, modes has its own timing and software requirements as BUSY goes HIGH, signaling a completed conversion. described below. These requirements must be rigidly met, as Under control of the RD input, the three-state data outputs improper timing may cause the ADC-908 to change modes. conversion ruts the dla us, Folowing the cata rena, HOW TO CHOOSE AN OPERATING MODE RD returns HIGH resetting the SAR to 1000 0000 and prepa. The Static-RAM interface mode offers advantages in a tightly ing the ADC for its next ‘ore sign Prepar controlled hardware and software environment, where the "9 7 relationship between WRITE and READ instruction pairs is PIN FUNCTIONS certain. As long as minimum timing is satisfied, converted 7 it on digital i data may be read at any convenient time after conversion. NOTE: For greater detail on digital input functions, consult Truth Tables and Timing Diagrams. The use of separate commands to start a conversion, and " then read the results, is conceptually easy. However, if the Pin 1. Vpo Power Supply input, +5V. software is subject to uncontrolled modifications, then the Pin 2. Vper Voltage Reference input, nominal —10V. paired relationship between WRITE and READ instructions 7 a may be lost. Resulting software bugs may result in converted Pin 3. Bors Bipolar Offset input. +10V input for bipolar ‘ mode operation, tie to Vy for unipolar mode data of unknown age, or altogether invalid data being read. operation. By contrast, the ROM mode may be more resistant to software in uni bugs. As long as minimum timing is satisfied, each READ Pin 4. Aw Analog Input. OV to +10V in unipolar mode, . " q “10V fo +10V in bipolar mode instruction obtains new, valid data. However, since the data FIGURE 1: D/A Converter Used in ADC-908 ha Bors . 8 * e ¢ an an Sam San | a > iuse | i set some. Noe" ous) 00s (won) | Jumevion comPanaton 1246 10/89, Rev. B
ADC-908 CMOS MICROPROCESSOR-COMPATIBLE FAST 8-BIT A/D CONVERTER output at any previous READ instruction is obtained from a _ succession, since only the first READ will produce valid data. conversion performed just after the previous READ instruc- A new conversion must be started using WRITE, and the tion, data may be out-of-date. To be sure of obtaining up-to- conversion must be completed, before a new READ will date data, READ instructions may be coded in pairs (with produce valid data. some NOPs between them); use only the data from the second READ in each pair. The first READ starts the conver- TABLE 1: Truth Table, Static RAM Mode sion, acting as a substitute for the static-RAM mode WRITE INPUTS OUTPUTS command; the second READ gets the results. The advantage CS RD BUSY DB7-pBo “OC-908 OPERATION of the ROM mode is the use of a single command, rather than | the alternating READ-WRITE required by static-RAM mode. Lo HH HIGHZ rite cycle) The slow-memory mode is the simplest mode of all. It is, §—§ >a the method of choice where compact coding is essential, LH Mita '° Read Data (Read Cycle) or where software bugs are a hazard. In this mode, a single, § ———___—______DATA__ READ instruction will initiate a data conversion, interrupt DATA to the microprocessor until completion (WAIT states are intro- L FH fianez Reset Converter duced), then read the results. if the system throughput x tolerates WAIT states, and the hardware is correct, then the H (Note 1) *% HIGH-Z _ No Effect (Not Selected) slow-memory mode is virtually immune to subsequent, software modifications. 3 : t 4 LHIGHZ (Converter Busy) OPERATING DESCRIPTION: STATIC-RAM MODE os LoL nigH-z No Effect In this mode, input GS is derived from the ADC-908 address (Converter Busy) decoder, and input RD is derived from an active-LOW memory | READ signal. (See Figure 2.) Late 1) & HIGH NCA To start a conversion, execute a memory WRITE to the = (9 ADC-008. The ‘completed conversion data is obtained by NOTE '"RD goes LOW to HIGH. he ADC sinter ree regan of executing a memory READ to the ADC-908. During conver- sion, output BUSY will be LOW. Do not attempt to read data until BUSY returns HIGH. The required minimum time OPERATING DESCRIPTION: ROM MODE = =—__ between WRITE and READ is usually obtained by including In ROM mode, input CS is tied LOW, and input RD is derived ‘one or more NOP or other program instructions. The use of from the ADC-908 address decoder. To satisty timing, it is branch or conditional commands between the WRITE and recommended that the decoder be enabled by a system READ instructions is not recommended due to the possibility MEMAD (8080), VMA (6800), or similar strobe. (See Figure 3.) of software bugs. In ROM mode, data is read by executing a READ instruction It is important that the WRITE and READ commands be to the ADC-908 address. At the conclusion of the READ alternately executed. A WRITE instruction has no effect unless _instruction, the ADC-908 automatically resets itself and then the results of the previous WRITE have already been read. Proceeds to perform a new data conversion. Output BUSY is Once data has been read, the ADC-908 is internally reset. In LOW during conversion. A new READ instruction to the ‘other words, two or more READ operations cannot be used in ADC-908 must not be executed until BUSY returns HIGH. FIGURE 2: Static RAM Mode Timing Diagram se | [|e | [eee r — _ g Bon g Zz fo} FB om) oO ‘comet z war z Vem 19) | [ eo) = ww bse, Lo 3 87 70 080 Y n MMMM aed MMMM aye Wr g NOTE: tag TING MEASURED AT “24V ANO s0.aV POINTS: 2 Zz 1247 10/89, Rev.B <
PMD ADC-908 CMOS MICROPROCESSOR-COMPATIBLE FAST 8-BIT A/D CONVERTER Do not execute a WRITE instruction at the ADC-908 address _For a cost-effective ~10.00V or —10.24V reference with excel- when in slow-memory mode, since bus conflicts will arise. In__lent accuracy and low temperature coefficient, ask for PMI's some architectures, an accidental WRITE instruction may be REF-08. Consult your sales representative for availability. locked out in hardware, by proper strobing of the ADC-908 address decoder. FIGURE 5: Using the Internal Clock Oscillator INITIALIZATION In all operating modes, the ADC-908 is initialized by executing im a READ instruction to the ADC-908 address. The data obtained should be ignored. A aero CLOCK OSCILLATOR ene The ADG-908 may be used with its internal asynchronous ‘vc-008 eux oGNo clock oscillator. An external resistor and capacitor are eu required. Typical values are R = 43k and C = 100pF, for cu} conversion times in the 6us range. For applications in which the fastest conversion times are required, an external clock is recommended. The external clock must be gated by the use of a 74125-type three-state buffer, with an output pullup FIGURE 6: Using an External Clock resistor. Optimum conversion accuracy is obtained when CS goes LOW on a positive clock edge. The maximum external ” clock frequency is 1.35MHz (See Figure 5 and 6.) if REFERENCE VOLTAGE we A negative reference voltage must be applied to the ADC-908 oo man Vaer input. Optimum full-scale accuracy is obtained using ox 10,00, although Ver may be —5.00V, —10.24V, or other AD c-808 Lo | voltages within its specified range. _ Over the full temperature range, optimum gain accuracy is [\\, exvennat obtained when the input to the Vper pin is from a low- YY clock ine impedance source. A resistor or trimmer may be used in ear ilal series with the Vagr pin, but this trim technique is not as accurate as a low-impedance source. (See Figure 7) FIGURE 7: Unipolar Operation UNIPOLAR OPERATION TRANSFER CHARACTERISTIC {StmAlGnT BINARY OUTPUT CODE) av 10-1 oureur % a in cove Pram Ea) Fite sian a od aati | | / ovo. Ope to / 2 ANALOG INPUT g SN ono 2 (0000 0019 & wy a 100 co10 3 avaioc 000 eon 6 noun oon Oo ome ono a92 a6 0 gy INPUT VOLTAGE (0415) z APPROXIMATE BIT WEIGHTS ARE SHOWN FOR ILLUSTRATION, 5 a nS 12-49 10/89, Rev.B <
mp ADC-908 CMOS MICROPROCESSOR-COMPATIBLE FAST 8.817 A/D CONVERTER Gain Adjustment: impedances may cause errors due to the loading effects of the 1) Apply +9.922V across the analog input. inputs’ finite impedances. 2) While performing continuous conversions, adjust R3 until Ground Management—AGND and DGND pi = pins should be DB7 to DB1 are HIGH and DBO (LSB) flickers. connected at or near the ADC to minimize noise effects. If the DIGITAL CONSIDERATIONS two grounds cannot be connected near the ADC, the grounds Control Timing—Fresh data from a recent conversion mustbe __should be clamped with back-to-back Schottky diodes between read before beginning a new conversion. Following the data the AGND and DGND pins. READ, as RD goes HIGH, it resets the SAR andclears the data Offset Correction—Conversion offset errors may be corrected from the previous conversion. by counter-offsetting the buffer amplifier driving Ajy. This The timing restrictions detailed in the interface timing diagrams _—Offset correction may be accomplished by applying a correction must be observed to prevent the ADC-908 from changing inter- current tothe buffer’s summing junction or by tapping a voltage face modes. For example, if CS is held LOW too long while in divider sitting between Vpp and Vper, and applying this tap RAM mode, the converter will change to ROM mode and initiate voltage to the noninverting input of the buffer. a new conversion. Ratiometric Operation—The R-2R type DAC in the ADC-908 Logic Deglitching—Unrelated activity on the address bus may _—~permits ratiometric operation of the ADC. Performance de- cause unexpected glitch inputs to the ADC. The glitches may gradation may, however, occur as Ver varies from —10.000V. cause unwanted READs, resets, or conversions. In ROM or _This decrease in performance is due to comparator limitations RAM modes, these may be avoided by gating the address including offset-voltage, gain, and input noise. decode logic with RD or WR (8080) or VMA (6800). in slow- The ADC-908 uses the reference as a power supply for the memory mode, ALE (8085) or SYNC (8080) may be used to comparator to increase speed and accuracy. Reference voltages latch the address. of a magnitude less than —9V must be avoided for accurate Initialization—Following power-up, the SAR is in an unknown, comparator operation. For best accuracy, the use of a 0.1uF state. Executing a memory READ (disregard the data) will reset bypass capacitor from Vper(Pin 2 to AGND) is recommended. the ADC, Power Supply Bypassing—For best accuracy, Vpp (Pin 1) ANALDG CONSIDERATIONS should be bypassed to AGND with a 0.1F capacitor. Analog Input Impedances—Low impedance sources must be used to drive the Vaer, Ain, and Bors inputs. Excessive source FIGURE 9: Complementary Offset Bipolar Operation 7 if Couptemewrany orrse Bnany OUTPUT CODE eros’ oe ee ls gm ourrur amt 3m woo ‘coe LN] noc ces 100 ' g, i] A vss set 1 | [o> Fined one 110 i 12 “a0 1000 ooo | 2 sao ww | fo 1000 ore I - | ‘ano Hs 1000 0011 ( iz LT a _—— 5) sono to o100 | 3 | woo é — "ao B20 OW) dO v0 00 BAO 320 0 8 strewn 4 INPUT VOLTAGE (nv) y anouno seat APPROXIMATE err weiaHTS ARE SHOWN FoR RuUstmaiOn | << Q g SSCs 12-21 10/89, Rev.B <