ADC80

ADC80 BURR-BROWN | Alldatasheet

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BURR-BROWN CORP BLE D MM 1731365 0020995 41b MBUB BURR-BROWN® ADC80 General Purpose FEATURES for faster conversion speed with reduced resolution, and an external clock may be used to synchronize @ INDUSTRY-STANDARD 12-BIT ADC the converter to the system clock or to obtain higher- e@ LOW COST speed operation. @ +0.012% LINEARITY Data is available in parallel and serial form with © 258 MAX CONVERSION TIME corresponding clock and status signals. All digital input and output signals are TTL/ LSTTL-compa- @ £12V or +15V OPERATION ° tible, with internal pull-up resistors included on all NO MISSING CODES —25°C to +85°C digital inputs to eliminate the need for external pull- e@ HERMETIC 32-PIN PACKAGE up resistors on digital inputs not requiring connec- © PARALLEL AND SERIAL OUTPUTS tion. The ADC80 operates equally well with either +15V or +12V analog power supplies, and also © 595mW MAX DISSIPATION requires use of a +5V logic power supply. However, unlike many ADC80-type products, a +5V analog DESCRIPTION power supply is not required. It is packaged in a . A A a he tic 32-pin side-brazed i 1-in-li The ADC80 is a 12-bit successive-approximation package. Pin side-brazed ceramic dual-in-line analog-to-digital converter, utilizing state-of-the-art . CMOS and laser-trimmed bipolar die custom designed for freedom from latch-up and optimum AC per- formance. It is complete with a comparator, a eee ° monolithic 12-bit DAC which includes a 6.3V refer- External » ence laser-trimmed for minimum temperature coeffi- Clock cient, and a CMOS logic chip containing the succes- Sele ° Clock Out sive approximation register (SAR), clock, and all Comparatorig Parallel other associated logic functions. In » Data : utpul Internal scaling resistors are provided for the selection} 7°V Fensee > Feces Lara of analog input signal ranges of £2.5V, +5V, +I10V, 10v Rangee Register ‘Serial 0 to +5V, or 0 to +10V. Gain and offset errors may = Out be externally trimmed to zero, enabling initial end- Comparstor point accuracies of better than +0.12% (+1/2LSB). verter The maximum conversion time of 25ys makes the Bipolar g 5 ADC80 ideal for a wide range of 12-bit applications Offset Reference Out requiring system throughput sampling rates up to ] 40kHz. In addition, the ADC80 may be short-cycled International Airport Industrial Park - P.0, Box 11400 - Tucson, Arizona 85734 - Tel. (602) 746-1111 - Twx: 910-952-1111 - Cable: BBRCORP - Telex: 66-6491 ©1986 Burr-Brown Corporation PDS-676 Printed in U.S.A. May, 1986

BURR-BROWN CORP bLE D MM 1731365 0020996 352 MBUB ELECTRICAL At Ta = +25°C, +Voc = 12V or 15V, Voo = +5V unless otherwise specified. [ae [oe | ‘RESOLUTION ADC80AG-12, ADC80-AGZ-12"" 12 Bits ren Oto +10V, +5V 5 51 ko Logic Characteristics (Over specification temperature range) Ver (Logic “1") 20 55 v Noe (Vw = +2.7V) 150 uh In (Vine = +0.4¥), 500 pA Convert Command Pulse Width” 100 2000 ns ACCURACY Gain Error™ 101 +03 ‘% of FSR” Offset Error™: Unipolar +£0.05 £02 % of FSR ADC80AG-10 $0,048 % of FSR Inherent Quantization Error +12 LsB 11.4V S + Vec S 16.5V +0.003 +£0.009 % of FSR/%*Voc +4.5V S Voo S +5.5V ‘+0.002 20.005 ‘% of FSR/%*Vo0 Total Accuracy, Bipolar™ +10 +23 ppm? Gain 15 +30 ppm/*c Bipolar +7 +15 ppm of FSR/°C Linearity Error Drift HH +3 ppm of FSR/°C° Monotonicity Over Temperature Range Guaranteed CONVERSION TIME” oom? z DIGITAL (Bits 1-12, Clock Out, Status, Serial Out) Output Codes” Bipolar COB, CTC ‘Serial (NRZ)* CSB, COB Logic 1 (Isounce = 80vA) +24 v INTERNAL REFERENCE VOLTAGE ‘Source Current Available for External Loads™ pA POWER SUPPLY REQUIREMENTS (For all models) Specification 25 +85 °c Operating (derated specs) 55 +125 °c Storage 65 +150 °c ‘specified conversion time. (3) Gain and offset errors are adjustable to zero. See “Optional External Gain and Offset Adjustment” section. (4) FSR means Full-Scale Range and is 20V for + 10V range, 10V for +5V and.O 10 +10V ranges, etc. (5) Includes drift due to linearity, gain, and offset drifts. (6) Conversion time is specified shorter conversion time; see “Short Cycle Feature” section. (7) CSB means Complementary Straight Binary, COB means Complementary Oftset Binary, and CTC

BURR-BROWN CORP 61E D MM 14731365 0020997 259 MBUB CONNECTION DIAGRAM TOP VIEW Pint -Bité Pin 32- Bit 7 Pin2 -BitS Pin 31- Bit8 r ) Pin3 -Bit4 Pin 30- Bit 9 a) 2) Pin4 -Bit3 Pin 29 - Bit 10 (LSB—10 Bits) @ — Pind -Bit2 Pin 28- Bit 11 Tt <5 {3)) Pin6 - Bit 1(MSB) Pin 27 - Bit 12 (LSB—12 Bits) ‘6, TH ae 130) Pin? -N/C* Pin 26 - Serial Out ol 2:5= a: eo Pin 8 - Bit 1 (MSB) Pin 25 - —Vec SS 8 Pin9 - +8V Digital Supply Pin 24 - Ref. Out (+6.3V) i iiliiiiiim “ 128) Pin 10 - Digital Common Pin 23 - Clock Out 6) 7) Pin 11 - Comparator In Pin 22- Status qj (\\ . Pin 12 - Bipolar Offset Pin 21 - Short Cycle 0) Sarr) (26) Pin 13 -R1 10V Range Pin 20 - Clock Inhibit (8) (25) Pin 14 - R2.20V Range Pin 19 - External Clock (ay @) a GO ol 1 C: I —h | a — CR | b * +5V applied to pin 7 has 0), (19) no effect on circuit. (5) fi) (9) R) MECHANICAL ORDERING INFORMATION

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B at MMC at Seating Plane. ‘ADCB80AG-10 79.50 63.0 44.00 i ADC80AG-12 81.00 64.00 44.50 1 10) 46 Seal ring is connected ADC80AG-120" 105.00 | 84.00 | 58.00 @ " pint ADCB0AGZ-12” 83.00 | 66.00 | 46.00 r NOTES: (1) Qsutfix indicates Environmental Screening; see Table IV for ras 0 J details. (2) ADC80AGZ-12 is not recommended for new designs. Stand- f { i i HH} \\ } { y fit i ard ADC8QAG-12 now meets the extended power supply range of the | a k L z| i ADC80AGZ-12. He tpl seating a Oe Pte | on be ae te Pin pumbers shown for ("A 17-580]7.620 | 40.15|43.16] reference only. Numbers A180 8001 20.36 |22,86] The information provided herein is believed to be reliable; however, may not be marked on ES Era BURR-BROWN assumes no responsibility for inaccuracies or omissions. packag Let odo tye + toe TYP] BURR-BROWN assumes no responsibility for the use of this information, CASE: Ceramic, hermetic [-¢-1100 BAST Ess BASIC and all use of such information shall be entirely at the user's own risk. MATING CONNECTOR: CHT 544i osel f.12] 1.43 Prices and specifications are subject to change without notice. No patent [JT 000! 0121 0.231 0.30) A i i 2302MC kcTciesl196) 4.191 470) rights or licenses to any of the circuits described herein are implied or LT 300! 9201 ae.86laa7) granted to any third party. BURR-BROWN does not authorize or warrant ABSOLUTE MAXIMUM RATINGS TYPICAL PERFORMANCE Logic Inputs (Convert Command, Clock In) 0.0 ———_ ++ — Analog Inputs (Analog In, Bipolar Offset) lg) es ee a” to Analog Common... es ssesssssesseseeseeseeveee H5V ee es Ss , Momentary Short to Vec =P og | Vee 35 0.008 oS & ee eee eee ae CAUTION: These devices are sensitive to electrostatic discharge. eS oo @ eerllciol ehinsiendnicheshanta bnmercisiosind 002 CE TIX Stresses above those listed under "Absolute Maximum Ratings” [——__}—_|__|—_ may cause permanent damage to the device. Exposure to absolute a a pov sty maximum conditions for extended periods may affect device relia~ bility, 1 10 100 1k 10k 100k Frequency (Hz)

BURR-BROWN CORP b1E D MM 1731365 0020998 125 MEBUB | LINEARITY ERROR VS CONVERSION TIME DIFFERENTIAL LINEARITY ERROR VS CONVERSION TIME . ATP PPT eer ry NTT PPP rrr Tr 0.175} yaisel (0.175 Fr/atse! B areal, Hepes, | TT TTY goles A peseoremon| TT TTT | sl ]@ 3 85 LL ficetoperation | | | | | & 88S TLV 108i operation [1s | #0125 Eg 0125 a = owl WA t i TT TT TT est | ANE PP PTT s F3 10 Bits V Z = 0.075 F10 Bits Fd E oosot nL NN ee om MANS TTS £ Ssh s = = > ves pe | Ns 5 oes pe) SS * oll =} =F 5 t=} PP 2 4 6 8 10 12 14 16 18 20 22 24 26 2 4 6 8 10 12 14 16 18 20 22 26 26 Conversion Time (us) Conversion Time (us) SPECIFICATIONS oon. con LINEARITY ERROR 001m ert es 1 | Linearity error is defined as the deviation of actual code 0024 ee it transition values from the ideal transition values. Under 5 7FDn 1 this definition of linearity (sometimes referred to as E 7FEq io integral linearity), ideal transition values lie on a line o Fru \\ i— drawn through zero (or minus full scale for bipolar E 800, Offset yi i ! operation) and plus full scale, providing a signficantly g 301% f Shifts i | { 1 better definition of converter accuracy than the best- Froyf ene a) i | straight-line-fit definition of linearity employed by some FFE it i ot manufacturers. rr, \\ [> Midscale ' | . . ” i] The zero or minus full-scale value is located at an analog Loy ti, it ® input value 1/2LSB before the first code transition V2LSB 4 i ak aise Rt +Full (FFFy to FFEx). The plus full-scale value is located at cru | velsB i Seale an analog value 3/2LSB beyond the last code transition Scale 1 Transition Values ——et (00x to 000). See Figure 1 which illustrates these ANALOG INPUT relationships, A linearity specification which guarantees £1/2LSB maximum linearity error assures the user that FIGURE 1. ADC80 Transfer Characteristic no code transition will differ from the ideal transition Terminology. value by more than +1/2LSB. Thus, for a converter connected for bipolar operation +9,99268V). Ideal transitions occur 1LSB (4.88mV) apart, and with a full-scale range (or span) of 20V (+10V and the +1/2LSB linearity specification guarantees that operation), the minus full-scale value of —10V is 2.44mV no actual transition will vary from the ideal by more below the first code transition (FFFx to FFEx at than 2.44mV. The LSB weights, transition values, and —9.99756V) and the plus full-scale value of +10V is code definitions for each possible ADC80 analog input ale P g inp 7.32mV above the last code transition (001n to 000y at signal range are described in Table I. TABLE I. Input Voltages, Transition Values, LSB Values, and Code Definitions. [cadecenanaton |__| Sovrorcro= | coawere | Copwcre | cso | ome | One Least Significant FSR/2" 20v/2" 10/2" $v/2" 1ov/2" 5/2" Transition Values e MSB LSB 001n to 000% +Full Scale | +1ov—s/aisB | +sv-saisB | +25v-g/2LsB | +10v-g/asa] +5V-3/2LSB 800, to 7FFH Mid Scale oO i) ° +5V +25V FFF y to FFEn —Full Scale -1ov+vaise | -sv+wvalsB | -25v+rase | 0+1/2188 0+ 1/2L8B “COB = Complementary Offset Binary CTC = Complementary Two's Complement—obtained by using the complement of the most *CSB = Complementary Straight Binary significant bit (MSB). MSB is available on pin 8.

61E D MH 4731365 0020999 ob1 @EBUB CODE WIDTH (QUANTUM) Specification temperature range. The temperature coeffi- Code width (or quantum) is defined as the range of cient applies independently to the two halves of the analog input values for which a given output code will temperature range above and below +25°C. occur. The ideal code width is ILSB, which for 12-bit e operation with a 20V span is equal to 4.88mV. Refer to POWER SUPPLY SENSITIVITY Table I for LSB values for other ADC80 input ranges. Electrical specifications for the ADC80 assume the application of the rated power supply voltages of +5V DIFFERENTIAL LINEARITY ERROR AND NO and £12V or +I5V. The major effect of power supply MISSING CODES voltage deviations from the rated values will be a small Differential linearity error is the difference between an Change in the plus full-scale value. This change, of ideal ILSB code width (quantum) and the actual code CUS, results in a proportional change in all code width. A specification which guarantees no missing (ransition values Ge., a gain error). The specification codes requires that every code combination appear in a lescribes the maximum change in the plus full-scale . . . . value from the initial value for independent changes in monotonically increasing sequence as the analog input is each power supply voltage. increased throughout the range, requiring that every P PPly Be input quantum must have a finite width. If an input TIMING CONSIDERATIONS quantum has a value of zero (a differential linearity error . . . a of —ILSB), a missing code will occur but the converter Timing relationships of the ADC80 are shown in Figure may still be monotonic. Thus, no missing codes represent 2. It should be noted that although the convert command a more stringent definition of performance than does pulse width must be between 100ns and 2us to obtain the monotonicity. ADC80 is guaranteed to have no missing specified conversion time with internal clock, the ADC80 codes to 12-bit resolution over its full specification Will accept longer convert commands with no loss of temperature range. accuracy, assuming that the analog input signal is stable. QUANTIZATION UNCERTAINTY Analog-to-digital converters have an inherent quantiza- Commande bk to tion error of +1/2LSB. This error is a fundamental Interna = SU LULL n_S property of the quantization process and cannot be Clock At Feteo “1 Peer “1 rtm eliminated. Status —! Le @ tra] be UNIPOLAR OFFSET ERROR att An ADC80 connected for unipolar operation has an im analog input range of OV to plus full scale. The first Bit2 output code transition should occur at an analog input value 1/2LSB above OV. Unipolar offset error is defined Bits ail a as the deviation of the actual transition value from the Bit 4 ideal value, and is applicable only to converters operating . in the unipolar mode. : Bitte Ze Z BIPOLAR OFFSET ERROR seri! rife tor rial A/D converter specifications have historically defined Data bipolar offset at the first transition value above the minus full-scale value. The ADC80 follows this conven- tion. Thus, bipolar offset error for the ADC80 is defined a jati iti jock delay from convert comman ns as the deviation of the actual transition value from the 2 | Nominal clock period 165] ss ideal transition value located 1/2LSB above minus full tew | Nominal clock pulse width 065} ys scale. tso | Status delay from convert command 130] ns * te _| All bits reset delay from convert command | 65 | ns tov _ | Data valid time from clock pulse high -5 | ns GAIN ERROR The last output code transition (001x to 00x) occurs for FIGURE 2. ADC80 Timing Diagram (nominal values an analog input value 3/2LSB below the nominal plus Or wig & 5 Moge at +25°C with internal clock). full-scale value. Gain error is the deviation of the actual analog value at the last transition point from the ideal Jy this situation, the actual indicated conversion time value. (during which status is high) for 12-bit operation will be @ equal to approximately Iyus less than the sum of the ACCURACY DRIFT VS TEMPERATURE factory-set conversion time and the length of the convert The temperature coefficients for gain, unipolar offset, command. The code returned by the converter at the end and bipolar offset specify the maximum change from the of the conversion will accurately represent the analog actual 25°C value to the value at the extremes of the input to the converter at the time the status returns to the

is present or the internal clock is not inhibited. close to the ADC80 as possible. pulse, and with valid output data ready to be read at that supply lines can degrade the converter’s performance. after the fall of the last clock pulse (pulse 13 for 12-bit especially troublesome. on the serial output of the ADC80; as in the parallel INPUT SCALING . Figure 5. ; Analog and digital commons are not connected together TABLE Ii. ADC80 Input Scaling Connections.

43 R2 the potentiometer is adjusted until bit 12 (the LSB)

FIGURE 3. ADC80 Input Scaling Circuit. 001 with an approximate 50% duty cycle. As in the case CALIBRATION end-point transitions to a precisely known value. external offset and gain trim potentiometers connected i" ws . ° use with an external clock, which is applied to pin 19. 28k output pin of the next bit after the desired resolution. FIGURE 4. Two Methods of Connecting Optional conversion cycle terminates and status is reset after the FIGURE 5. Two Methods of Connecting Optional Gain TABLE III. Short-Cycle Connections and Conversion alternating between FFEn and FFFu with approximately NOTE: (1) Conversion time to maintain +1/2LSB linearity error.

1 Gonvert : = Common

FIGURE 6. Internal Clock—Normal FIGURE 7. Continuous External Clock. (Conversion initiated by FIGURE 8. Continuous Conversion with FIGURE 9. Continuous Conversion with 600ns between ) TABLE IV. Screening Flow for ADC80AG-12Q. models are environmentally screened versions of our to +180°C.