ADADC80 AD | Alldatasheet
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FEATURES FUNCTIONAL BLOCK DIAGRAM True 12-Bit Operation: Max Nonlinearity +0.012% Low Gain T.C.: +30ppm/°C max Low Power: 800mW aire [1 } Cc 132] sir7 Fast Conversion Time: 25us ats [2 | a a fai] are Precision 6.3V Reference for External Application 1 fd —— Short-Cycle Capability ara Sap wor K——| [20] sire Serial or Parallel Data Outputs arse} —$ttr] &** Ftp —f Fro] air so Monolithic DAC with Scaling Resistors for Stability nn et . ai pir mh }3=6Aa oo Fra] err 1 Low Chip Count—High Reliability v2 [s } toc Industry Standard Pinout arr imss Beale Ht tt — Fa err tise “Z" Models for +12V Supplies [ | sev anatog [7] fas] senvac our arr [s | | 25] -15v oR -12v +8V DIGITAL REF OUT lcontrot| piciTat ano [70] ciRcuITs|-4 23] cLock out cmon * TT TEL “oa =| ¥ Lees ni Vv al rov span in [13 | 2 water zov sean in [re] Es Fa] extenvae ANALOG Gno [15 | aL OR Gain aosust [16 | AD ADC8O [17] +18v on +12v PRODUCT DESCRIPTION The AD ADC80 is a complete 12-bit successive approximation analog-to-digital converter that includes an internal clock, refer” prODUCT HIGHLIGHTS ence and comparator. Its hybrid IC design utilizes MSI digital 1. The AD ADC80 is a complete 12-bit A/D converter. No and linear monolithic chips in conjunction with a 12-bit mono- external components are required to perform a conversion. lithic DAC to provide modular performance and versatility with a . . IC size, price and reliability 2. A monolithic 12-bit feedback DAC is used for reduced , _ . chip count and higher reliability. Important performance characteristics of the AD ADC80 in- ; clude a maximum linearity error at +25°C of +0.012%, max 3. The internal buried zener reference is laser trimmed to 6.3 gain T.C. of 30ppm/°C, typical power dissipation of 800mW volts. The reference voltage is available externally and can and max conversion time of 25s. Monotonic operation of the supply up to 1.5mA beyond that required for the reference feedback D/A converter guarantees no missing codes over the and bipolar offset current. temperature range of -25°C to +85°C. 4. The scaling resistors are included on the monolithic DAC The design of the AD ADC80 includes scaling resistors that for exceptional thermal tracking. provide analog signal ranges of 2.5, +5.0, +10, 0 to +5 or 0 5. The AD ADC80 directly replaces other devices of this type to +10 volts, The 6.3V precision reference may be used for ex- with significant increases in performance. ternal applications. All digital signals are fully DTL and TTL 6. The fast conversion rate of the AD ADC80 makes it an comparibles output data may be read in both serial and par- excellent choice for applications requiring high system el form. throughput rates. The AD ADC80 is available in two performance grades, the 7. The short cycle and external clock options are provided for AD ADC80-12 (0.012% of FSR max) and the AD ADC80-10 applications requiring faster conversion speeds or lower (0.048% of FSR max). Both grades are specified for use over resolutions. the -25°C to +85°C temperature range and both are available in a 32-pin ceramic DIP. REV.A Information furnished by Analog Devices is believed to be accurate and use, nor for any infringements of patents or other rights of third parties ne Technology Way, P.O. Box 9106, Norwood, USA. which may result from its use. No license is granted by implication or Tel: 617/329-4700 Fax: 617/326-8703 Twx: 710/394-6577 otherwise under any patent or patent rights of Analog Devices. Telex: 924491 Cable: ANALOG NORWOODMASS
AD ADC80 — SPECIFI CATIONS (typical @ +25°C, +15V and +5V unless otherwise specified) ila tn MODEL AD ADC80-12 AD ADC80-10 1LSB, ANALOG INPUTS & Voltage Ranges & sei Bipolar 42.5V, 45V, *10V > Unipolar OV to +8V, OV to +10V © wise Impedance (Direct tnput) vio si0v.30 a : : LENIN ENE OV to +10V, +5 SkQ . 5 s0v 10k * > yaLsB N N = ee \\ExSEEEEEE Convert Command Positive Pulse 100ns Wide (min) SS (0" to "1" Initiates Conversion) Logic Loading as o 2 4 6 8 10 12 4 16 18 20 22 24 26 External Clock ITTL Load CONVERSION TIME — 4s TRANSFER CHARACTERISTICS ERROR . Figure 1. Linearity Error vs. Conversion Gain Error 20.1% of F ‘ i Offset Error? Time (Normalized) Unipolar 40.05% of FSR . Bipolar 20.1% of FSR . 1LSB Linearity Error (max)* +0.012% of FSR +0.048% of FSR Inherent Quantization Error t1/2LSB . Differential Linearity Error #1/2LSB ° 3% 3/4LsB No Missing Codes Temperature Range -25°C to +85°C . ge Power Supply Sensitivity Be \\ t15V +0.0030% of FSR/% Vs * ] z 1/2LSB DRIFT ie Specification Temperature Range -28°C 10 485°C : 52 vase \\ N Gain (max) 230ppm/°C Ss \\ a Offset Bipolar (max) £15ppm of FSR/*C a Linearity (max) +#3ppm of FSR/°C. : o 2 4 6 8 10 12 14 16 18 20 22 24 26 —Monownicity GUARANTEED CONVERSION TIME — ps —— Figure 2. Differential Linearity Error vs. {all codes complementary) Conversion Time (Normalized) Parallel ; « Output Codes % +03 Bipolar COB, CTC z +402 Serial Data Codes (NRZ) CSB, COB +01 PR Soy ‘Output Drive 2TTL Loads 5 NK ee states Logie "1" During Conversion 2 9 \\\\ iss <Q Y Status Output Drive 2TTL Loads & \\\\\\ \\\\ Frequency? S7SkHe a -02 Max, External Current (with no g 35 > 5 rerum degradation of specifications) 1.5mA, “ 5 ‘Tempco of Drift 10ppm/*C typ, #20ppm/°C max TEMPERATURE — °C POWER REQUIREMENTS —— Rated Voltages z1sv. SV Figure 3, Maximum Gain Drift Error—% of Range for Rated Accuracy 4.75V to 5.25V and £14.0V to 216.0V Supply Drain +15V +10mA -135V -20mA av TOMA SO TEMPERATURE RANGE = ooh} | dr Specificat -25°C 10 +85°C Ss S a < peraing (Derated Specs 5°e to 00" Eaaryey ANNNY <A Operating (Derated Specs) 5°C to +100% = 0.04 ~ SAAN Storage 89°C 10 o128°C Feaeeyey NNANNANNS SS ANN FacAGE OPTION E SRD AMY
3 AD ADC80-12 AD ADCB80-10 SY re - ~~ \\TyPICAL y
NOTES emeuchie ie, toge“0" i" 8 oa Ager SAAN DTL/TTL compatible ic, Logic “O" =O.8V max, Logic “1” =2.0V min for digital inputs, Z 0.04 We SR sstable to zero with external trims ia Y 2 PSM means Pal Sale Range-for example, unit connected for +10V range has 20V FSR. ¢ a “Error shown is the same as #1/2LSB max for resolution of A/D converter. B -0.038 Eo conversion time with interaal clock “See Table I. CSB. — Complementary Straight Binary 65 8 ° +28 #85 +100 SOB — Complemencary Offect Binary CIC. ~ Complementary Two's Complement ‘TEMPERATURE — °C
7 For conversion speeds specified
‘or pekage oa informacion sz Pachage Information section, Figure 4, Reference Drift—% Error Specifications same as AD ADC80-12. vs. Temperature Specifications subject to change withoutnoitice. Specifications subject to change without notice. -2- REV. A
DAC output, one bit at a time (MSB first, LSB last). The clock output to the Logic “‘0” state. The timing diagram is shown in Figure 5. Receipt of a CON- receiving shift register on these edges (see Figure 5). SAR parallel bit and STATUS flip-flops are initialized on the initiated by the trailing edge of the STATUS signal.
- THE CONVERT START PULSE WIDTH IS 100ns MIN AND MUST REMAIN LOW DURING
- 25us FOR 12 BITS AND 21ys FOR 10 BITS (MAX).
- LSB DECISION 40ns PRIOR TO THE STATUS GOING LOW
Figure 5. Timing Diagram (Binary Code 011001110110)
the receiving shift register locations shown at the completion common 15 O—. ***CSB = Complementary Straight Binary. ‘****Voltages given are the nominal value for transition to the code specified. Table 11. Input Voltages and Code Definitions
2.3ppm/°C of FSR, if the OFFSET AD) potentiometer is set. _the analog range. at either end of its adjustment range. Since the maximum off- 0 to +10V Range: Set analog input to +1LSB = +0.0024V. tributes no more than 1ppm/°C of FSR offset tempco. calibrated. Set analog input to +FSR -2LSB = +9.9952V. Figure 7. Offset Adjustment Circuit binary) code. Set analog input to +9.9902V; adjust Gain for ppm/*C) are used, is shown in Figure 8. 0111111111111. The gain adjust circuit consists of a potentiometer connected Inc., 1977, Part IT, Chapter 3. across +Vg with its slider connected through a 10MQ& resistor . to the gain adjust pin 16 as shown in Figure 9. **Figure 9. Gain Adjustment Circuit 5* | V**
11 ADADCBO
Figure 10. Low Tempco Gain Adjustment Circuit Unipolar 0-10V Input Range
$ 10m anton Figure 14. Internal Clock—Normal Operating Mode. Figure 12. Analog and Power Connections for Bipolar Ground. These grounds must be tied together at one point, Figure 15. Continuous Conversion with External Clock. solid ground would be desirable. However, since current flows Continuously. this way supply currents and logic-gate return currents are not IL 18}eowy. ct0cK 122 sara. to the Analog Power Return pin and the logic supply is by- Dimensions shown in inches and (mm). passed to the Logic Power Return pin.
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Figure 13. Basic Grounding Practice vanes ——l