ADC78H90

ADC78H90 8-Channel, 500 kSPS, 12-Bit A/D Converter datasheet (Rev. D)

Document overview

• Manufacturer or author: Texas Instruments, Incorporated [SNAS227,D]
• PDF pages: 26

Technical content

www.ti.com SNAS227D –NOVEMBER 2003–REVISED MARCH 2013 ADC78H908-Channel,500kSPS,12-BitA/DConverter Check forSamples: ADC78H90 The ADC78H90 is packaged in a 16-leadTSSOP1FEATURES package. Operationover the industrialtemperature 2• Eightinputchannels rangeof−40°C to+85°C isensured.

• Variablepower management Connection Diagram• Independentanalog and digitalsupplies
• SPI™ /QSPI™ /MICROWIRE ™ /DSP compatible
• Packaged in16-leadTSSOP

APPLICATIONS

• Automotive Navigation
• PortableSystems
• MedicalInstruments
• MobileCommunications
• Instrumentationand ControlSystems KEY SPECIFICATIONS Figure1. 16-Lead TSSOP• Conversion Rate:500kSPS See PW Package
• DNL: ± 1LSB (max)
• INL:± 1LSB (max) Block Diagram• Power Consumption – 3V Supply:1.5mW (typ) – 5V Supply:8.3mW (typ)

DESCRIPTION

The ADC78H90 isa low-power,eight-channelCMOS 12-bitanalog-to-digitalconverterwith a conversion throughputof500 kSPS. The converterisbased on a successive-approximationregisterarchitecturewith an internaltrack-and-holdcircuit.Itcan be configured to accept up to eightinputsignalsat inputsAIN1 throughAIN8. The output serialdata is straightbinary,and is compatiblewithseveralstandards,such as SPI™ , QSPI ™ , MICROWIRE ™ , and many common DSP PIN DESCRIPTIONS AND EQUIVALENT CIRCUITSserialinterfaces. Pin Equivalent DescriptionSymbolThe ADC78H90 may be operatedwithindependent No. Circuit analogand digitalsupplies.The analogsupply(AVDD ) ANALOG I/O power consumptionusinga +3V or+5V supplyis1.5 DIGITAL I/OmW and 8.3 mW, respectively.The power-down featurereduces the power consumptionto just0.3 µW using a +3V supply,or 0.5 µW using a +5V supply. Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2003–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

SNAS227D –NOVEMBER 2003–REVISED MARCH 2013 www.ti.com PIN DESCRIPTIONS AND EQUIVALENT PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS (continued) CIRCUITS (continued) Pin Equivalent Description Pin Equivalent DescriptionSymbol SymbolNo. Circuit No. Circuit Digitalclockinput.The rangeof Positiveanalogsupplypin.This frequenciesforthisinputis50 pinshouldbe connectedtoa kHz to8 MHz, withensured quiet+2.7V to+5.25V source 16 SCLK performanceat8 MHz. This and bypassedtoGND witha 12 AV DDclockdirectlycontrolsthe µF tantalumcapacitorand a 0.1 conversionand readout µF ceramicmonolithiccapacitor processes. locatedwithin1 cm ofthe power pin.Digitaldataoutput.The output samplesareclockedoutofthis Positivedigitalsupplypin.This15 DOUT pinon fallingedges ofthe pinshouldbe connectedtoa SCLK pin. +2.7V toAV DD supply,and 13 DV DD bypassedtoGND witha 0.1µFDigitaldatainput.The ceramicmonolithiccapacitorADC78H90's ControlRegister14 DIN locatedwithin1 cm oftheisloadedthroughthispinon power pin.risingedges oftheSCLK pin. POWER SUPPLY These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. AbsoluteMaximum Ratings (1)(2) AnalogSupplyVoltageAV DD −0.3Vto6.5V DigitalSupplyVoltageDV DD −0.3VtoAV DD + 0.3V,max 6.5V Voltageon Any PintoGND −0.3VtoAV DD +0.3V InputCurrentatAny Pin (3) ±10 mA Package InputCurrent(3) ±20 mA Power DissipationatTA = 25°C See (4) ESD Susceptibility(5) Human Body Model 2500V Machine Model 250V SolderingTemperature,Infrared, 10 seconds (6) 260°C JunctionTemperature +150°C StorageTemperature −65°C to+150°C (1) AbsoluteMaximum Ratingsindicatelimitsbeyond whichdamage tothedevicemay occur.OperatingRatingsindicateconditionsfor whichthedeviceisfunctional,butdo notensurespecificperformancelimits.Forensuredspecificationsand testconditions,see the ElectricalCharacteristics.The ensuredspecificationsapplyonlyforthetestconditionslisted.Some performancecharacteristicsmay degradewhen thedeviceisnotoperatedunderthelistedtestconditions. (2) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTexas InstrumentsSalesOffice/Distributorsforavailabilityand specifications. (3) When theinputvoltageatany pinexceedsthepower supplies(thatis,VIN < AGND orVIN >VA orVD ),thecurrentatthatpinshouldbe limitedto10 mA. The 20 mA maximum package inputcurrentratinglimitsthenumber ofpinsthatcan safelyexceed thepower supplies withan inputcurrentof10 mA totwo. (4) The absolutemaximum junctiontemperature(TJmax) forthisdeviceis150°C. The maximum allowablepower dissipationisdictatedby TJmax, thejunction-to-ambientthermalresistance(θJA),and theambienttemperature(TA),and can be calculatedusingtheformula PD MAX = (TJmax − TA)/θJA.Inthe16-pinTSSOP,θJA is96°C/W, so PD MAX = 1,200mW at25°C and 625 mW atthemaximum operatingambienttemperatureof85°C. Note thatthepower consumptionofthisdeviceundernormaloperationisa maximum of12 mW. The valuesformaximum power dissipationlistedabove willbe reachedonlywhen theADC78H90 isoperatedina severefaultcondition (e.g.when inputoroutputpinsaredrivenbeyond thepower supplyvoltages,orthepower supplypolarityisreversed).Obviously,such conditionsshouldalwaysbe avoided. (5) Human body model is100 pF capacitordischargedthrougha 1.5kΩ resistor.Machine model is220 pF dischargedthroughZERO ohms (6) See AN450, “SurfaceMountingMethods and TheirEffecton ProductReliability”,orthesectionentitled“SurfaceMount”foundinany post1986 Texas InstrumentsLinearData Book,forothermethods ofsolderingsurfacemount devices.

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www.ti.com SNAS227D –NOVEMBER 2003–REVISED MARCH 2013 OperatingRatings (1)(2) OperatingTemperatureRange −40°C ≤ TA ≤ +85°C AV DD SupplyVoltage +2.7V to+5.25V DV DD SupplyVoltage +2.7V toAV DD DigitalInputPinsVoltageRange -0.3VtoAV DD ClockFrequency 50 kHz to8 MHz AnalogInputVoltage 0V toAV DD (1) AbsoluteMaximum Ratingsindicatelimitsbeyond whichdamage tothedevicemay occur.OperatingRatingsindicateconditionsfor whichthedeviceisfunctional,butdo notensurespecificperformancelimits.Forensuredspecificationsand testconditions,see the ElectricalCharacteristics.The ensuredspecificationsapplyonlyforthetestconditionslisted.Some performancecharacteristicsmay degradewhen thedeviceisnotoperatedunderthelistedtestconditions. (2) Allvoltagesaremeasured withrespecttoGND = 0V,unlessotherwisespecified. Package Thermal Resistance Package θJA 16-leadTSSOP on 4-layer,2 oz.PCB 96°C /W Copyright© 2003–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:ADC78H90

SNAS227D –NOVEMBER 2003–REVISED MARCH 2013 www.ti.com ADC78H90 ConverterElectricalCharacteristics(1) The followingspecificationsapplyforAV DD = DV DD = +2.7V to5.25V,AGND = DGND = 0V,fSCLK = 8 MHz, fSAMPLE = 500 KSPS, unlessotherwisenoted.BoldfacelimitsapplyforTA = TMIN toTMAX :allotherlimitsTA = 25°C. LimitsSymbol Parameter Conditions Typical Units(2) STATIC CONVERTER CHARACTERISTICS ResolutionwithNo MissingCodes 12 Bits INL IntegralNon-Linearity AV DD = +5.0V,DV DD = +3.0V ±1 LSB (max) DNL DifferentialNon-Linearity AV DD = +5.0V,DV DD = +3.0V ±1 LSB (max) VOFF OffsetError AV DD = +5.0V,DV DD = +3.0V ±2 LSB (max) OEM OffsetErrorMatch AV DD = +5.0V,DV DD = +3.0V ±2 LSB (max) GE Gain Error AV DD = +5.0V,DV DD = +3.0V ±3 LSB (max) GEM Gain ErrorMatch AV DD = +5.0V,DV DD = +3.0V ±3 LSB (max) DYNAMIC CONVERTER CHARACTERISTICS AV DD = +5.0V,DV DD = +3.0V,SINAD Signal-to-NoisePlusDistortionRatio 73 70 dB (min)fIN = 40.2kHz,−0.02dBFS AV DD = +5.0V,DV DD = +3.0V,THD TotalHarmonicDistortion −86 −74 dB (max)fIN = 40.2kHz,−0.02dBFS ENOB EffectiveNumber ofBits AV DD = +5.0V,DV DD = +3.0V, 11.8 11.3 Bits(min) AV DD = +5.0V,DV DD = +3.0V,Channel-to-ChannelCrosstalk -82 dBfIN = 40.2kHz IntermodulationDistortion,Second AV DD = +5.0V,DV DD = +3.0V, -93 dBOrderTerms fa = 40.161kHz,fb = 41.015kHz IMD IntermodulationDistortion,ThirdOrder AV DD = +5.0V,DV DD = +3.0V, -90 dBTerms fa = 40.161kHz,fb = 41.015kHz AV DD = +5V 11 MHz FPBW -3dB FullPower Bandwidth AV DD = +3V 8 MHz ANALOG INPUT CHARACTERISTICS VIN InputRange 0 toAV DD V IDCL DC Leakage Current ±1 µA (max) TrackMode 33 pF C INA InputCapacitance HoldMode 3 pF DIGITAL INPUT CHARACTERISTICS DV DD = +4.75Vto+5.25V 2.4 V (min) VIH InputHighVoltage DV DD = +2.7V to+3.6V 2.1 V (min) VIL InputLow Voltage DV DD = +2.7V to+5.25V 0.8 V (max) IIN InputCurrent VIN = 0V orDV DD ±0.01 ±1 µA (max) C IND DigitalInputCapacitance 2 4 pF (max) DIGITAL OUTPUT CHARACTERISTICS ISOURCE = 200 µA,DV DD = +2.7V toVOH OutputHighVoltage DV DD −0.5 V (min)+5.25V VOL OutputLow Voltage ISINK = 200 µA 0.4 V (max) IOZH ,IOZL TRI-STATE ® Leakage Current ±1 µA (max) C OUT TRI-STATE ® OutputCapacitance 2 4 pF (max) OutputCoding Straight(Natural)Binary (1) Data sheetmin/max specificationlimitsareensuredby design,test,orstatisticalanalysis. (2) TestedlimitsarespecifiedtoTI's AOQL (AverageOutgoingQualityLevel).

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www.ti.com SNAS227D –NOVEMBER 2003–REVISED MARCH 2013 ADC78H90 ConverterElectricalCharacteristics(1)(continued) The followingspecificationsapplyforAV DD = DV DD = +2.7V to5.25V,AGND = DGND = 0V,fSCLK = 8 MHz, fSAMPLE = 500 KSPS, unlessotherwisenoted.BoldfacelimitsapplyforTA = TMIN toTMAX :allotherlimitsTA = 25°C. LimitsSymbol Parameter Conditions Typical Units(2) POWER SUPPLY CHARACTERISTICS (CL = 10 pF) 2.7 V (min)AV DD , Analogand DigitalSupplyVoltages AV DD ≥ DV DDDV DD 5.25 V (max) AV DD = DV DD = +4.75V to+5.25V, 1.65 2.3 mA (max)fSAMPLE = 500 kSPS, fIN = 40 kHzTotalSupplyCurrent,Normal Mode (Operational,CS low) AV DD = DV DD = +2.7V to+3.6V, 0.5 2.3 mA (max)fSAMPLE = 500 kSPS, fIN = 40 kHz IA + ID AV DD = DV DD = +4.75V to+5.25V, 200 nAfSAMPLE = 0 kSPSTotalSupplyCurrent,Shutdown (CS high) AV DD = DV DD = +2.7V to+3.6V, 200 nAfSAMPLE = 0 kSPS \\AVDD = DV DD = +4.75V to+5.25V 8.3 12 mW (max)Power Consumption,Normal Mode (Operational,CS low) AV DD = DV DD = +2.7V to+3.6V 1.5 8.3 mW (max) PD AV DD = DV DD = +4.75V to+5.25V 0.5 µWPower Consumption,Shutdown (CS high) AV DD = DV DD = +2.7V to+3.6V 0.3 µW AC ELECTRICAL CHARACTERISTICS fSCLK Maximum ClockFrequency 8 MHz (min) fSMIN Minimum ClockFrequency 50 kHz fS Maximum Sample Rate 500 KSPS (min) tCONV ConversionTime 13 SCLK cycles 40 % (min) DC SCLK DutyCycle 50 60 % (max) tACQ Track/HoldAcquisitionTime Full-ScaleStepInput 3 SCLK cycles ThroughputTime AcquisitionTime + ConversionTime 16 SCLK cycles fRATE ThroughputRate 500 kSPS (min) tAD ApertureDelay 4 ns ADC78H90 Timing Specifications The followingspecificationsapplyforAV DD = DV DD = +2.7V to5.25V,AGND = DGND = 0V,fSCLK = 8 MHz, fSAMPLE = 500 KSPS, C L = 50 pF,BoldfacelimitsapplyforTA = TMIN toTMAX :allotherlimitsTA = 25°C. LimitsSymbol Parameter Conditions Typical Units(1) SetupTime SCLK HightoCS Fallingt1a (2) 10 ns (min)Edge HoldtimeSCLK Low toCS Fallingt1b (2) 10 ns (min)Edge t2 DelayfromCS UntilDOUT active 30 ns (max) Data Access Time afterSCLK Fallingt3 30 ns (max)Edge Data SetupTime PriortoSCLK Risingt4 10 ns (min)Edge t5 Data ValidSCLK HoldTime 10 ns (min) t6 SCLK HighPulseWidth 0.4x tSCLK ns (min) t7 SCLK Low PulseWidth 0.4x tSCLK ns (min) CS RisingEdge toDOUT High-t8 20 ns (max)Impedance (1) TestedlimitsarespecifiedtoTI's AOQL (AverageOutgoingQualityLevel). (2) Clockmay be inany state(highorlow)when CS isasserted,withtherestrictionson setupand holdtimegivenby t1a and t1b. Copyright© 2003–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:ADC78H90

DONT DONTC ADD2 ADD1 ADD0 DONTC DONTC DONTC DB11 DB9 DB8 DB1 1687654321 DB0 DIN DOUT SCLK CS ADC78H90 SNAS227D –NOVEMBER 2003–REVISED MARCH 2013 www.ti.com Timing Diagrams Figure2. Timing TestCircuit Figure3. ADC78H90 OperationalTiming Diagram Figure4. ADC78H90 SerialTiming Diagram

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www.ti.com SNAS227D –NOVEMBER 2003–REVISED MARCH 2013 Figure5. SCLK and CS Timing Parameters SpecificationDefinitions ACQUISITION TIME isthetimerequiredtoacquiretheinputvoltage.Thatis,itistimerequiredforthehold capacitortochargeup totheinputvoltage. APERTURE DELAY isthetimebetween thefourthfallingSCLK edge ofa conversionand thetimewhen the inputsignalisacquiredorheldforconversion. CONVERSION TIME isthetimerequired,aftertheinputvoltageisacquired,fortheADC toconverttheinput voltagetoa digitalword. CROSSTALK isthecouplingofenergyfromone channelintotheotherchannel,ortheamount ofsignalenergy fromone analoginputthatappearsatthemeasured analoginput. DIFFERENTIAL NON-LINEARITY (DNL) isthemeasure ofthemaximum deviationfromtheidealstepsizeof1 LSB. DUTY CYCLE istheratioofthetimethata repetitivedigitalwaveform ishightothetotaltimeofone period.The specificationherereferstotheSCLK. EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) isanothermethod ofspecifyingSignal-to-Noise and DistortionorSINAD. ENOB isdefinedas (SINAD -1.76)/6.02and saysthattheconverteris equivalenttoa perfectADC ofthis(ENOB) number ofbits FULL POWER BANDWIDTH isa measure ofthefrequencyatwhichthereconstructedoutputfundamental drops3 dB belowitslowfrequencyvaluefora fullscaleinput. LSB),afteradjustingforoffseterror. INTEGRAL NON-LINEARITY (INL)isa measure ofthedeviationofeach individualcode froma linedrawn from negativefullscale(½ LSB belowthefirstcode transition)throughpositivefullscale(½ LSB above thelast code transition).The deviationofany givencode fromthisstraightlineismeasured fromthecenterofthat code value. INTERMODULATION DISTORTION (IMD)isthecreationofadditionalspectralcomponents as a resultoftwo sinusoidalfrequenciesbeingappliedtotheADC inputatthesame time.Itisdefinedas theratioofthe power inthesecond and thirdorderintermodulationproductstothesum ofthepower inbothofthe originalfrequencies.IMD isusuallyexpressedindB. MISSING CODES arethoseoutputcodes thatwillneverappearattheADC outputs.The ADC78H90 isensured nottohave any missingcodes. 0.5LSB). SIGNAL TO NOISE RATIO (SNR) istheratio,expressedindB,oftherms valueoftheinputsignaltotherms valueofthesum ofallotherspectralcomponents belowone-halfthesamplingfrequency,notincluding harmonicsord.c. SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Istheratio,expressedindB,oftherms valueof theinputsignaltotherms valueofalloftheotherspectralcomponents belowhalftheclockfrequency, Copyright© 2003–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:ADC78H90

10‡ A A ++A logTHD = 20 ADC78H90 SNAS227D –NOVEMBER 2003–REVISED MARCH 2013 www.ti.com includingharmonicsbutexcludingd.c. SPURIOUS FREE DYNAMIC RANGE (SFDR) isthedifference,expressedindB,between therms valuesofthe inputsignaland thepeak spurioussignalwhere a spurioussignalisany signalpresentintheoutput spectrumthatisnotpresentattheinput,excludingd.c. TOTAL HARMONIC DISTORTION (THD) istheratio,expressedindB ordBc,oftherms totalofthefirstfive harmoniccomponents attheoutputtotherms leveloftheinputsignalfrequencyas seen attheoutput. THD iscalculatedas where

• Af1 istheRMS power oftheinputfrequencyattheoutput
• Af2 throughAf6 aretheRMS power inthefirst5 harmonicfrequencies (1) THROUGHPUT TIME istheminimum timerequiredbetween thestartoftwo successiveconversion.Itisthe acquisitiontimeplustheconversiontime.Inthecase oftheADC78H90, thisis16 SCLK periods.

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www.ti.com SNAS227D –NOVEMBER 2003–REVISED MARCH 2013 TypicalPerformance Characteristics TA = +25°C, fSAMPLE = 500 kSPS, fSCLK = 8 MHz, fIN = 40.2kHz unlessotherwisestated. DNL DNL Figure6. Figure7. INL INL Figure8. Figure9. DNL vs.Supply INL vs.Supply Figure10. Figure11. Copyright© 2003–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:ADC78H90

SNAS227D –NOVEMBER 2003–REVISED MARCH 2013 www.ti.com TypicalPerformance Characteristics(continued) TA = +25°C, fSAMPLE = 500 kSPS, fSCLK = 8 MHz, fIN = 40.2kHz unlessotherwisestated. SNR vs.Supply THD vs.Supply Figure12. Figure13. ENOB vs.Supply SNR vs.InputFrequency Figure14. Figure15. THD vs.InputFrequency ENOB vs.InputFrequency Figure16. Figure17.

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www.ti.com SNAS227D –NOVEMBER 2003–REVISED MARCH 2013 TypicalPerformance Characteristics(continued) TA = +25°C, fSAMPLE = 500 kSPS, fSCLK = 8 MHz, fIN = 40.2kHz unlessotherwisestated. SpectralResponse SpectralResponse Figure18. Figure19. Power Consumption vs.Throughput Figure20. Copyright© 2003–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:ADC78H90

+ CONTROL LOGIC CHARGE REDISTRIBUTION DAC SW2 AIN8 AV DD /2 AIN1 MUX AGND SAMPLING CAPACITOR SW1 + CONTROL LOGIC CHARGE REDISTRIBUTION DAC AV DD /2 SW2 AIN8 ADC78H90 SNAS227D –NOVEMBER 2003–REVISED MARCH 2013 www.ti.com APPLICATIONS INFORMATION ADC78H90 OPERATION The ADC78H90 is a successive-approximationanalog-to-digitalconverterdesigned around a charge- redistributiondigital-to-analogconverter.Simplifiedschematicsof the ADC78H90 in both trackand hold operationare shown inFigure21 and Figure22, respectively.In Figure21, the ADC78H90 isintrackmode: switchSW1 connectsthesamplingcapacitortoone ofeightanaloginputchannelsthroughthemultiplexer,and SW2 balancesthecomparatorinputs.The ADC78H90 isinthisstateforthefirstthreeSCLK cyclesafterCS is broughtlow. There isno power-updelayordummy conversionswiththeADC78H90. The ADC isabletosample and convert an inputtofullresolutioninthefirstconversionimmediatelyfollowingpower up.The firstconversionresultafter power up willbe thatofthefirstchannel. Figure22 shows the ADC78H90 in hold mode: switchSW1 connects the sampling capacitorto ground, maintainingthesampled voltage,and switchSW2 unbalancesthecomparator.The controllogictheninstructs thecharge-redistributionDAC toadd orsubtractfixedamounts ofchargetoorfromthesamplingcapacitoruntil thecomparatorisbalanced.When thecomparatorisbalanced,thedigitalword suppliedtotheDAC isthedigital representationoftheanaloginputvoltage.The ADC78H90 isinthisstateforthelastthirteenSCLK cyclesafter CS isbroughtlow. Figure21. ADC78H90 inTrack Mode Figure22. ADC78H90 inHold Mode The timewhen CS islowisconsidereda serialframe.Each oftheseframesshouldcontainan integermultipleof

16 SCLK cycles,duringwhich timea conversionisperformedand clockedout at the DOUT pinand data is

clockedintotheDIN pintoindicatethemultiplexeraddressforthenextconversion.

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www.ti.com SNAS227D –NOVEMBER 2003–REVISED MARCH 2013 USING THE ADC78H90 Figure3 and Figure4 fortheADC78H90 are shown inTimingDiagrams.CS, chipselect,initiatesconversions and framestheserialdatatransfers.SCLK (serialclock)controlsboththeconversionprocessand thetimingof serialdata.DOUT istheserialdataoutputpin,where a conversionresultissentas a serialdatastream,MSB first.Data tobe writtentotheADC78H90's ControlRegisterisplacedon DIN,theserialdatainputpin.New data iswrittentoDIN witheach conversion. A serialframeisinitiatedon thefallingedge ofCS and ends on therisingedge ofCS. Each framemust contain an integermultipleof16 risingSCLK edges.The ADC outputdata(DOUT) isina highimpedance statewhen CS ishighand isactivewhen CS islow.Thus,CS actsas an outputenable.Additionally,thedevicegoes intoa power down statewhen CS ishigh. Duringthe first3 cyclesof SCLK, the ADC isinthe trackmode, acquiringthe inputvoltage.For the next13 SCLK cyclestheconversionisaccomplishedand thedataisclockedout,MSB first.Ifthereismore thanone conversionina frame,theADC willre-enterthetrackmode on thefallingedge ofSCLK aftertheN*16thrising edge ofSCLK, and re-enterthehold/convertmode on theN*16+4thfallingedge ofSCLK, where "N"must be an integer. When CS isbroughthigh,SCLK isinternallygated off.IfSCLK isin a low statewhen CS goes high,the subsequentfallofCS willgeneratea fallingedge oftheinternalversionofSCLK, puttingtheADC intothetrack mode. Thisisseen by theADC as thefirstfallingedge ofSCLK. IfSCLK isina highstatewhen CS goes high, theADC entersthetrackmode on thefirstfallingedge ofSCLK afterthefallingedge ofCS. Duringeach conversion,dataisclockedintotheDIN pinon thefirst8 risingedges ofSCLK afterthefallofCS. For each conversion,itisnecessarytoclockinthedataindicatingtheinputthatisselectedfortheconversion afterthecurrentone.See Table1,Table2,and Table3. IfCS and SCLK go low simultaneously,itisthefollowingrisingedge ofSCLK thatisconsideredthefirstrising edge forclockingdataintoDIN. Table1.ControlRegisterBits Bit7 (MSB) Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 DONTC DONTC ADD2 ADD1 ADD0 DONTC DONTC DONTC Table2.ControlRegisterBitDescriptions Bit#: Symbol: Description 7,6,2,1,0 DONTC Don'tcare.The valueofthesebitdo notaffectthedevice.

5 ADD2 These threebitsdeterminewhichinputchannelwillbe sampled and convertedon thenextfalling

edge ofCS. The mapping between codes and channelsisshown inTable3.4 ADD1

3 ADD0

Table3.InputChannel Selection ADD2 ADD1 ADD0 InputChannel 0 0 0 AIN1 (Default) 0 0 1 AIN2 0 1 0 AIN3 0 1 1 AIN4 1 0 0 AIN5 1 0 1 AIN6 1 1 0 AIN7 1 1 1 AIN8 Copyright© 2003–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:ADC78H90

100:

0.1 PF 680 nF 1 PF

TANT 0.1 PF 0.1 PF1 PF DGND ADC78H90 SNAS227D –NOVEMBER 2003–REVISED MARCH 2013 www.ti.com ADC78H90 TRANSFER FUNCTION The outputformatof the ADC89H90 isstraightbinary.Code transitionsoccur midway between successive integerLSB values.The LSB widthfortheADC78H90 isAV DD /4096.The idealtransfercharacteristicisshown inFigure23.The transitionfroman outputcode of0000 0000 0000 toa code of0000 0000 0001 isat1/2LSB, ora voltageofAV DD /8192.Othercode transitionsoccuratstepsofone LSB. Figure23. IdealTransferCharacteristic TYPICAL APPLICATION CIRCUIT A typicalapplicationof the ADC78H90 isshown inFigure24. The splitanalogand digitalsuppliesare both providedinthisexample by the TI LP2950 low-dropoutvoltageregulator,availablein a varietyof fixedand adjustableoutputvoltages.The analog supplyis bypassed witha capacitornetwork locatedcloseto the ADC78H90. The digitalsupplyisseparatedfromtheanalogsupplyby an isolationresistorand conditionedwith additionalbypass capacitors.The ADC78H90 uses the analogsupply(AVDD ) as itsreferencevoltage,so itis veryimportantthatAV DD be keptas cleanas possible.Because oftheADC78H90's lowpower requirements,itis alsopossibletouse a precisionreferenceas a power supplytomaximizeperformance.The four-wireinterfaceis alsoshown connectedtoa microprocessororDSP. Figure24. TypicalApplicationCircuit

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www.ti.com SNAS227D –NOVEMBER 2003–REVISED MARCH 2013 ANALOG INPUTS An equivalentcircuitforone oftheADC78H90's inputchannelsisshown inFigure25.DiodesD1 and D2 provide ESD protectionfortheanaloginputs.At no timeshouldan analoginputgo beyond (AVDD + 300 mV) or(GND - 300 mV), as theseESD diodeswillbeginconducting,whichcouldresultinerraticoperation. The capacitorC1 inFigure25 has a typicalvalueof3 pF,and ismainlythepackage pincapacitance.Resistor R1 istheon resistanceofthemultiplexerand track/holdswitch,and istypically500 ohms. CapacitorC2 isthe ADC78H90 samplingcapacitor,and istypically30 pF.The ADC78H90 willdeliverbestperformancewhen driven by a low-impedancesourcetoeliminatedistortioncaused by thechargingofthesamplingcapacitance.Thisis especiallyimportantwhen usingtheADC78H90 tosample AC signals.Alsoimportantwhen samplingdynamic signalsisa band-passorlow-passfiltertoreduceharmonicsand noise,improvingdynamicperformance. Figure25. EquivalentInputCircuit DIGITAL INPUTS AND OUTPUTS The ADC78H90's digitalinputs(SCLK, CS, and DIN)arelimitedby and cannotexceed theanalogsupplyvoltage AV DD .The digitalinputpinsarenotpronetolatch-up;SCLK, CS, and DIN may be assertedbeforeDV DD without any risk. POWER SUPPLY CONSIDERATIONS The ADC78H90 has two supplies,althoughtheycouldbothhave thesame potential.There aretwo majorpower supplyconcernswiththisproduct.They arerelativepower supplylevels,includingpower on sequencing,and the effectofdigitalsupplynoiseon theanalogsupply. Power Management The ADC78H90 isa dual-supplydevice.These two suppliesshare ESD resources,and thus care must be exercisedtoensurethatthepower suppliesare appliedinthecorrectsequence.To avoidturningon theESD diodes,the digitalsupply (DVDD ) cannot exceed the analog supply (AVDD ) by more than 300 mV. The ADC78H90's analogpower supplymust,therefore,be appliedbefore(orconcurrentlywith)the digitalpower supply. The ADC78H90 isfullypowered-upwhenever CS islow,and fullypowered-down whenever CS ishigh,withone exception:theADC78H90 automaticallyenterspower-down mode between the16thfallingedge ofa conversion and the1stfallingedge ofthesubsequentconversion(seeFigure3). The ADC78H90 can performmultipleconversionsback toback;each conversionrequires16 SCLK cycles.The ADC78H90 willperformconversionscontinuouslyas longas CS isheldlow. The usermay tradeoffthroughputforpower consumptionby simplyperformingfewerconversionsperunittime. Figure20 inTypicalPerformanceCharacteristicsshows thetypicalpower consumptionoftheADC78H90 versus throughput.To calculatethepower consumption,simplymultiplythefractionoftimespentinthenormalmode by thenormalmode power consumption(8.3mW withAV DD = DV DD = +3.6V,forexample),and add thefractionof timespentinshutdown mode multipliedby theshutdown mode power dissipation(0.3mW withAV DD = DV DD = +3.6V). Copyright© 2003–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:ADC78H90

SNAS227D –NOVEMBER 2003–REVISED MARCH 2013 www.ti.com Power Supply Noise Considerations The chargingofany outputloadcapacitancerequirescurrentfrom thedigitalsupply,DV DD .The currentpulses requiredfrom thesupplytochargetheoutputcapacitancewillcause voltagevariationson thedigitalsupply.If these variationsare largeenough, they could cause degrade SNR and SINAD performanceof the ADC. Furthermore,iftheanalogand digitalsuppliesare tieddirectlytogether,thenoiseon thedigitalsupplywillbe coupled directlyintothe analog supply,causinggreaterperformancedegradationthan noise on the digital supply.Furthermore,dischargingtheoutputcapacitancewhen thedigitaloutputgoes froma logichightoa logic low willdump currentintothe die substrate,which isresistive.Load dischargecurrentswillcause "ground bounce"noiseinthesubstratethatwilldegradenoiseperformanceifthatcurrentislargeenough.The largeris theoutputcapacitance,themore currentflowsthroughthediesubstrateand thegreateristhenoisecoupledinto theanalogchannel,degradingnoiseperformance. The firstsolutionisto decouplethe analogand digitalsuppliesfrom each other,or use separatesuppliesfor them,tokeep digitalnoiseoutoftheanalogsupply.To keep noiseoutofthedigitalsupply,keep theoutputload capacitanceas smallas practical.Iftheloadcapacitanceisgreaterthan25 pF, use a 100 Ω seriesresistorat the ADC output,locatedas closeto the ADC outputpinas practical.Thiswilllimitthe charge and discharge currentoftheoutputcapacitanceand improvenoiseperformance.

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REVISION HISTORY

Changes from RevisionC (March 2013)toRevisionD Page Copyright© 2003–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:ADC78H90

www.ti.com 1-Nov-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) ADC78H90CIMT/NOPB Active Production TSSOP (PW) | 16 92 | TUBE Yes SN Level-1-260C-UNLIM -40 to 85 78H90 CIMT ADC78H90CIMT/NOPB.A Active Production TSSOP (PW) | 16 92 | TUBE Yes SN Level-1-260C-UNLIM -40 to 85 78H90 CIMT ADC78H90CIMT/NOPB.B Active Production TSSOP (PW) | 16 92 | TUBE - Call TI Call TI -40 to 85 ADC78H90CIMTX/NOPB Active Production TSSOP (PW) | 16 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 78H90 CIMT ADC78H90CIMTX/NOPB.A Active Production TSSOP (PW) | 16 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 78H90 CIMT ADC78H90CIMTX/NOPB.B Active Production TSSOP (PW) | 16 2500 | LARGE T&R - Call TI Call TI -40 to 85 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative Addendum-Page 1

www.ti.com 1-Nov-2025 and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADC78H90CIMTX/NOPB TSSOP PW 16 2500 367.0 367.0 35.0 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) ADC78H90CIMT/NOPB PW TSSOP 16 92 495 8 2514.6 4.06 ADC78H90CIMT/NOPB.A PW TSSOP 16 92 495 8 2514.6 4.06 Pack Materials-Page 3

www.ti.com PACKAGE OUTLINE C 14X 0.65 4.55 16X 0.30 0.17 6.6

6.2 TYP

1.2 MAX

0.15 0.05 0.25 GAGE PLANE 0 -8 4X (0 -12 ) B 4.5 4.3 NOTE 4 A 5.1 4.9 NOTE 3 0.75 0.50 (0.15) TYP TSSOP - 1.2 mm max heightPW0016A SMALL OUTLINE PACKAGE 4220204/B 12/2023

0.1 C A B

0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. SEATING PLANE A 20 DETAIL A TYPICAL SCALE 2.500

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

0.05 MIN

16X (1.5) 16X (0.45) 14X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0016A SMALL OUTLINE PACKAGE 4220204/B 12/2023 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SYMM SYMM 8 9 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 16X (1.5) 16X (0.45) 14X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0016A SMALL OUTLINE PACKAGE 4220204/B 12/2023 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X SYMM SYMM 8 9

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