ADC700

ADC700 BURR-BROWN | Alldatasheet

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Technical content

16-Bit Resolution With Microprocessor Interface A/D CONVERTER

DESCRIPTION

The ADC700 is a complete 16-bit resolution succes- sive approximation analog-to-digital converter. The reference circuit, containing a buried zener, is laser-trimmed for minimum temperature coefficient. The clock oscillator is current-controlled for excellent stability over temperature. Gain and Zero errors may be externally trimmed to zero. Analog input ranges of 0V to +5V, 0V to +10V, 0V to +20V, ±2.5V, ±5V, and ±10V are available. The conversion time is 17µs max for a 16-bit conver- sion over the three specification temperature ranges. After a conversion, output data is stored in a latch separate from the successive approximation logic. This permits reading data during the next conversion, a feature that provides flexible interface timing, espe- cially for interrupt-driven interfaces. Data is available in two 8-bit bytes from TTL-compat- ible three-state output drivers. Output data is coded in Straight Binary for unipolar input signals and Bipolar Offset Binary or Twos complement for bipolar input signals. BOB or BTC is selected by a logic function available on one of the pins. The ADC700 is available in commercial, industrial and military temperature ranges. It is packaged in a hermetic 28-pin side-braze ceramic DIP.

FEATURES

l COMPLETE WITH REFERENCE, CLOCK, 8-BIT PORT MICROPROCESSOR INTERFACE l CONVERSION TIME: 17 µs max l LINEARITY ERROR: ±0.003% FSR max l NO MISSING CODES TO 14 BITS OVER TEMPERATURE l SPECIFIED AT ±12V AND ±15V SUPPLIES l OUTPUT BUFFER LATCH FOR IMPROVED INTERFACE TIMING FLEXIBILITY l PARALLEL AND SERIAL DATA OUTPUT l SMALL PACKAGE: 28-Pin DIP Clock and Control Logic CS RD WR HBEN BTCEN Reset Successive Approximation Register Status Serial Data Strobe Data Ready Serial Data 20V 10V Analog Inputs Comparator 16-Bit D/A Converter Data Latch State State Parallel Data Voltage Reference Bipolar Offset SJ International Airport Industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1989 Burr-Brown Corporation PDS-856A Printed in U.S.A. October, 1993

At TA = 25°C and at rated supplies: VDD = +5V, +VCC = +12V or +15V, –VCC = –12V or –15V, unless otherwise noted. ADC700JH,AH,RH ADC700KH,BH,SH CHARACTERISTICS MIN TYP MAX MIN TYP MAX UNITS RESOLUTION 16 * Bits ANALOG INPUTS Voltage Ranges Bipolar ±2.5, ±5, ±10 * V Unipolar 0 to +5, 0 to +10, 0 to +20 * V Impedance (Direct Input) 0V to +10V, ±5V 5 ±1% * k Ω 0V to +20V, ±10V 10 ±1% * k Ω DIGITAL SIGNALS (Over Specification Temperature Range) Inputs Logic Levels(1) VIL 0 +0.8 * * V IIH (VI = +2.7V) ±10 * µA IIL (VI = +0.4V) ±20 * µA Outputs Logic Levels V OL (IOL = –1.6mA) +0.4 * V VOH (IOH = +20µA) +2.4 * V ILEAKAGE Data Outputs Only, High Z 10 * nA TRANSFER CHARACTERISTICS ACCURACY Linearity Error ±0.006 ±0.003 % of FSR (2) Differential Linearity Error ±0.012 ±0.006 % of FSR Gain Error(3) ±0.1 ±0.2 * * % Zero Error(3) Bipolar Zero ±0.1 ±0.2 * * % of FSR Unipolar Zero ±0.05 ±0.1 * * % of FSR Noise at Transitions (3σp-p) ±0.001 ±0.003 * * % of FSR Power Supply Sensitivity +VCC ±0.0015 * %FSR/%V CC –VCC ±0.0015 * %FSR/%V CC VDD ±0.0005 * %FSR/%V DD DRIFT (Over Specification Temperature Range) Gain Drift ±8 ±15 * * ppm/ °C Zero Drift Bipolar Zero ±5 ±10 * * ppm of FSR/ °C Unipolar Zero ±2 ±4 * * ppm of FSR/ °C Linearity Drift ±1 ±3* ±2 ppm of FSR/ °C No Missing Codes Temperature Range JH (13-bit), KH (14-bit) 0 +70 * * °C AH (13-bit), BH (14 bit) –25 +85 * * °C RH (13-bit), SH (14-bit) –55 +125 * * °C CONVERSION TIME 16 bits 15 17 * * µs WARM–UP TIME 5 * min OUTPUT DATA CODES (4) Unipolar Parallel USB * Bipolar Parallel(5) BTC, BOB * Serial Output (NRZ) USB, BOB * POWER SUPPLY REQUIREMENTS Voltage Range Current(5) +VCC +10 +15 * * mA VDD +17 +20 * * mA Power Dissipation 645 765 * * mW TEMPERATURE RANGE Specification J, K Grades 0 +70 * * °C A, B Grades –25 +85 * * °C R, S Grades –55 +125 * * °C Storage –65 +150 * * °C

*Same specs as ADC700JH, AH, RH.

ORDERING INFORMATION

MODEL RANGE ERROR (%FSR) 1–24 25–99 100+ ADC700JH 0 °C to 70°C ±0.006 ADC700KH 0 °C to 70°C ±0.003 ADC700AH –25 °C to +85°C ±0.006 ADC700BH –25 °C to +85°C ±0.003 ADC700RH –55 °C to +125°C ±0.006 ADC700SH –55 °C to +125°C ±0.003 ABSOLUTE MAXIMUM RATINGS DD + 0.5V NOTES: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maxi- mum rating conditions for extended periods may affect device reliability. PACKAGING INFORMATION PACKAGE DRAWING MODEL PACKAGE NUMBER (1) ADC700JH 28-Pin Ceramic DIP 237 ADC700KH 28-Pin Ceramic DIP 237 ADC700AH 28-Pin Ceramic DIP 237 ADC700BH 28-Pin Ceramic DIP 237 ADC700RH 28-Pin Ceramic DIP 237 ADC700SH 28-Pin Ceramic DIP 237 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. LIMIT AT LIMIT AT T A = 0, +70°C LIMIT AT PARAMETER T A = 25°C –25 °C, +85°CT A = –55°C, +125°C UNITS DESCRIPTION CONVERSION AND SERIAL DATA OUTPUT TIMING t1 0 0 0 ns, min CS to WR Setup time t2 110 130 145 ns, max WR to Status delay t3 40 40 40 ns, min WR pulse width t4 0 0 0 ns, min CS to WR Hold time t5 15 17 17 µs, max Conversion time t6 550 600 650 ns, max Data Ready to Status time t7 1100 1150 1250 ns, max WR to first Serial Data Strobe t8 250 210 200 ns, min First Serial Data to first Serial Data Strobe t9 310 360 400 ns, max Last Serial Data Strobe to Status t10 0 0 0 ns, min Status to WR Setup time PARALLEL DATA OUTPUT TIMING t11 0 0 0 ns, min HBEN to RD Setup time t12 0 0 0 ns, min CS to RD Setup time t13 (7) 50 58 66 ns, max High Byte Data Valid after RD C L = 20pF (High Byte bus access time) 70 81 95 ns, max High Byte Data Valid after RD C L = 100pF (High Byte bus access time) t14 40 40 40 ns, min RD pulse width t15 40 45 50 ns, max Data Ready delay from RD (HBEN asserted) t16(8) 50 60 65 ns, max Data Hold time after RD (bus relinquish time) t17 0 0 0 ns, min RD to CS Hold time t18 0 0 0 ns, min RD to HBEN Hold time RESET TIMING t19 60 70 80 ns, max Data Ready low delay from Reset t20 70 81 95 ns, max Status low delay from Reset NOTES: (1) TTL, LSTTL, and 5V CMOS compatible. (2) FSR means Full Scale Range. For example, unit connected for ±10V range has 20V FSR. (3) Externally adjustable to zero. (4) See Table I. USB – Unipolar Straight Binary; BTC – Binary Two’s Complement; BOB – Bipolar Offset Binary; NRZ – Non Return to Zero. (5) Max supply current is specified at rated supply voltages. (6) All input control signals are specified with t RISE = tFALL = 5ns (10% to 90% of 5V) and timed from a voltage required for the data lines to change 0.5V when loaded with the circuits of Figure 2. TIMING SPECIFICATIONS (6) At VDD = +5V, +VCC = +12V or +15V, –VCC = –12V or –15V, unless otherwise noted.

ADC700 Parallel Output Timing. Start of Conversion and Serial Data Output Timing. t11 HBEN Low Byte High Byte CS RD Parallel Data Data Ready t18 t11 t17t12t17t12 t13 t16 t13 t16 DB8–DB15 DB0–DB7t15 t14 t14 ADC700 Reset Function Timing Diagram. t19 t20 Reset Data Ready Status The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. t10 t3t1 t4 CS WR Status Data Ready Serial Data Strobe Serial Data t7 t9

The ADC700 is a 16-bit resolution successive approxima- tion A/D converter. Parallel digital data as well as serial data is available. Several features have been included in the ADC700 making it easier to interface with microprocessors and/or serial data systems. Several analog input ranges are available. Some of the key operating features are described here. More detail is given in later sections of the data sheet. Refer to the block diagram above. RESET The ADC700 has a Reset input that must be asserted upon power-up or after a power interruption. This initializes the SAR, the output buffer register and Data Ready flag. Since microprocessor systems already use a power-on reset circuit, the same system reset signal can be used to initialize the ADC700. PARALLEL DATA The parallel data output is available through an 8-bit port with 3-state output drivers. High byte and low byte are selected by HBEN (pin 10). A buffer/latch is included between the successive approxi- mation register (SAR) and the 3-state drivers. This feature permits more flexible interface timing than is possible from most successive approximation converters. The “old” word can be read during the next conversion. A Data Ready flag (pin 12) is asserted when a “new” word is in the buffer register. The Data Ready flag goes low (“0”) when the most significant byte (high byte) is read. If the “old” word is not read, or if only the least significant byte (low byte) is read, Data Ready is not reset. The next conversion output will overwrite the data latch when the conversion is complete. The Data Ready flag remains high. Refer to timing diagrams in the Specifications section. SERIAL DATA Sixteen-bit serial data output is available (pin 11) along with a serial output strobe (pin 14). This serial data strobe is not the internal SAR clock but is a special strobe for serial data consisting of 16 negative-going edges (during conversion) occurring about 200ns after each serial data bit is valid. This feature eases the interface to shift registers or through opto- couplers for applications requiring galvanic isolation. STATUS The familiar Status (or Busy) flag, present in successive approximation A/D converters, is available (pin 13) and indicates that a conversion is in progress. Status is valid 110ns after assertion of the convert command (WR low). Status cannot be used as a sample-hold control because there is not enough time for the sample-hold to settle to the required error band before the ADC700 makes its first conversion decision. CHIP SELECT CS (pin 9) selects the ADC700. No other functions can be implemented unless CS is asserted. WR (pin 7) is the start- of-conversion strobe. RD strobes each output data byte, selected by HBEN (pin 10), to the 3-state drivers. LSB 16-Bit D/A Converter Successive Approximation Register 20V Range 10V Range Analog Common Digital Common V BTCEN DB15/DB7 DB14/DB6 DB13/DB5 DB12/DB4 DB11/DB3 DB10/DB2 DB9/DB1 DB8/DB0 DD Comparator In Bipolar Offset Gain Adjust Reset WR RD CS HBEN Serial Data Data Ready Status Serial Data Strobe CC+V CC–V All internal control lines not shown. Refer to Figures 4 and 5 for Offset and Gain Adjust connections. Data Latch 3-State Drivers MSB LSB Voltage Reference Clock and Clock Logic 5kΩ5kΩ MSB Control Logic

ally measured for this spec. The ideal gain is VFSR –2LSB. Gain Error is expressed in % (of reading). See Figure 3. external trim potentiometers. Again, transition values are the actual measured parameters. expressed as a percentage of FSR. Error is expressed as a percentage of FSR. units of %FSR/% change in each supply voltage. tivity performance of ADC700 versus ripple frequency. first-order errors in 16-bit resolution devices. pling into sensitive converter circuits. separate the analog and digital common lines. Common pins as close to the package as possible. minimum length to minimize crosstalk to analog wiring. signals. If they must cross, cross them at right angles. FIGURE 4. Power Supply Rejection Ripple vs Frequency.

capacitor whether or not the gain adjust feature is used. plane to reduce noise pickup. select the proper driving amplifier. frequencies yet preserves the accuracy at low frequencies. described in the calibration section. procedure in described in the Operating Instructions section. bypassed with 0.01µF or larger to Analog Common. Gain potentiometers. Offset is adjusted first and then Gain. in the static calibration example. TABLE I. ADC700 Input Range Connections. FIGURE 5. Wideband Buffer Reduces Output Impedance at