ADC601

ADC601 BURR-BROWN | Alldatasheet

Document overview

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Technical content

Duolithic™ Burr-Brown Corporation 12-Bit 900ns ANALOG-TO-DIGITAL CONVERTER

FEATURES

G FAST CONVERSION: 900ns G CAN BE SHORT-CYCLED G INPUT RANGES: ±5V, ±10V, 0 to –10V G HIGH SIGNAL/NOISE RATIO: 68dB G LOW IMD: 75dB G PARALLEL AND SERIAL OUTPUT G 32-PIN CERAMIC DIP PACKAGE

APPLICATIONS

G DIGITAL SIGNAL PROCESSING G HIGH-SPEED DATA ACQUISITION SYSTEMS G MEDICAL INSTRUMENTATION G ANALYTICAL INSTRUMENTATION G TEST AND IMAGING SYSTEMS G WAVEFORM ANALYZERS

DESCRIPTION

The ADC601 is a high-speed Duolithic™ (two chips) successive approximation analog-to-digital converter. This unique two-chip design utilizes a bipolar technol- ogy with on-chip thin film resistors to preserve analog accuracy and a high-speed CMOS chip to perform digital logic control. Outstanding linearity, noise, and dynamic range are achieved by this converter design. The ADC601 has been tested with several sample/hold amplifiers and distortion results are documented in this data sheet. The ADC601 is complete with internal reference, clock, and comparator and is packaged in a 32-pin ceramic DIP. Conversion time is set at the factory to 900ns. Serial and parallel output performance is guaranteed with no missing codes over the full input voltage, power supply, and operating temperature range. The gain and offset errors are laser trimmed to specifica- tion. Optionally they may be externally adjusted to zero. Internal scaling resistors are provided for the selection of analog signal input ranges of ±5V, ±10V and 0V to –10V. The ADC601’s input is specifically designed to be easily driven with minimal disturbance to the driv- ing amplifier. Output codes are available in complementary binary for unipolar inputs and bipolar offset binary for bipolar inputs. All digital inputs and outputs are TTL-compatible. Power supply requirements are ±15V and +5V. 12-Bit Successive Approx Register (SAR) Clock Reference 12-Bit D/A Converter Parallel Digital Output Clock Rate Control Clock Out Status Serial Out Bipolar Offset Comparator In Input Range Select Convert Command Comparator International Airport Industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 ©1989 Burr-Brown Corporation PDS-867C Printed in U.S.A. March, 1992 ADC601

TCASE = +25°C, 900ns conversion time, ±VCC = ±15V, +VDD = +5V, and 6-minute warm-up in a normal convection environment unless otherwise noted. Guaranteed Guaranteed ADC601JG ADC601KG PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS RESOLUTION Bits ANALOG CHARACTERISTICS INPUTS Voltage Ranges: Bipolar Full Scale(FSR)(1)(2) ±5, ±10 V Unipolar Full Scale(FSR)(1)(2) 0 to –10 V Impedance: –10V to 0V, ±5V 1.4 kΩ ±10V 2.4 kΩ TRANSFER CHARACTERISTICS ACCURACY Gain Error(3) 990ns Conversion Time ±0.08 ±0.55 ±0.2 Input Offset Error(3): Unipolar 990ns Conversion Time ±0.12 ±1.2 ±0.5 % of FSR Bipolar 990ns Conversion Time ±0.08 ±0.8 ±0.25 % of FSR Integral Linearity Error 990ns Conversion Time ±0.024 ±0.012 % of FSR Differential Linearity Error 990ns Conversion Time ±0.024 ±0.012 % of FSR No Missing Codes Power Supply Rejection of Offset and Gain ∆ +VCC = ±5% ±0.0036 %FSR/%VCC ∆ –VCC = ±5% ±0.0005 %FSR/%VCC ∆ +VDD = ±5% ±0.001 %FSR/%VDD DIGITAL CHARACTERISTICS INPUT Logic Family TTL-Compatible CMOS Convert Command Logic Voltages Logic Low +0.8 V Logic High +VDD V Convert Command Currents Logic Low –150 µA Logic High –150 µA Convert Command High Level When Converting CONVERSION TIME Factory Set Without User Adjustment 0.9 µs Power Supply Rejection of Conversion Time D +VDD = ±5% ns/%VDD OUTPUT Logic Family TTL-Compatible CMOS Bits 1 through 12, Serial, Status, Clock Out Logic Low, IOL = 3.2mA +0.1 +0.4 V Logic High, IOH = –1mA +2.7 +4.9 V Internal Clock Frequency MHz Status Low Level When Data Valid DYNAMIC CHARACTERISTICS (4) (5) (6) Tested using Sample/Hold Amplifier SHC804 and ADC601 (See Typical Performance Curves) Differential Linearity Error fC = 10kHz: 68.3% of All Codes 0.5 0.4 LSB 99.7% of All Codes 0.8 0.6 LSB 100% of All Codes 1.0 0.7 LSB Total Harmonic Distortion fC = 10kHz, fS = 500kHz –70 dBc fC = 10kHz, fS = 1MHz –74 dBc fC = 250kHz, fS = 500kHz –70 dBc fC = 500kHz, fS = 1MHz –68 dBc Two-Tone Intermodulation Distortion(7) fC = 11kHz and 15kHz, fS = 500kHz –79 dBc fC = 50kHz and 55kHz, fS = 500kHz –78 dBc fC = 90kHz and 110kHz, fS = 500kHz –77 dBc Signal-to-Noise and Distortion fC = 250kHz, fS = 500kHz dB (SINAD) Ratio fC = 500kHz, fS = 1MHz dB Signal-to-Noise Ratio (SNR) fC = 250kHz, fS = 500kHz dB fC = 500kHz, fS = 1MHz dB PERFORMANCE OVER TEMPERATURE Gain TMIN to TMAX ±10 ±30 ppm of FSR/°C Input Offset:Unipolar TMIN to TMAX ppm of FSR/°C Bipolar TMIN to TMAX ±10 ppm of FSR/°C Internal Linearity Error 0.9µs Conversion Time TMIN to TMAX ±0.02 ±0.015 % of FSR Differential Linearity Error 0.9µs Conversion Time TMIN to TMAX ±0.02 ±0.015 % of FSR No Missing Codes 0.9µs Conversion Time TMIN to TMAX\` Conversion Drift ns/°C

Supply Voltages: +VCC +14.25 +15 +15.75 V –VCC –14.25 –15 –15.75 V +VDD +4.75 +5.25 V Supply Currents: +ICC 5.4 7.0 mA –ICC –65 –84.5 mA +IDD 68.9 mA Power Consumption Nominal ±VCC and +VDD 1.3 1.7 W Thermal Resistance, θJC °C/W TEMPERATURE RANGE(8) Specification +70 Operating –25 +85 * Same specifications as for ADC601JG. NOTES: (1) Over or under range on the analog input results in constant maximum or minimum digital output. (2) FSR = Full Scale Range. (3) Adjustable to zero. (4) Dynamic tests are performed using SHC804 with ADC601 unless otherwise specified. Performance may vary depending upon choice of sample/hold. (5) See Typical Performance Curves. (6) dBc = level referred to carrier input signal = 0dB; fC = input frequency; fS = sampling frequency. (7) IMD is referred to the larger of the two input test signals. If referred to the peak envelope signal (≈0dB), the intermodulation products will be 6dB lower. For example, unit connected for ±10V has 20V FSR. (8) Temperature ranges refer to case temperature. Thermal resistance was measured on a small (5" diameter) handwired circuit board; with the test device in a (zero insertion force) socket. Thermal resistance will be lower if the ADC601 is soldered into the PC board, a ground plane is used directly underneath the package, multiple PC board layers are used, or forced air cooling is employed. Use heat sinking if necessary to keep the case at specified and operating temperatures. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ADC601 ( ) G Basic Model Number Performance Grade Code J, K: 0°C to +70°C Case Temperature Package Code G: Ceramic DIP

ORDERING INFORMATION

Stresses above these ratings may permanently damage the device. ABSOLUTE MAXIMUM RATINGS PACKAGE INFORMATION(1) PACKAGE DRAWING MODEL PACKAGE NUMBER ADC601JG 32-Pin Hermetic DIP 172–2 ADC601KG 32-Pin Hermetic DIP 172–2 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. SPECIFICATIONS (CONT) ELECTRICAL TCASE = +25°C, 900ns conversion time, ±VCC = ±15V, +VDD = +5V, and 6-minute warm-up in a normal convection environment unless otherwise noted.

12-bit parallel output data capable of sinking 3.2mA. Serial Out 12-bit serial data output synchronized with the negative edge of each appropriate clock cycle. Status Conversion status strobe is high during data conversion; low when parallel data is valid. Negative edge may be used to latch parallel data, however, appropriate latch set-up time must be provided. Refer to tBBL in the ADC601 timing diagram. Clock Out Negative edge indicates when serial data is valid. After convert command goes high, fist cycle clocks bit 1 (MSB). The clock continues to run when convert command is high and resets low with convert command. Convert Command High transition starts conversion; and should remain high during conversion. Low will reset clock and SAR logic. Clock Rate Control May be used to increase clock speed, by increasing the positive portion of the clock. High is normal operation. 20V Input 20V input range allows ±10Vp-p analog input signal. Short to ground when not used. 10V Input 10V input range allows 0 to –10Vp-p or ±5Vp-p input range. Comparator In Only used in bipolar mode when it is connected to bipolar offset pin through short lead with low resistance. Ground Sense Ground Sense pin. (See text for use). Bipolar Offset Current Bipolar offset current short to comparator In through very short lead with very low resistance for bipolar operation. Short to ground for unipolar operation. PIN CONFIGURATION PIN DEFINITIONS (1) NC = No internal connection. Any voltage may be connected to pin 31, however. (2) Pin 22 must be very cleanly decoupled to keep digital noise out of the analog circuits. Clock Reference 12-Bit D/A Converter (MSB) Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 +V (+5V) Digital Common (Digital) Serial Out Status Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 Common (Analog) NC –V (–15V) Analog Bipolar Offset Current Common (Analog) Ground Sense Comparator Input 10V Input 20V Input –V (–15V) Analog +V (+5V) Digital Common (Digital) +V (+15V) Analog Clock Rate Control Convert Command Clock Out 545Ω 1kΩ DD CC CC DD CC 12-Bit (SAR) CMOS Bipolar (1) (2) 2kΩ