ADC574

ADC574A BURR-BROWN | Alldatasheet

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ANALOG-TO-DIGITAL CONVERTER

FEATURES

l COMPLETE 12-BIT A/D CONVERTER WITH REFERENCE, CLOCK, AND 8-, 12-, or 16- BIT MICROPROCESSOR BUS INTERFACE l IMPROVED PERFORMANCE SECOND SOURCE FOR 574A-TYPE A/D CONVERTERS Conversion Time: 25 µs max Bus Access Time: 150ns max A O Input: Bus Contention During Read Operation Eliminated l DUAL IN-LINE PLASTIC, PLCC AND HERMETIC CERAMIC l FULLY SPECIFIED FOR OPERATION ON ±12V OR ±15V SUPPLIES l NO MISSING CODES OVER TEMPERATURE: °C to +75°C: ADC574AJ and K Grades –55°C to +125°C: ADC574ASH, TH

DESCRIPTION

The ADC574A is a 12-bit successive approximation analog-to-digital converter, utilizing state-of-the-art CMOS and laser-trimmed bipolar die custom-designed for freedom from latch-up and for optimum AC per- formance. It is complete with a self-contained +10V reference, internal clock, digital interface for micropro- cessor control, and three-state outputs. The reference circuit, containing a buried zener, is laser- trimmed for minimum temperature coefficient. The clock oscillator is current-controlled for excellent sta- bility over temperature. Full-scale and offset errors may be externally trimmed to zero. Internal scaling resistors are provided for the selection of analog input signal ranges of 0V to +10V , 0V to +20V, ±5V, and ±10V. The converter may be externally programmed to pro- vide 8- or 12-bit resolution. The conversion time for 12 bits is factory set for 25µs maximum. Output data are available in a parallel format from TTL- compatible three-state output buffers. Output data are coded in straight binary for unipolar input signals and bipolar offset binary for bipolar input signals. The ADC574A, available in both industrial and military temperature ranges, requires supply voltages of +5V and ±12V or ±15V. It is packaged in a 28-pin plastic DIP, and a hermetic side-brazed ceramic DIP. International Airport Industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 Successive Approximation Register Control Logic Comparator 12-Bit D/A Converter 10V Control Inputs Bipolar Offset 20V Range 10V Range Reference Input Reference Output Three-State Buffers Status Parallel Data Output Clock Reference © 1984 Burr-Brown Corporation PDS-550G Printed in U.S.A., August, 1993

At TA = +25°C, VCC = +12V or +15V, VEE = –12V or –15V, and VLOGIC = +5V unless otherwise specified. ADC574AJP, JH, SH ADC574AKP, KH, TH PARAMETER MIN TYP MAX MIN TYP MAX UNITS RESOLUTION 12 * Bits INPUTS ANALOG Voltage Ranges: Unipolar 0 to +10, 0 to +20 * V Bipolar ±5, ±10 * V Impedance: 0 to +10V, ±5V 4.7 5 5.3 * * * k Ω ±10V, 0V to +20V 9.4 10 10.6 * * * k Ω DIGITAL (CE, CS, R/C, A O , 12/8) Over Temperature Range Voltages: Logic 1 +2 +5.5 * * V Logic 0 –0.5 +0.8 * * V Current –5 0.1 +5 * * * µA Capacitance 5 * pF TRANSFER CHARACTERISTICS ACCURACY At +25°C Linearity Error ±1 ±1/2 LSB Unipolar Offset Error (Adjustable to Zero) ±2 * LSB Bipolar Offset Error (Adjustable to Zero) ±10 ±4 LSB Full-Scale Calibration Error (1) (Adjustable to Zero) ±0.25 * % of FS (2) No Missing Codes Resolution (Diff. Linearity) 11 12 Bits Inherent Quantization Error ±1/2 * LSB TMIN to TMAX Linearity Error: J, K Grades ±1 ±1/2 LSB S, T Grades ±1 ±3/4 LSB Full-Scale Calibration Error Without Initial Adjustment(1): J, K Grades ±0.47 ±0.37 % of FS S, T Grades ±0.75 ±0.5 % of FS Adjusted to Zero at +25°C: J, K Grades ±0.22 ±0.12 % of FS S, T Grades ±0.5 ±0.25 % of FS No Missing Codes Resolution (Diff. Linearity) 11 12 Bits TEMPERATURE COEFFICIENTS (T MIN to TMAX )(3) Unipolar Offset: J, K Grades ±10 ±5 ppm/ °C S, T Grades ±5 ±2.5 ppm/ °C Max Change: All Grades ±2 ±1 LSB Bipolar Offset: All Grades ±10 ±5 ppm/ °C Max Change: J, K Grades ±2 ±1 LSB S, T Grades ±4 ±2 LSB Full-Scale Calibration: J, K Grades ±45 ±25 ppm/ °C S, T Grades ±50 ±25 ppm/ °C Max Change: J, K Grades ±9 ±5 LSB S, T Grades ±20 ±10 LSB POWER SUPPLY SENSITIVITY Change in Full-Scale Calibration +13.5V < VCC < +16.5V or +11.4V < VCC < + 12.6V ±2 ±1 LSB –16.5V < VEE < –13.5V or –12.6V < VEE < – 11.4V ±2 ±1 LSB +4.5V < VLOGIC < +5.5V ±1/2 * LSB CONVERSION TIME (4) 8-Bit Cycle 10 13 17 * * * µs 12-Bit Cycle 15 20 25 * • • µs OUTPUTS DIGITAL (DB11–DB 0, STATUS) (Over Temperature Range) Output Codes: Unipolar Unipolar Straight Binary (USB) Bipolar Bipolar Offset Binary (BOB) Logic Levels: Logic 0 (ISINK = 1.6mA) +0.4 * V Logic 1 (ISOURCE = 500µA) +2.4 * V Leakage, Data Bits Only, High -Z State –5 0.1 +5 * * * µA Capacitance 5 * pF

SPECIFICATIONS (CONT) ELECTRICAL At TA = +25°C, VCC = +12V or +15V, VEE = –12V or –15V, and VLOGIC = +5V unless otherwise specified. ADC574AJP, JH, SH ADC574AKP, KH, TH PARAMETERS MIN TYP MAX MIN TYP MAX UNITS * Same specifications as ADC574AJP, AJH, ASH. NOTES: (1) With fixed 50Ω resistor from REF OUT to REF IN. This parameter is also adjustable to zero at ±25°C (see Optional External Full Scale and Offset Adjustments section). (2) FS in this specification table means Full Scale Range. That is, for a ±10V input range, FS means 20V; for a 0 to +10V range, FS means 10V. The term Full Scale for these specifications instead of Full-Scale Range is used to be consistent with other vendors' 574 and 574A type specifications tables. (3) Using internal reference. (4) See Controlling the ADC574A section for detailed information concerning digital timing. (5) External loading must be constant during conversion. The reference output requires no buffer amplifier with either ±12V or ±15V power supplies. PIN CONFIGURATION +5VDC Supply (V ) CS A R/C CE Ref Out Analog Common Ref In V Bipolar Offset 10V Range 20V Range Status DB11 (MSB) DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 (LSB) Digital Common LOGIC CC EE 5kΩ 10kΩ 10V Reference 12-Bit D/A Converter Successive Approximation Register Control Logic Power-up Reset Clock

12 Bits

Three-State Buffers and Control O 5kΩ INTERNAL REFERENCE VOLTAGE Voltage +9.9 +10.0 +10.1 * * * V Source Current Available for External Loads(5) 2.0 * mA POWER SUPPLY REQUIREMENTS Voltage: VCC +11.4 +16.5 * * V VLOGIC +4.5 +5.5 * * V Current: ICC 3.5 5 * * mA IEE 15 20 * * mA ILOGIC 91 5 * *m A Power Dissipation (±15V Supplies) 325 450 * * mW TEMPERATURE RANGE (Ambient: TMIN , TMAX ) Specifications: J, K Grades 0 +75 * * °C S, T Grades –55 +125 * * °C Storage –65 +150 * * °C

MODEL PACKAGE RANGE (T MIN TO TMAX ) ADC574AJP Plastic DIP 0 °C to +75°C ±1LSB ADC574AKP Plastic DIP 0 °C to +75°C ±1/2LSB ADC574AJH Ceramic DIP 0 °C to +75°C ±1LSB ADC574AKH Ceramic DIP 0 °C to +75°C ±1/2LSB ADC574ASH Ceramic DIP –55 °C to +125°C ±1LSB ADC574ATH Ceramic DIP –55 °C to +125°C ±3/4LSB BURN-IN SCREENING OPTION See text for details. ABSOLUTE MAXIMUM RATINGS Control Inputs (CE, CS, AO , 12/8, R/C) Analog Inputs (Ref In, Bipolar Offset, 10VIN ) Momentary Short to VCC CAUTION: These devices are sensitive to electrostatic discharge. Appropriate I.C. handling procedures should be followed. BURN-IN SCREENING Burn-in screening is available for both plastic and ceramic package ADC574s. Burn-in duration is 160 hours at the temperature (or equivalent combination of time and tem- perature) indicated below: Plastic “–BI” models: +85°C Ceramic “–BI” models: +125°C All units are 100% electrically tested after burn-in is com- pleted. To order burn-in, add “–BI” to the base model number (e.g., ADC574AKP-BI). PACKAGE DRAWING MODEL PACKAGE NUMBER (1) ADC574AJP Plastic DIP 215 ADC574AKP Plastic DIP 215 ADC574AJH Ceramic DIP 149 ADC574AKH Ceramic DIP 149 ADC574ASH Ceramic DIP 149 ADC574ATH Ceramic DIP 149 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book.

ORDERING INFORMATION

MODEL PACKAGE RANGE (160 Hours) ADC574AJP-BI Plastic DIP 0 °C to +75°C +85 °C ADC574AKP-BI Plastic DIP 0 °C to +75°C +85 °C ADC574AJH-BI Ceramic DIP 0 °C to +75°C +125 °C ADC574AKH-BI Ceramic DIP 0 °C to +75°C +125 °C ADC574ASH-BI Ceramic DIP –55 °C to +125°C +125 °C ADC574ATH-BI Ceramic DIP –55 °C to +125°C +125 °C The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.

PACKAGE INFORMATION

transition (FFEH to FFFH ) (see Figure 1). FIGURE 1. ADC574A Transfer Characteristics Terminology. spective specification temperature ranges. deviation of the actual transition value from the ideal value. versus a change in ambient temperature. TABLE I. Input Voltages, Transition Values, and LSB Values. FFF H at +9.99268) (see Table I).

change in each power supply voltage. quantization process and cannot be eliminated. pattern then connects these two pins to the system common. returns from appearing in series with the input signal. pin 12 to pin 9, omitting the adjustment network. Figure 2. Sweep the input through the end-point transition

CE (Pin 6) Chip Enable Must be high (“1”) to either initiate a conversion or read output data. 0-1 edge may be used to initiate a conversion. CS (Pin 3) Chip Select Must be low (“0”) to either initiate a conversion or read output data. 1-0 edge may be used to initiate a conversion. R/C(Pin 5) Read/Convert Must be low (“0”) to initiate either 8- or 12-bit conversions. 1-0 edge may be used to initiate a conversion. (“1” = read) Must be high (“1”) to read output data. 0-1 edge may be used to initiate a read operation. Short Cycle in two 8-bit bytes, A O = “0” accesses 8 MSBs (high byte) and AO = “1” accesses 4 LSBs and trailing “0s” (low byte). (“1” = 12 bits) or LSBs as determined by the AO line. TABLE II. ADC574A Control Line Functions. FIGURE 3. Bipolar Configuration.FIGURE 2. Unipolar Configuration. bits DB1-DB11 are ON and DB0 is toggling ON and OFF. toggle ON and OFF with all other bits ON. table is listed in Table III.

other control inputs are latched. Figure 6. The specifications for timing are contained in verter by being in a high state only during conversion. TABLE III. Control Input Truth Table.

0 X X X X None

FIGURE 5. R/C Pulse High—Outputs Enabled Only While FIGURE 4. R/C Pulse Low—Outputs Enabled After Con- require full bus interface capability. Conversion is initiated by a high-to-low transition of R/C. remain low for a minimum of 50ns. timing when conversion is initiated by a positive R/C pulse. specifications for stand-alone operation. TABLE IV. Stand-Alone Mode Timing.

NOTE: Specifications are at +25°C and measured at 50% level of transitions. TABLE V. Timing Specifications. FIGURE 7. Read Cycle Timing.FIGURE 6. Conversion Cycle Timing.