ADC32RF55IRTD

Texas Instruments

ADC32RF5x Dual Channel 14-bit 2.6 to 3-GSPS RF Sampling Data Converter REVISED DECEMBER 2022

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Technical content

ADC32RF5x Dual Channel 14-bit 2.6 to 3-GSPS RF Sampling Data Converter

1 Features

14-Bit, dual channel 2.6/3.0-GSPS ADC
Noise spectral density: – NSD = -155.6 dBFS/Hz (no AVG) – NSD = -158.1 dBFS/Hz (2x AVG) – NSD = -160.4 dBFS/Hz (4x AVG)
Single core (non-interleaved) ADC architecture
Aperture jitter: 50 fs
Low close-in residual phase noise: – -127 dBc/Hz at 10 kHz offset
Spectral performance (fIN = 1 GHz, -4 dBFS): – 2x internal averaging – SNR: 62.3 dBFS – SFDR HD2,3: 63 dBc – SFDR worst spur: 85 dBFS
Spectral performance (fIN = 1.8 GHz, -4 dBFS): – 2x internal averaging – SNR: 63.0 dBFS – SFDR HD2,3: 68 dBc – SFDR worst spur: 86 dBFS
Input fullscale: 1.1/1.35 Vpp (2/3.5 dBm)
Code error rate (CER): 10-15
Full power input bandwidth (-3 dB): 2.75 GHz
JESD204B serial data interface – Maximum lane rate: 13 Gbps – Supports subclass 1 deterministic latency
Digital down-converters – Up to four DDC per ADC channel – Complex output: 4x to 128x decimation – 48-bit NCO phase coherent frequency hopping – Fast frequency hopping: < 1 us
Power consumption: 2.6 W/channel (2x AVG)
Power supplies: 1.8 V, 1.2 V

2 Applications

Phased array radar
Spectrum analyzer
Software defined radio (SDR)
Electronic warfare
High-speed digitizer
Cable infrastructure
Communications infrastructure

3 Description

The ADC32RF5x is a single core 14-bit, 2.6 GSPS to 3 GSPS, dual channel analog to digital converters (ADC) that supports RF sampling with input frequencies up to 3 GHz. The design maximizes signal-to-noise ratio (SNR) and delivers a noise spectral density of -155 dBFS/Hz. Using additional internal ADCs along with on-chip signal averaging, the noise density improves to -161 dBFS/Hz. Each ADC channel can be connected to a quad-band digital down-converter (DDC) using a 48-bit NCO which supports phase coherent frequency hopping. Using the GPIO pins for NCO frequency control, frequency hopping can be achieved in less than 1 µs. The ADC32RF54 and ADC32RF55 supports the JESD204B serial data interface with subclass 1 deterministic latency using data rates up to 13 Gbps. The power efficient ADC architecture consumes 2.1 W/ch at 3 Gsps and provides power scaling with lower sampling rates.

Package Information

PART NUMBER PACKAGE(1) BODY SIZE (NOM) ADC32RF5x VQFN (64) 9.00 mm x 9.00 mm (1) For all available packages, see the package option addendum at the end of the data sheet. Table 3-1. Device Comparison PART NUMBER SAMPLING RATE ADC32RF55 3.0 GSPS ADC32RF54(1) 2.6 GSPS (1) Product preview. N N DDCNCO N N DDCNCO N N DDCNCO INA1P/M SYSREFP/M CLKP/M 100 3Gsps ADC DOUT0P/M ADC 100 3Gsps ADCADC 100 3Gsps ADCADC INB1P/M 100 3Gsps ADCADC N N DDCNCO 1x/2x/4x Averaging INA2P/M INB2P/M N N DDCNCO N N DDCNCO N N DDCNCO N N DDCNCO JESD204B DOUT3P/M DOUT4P/M DOUT7P/M 1x/2x/4x Averaging SEN SCLK SDIO GPIO1 GPIO2 RESETb SPISEL SPI Registers and Device Control Block Diagram ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.

6.7 Electrical Characteristics - ADC32RF54 AC

6.8 Electrical Characteristics - ADC32RF54 AC

6.9 Electrical Characteristics - ADC32RF55 AC

6.10 Electrical Characteristics - ADC32RF55 AC

9.1 Receiving Notification of Documentation Updates.. 117

10 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision * (June 2022) to Revision A (December 2022) Page ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 www.ti.com

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5 Pin Configuration and Functions

64 DOUT2M17AVDD18

1 DOUT1P 48 DOUT5P

63 DOUT2P18INA2P

2 DOUT1M 47 DOUT5M

62 DGND19INA2M

3 DVDD 46 DVDD

61 DOUT3M20AVDD18

4 DOUT0P 45 DOUT4P

60 DOUT3P21AVDD12

5 DOUT0M 44 DOUT4M

59 DVDD22CLKGND

6 DGND 43 DGND

58 AVDD1823CLKP

7 DVDD 42 DVDD

57 SEN24CLKM

8 DGND 41 DGND

56 SDIO25CLKVDD

9 DVDD 40 DVDD

55 SCLK26VCM

10 SPISEL 39 GPIO1

54 DVDD27SYSREFP

53 DOUT7P28SYSREFM

12 AGND 37 AGND

52 DOUT7M29AVDD18

13 AVDD12 36 AVDD12

51 DGND30INB2M

14 INA1P 35 INB1P

50 DOUT6P31INB2P

15 INA1M 34 INB1M

49 DOUT6M32AVDD18

16 AVDD12 33 AVDD12

Figure 5-1. RTD Package, 64 Pin VQFNP (Top View) Table 5-1. Pin Functions PIN TYPE(1) DESCRIPTION NAME NO. ANALOG INPUTS INA1P 14 I Differential analog input for channel A. 100 Ω (default) or 50 Ω differential internal termination. INA1M 15 INA2P 18 I Differential analog input for alternate channel A input. This input is used for additional ADC averaging for channel A. 100 Ω (default) or 50 Ω differential internal termination. Should be connected to GND if unused.INA2M 19 www.ti.com ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: ADC32RF54 ADC32RF55

Table 5-1. Pin Functions (continued) PIN TYPE(1) DESCRIPTION NAME NO. INB1P 35 I Differential analog input for channel B. 100 Ω (default) or 50 Ω differential internal termination. INB1M 34 INB2P 31 I Differential analog input for alternate channel B input. This input is used for additional ADC averaging for channel B. 100 Ω (default) or 50 Ω differential internal termination. Should be connected to GND if unused.INB2M 30 VCM 26 O Common-mode voltage output for the analog inputs. CLOCK, SYNCHRONIZATION CLKP 23 I Differential sampling clock input. 100 Ω differential internal termination. CLKM 24 SYSREFP 27 I Differential external synchronization input. SYSREFM 28 CONTROL RESET 11 I Hardware reset. Active low. This pin has an internal 21 kΩ pullup resistor to AVDD18. SEN 57 I Serial interface enable. Active low. This pin has an internal 21 kΩ pull-up resistor to AVDD18. SCLK 55 I Serial interface clock input. This pin has an internal 21 kΩ pull-down resistor. SDIO 56 I/O Serial interface data input and output. This pin has an internal 21 kΩ pull-down resistor. GPIO1 39 I GPIO control pin. This pin is configured through SPI interface for power down or NCO control function. GPIO2 38 I GPIO control pin. This pin is configured through SPI interface for power down or NCO control function. SPISEL 10 I Determines SPI control: either normal SPI for register writes or fast access to NCO selection only for fast frequency hopping. DIGITAL DATA INTERFACE DOUT0P 4 O JESD204B high-speed serial data output interface pins for channel A. DOUT0M 5 DOUT1P 1 DOUT1M 2 DOUT2P 63 DOUT2M 64 DOUT3P 60 DOUT3M 61 DOUT4P 45 O JESD204B high-speed serial data output interface pins for channel B. DOUT4M 44 DOUT5P 48 DOUT5M 47 DOUT6P 50 DOUT6M 49 DOUT7P 53 DOUT7M 52 POWER SUPPLY AVDD18 17,20,29,32, 58 I Analog 1.8-V power supply AVDD12 13,16,21,33, 36 I Analog 1.2-V power supply CLKVDD 25 I Clock 1.2-V power supply. Very sensitive to power supply noise. Directly impacts close in aperture phase noise. DVDD 3,7,9,40,42, 46,54,59 I Digital 1.2-V power supply AGND 12,37 I Analog ground, shorted to thermal pad. CLKGND 22 I Clock ground. DGND 6,8,41,43,51,62 I Digital ground. (1) I = Input, O = Output, I/O = Input or Output. ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 www.ti.com

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) PARAMETER TEST CONDITIONS MIN MAX UNIT Supply voltage range, AVDD18 –0.3 2.1 V Supply voltage range, AVDD12/CLKVDD/DVDD –0.3 1.4 V Voltage applied to input pins INA1P/M, INB1P/M, INA2P/M, INB2P/M –0.6 1.2 V CLKP/M –0.3 VDDCLK + 0.3 SYSREFP/M –0.3 AVDD12 + 0.6 GPIO1/2, PDN, RESET, SCLK, SEN, SDIO, SPISEL –0.3 AVDD18 + 0.2 Peak RF input power (INx1P/M, INx2P/M) Differential 100 Ω termination. 12 dBm Junction temperature, TJ 115 °C Storage temperature, Tstg –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ± 1000 V Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002(2) ± 500 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT AVDD18 1.8 V analog supply 1.75 1.8 1.85 V AVDD12 1.2 V analog supply 1.175 1.2 1.225 CLKVDD 1.2 V clock supply 1.175 1.2 1.225 DVDD 1.2 V digital supply 1.175 1.2 1.225 TA Operating free-air temperature –40 85 °C TJ Operating junction temperature 105(1) °C (1) Prolonged use above this junction temperature may increase the device failure-in-time (FIT) rate. www.ti.com ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: ADC32RF54 ADC32RF55

6.4 Thermal Information

THERMAL METRIC(1) ADC32RF5x UNITRTD (QFN)

64 Pins

RΘJA Junction-to-ambient thermal resistance 20.1 °C/W RΘJC(top) Junction-to-case (top) thermal resistance 6.8 °C/W RΘJB Junction-to-board thermal resistance 5.2 °C/W ΨJT Junction-to-top characterization parameter 0.1 °C/W ΨJB Junction-to-board characterization parameter 5.1 °C/W RΘJC(bot) Junction-to-case (bottom) thermal resistance 0.5 °C/W (1) For more information about thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 www.ti.com

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6.5 Electrical Characteristics - Power Consumption

230 TBD

IAVDD12 Supply current, 1.2 V analog supply 770 TBD ICLKVDD Supply current, 1.2 V clock supply 120 TBD IDVDD Supply current, 1.2 V digital supply 1550 TBD PDIS Power dissipation 3.4 TBD W IAVDD18 Supply current, 1.8 V analog supply 2x averaging, LMFS = 8224 320 mA IAVDD12 Supply current, 1.2 V analog supply 1050 ICLKVDD Supply current, 1.2 V clock supply 130 IDVDD Supply current, 1.2 V digital supply 1700 PDIS Power dissipation 4.1 W IAVDD18 Supply current, 1.8 V analog supply 4x averaging, LMFS = 8224 490 mA IAVDD12 Supply current, 1.2 V analog supply 1600 ICLKVDD Supply current, 1.2 V clock supply 150 IDVDD Supply current, 1.2 V digital supply 2100 PDIS Power dissipation 5.5 W POWER DOWN MODES PDIS Power down mode power consumption 190 mW www.ti.com ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: ADC32RF54 ADC32RF55

6.6 Electrical Characteristics - DC Specifications

Maximum and minimum values are specified over the operating free-air temperature range and nominal supply voltages. Typical values are specified at TA = 25°C, ADC sampling rate = 3.0 GSPS, Bypass mode, 50% clock duty cycle, AVDD18 = 1.8 V, AVDD12, AVDDCLK, DVDD = 1.2 V and –1-dBFS differential input, unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DC ACCURACY: ADC32RF55 DNL Differential nonlinearity FIN = 10 MHz ±0.85 LSB INL Integral nonlinearity FIN = 10 MHz ±4 LSB VOS_ERR Offset error ±0.2 %FSR GAINERR Gain error ±0.2 %FSR GAINMatch Gain matching across channels ±0.2 dB DC ACCURACY: ADC32RF54 DNL Differential nonlinearity FIN = 10 MHz ±0.85 LSB INL Integral nonlinearity FIN = 10 MHz ±4 LSB VOS_ERR Offset error ±0.2 %FSR GAINERR Gain error ±0.2 %FSR GAINMatch Gain matching across channels ±0.2 dB ADC ANALOG INPUTS (INA1P/M, INB1P/M, INA2P/M, INB2P/M) FS Input full scale Differential, non-average mode 1.1 Vpp Input full scale Differential, 2x or 4x average mode 1.35 VICM Input common model voltage 250 350 450 mV ZIN Differential input impedance Differential at 100 MHz 100 Ω VOCM Output common mode voltage 350 mV BW Analog Input Bandwidth (-3 dB) 1x, 2x AVG, RSW=1 2.75 GHz 4x AVG, RSW=1 2.1 Phase imbalance, analog input ±2 deg Amplitude imablance, analog input ±0.5 dB CMRR Common mode rejection ratio FIN = 100 MHz 25 dB CLOCK INPUT (CLKP/M) Input clock frequency ADC32RF54 500 2600 MHz ADC32RF55 500 3000 MHz VID Differential input voltage 1 2.4 Vpp VICM Input common mode voltage 0.65 0.75 0.85 V ZIN Differential input impedance Differential at 2.6 GHz 100 Ω Clock duty cycle 45 50 55 % SYSREF INPUT (SYSREFP/M) VID Differential input voltage 600 800 1000 mVpp VICM Input common mode voltage Input common mode voltage 1.05 1.2 1.4 V ZIN Differential input impedance 100 Ω DIGITAL INPUTS (RESET, PDN, SCLK, SEN, SDIO, GPIO1/2, SPISEL) VIH High-level input voltage 0.8 V VIL Low-level input voltage 0.4 V CI Input capacitance 0.6 pF DIGITAL OUTPUT (SDIO) VOH High-level output voltage ILOAD = -400 uA AVDD18 – 0.1 AVDD18 V VOL Low-level output voltage ILOAD = 400 uA 0.1 V ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 www.ti.com

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6.6 Electrical Characteristics - DC Specifications (continued)

6.7 Electrical Characteristics - ADC32RF54 AC Specifications (Dither DISABLED)

Maximum and minimum values are specified over the operating free-air temperature range and nominal supply voltages. Typical values are specified at TA = 25°C, ADC sampling rate = 2.6 GSPS, Bypass mode, 50% clock duty cycle, AVDD18 = 1.8 V, AVDD12, AVDDCLK, DVDD = 1.2 V, –1-dBFS differential input and dither DISABLED, unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT NSD Noise Spectral Density fIN = 900 MHz, AIN = -20 dBFS no averaging -155.5 dBFS/HzfIN = 900 MHz, AIN = -20 dBFS 2x averaging -158.2 fIN = 900 MHz, AIN = -20 dBFS 4x averaging –161.2 NF Noise Figure fIN = 900 MHz, AIN = -20 dBFS no averaging 20.3 dBfIN = 900 MHz, AIN = -20 dBFS 2x averaging 19.3 fIN = 900 MHz, AIN = -20 dBFS 4x averaging 19.7 SNR Signal-to-noise ratio no averaging fIN = 100 MHz 61.9 dBFS fIN = 500 MHz 61.9 fIN = 900 MHz 61.7 fIN = 900 MHz, Ain = -20 dBFS 64.4 fIN = 1.8 GHz 60.6 fIN = 2.4 GHz 60.0 Signal-to-noise ratio 2x averaging fIN = 100 MHz 62.8 fIN = 500 MHz 63.2 fIN = 900 MHz 62.8 fIN = 900 MHz, Ain = -20 dBFS 67.1 fIN = 1.8 GHz 62.5 fIN = 2.4 GHz 61.8 Signal-to-noise ratio 4x averaging fIN = 100 MHz 65.5 fIN = 500 MHz 65.9 fIN = 900 MHz 65.6 fIN = 900 MHz, Ain = -20 dBFS 69.8 fIN = 1.8 GHz 65.4 fIN = 2.4 GHz 64.9 SINAD Signal to noise and distortion ratio fIN = 100 MHz 61.4 dBFS fIN = 500 MHz 60.2 fIN = 900 MHz TBD 59.4 fIN = 1.8 GHz 57.6 fIN = 2.4 GHz 55.3 ENOB Effective number of bits fIN = 100 MHz 9.9 Bits fIN = 500 MHz 9.7 fIN = 900 MHz TBD 9.6 fIN = 1.8 GHz 9.3 fIN = 2.4 GHz 8.9 ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 www.ti.com

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6.7 Electrical Characteristics - ADC32RF54 AC Specifications (Dither DISABLED) (continued)

6.8 Electrical Characteristics - ADC32RF54 AC Specifications (Dither ENABLED)

Maximum and minimum values are specified over the operating free-air temperature range and nominal supply voltages. Typical values are specified at TA = 25°C, ADC sampling rate = 2.6 GSPS, Bypass mode, 50% clock duty cycle, AVDD18 = 1.8 V, AVDD12, AVDDCLK, DVDD = 1.2 V, –4-dBFS differential input and dither ENABLED, unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT NSD(1) Noise Spectral Density fIN = 900 MHz, AIN = -20 dBFS no averaging -155.6 dBFS/HzfIN = 900 MHz, AIN = -20 dBFS 2x averaging -158.0 fIN = 900 MHz, AIN = -20 dBFS 4x averaging –160.7 NF(1) Noise Figure fIN = 900 MHz, AIN = -20 dBFS no averaging 20.2 dBfIN = 900 MHz, AIN = -20 dBFS 2x averaging 19.5 fIN = 900 MHz, AIN = -20 dBFS 4x averaging 19.9 SNR(1) Signal-to-noise ratio no averaging fIN = 100 MHz 62.4 dBFS fIN = 500 MHz 62.2 fIN = 900 MHz 62.7 fIN = 900 MHz, Ain = -20 dBFS 64.5 fIN = 1.8 GHz TBD 62.0 fIN = 2.4 GHz 61.5 Signal-to-noise ratio 2x averaging fIN = 100 MHz 64.1 fIN = 500 MHz 64.3 fIN = 900 MHz 64.2 fIN = 900 MHz, Ain = -20 dBFS 66.9 fIN = 1.8 GHz 63.9 fIN = 2.4 GHz 63.3 Signal-to-noise ratio 4x averaging fIN = 100 MHz 67.2 fIN = 500 MHz 67.7 fIN = 900 MHz 67.3 fIN = 900 MHz, Ain = -20 dBFS 69.6 fIN = 1.8 GHz 67.0 fIN = 2.4 GHz 66.8 SINAD(1) Signal to noise and distortion ratio fIN = 100 MHz 62.1 dBFS fIN = 500 MHz 61.9 fIN = 900 MHz 62.2 fIN = 1.8 GHz TBD 60.5 fIN = 2.4 GHz 59.3 ENOB(1) Effective number of bits fIN = 100 MHz 10.0 Bits fIN = 500 MHz 10.0 fIN = 900 MHz 10.0 fIN = 1.8 GHz TBD 9.8 fIN = 2.4 GHz 9.6 THD Total Harmonic Distortion (First five harmonics) fIN = 100 MHz 71 dBc fIN = 500 MHz 70 fIN = 900 MHz 68 fIN = 1.8 GHz TBD 63 fIN = 2.4 GHz 61 ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 www.ti.com

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6.9 Electrical Characteristics - ADC32RF55 AC Specifications (Dither DISABLED)

Maximum and minimum values are specified over the operating free-air temperature range and nominal supply voltages. Typical values are specified at TA = 25°C, ADC sampling rate = 3.0 GSPS, Bypass mode, 50% clock duty cycle, AVDD18 = 1.8 V, AVDD12, AVDDCLK, DVDD = 1.2 V, –1-dBFS differential input and dither DISABLED, unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT NSD Noise Spectral Density fIN = 900 MHz, AIN = -20 dBFS no averaging -155.6 dBFS/HzfIN = 900 MHz, AIN = -20 dBFS 2x averaging -158.1 fIN = 900 MHz, AIN = -20 dBFS 4x averaging -160.4 NF Noise Figure fIN = 900 MHz, AIN = -20 dBFS no averaging 20.2 dBfIN = 900 MHz, AIN = -20 dBFS 2x averaging 19.8 fIN = 900 MHz, AIN = -20 dBFS 4x averaging 17.5 SNR Signal-to-noise ratio no averaging fIN = 100 MHz 62.1 dBFS fIN = 500 MHz 61.8 fIN = 900 MHz 61.7 fIN = 900 MHz, Ain = -20 dBFS 63.8 fIN = 1.8 GHz 61.1 fIN = 2.4 GHz 60.2 Signal-to-noise ratio 2x averaging fIN = 100 MHz 63.6 fIN = 500 MHz 63.3 fIN = 900 MHz 63.5 fIN = 900 MHz, Ain = -20 dBFS 66.3 fIN = 1.8 GHz 62.7 fIN = 2.4 GHz 62.4 Signal-to-noise ratio 4x averaging fIN = 100 MHz 66.7 fIN = 500 MHz 65.0 fIN = 900 MHz 65.7 fIN = 900 MHz, Ain = -20 dBFS 68.6 fIN = 1.8 GHz 64.7 fIN = 2.4 GHz 64.5 SINAD Signal to noise and distortion ratio fIN = 100 MHz 58.2 dBFS fIN = 500 MHz 57.9 fIN = 900 MHz 55.8 fIN = 1.8 GHz 58.2 fIN = 2.4 GHz 54.8 ENOB Effective number of bits fIN = 100 MHz 10.0 Bits fIN = 500 MHz 10.0 fIN = 900 MHz 10.0 fIN = 1.8 GHz 9.9 fIN = 2.4 GHz 9.7 THD Total Harmonic Distortion (First five harmonics) fIN = 100 MHz 61 dBc fIN = 500 MHz 60 fIN = 900 MHz 57 fIN = 1.8 GHz 63 fIN = 2.4 GHz 57 ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 www.ti.com

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6.10 Electrical Characteristics - ADC32RF55 AC Specifications (Dither ENABLED)

Maximum and minimum values are specified over the operating free-air temperature range and nominal supply voltages. Typical values are specified at TA = 25°C, ADC sampling rate = 3.0 GSPS, Bypass mode, 50% clock duty cycle, AVDD18 = 1.8 V, AVDD12, AVDDCLK, DVDD = 1.2 V, –4-dBFS differential input and dither ENABLED, unless otherwise noted PARAMETER TEST CONDITIONS MIN(2) TYP MAX UNIT NSD(1) Noise Spectral Density fIN = 900 MHz, AIN = -20 dBFS no averaging -155.1 dBFS/HzfIN = 900 MHz, AIN = -20 dBFS 2x averaging -157.3 fIN = 900 MHz, AIN = -20 dBFS 4x averaging -159.8 NF(1) Noise Figure fIN = 900 MHz, AIN = -20 dBFS no averaging 20.7 dBfIN = 900 MHz, AIN = -20 dBFS 2x averaging 20.6 fIN = 900 MHz, AIN = -20 dBFS 4x averaging 18.1 SNR(1) Signal-to-noise ratio no averaging fIN = 100 MHz 61.7 dBFS fIN = 500 MHz 61.8 fIN = 900 MHz 58.9 60.9 fIN = 900 MHz, Ain = -20 dBFS 62.0 63.3 fIN = 1.8 GHz 61.4 fIN = 2.4 GHz 61.2 Signal-to-noise ratio 2x averaging fIN = 100 MHz 63.1 fIN = 500 MHz 63.4 fIN = 900 MHz 62.3 fIN = 900 MHz, Ain = -20 dBFS 65.5 fIN = 1.8 GHz 63.0 fIN = 2.4 GHz 63.1 Signal-to-noise ratio 4x averaging fIN = 100 MHz 66.7 fIN = 500 MHz 66.2 fIN = 900 MHz 64.9 66.1 fIN = 900 MHz, Ain = -20 dBFS 67.1 68.0 fIN = 1.8 GHz 65.5 fIN = 2.4 GHz 65.4 SINAD(1) Signal to noise and distortion ratio fIN = 100 MHz 60.5 dBFS fIN = 500 MHz 60.8 fIN = 900 MHz 59.5 fIN = 1.8 GHz 60.3 fIN = 2.4 GHz 58.6 ENOB(1) Effective number of bits fIN = 100 MHz 10.0 Bits fIN = 500 MHz 10.0 fIN = 900 MHz 9.8 fIN = 1.8 GHz 9.9 fIN = 2.4 GHz 9.7 THD(1) Total Harmonic Distortion (First five harmonics) fIN = 100 MHz 67 dBc fIN = 500 MHz 68 fIN = 900 MHz 65 fIN = 1.8 GHz 69 fIN = 2.4 GHz 64 ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 www.ti.com

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6.11 Timing Requirements

Maximum and minimum values are specified over the operating free-air temperature range and nominal supply voltages. Typical values are specified at TA = 25°C, ADC sampling rate = 3.0 GSPS, Bypass mode, 50% clock duty cycle, AVDD18 = 1.8V, AVDD12, AVDDCLK, DVDD = 1.2V and –1-dBFS differential input, unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ADC TIMING SPECIFICATIONS TAD Aperture Delay 0.17 ns Aperure Delay variation 0.07 ns TA Aperture Jitter 50 fs Overload recovery time 3-dB overload condition 10 clock cycles6-dB overload condition 50 tADC ADC latency from sampling instant to internal hand-off to digital 68 clock cycles Internal propagation delay 5 ns Latency adder for 2x or 4x averaging 4 clock cycles Deterministic delay from digital block (DDC (if used) and JESD interface) LMFS = 8-2-8-20 260 clock cycles LMFS = 8-2-2-4 280 4x complex decimation, LMFS = 8-4-2-2 456 4x real decimation, LMFS = 4-2-2-2 456 4x decimation, F (number of octets) = 2 394 4x decimation, F = 4 374 4x decimation, F = 8 367 8x decimation, F = 2 560 8x decimation, F = 4 520 8x decimation, F = 8 506 8x decimation, F = 16 491 16x decimation, F = 2 900 16x decimation, F = 4 820 16x decimation, F = 8 792 16x decimation, F = 16 762 16x decimation, F = 32 748 32x decimation, F = 2 1596 32x decimation, F = 4 1436 32x decimation, F = 8 1380 32x decimation, F = 16 1320 32x decimation, F = 32 1292 64x decimation, F = 2 2940 64x decimation, F = 4 2620 64x decimation, F = 8 2508 64x decimation, F = 16 2388 64x decimation, F = 32 2332 128x decimation, F = 2 5668 128x decimation, F = 4 5028 128x decimation, F = 8 4804 128x decimation, F = 16 4564 128x decimation, F = 32 4452 ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 www.ti.com

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6.12 Typical Characteristics - ADC32RF54

Typical values are at TA = 25°C, ADC sampling rate = 2.6 GSPS, LMFS = 8224, 50% clock duty cycle, AVDD18 = 1.8 V, AVDD12, CLKVDD, DVDD = 1.2 V and –1-dBFS differential input, unless otherwise noted SNR = 62.1 dBFS, SFDR = 71 dBc, Non HD23 = 76 dBFS AIN = -1 dBFS, 1x AVG, Dither = DIS Figure 6-1. Single Tone FFT at FIN = 100 MHz Input Frequency (MHz) Amplitude (dBFS) 0 200 400 600 800 1000 1200 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 Dither region (DC to 100 MHz) Usable Band (100 MHz to FS/2) SNR = 63.2 dBFS1, SFDR = 77 dBc, Non HD23 = 87 dBFS AIN = -4 dBFS, 1x AVG, Dither = EN Figure 6-2. Single Tone FFT at FIN = 100 MHz SNR = 62.1 dBFS, SFDR = 64 dBc, Non HD23 = 78 dBFS AIN = -1 dBFS, 1x AVG, Dither = DIS Figure 6-3. Single Tone FFT at FIN = 500 MHz Input Frequency (MHz) Amplitude (dBFS) 0 200 400 600 800 1000 1200 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 SNR = 62.4 dBFS1, SFDR = 73 dBc, Non HD23 = 90 dBFS AIN = -4 dBFS, 1x AVG, Dither = EN Figure 6-4. Single Tone FFT at FIN = 500 MHz SNR = 61.8 dBFS, SFDR = 64 dBc, Non HD23 = 81 dBFS AIN = -1 dBFS, 1x AVG, Dither = DIS Figure 6-5. Single Tone FFT at FIN = 900 MHz Input Frequency (MHz) Amplitude (dBFS) 0 200 400 600 800 1000 1200 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 SNR = 63.1 dBFS1, SFDR = 76 dBc, Non HD23 = 85 dBFS AIN = -4 dBFS, 1x AVG, Dither = EN Figure 6-6. Single Tone FFT at FIN = 900 MHz

1 Measured from 100 MHz to FS/2

ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 www.ti.com

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6.12 Typical Characteristics - ADC32RF54 (continued)

Typical values are at TA = 25°C, ADC sampling rate = 2.6 GSPS, LMFS = 8224, 50% clock duty cycle, AVDD18 = 1.8 V, AVDD12, CLKVDD, DVDD = 1.2 V and –1-dBFS differential input, unless otherwise noted SNR = 61.0 dBFS, SFDR = 62 dBc, Non HD23 = 80 dBFS AIN = -1 dBFS, 1x AVG, Dither = DIS Figure 6-7. Single Tone FFT at FIN = 1400 MHz Input Frequency (MHz) Amplitude (dBFS) 0 200 400 600 800 1000 1200 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 SNR = 62.5 dBFS1, SFDR = 79 dBc, Non HD23 = 88 dBFS AIN = -4 dBFS, 1x AVG, Dither = EN Figure 6-8. Single Tone FFT at FIN = 1400 MHz SNR = 60.9 dBFS, SFDR = 60 dBc, Non HD23 = 77 dBFS AIN = -1 dBFS, 1x AVG, Dither = DIS Figure 6-9. Single Tone FFT at FIN = 1900 MHz Input Frequency (MHz) Amplitude (dBFS) 0 200 400 600 800 1000 1200 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 SNR = 62.3 dBFS1, SFDR = 61 dBc, Non HD23 = 79 dBFS AIN = -4 dBFS, 1x AVG, Dither = EN Figure 6-10. Single Tone FFT at FIN = 1900 MHz SNR = 60.2 dBFS, SFDR = 58 dBc, Non HD23 = 76 dBFS AIN = -1 dBFS, 1x AVG, Dither = DIS Figure 6-11. Single Tone FFT at FIN = 2200 MHz Input Frequency (MHz) Amplitude (dBFS) 0 200 400 600 800 1000 1200 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 SNR = 62.6 dBFS1, SFDR = 61 dBc, Non HD23 = 79 dBFS AIN = -4 dBFS, 1x AVG, Dither = EN Figure 6-12. Single Tone FFT at FIN = 2200 MHz www.ti.com ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: ADC32RF54 ADC32RF55

Typical values are at TA = 25°C, ADC sampling rate = 2.6 GSPS, LMFS = 8224, 50% clock duty cycle, AVDD18 = 1.8 V, AVDD12, CLKVDD, DVDD = 1.2 V and –1-dBFS differential input, unless otherwise noted SNR = 62.8 dBFS, SFDR = 70 dBc, Non HD23 = 80 dBFS AIN = -1 dBFS, 2x AVG, Dither = DIS Figure 6-13. Single Tone FFT at FIN = 900 MHz Input Frequency (MHz) Amplitude (dBFS) 0 200 400 600 800 1000 1200 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 SNR = 65.4 dBFS1, SFDR = 73 dBc, Non HD23 = 78 dBFS AIN = -4 dBFS, 2x AVG, Dither = EN Figure 6-14. Single Tone FFT at FIN = 900 MHz SNR = 65.6 dBFS, SFDR = 67 dBc, Non HD23 = 73 dBFS AIN = -1 dBFS, 4x AVG, Dither = DIS Figure 6-15. Single Tone FFT at FIN = 900 MHz Input Frequency (MHz) Amplitude (dBFS) 0 200 400 600 800 1000 1200 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 SNR = 67.8 dBFS1, SFDR = 71 dBc, Non HD23 = 76 dBFS AIN = -4 dBFS, 4x AVG, Dither = EN Figure 6-16. Single Tone FFT at FIN = 900 MHz SNR = 64.4 dBFS, SFDR = 60 dBc, Non HD23 = 81 dBFS AIN = -20 dBFS, 1x AVG, Dither = DIS Figure 6-17. Single Tone FFT at FIN = 900 MHz Input Frequency (MHz) Amplitude (dBFS) 0 200 400 600 800 1000 1200 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 SNR = 64.6 dBFS1, SFDR = 73 dBc, Non HD23 = 92 dBFS AIN = -20 dBFS, 1x AVG, Dither = EN Figure 6-18. Single Tone FFT at FIN = 900 MHz ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 www.ti.com

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Typical values are at TA = 25°C, ADC sampling rate = 2.6 GSPS, LMFS = 8224, 50% clock duty cycle, AVDD18 = 1.8 V, AVDD12, CLKVDD, DVDD = 1.2 V and –1-dBFS differential input, unless otherwise noted SNR = 67.1 dBFS, SFDR = 56 dBc, Non HD23 = 80 dBFS AIN = -20 dBFS, 2x AVG, Dither = DIS Figure 6-19. Single Tone FFT at FIN = 900 MHz Input Frequency (MHz) Amplitude (dBFS) 0 200 400 600 800 1000 1200 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 SNR = 66.8 dBFS1, SFDR = 65 dBc, Non HD23 = 93 dBFS AIN = -20 dBFS, 2x AVG, Dither = EN Figure 6-20. Single Tone FFT at FIN = 900 MHz SNR = 70.0 dBFS, SFDR = 58 dBc, Non HD23 = 85 dBFS AIN = -20 dBFS, 4x AVG, Dither = DIS Figure 6-21. Single Tone FFT at FIN = 900 MHz Input Frequency (MHz) Amplitude (dBFS) 0 200 400 600 800 1000 1200 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 SNR = 69.5 dBFS1, SFDR = 67 dBc, Non HD23 = 88 dBFS AIN = -20 dBFS, 4x AVG, Dither = EN Figure 6-22. Single Tone FFT at FIN = 900 MHz IMD3 = 72 dBc AIN = -7 dBFS/tone, 1x AVG, Dither = DIS Figure 6-23. Two Tone FFT at FIN = 900/1000 MHz IMD3 = 74 dBc AIN = -10 dBFS/tone, 1x AVG, Dither = EN Figure 6-24. Two Tone FFT at FIN = 900/1000 MHz www.ti.com ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: ADC32RF54 ADC32RF55

Typical values are at TA = 25°C, ADC sampling rate = 2.6 GSPS, LMFS = 8224, 50% clock duty cycle, AVDD18 = 1.8 V, AVDD12, CLKVDD, DVDD = 1.2 V and –1-dBFS differential input, unless otherwise noted IMD3 = 60 dBc AIN = -26 dBFS/tone, 1x AVG, Dither = DIS Figure 6-25. Two Tone FFT at FIN = 900/1000 MHz IMD3 = 72 dBc AIN = -26 dBFS/tone, 1x AVG, Dither = EN Figure 6-26. Two Tone FFT at FIN = 900/1000 MHz AIN = -1 dBFS, Dither = DIS Figure 6-27. AC Performance vs FIN AIN = -4 dBFS, Dither = EN Figure 6-28. AC Performance vs FIN AIN = -1 dBFS (Dither = DIS) AIN = -4 dBFS (Dither = EN) Figure 6-29. ENOB Performance vs FIN FIN = 900 MHz, Dither = DIS Figure 6-30. AC Performance vs AIN ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 www.ti.com

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Typical values are at TA = 25°C, ADC sampling rate = 2.6 GSPS, LMFS = 8224, 50% clock duty cycle, AVDD18 = 1.8 V, AVDD12, CLKVDD, DVDD = 1.2 V and –1-dBFS differential input, unless otherwise noted FIN = 900 MHz, Dither = EN Figure 6-31. AC Performance vs AIN Input Amplitude/Tone (dBFS) IMD3 (dBFS) -80 -70 -60 -50 -40 -30 -20 -10 0 100 110 120 130 1x (FIN = 1700/1800 MHz) 2x (FIN = 1700/1800 MHz) 4x (FIN = 1700/1800 MHz) 1x (FIN = 700/800 MHz) 2x (FIN = 700/800 MHz) 4x (FIN = 700/800 MHz) Dither = DIS Figure 6-32. IMD3 Performance vs AIN Input Amplitude/Tone (dBFS) IMD3 (dBFS) -80 -70 -60 -50 -40 -30 -20 -10 0 100 110 120 130 1x (FIN = 1700/1800 MHz) 2x (FIN = 1700/1800 MHz) 4x (FIN = 1700/1800 MHz) 1x (FIN = 700/800 MHz) 2x (FIN = 700/800 MHz) 4x (FIN = 700/800 MHz) Dither = EN Figure 6-33. IMD3 Performance vs AIN FIN = 900 MHz, AIN = -1 dBFS, Dither = DIS Figure 6-34. AC Performance vs FS FIN = 900 MHz, AIN = -1 dBFS, Dither = DIS, Other supplies nominal Figure 6-35. AC Performance vs AVDD18 FIN = 900 MHz, AIN = -1 dBFS, Dither = DIS, Other supplies nominal Figure 6-36. AC Performance vs AVDD12 www.ti.com ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: ADC32RF54 ADC32RF55

Typical values are at TA = 25°C, ADC sampling rate = 2.6 GSPS, LMFS = 8224, 50% clock duty cycle, AVDD18 = 1.8 V, AVDD12, CLKVDD, DVDD = 1.2 V and –1-dBFS differential input, unless otherwise noted Ambient Temperature (°C) SNR (dBFS) HD23, Non HD23 (dBFS) -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 62 65 63 70 64 75 65 80 66 85 67 90 68 95 69 100 70 105 SNR (1x) SNR (2x) SNR (4x) HD23 (1x) HD23 (2x) HD23 (4x) Non HD23 (1x) Non HD23 (2x) Non HD23 (4x) FIN = 900 MHz, AIN = -1 dBFS, Dither = DIS Figure 6-37. AC Performance vs Temperature Ambient Temperature (°C) SNR (dBFS) HD23, Non HD23 (dBFS) -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 62 65 63 70 64 75 65 80 66 85 67 90 68 95 69 100 70 105 SNR (1x) SNR (2x) SNR (4x) HD23 (1x) HD23 (2x) HD23 (4x) Non HD23 (1x) Non HD23 (2x) Non HD23 (4x) FIN = 900 MHz, AIN = -4 dBFS, Dither = EN Figure 6-38. AC Performance vs Temperature FIN = 900 MHz, AIN = -1 dBFS, Dither = DIS Figure 6-39. AC Performance vs Clock Duty Cycle Figure 6-40. Isolation vs Input Frequency FIN = 900 MHz, Dither = DIS Figure 6-41. INL vs Code FIN = 900 MHz, Dither = DIS Figure 6-42. DNL vs Code ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 www.ti.com

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Typical values are at TA = 25°C, ADC sampling rate = 2.6 GSPS, LMFS = 8224, 50% clock duty cycle, AVDD18 = 1.8 V, AVDD12, CLKVDD, DVDD = 1.2 V and –1-dBFS differential input, unless otherwise noted Dither = DIS Figure 6-43. DC Offset Histogram AIN = -1 dBFS, 1x AVG, Dither = DIS Figure 6-44. CMRR AIN = -1 dBFS, Dither = DIS, DDC Bypass Figure 6-45. Current vs Sampling Rate vs Averaging Sampling Rate (MSPS) DVDD Current (A) 600 800 1000 1200 1400 1600 1800 2000 2200 2400 2600 0.25 0.5 0.75 1.25 1.5 1.75 2.25 /4 (4-4-2-1) /8 (4-4-2-1) /16 (4-4-2-1) /32 (4-4-2-1) /64 (4-4-2-1) /8 (2-4-4-1) /16 (2-4-4-1) /32 (2-4-4-1) /64 (2-4-4-1) AIN = -1 dBFS, 1x AVG, Dither = DIS Single Band Decimation Figure 6-46. Current vs Sampling Rate vs Decimation Sampling Rate (MSPS) DVDD Current (A) 600 800 1000 1200 1400 1600 1800 2000 2200 2400 2600 0.25 0.5 0.75 1.25 1.5 1.75 2.25 /8 (2-4-4-1) /16 (2-4-4-1) /32 (2-4-4-1) /64 (2-4-4-1) /128 (2-4-4-1) /16 (1-4-8-1) /32 (1-4-8-1) /64 (1-4-8-1) /128 (1-4-8-1) AIN = -1 dBFS, 1x AVG, Dither = DIS Single Band Decimation Figure 6-47. Current vs Sampling Rate vs Decimation Sampling Rate (MSPS) DVDD Current (A) 600 800 1000 1200 1400 1600 1800 2000 2200 2400 2600 0.5 0.75 1.25 1.5 1.75 2.25 2.5 /8 (8-8-2-1) /16 (8-8-2-1) /32 (8-8-2-1) /64 (8-8-2-1) /8 (4-8-4-1) /16 (4-8-4-1) /32 (4-8-4-1) /64 (4-8-4-1) /128 (4-8-4-1) AIN = -1 dBFS, 1x AVG, Dither = DIS Dual Band Decimation Figure 6-48. Current vs Sampling Rate vs Decimation www.ti.com ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: ADC32RF54 ADC32RF55

Typical values are at TA = 25°C, ADC sampling rate = 2.6 GSPS, LMFS = 8224, 50% clock duty cycle, AVDD18 = 1.8 V, AVDD12, CLKVDD, DVDD = 1.2 V and –1-dBFS differential input, unless otherwise noted Sampling Rate (MSPS) DVDD Current (A) 600 800 1000 1200 1400 1600 1800 2000 2200 2400 2600 0.25 0.5 0.75 1.25 1.5 1.75 2.25 /16 (2-8-8-1) /32 (2-8-8-1) /64 (2-8-8-1) /128 (2-8-8-1) /32 (1-8-16-1) /64 (1-8-16-1) /128 (1-8-16-1) AIN = -1 dBFS, 1x AVG, Dither = DIS Dual Band Decimation Figure 6-49. Current vs Sampling Rate vs Decimation Sampling Rate (MSPS) DVDD Current (A) 600 800 1000 1200 1400 1600 1800 2000 2200 2400 2600 0.5 0.75 1.25 1.5 1.75 2.25 2.5 /16 (8-16-4-1) /32 (8-16-4-1) /64 (8-16-4-1) /128 (8-16-4-1) /16 (4-16-8-1) /32 (4-16-8-1) /64 (4-16-8-1) /128 (4-16-8-1) AIN = -1 dBFS, 1x AVG, Dither = DIS Quad Band Decimation Figure 6-50. Current vs Sampling Rate vs Decimation Sampling Rate (MSPS) DVDD Current (A) 600 800 1000 1200 1400 1600 1800 2000 2200 2400 2600 0.5 0.75 1.25 1.5 1.75 2.25 2.5 /32 (2-16-16-1) /64 (2-16-16-1) /128 (2-16-16-1) /64 (1-16-32-1) /128 (1-16-32-1) AIN = -1 dBFS, 1x AVG, Dither = DIS Quad Band Decimation Figure 6-51. Current vs Sampling Rate vs Decimation ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 www.ti.com

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6.13 Typical Characteristics - ADC32RF55

Typical values are at TA = 25°C, ADC sampling rate = 3 GSPS, LMFS = 82820, 50% clock duty cycle, AVDD18 = 1.8 V, AVDD12, CLKVDD, DVDD = 1.2 V and –1-dBFS differential input, unless otherwise noted Input Frequency (MHz) Amplitude (dBFS) 0 250 500 750 1000 1250 1500 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 SNR = 62.1 dBFS, SFDR = 57 dBc, Non HD23 = 75 dBFS AIN = -1 dBFS, 1x AVG, Dither = DIS Figure 6-52. Single Tone FFT at FIN = 100 MHz Input Frequency (MHz) Amplitude (dBFS) 0 250 500 750 1000 1250 1500 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 SNR = 61.7 dBFS2, SFDR = 58 dBc, Non HD23 = 83 dBFS AIN = -4 dBFS, 1x AVG, Dither = EN Figure 6-53. Single Tone FFT at FIN = 100 MHz Input Frequency (MHz) Amplitude (dBFS) 0 250 500 750 1000 1250 1500 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 SNR = 61.9 dBFS, SFDR = 63 dBc, Non HD23 = 77 dBFS AIN = -1 dBFS, 1x AVG, Dither = DIS Figure 6-54. Single Tone FFT at FIN = 500 MHz Input Frequency (MHz) Amplitude (dBFS) 0 250 500 750 1000 1250 1500 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 SNR = 61.8 dBFS1, SFDR = 68 dBc, Non HD23 = 84 dBFS AIN = -4 dBFS, 1x AVG, Dither = EN Figure 6-55. Single Tone FFT at FIN = 500 MHz Input Frequency (MHz) Amplitude (dBFS) 0 250 500 750 1000 1250 1500 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 SNR = 61.8 dBFS, SFDR = 60 dBc, Non HD23 = 76 dBFS AIN = -1 dBFS, 1x AVG, Dither = DIS Figure 6-56. Single Tone FFT at FIN = 900 MHz Input Frequency (MHz) Amplitude (dBFS) 0 250 500 750 1000 1250 1500 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 SNR = 60.9 dBFS1, SFDR = 64 dBc, Non HD23 = 82 dBFS AIN = -4 dBFS, 1x AVG, Dither = EN Figure 6-57. Single Tone FFT at FIN = 900 MHz

2 Measured from 100 MHz to FS/2

6.13 Typical Characteristics - ADC32RF55 (continued)

Typical values are at TA = 25°C, ADC sampling rate = 3 GSPS, LMFS = 82820, 50% clock duty cycle, AVDD18 = 1.8 V, AVDD12, CLKVDD, DVDD = 1.2 V and –1-dBFS differential input, unless otherwise noted Input Frequency (MHz) Amplitude (dBFS) 0 250 500 750 1000 1250 1500 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 SNR = 62.1 dBFS, SFDR = 57 dBc, Non HD23 = 76 dBFS AIN = -1 dBFS, 1x AVG, Dither = DIS Figure 6-58. Single Tone FFT at FIN = 1400 MHz Input Frequency (MHz) Amplitude (dBFS) 0 250 500 750 1000 1250 1500 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 SNR = 62.2 dBFS1, SFDR = 63 dBc, Non HD23 = 83 dBFS AIN = -4 dBFS, 1x AVG, Dither = EN Figure 6-59. Single Tone FFT at FIN = 1400 MHz Input Frequency (MHz) Amplitude (dBFS) 0 250 500 750 1000 1250 1500 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 SNR = 60.9 dBFS, SFDR = 62 dBc, Non HD23 = 74 dBFS AIN = -1 dBFS, 1x AVG, Dither = DIS Figure 6-60. Single Tone FFT at FIN = 1900 MHz Input Frequency (MHz) Amplitude (dBFS) 0 250 500 750 1000 1250 1500 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 SNR = 61.2 dBFS1, SFDR = 67 dBc, Non HD23 = 80 dBFS AIN = -4 dBFS, 1x AVG, Dither = EN Figure 6-61. Single Tone FFT at FIN = 1900 MHz Input Frequency (MHz) Amplitude (dBFS) 0 250 500 750 1000 1250 1500 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 SNR = 60.4 dBFS, SFDR = 58 dBc, Non HD23 = 73 dBFS AIN = -1 dBFS, 1x AVG, Dither = DIS Figure 6-62. Single Tone FFT at FIN = 2200 MHz Input Frequency (MHz) Amplitude (dBFS) 0 250 500 750 1000 1250 1500 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 SNR = 61.1 dBFS1, SFDR = 60 dBc, Non HD23 = 82 dBFS AIN = -4 dBFS, 1x AVG, Dither = EN Figure 6-63. Single Tone FFT at FIN = 2200 MHz ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 www.ti.com

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Typical values are at TA = 25°C, ADC sampling rate = 3 GSPS, LMFS = 82820, 50% clock duty cycle, AVDD18 = 1.8 V, AVDD12, CLKVDD, DVDD = 1.2 V and –1-dBFS differential input, unless otherwise noted Input Frequency (MHz) Amplitude (dBFS) 0 250 500 750 1000 1250 1500 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 SNR = 63.5 dBFS, SFDR = 59 dBc, Non HD23 = 80 dBFS AIN = -1 dBFS, 2x AVG, Dither = DIS Figure 6-64. Single Tone FFT at FIN = 900 MHz Input Frequency (MHz) Amplitude (dBFS) 0 250 500 750 1000 1250 1500 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 SNR = 62.3 dBFS1, SFDR = 66 dBc, Non HD23 = 82 dBFS AIN = -4 dBFS, 2x AVG, Dither = EN Figure 6-65. Single Tone FFT at FIN = 900 MHz Input Frequency (MHz) Amplitude (dBFS) 0 250 500 750 1000 1250 1500 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 SNR = 65.6 dBFS, SFDR = 60 dBc, Non HD23 = 80 dBFS AIN = -1 dBFS, 4x AVG, Dither = DIS Figure 6-66. Single Tone FFT at FIN = 900 MHz Input Frequency (MHz) Amplitude (dBFS) 0 250 500 750 1000 1250 1500 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 SNR = 66.2 dBFS1, SFDR = 66 dBc, Non HD23 = 83 dBFS AIN = -4 dBFS, 4x AVG, Dither = EN Figure 6-67. Single Tone FFT at FIN = 900 MHz Input Frequency (MHz) Amplitude (dBFS) 0 250 500 750 1000 1250 1500 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 SNR = 63.9 dBFS, SFDR = 60 dBc, Non HD23 = 87 dBFS AIN = -20 dBFS, 1x AVG, Dither = DIS Figure 6-68. Single Tone FFT at FIN = 900 MHz Input Frequency (MHz) Amplitude (dBFS) 0 250 500 750 1000 1250 1500 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 SNR = 63.4 dBFS1, SFDR = 73 dBc, Non HD23 = 92 dBFS AIN = -20 dBFS, 1x AVG, Dither = EN Figure 6-69. Single Tone FFT at FIN = 900 MHz www.ti.com ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: ADC32RF54 ADC32RF55

Typical values are at TA = 25°C, ADC sampling rate = 3 GSPS, LMFS = 82820, 50% clock duty cycle, AVDD18 = 1.8 V, AVDD12, CLKVDD, DVDD = 1.2 V and –1-dBFS differential input, unless otherwise noted Input Frequency (MHz) Amplitude (dBFS) 0 250 500 750 1000 1250 1500 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 SNR = 66.4 dBFS, SFDR = 63 dBc, Non HD23 = 86 dBFS AIN = -20 dBFS, 2x AVG, Dither = DIS Figure 6-70. Single Tone FFT at FIN = 900 MHz Input Frequency (MHz) Amplitude (dBFS) 0 250 500 750 1000 1250 1500 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 SNR = 65.5 dBFS1, SFDR = 73 dBc, Non HD23 = 95 dBFS AIN = -20 dBFS, 2x AVG, Dither = EN Figure 6-71. Single Tone FFT at FIN = 900 MHz Input Frequency (MHz) Amplitude (dBFS) 0 250 500 750 1000 1250 1500 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 SNR = 68.7 dBFS, SFDR = 62 dBc, Non HD23 = 87 dBFS AIN = -20 dBFS, 4x AVG, Dither = DIS Figure 6-72. Single Tone FFT at FIN = 900 MHz Input Frequency (MHz) Amplitude (dBFS) 0 250 500 750 1000 1250 1500 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 SNR = 68.1 dBFS1, SFDR = 71 dBc, Non HD23 = 78 dBFS AIN = -20 dBFS, 4x AVG, Dither = EN Figure 6-73. Single Tone FFT at FIN = 900 MHz Input Frequency (MHz) Amplitude (dBFS) 0 250 500 750 1000 1250 1500 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 IMD3 = 68 dBc AIN = -7 dBFS/tone, 1x AVG, Dither = DIS Figure 6-74. Two Tone FFT at FIN = 900/1000 MHz Input Frequency (MHz) Amplitude (dBFS) 0 250 500 750 1000 1250 1500 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 IMD3 = 70 dBc AIN = -10 dBFS/tone, 1x AVG, Dither = EN Figure 6-75. Two Tone FFT at FIN = 900/1000 MHz ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 www.ti.com

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Typical values are at TA = 25°C, ADC sampling rate = 3 GSPS, LMFS = 82820, 50% clock duty cycle, AVDD18 = 1.8 V, AVDD12, CLKVDD, DVDD = 1.2 V and –1-dBFS differential input, unless otherwise noted Input Frequency (MHz) Amplitude (dBFS) 0 250 500 750 1000 1250 1500 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 IMD3 = 54 dBc AIN = -26 dBFS/tone, 1x AVG, Dither = DIS Figure 6-76. Two Tone FFT at FIN = 900/1000 MHz Input Frequency (MHz) Amplitude (dBFS) 0 250 500 750 1000 1250 1500 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 IMD3 = 71 dBc AIN = -26 dBFS/tone, 1x AVG, Dither = EN Figure 6-77. Two Tone FFT at FIN = 900/1000 MHz Input Frequency (MHz) SNR (dBFS) SFDR, Non HD23 (dBFS) 0 250 500 750 1000 1250 1500 1750 2000 2250 2500 59 50 60 55 61 60 62 65 63 70 64 75 65 80 66 85 67 90 68 95 69 100 SNR (1x) SNR (2x) SNR (4x) HD23 (1x) HD23 (2x) HD23 (4x) Non HD23 (1x) Non HD23 (2x) Non HD23 (4x) AIN = -1 dBFS, Dither = DIS Figure 6-78. AC Performance vs FIN Input Frequency (MHz) SNR (dBFS) SFDR, Non HD23 (dBFS) 0 400 800 1200 1600 2000 2400 60 55 61 60 62 65 63 70 64 75 65 80 66 85 67 90 68 95 69 100 70 105 SNR (1x) SNR (2x) SNR (4x) HD23 (1x) HD23 (2x) HD23 (4x) Non HD23 (1x) Non HD23 (2x) Non HD23 (4x) AIN = -4 dBFS, Dither = EN Figure 6-79. AC Performance vs FIN Input Amplitude (dBFS) Dither Spur (dBFS) -80 -70 -60 -50 -40 -30 -20 -10 0 100 105 110 115 120 FIN = 900 MHz, Figure 6-80. Dither Spur vs AIN FIN (MHz) NSD (dBFS/Hz) 0 500 1000 1500 2000 2500 3000 -162 -161 -160 -159 -158 -157 -156 -155 -154 -153 Dither DIS (1x) Dither DIS (2x) Dither DIS (4x) Dither EN (1x) Dither EN (2x) Dither EN (4x) AIN = -20 dBFS Figure 6-81. NSD Performance vs FIN www.ti.com ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 33 Product Folder Links: ADC32RF54 ADC32RF55

Typical values are at TA = 25°C, ADC sampling rate = 3 GSPS, LMFS = 82820, 50% clock duty cycle, AVDD18 = 1.8 V, AVDD12, CLKVDD, DVDD = 1.2 V and –1-dBFS differential input, unless otherwise noted Input Amplitude (dBFS) SNR (dBFS) HD23, Non HD23 (dBc) 61 45 62 60 63 75 64 90 65 105 66 120 67 135 68 150 69 165 70 180 71 195 SNR (1x) SNR (2x) SNR (4x) HD23 (1x) HD23 (2x) HD23 (4x) Non HD23 (1x) Non HD23 (2x) Non HD23 (4x) FIN = 900 MHz, Dither = DIS Figure 6-82. AC Performance vs AIN Input Amplitude (dBFS) SNR (dBFS) HD23, Non HD23 (dBc) 61 75 62 80 63 85 64 90 65 95 66 100 67 105 68 110 69 115 70 120 71 125 72 130 73 135 74 140 75 145 SNR (1x) SNR (2x) SNR (4x) HD23 (1x) HD23 (2x) HD23 (4x) Non HD23 (1x) Non HD23 (2x) Non HD23 (4x) FIN = 900 MHz, Dither = EN Figure 6-83. AC Performance vs AIN Input Amplitude/Tone (dBFS) IMD3 (dBFS) -80 -70 -60 -50 -40 -30 -20 -10 0 100 110 120 130 140 150 160 1x (FIN = 1700/1800 MHz) 2x (FIN = 1700/1800 MHz) 4x (FIN = 1700/1800 MHz) 1x (FIN = 700/800 MHz) 2x (FIN = 700/800 MHz) 4x (FIN = 700/800 MHz) Dither = DIS Figure 6-84. IMD3 Performance vs AIN Input Amplitude/Tone (dBFS) IMD3 (dBFS) 100 110 120 130 140 150 160 1x (FIN = 1700/1800 MHz) 2x (FIN = 1700/1800 MHz) 4x (FIN = 1700/1800 MHz) 1x (FIN = 700/800 MHz) 2x (FIN = 700/800 MHz) 4x (FIN = 700/800 MHz) Dither = EN Figure 6-85. IMD3 Performance vs AIN Sampling Rate (GSPS) SNR (dBFS) SFDR, Non HD23 (dBc) 60 60 65 65 70 70 75 75 80 80 85 85 90 90 95 95 SNR (1x) HD2/3 (1x) Non HD23 (1x) SNR (2x) HD2/3 (2x) Non HD23 (2x) SNR (4x) HD2/3 (4x) Non HD23 (4x) FIN = 900 MHz, AIN = -1 dBFS, Dither = DIS Figure 6-86. AC Performance vs FS AVDD18 (V) SNR (dBFS) HD23, Non HD23 (dBFS) 61 60 62 65 63 70 64 75 65 80 66 85 67 90 SNR (1x) SNR (2x) SNR (4x) HD23 (1x) HD23 (2x) HD23 (4x) Non HD23 (1x) Non HD23 (2x) Non HD23 (4x) FIN = 900 MHz, AIN = -1 dBFS, Dither = DIS, Other supplies nominal Figure 6-87. AC Performance vs AVDD18 ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 www.ti.com

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Typical values are at TA = 25°C, ADC sampling rate = 3 GSPS, LMFS = 82820, 50% clock duty cycle, AVDD18 = 1.8 V, AVDD12, CLKVDD, DVDD = 1.2 V and –1-dBFS differential input, unless otherwise noted AVDD12 (V) SNR (dBFS) HD23, Non HD23 (dBFS) 1.175 1.2 1.225 60 60 61 65 62 70 63 75 64 80 65 85 66 90 67 95 1.175 1.2 1.225 SNR (1x) SNR (2x) SNR (4x) HD23 (1x) HD23 (2x) HD23 (4x) Non HD23 (1x) Non HD23 (2x) Non HD23 (4x) FIN = 900 MHz, AIN = -1 dBFS, Dither = DIS, Other supplies nominal Figure 6-88. AC Performance vs AVDD12 Ambient Temperature (degC) SNR (dBFS) HD23, Non HD23 (dBFS) -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 60 65 61 70 62 75 63 80 64 85 65 90 66 95 67 100 68 105 69 110 SNR (1x) SNR (2x) SNR (4x) HD23 (1x) HD23 (2x) HD23 (4x) Non HD23 (1x) Non HD23 (2x) Non HD23 (4x) FIN = 900 MHz, AIN = -1 dBFS, Dither = DIS Figure 6-89. AC Performance vs Temperature Ambient Temperature (degC) SNR (dBFS) HD23, Non HD23 (dBFS) -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 60 55 61 60 62 65 63 70 64 75 65 80 66 85 67 90 68 95 SNR (1x) SNR (2x) SNR (4x) HD23 (1x) HD23 (2x) HD23 (4x) Non HD23 (1x) Non HD23 (2x) Non HD23 (4x) FIN = 900 MHz, AIN = -4 dBFS, Dither = EN Figure 6-90. AC Performance vs Temperature Clock Duty Cycle (%) SNR (dBFS) HD23, NonHD23 (dBFS) 40 45 50 55 60 60 60 61 65 62 70 63 75 64 80 65 85 66 90 SNR, 1x AVG HD23, 1x AVG Non HD23, 1x AVG SNR, 2x AVG HD23, 2x AVG Non HD23, 2x AVG FIN = 900 MHz, AIN = -1 dBFS, Dither = DIS Figure 6-91. AC Performance vs Clock Duty Cycle Input Frequency (MHz) Isolation (dBc) 0 250 500 750 1000 1250 1500 1750 2000 2250 2500 100 110 120 130 1x AVG 2x AVG 4x AVG Figure 6-92. Isolation vs Input Frequency Code Integral Nonlinearity (LSB) 0 1024 2048 3072 4096 1x AVG 2x AVG 4x AVG FIN = 900 MHz, Dither = DIS Figure 6-93. INL vs Code www.ti.com ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 35 Product Folder Links: ADC32RF54 ADC32RF55

Typical values are at TA = 25°C, ADC sampling rate = 3 GSPS, LMFS = 82820, 50% clock duty cycle, AVDD18 = 1.8 V, AVDD12, CLKVDD, DVDD = 1.2 V and –1-dBFS differential input, unless otherwise noted Code Differential Nonlinearity (LSB) 0 1024 2048 3072 4096 -1.5 -1.25 -0.75 -0.5 -0.25 0.25 0.5 0.75 1.25 1.5 1x AVG 2x AVG 4x AVG FIN = 900 MHz, Dither = DIS Figure 6-94. DNL vs Code Output Code Count (%) 10% 15% 20% 25% 30% 35% 40% 45% 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 1x AVG 2x AVG 4x AVG Dither = DIS Figure 6-95. DC Offset Histogram Frequency (MHz) CMRR (dB) 0.01 0.1 1 10 100 500 FIN = 900 MHz FIN = 1800 MHz AIN = -1 dBFS, 1x AVG, Dither = DIS Figure 6-96. CMRR Sampling Rate (GSPS) Current (A) 0.5 1 1.5 2 2.5 3 0.5 1.5 2.5 3.5 AVDD18 (1x) AVDD12 (1x) DVDD (1x) CLKVDD (1x) AVDD18 (2x) AVDD12 (2x) DVDD (2x) CLKVDD (2x) AVDD18 (4x) AVDD12 (4x) DVDD (4x) CLKVDD (4x) AIN = -1 dBFS, Dither = DIS, DDC Bypass Figure 6-97. Current vs Sampling Rate vs Averaging Sampling Rate (MSPS) DVDD Current (A) 0.25 0.5 0.75 1.25 1.5 1.75 /4 (4-2-2-1) /8 (4-2-2-1) /16 (4-2-2-1) AIN = -1 dBFS, 1x AVG Figure 6-98. Current vs Sampling Rate vs Real Decimation Sampling Rate (MSPS) DVDD Current (A) 0.25 0.5 0.75 1.25 1.5 1.75 /4 (2-2-2-1) /8 (2-2-2-1) /16 (2-2-2-1) /32 (2-2-2-1) /64 (2-2-2-1) /4 (1-2-4-1) /8 (1-2-4-1) /16 (1-2-4-1) /32 (1-2-4-1) /64 (1-2-4-1) AIN = -1 dBFS, 1x AVG Figure 6-99. Current vs Sampling Rate vs Real Decimation ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 www.ti.com

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Typical values are at TA = 25°C, ADC sampling rate = 3 GSPS, LMFS = 82820, 50% clock duty cycle, AVDD18 = 1.8 V, AVDD12, CLKVDD, DVDD = 1.2 V and –1-dBFS differential input, unless otherwise noted Sampling Rate (MSPS) DVDD Current (A) 0.25 0.5 0.75 1.25 1.5 1.75 2.25 /4 (8-4-2-2) /8 (8-4-2-2) /16 (8-4-2-2) /32 (8-4-2-2) /4 (4-4-2-1) /8 (4-4-2-1) /16 (4-4-2-1) /32 (4-4-2-1) /64 (4-4-2-1) AIN = -1 dBFS, 1x AVG Single Band Decimation Figure 6-100. Current vs Sampling Rate vs Complex Decimation Sampling Rate (GSPS) DVDD Current (A) 0.25 0.5 0.75 1.25 1.5 1.75 2.25 /8 (2-4-4-1) /16 (2-4-4-1) /32 (2-4-4-1) /64 (2-4-4-1) /16 (1-4-8-1) /32 (1-4-8-1) /64 (1-4-8-1) /128 (1-4-8-1) AIN = -1 dBFS, 1x AVG Single Band Decimation Figure 6-101. Current vs Sampling Rate vs Complex Decimation Sampling Rate (MSPS) DVDD Current (A) 0.25 0.5 0.75 1.25 1.5 1.75 2.25 /8 (8-8-2-1) /16 (8-8-2-1) /32 (8-8-2-1) /64 (8-8-2-1) /8 (4-8-4-1) /16 (4-8-4-1) /32 (4-8-4-1) /64 (4-8-4-1) /128 (4-8-4-1) AIN = -1 dBFS, 1x AVG Dual Band Decimation Figure 6-102. Current vs Sampling Rate vs Complex Decimation Sampling Rate (MSPS) DVDD Current (A) 0.25 0.5 0.75 1.25 1.5 1.75 2.25 /16 (2-8-8-1) /32 (2-8-8-1) /64 (2-8-8-1) /128 (2-8-8-1) /32 (1-8-16-1) /64 (1-8-16-1) /128 (1-8-16-1) AIN = -1 dBFS, 1x AVG Dual Band Decimation Figure 6-103. Current vs Sampling Rate vs Complex Decimation Sampling Rate (MSPS) DVDD Current (A) 0.25 0.5 0.75 1.25 1.5 1.75 2.25 /16 (8-16-4-1) /32 (8-16-4-1) /64 (8-16-4-1) /128 (8-16-4-1) /16 (4-16-8-1) /32 (4-16-8-1) /64 (4-16-8-1) /128 (4-16-8-1) AIN = -1 dBFS, 1x AVG Quad Band Decimation Figure 6-104. Current vs Sampling Rate vs Complex Decimation Sampling Rate (MSPS) DVDD Current (A) 0.25 0.5 0.75 1.25 1.5 1.75 2.25 /32 (2-16-16-1) /64 (2-16-16-1) /128 (2-16-16-1) /64 (1-16-32-1) /128 (1-16-32-1) AIN = -1 dBFS, 1x AVG Quad Band Decimation Figure 6-105. Current vs Sampling Rate vs Complex Decimation www.ti.com ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 37 Product Folder Links: ADC32RF54 ADC32RF55

Typical values are at TA = 25°C, ADC sampling rate = 3 GSPS, LMFS = 82820, 50% clock duty cycle, AVDD18 = 1.8 V, AVDD12, CLKVDD, DVDD = 1.2 V and –1-dBFS differential input, unless otherwise noted AVDD18 (V) Current (A) AVDD12 (1x) AVDD12 (2x) AVDD12 (4x) AVDD18 (1x) AVDD18 (2x) AVDD18 (4x) DVDD (1x) DVDD (2x) DVDD (4x) AIN = -1 dBFS, DDC Bypass Figure 6-106. IAVDD18 vs Supply AVDD12 (V) Current (A) AVDD12 (1x) AVDD12 (2x) AVDD12 (4x) AVDD18 (1x) AVDD18 (2x) AVDD18 (4x) DVDD (1x) DVDD (2x) DVDD (4x) AIN = -1 dBFS, DDC Bypass Figure 6-107. IAVDD12 vs Supply DVDD (V) Current (A) AVDD12 (1x) AVDD12 (2x) AVDD12 (4x) AVDD18 (1x) AVDD18 (2x) AVDD18 (4x) DVDD (1x) DVDD (2x) DVDD (4x) AIN = -1 dBFS, DDC Bypass Figure 6-108. IDVDD vs Supply Ambient Temperature (degC) Current (A) -60 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 0.5 1.5 2.5 3.5 AVDD18 (1x) AVDD18 (2x) AVDD18 (4x) AVDD12 (1x) AVDD12 (2x) AVDD12 (4x) DVDD (1x) DVDD (2x) DVDD (4x) CLKVDD (1x) CLKVDD (2x) CLKVDD (4x) AIN = -1 dBFS, DDC Bypass Figure 6-109. Current vs Temperature AVDD12 (A) Count (%) 10% 12% 14% AIN = -1 dBFS, DDC Bypass Figure 6-110. AVDD12 Distribution DVDD (A) Count (%) 2.5% 7.5% 10% 12.5% 15% 17.5% AIN = -1 dBFS, DDC Bypass Figure 6-111. DVDD Distribution ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 www.ti.com

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7 Detailed Description

7.1 Overview

The ADC32RF5x is a single core (non-interleaved) 14-bit, 2.6 GSPS to 3 GSPS, dual channel analog to digital converter (ADC). The design maximizes signal-to-noise ratio (SNR) and delivers a noise spectral density of -155 dBFS/Hz. Additional internal ADCs can be used for on-chip averaging (2x and 4x) to further improve the noise density to as low as -161 dBFS/Hz. The analog signal input is non-buffered to save power consumption with a nominal differential input impedance of 100 Ω. The full power input bandwidth is 2.75 GHz (-3 dB) and the device supports direct RF sampling with input frequencies in the through the L-band. The device is designed for low residual phase noise to support high performance radar applications. The sampling clock input has a dedicated power supply input which requires a very clean power supply. Each ADC channel can be connected to a quad-band digital down-converter (DDC) using a 48-bit NCO which supports phase coherent frequency hopping. Using the GPIO pins for NCO frequency control, frequency hopping can be achieved in less than 1 µs. The digital down converters support a wide range of instantaneous bandwidth (IBW) coverage - from single wide band mode with 4x complex decimation to up to four narrow bandwidth channels with as high as 128x complex decimation. The ADC32RF5x supports the JESD204B serial data interface with subclass 1 deterministic latency using data to 3 Gsps a 12-bit interface with more efficient data packing can be used at expense of quantization noise. When using decimation the output is 16-bit.

7.2 Functional Block Diagram

N N DDCNCO N N DDCNCO N N DDCNCO INA1P/M SYSREFP/M CLKP/M 100 3Gsps ADC DOUT0P/M ADC 100 3Gsps ADCADC 100 3Gsps ADCADC INB1P/M 100 3Gsps ADCADC N N DDCNCO 1x/2x/4x Averaging INA2P/M INB2P/M N N DDCNCO N N DDCNCO N N DDCNCO N N DDCNCO JESD204B DOUT3P/M DOUT4P/M DOUT7P/M 1x/2x/4x Averaging SEN SCLK SDIO GPIO1 GPIO2 RESETb SPISEL SPI Registers and Device Control www.ti.com ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 39 Product Folder Links: ADC32RF54 ADC32RF55

7.3 Feature Description

7.3.1 Analog Inputs

The ADC32RF5x provides up to four internal ADCs per channel for purpose of averaging in order to improve the noise performance. Two ADCs internally are connected to the same differential input pins as shown in the equivalent input schematic (see Figure 7-1). The analog inputs have a differential 100 Ω split termination with internal biasing. This can be changed to differential 50 Ω termination via SPI register write. When only a single ADC is used, there is a minor parasitic capacitance remaining from the unused ADC. 0.2 pF GND 1 nHxINP/ xINM 0.4 pF GND Sampling Switch 0.6 nH 1.4 pF GND 0.7 pF GND 0.4 pF GND 1.4 pF GND 0.7 pF GND ADCx ADCyVCM GND AVDD12 Figure 7-1. Equivalent Input Schematic

7.3.1.1 Input Bandwidth and Full-Scale

The input bandwidth (-3 dB) and input fullscale are dependent on what input termination and averaging mode are chosen as shown in the summary in Table 7-1. With 4x averaging enabled, the -3 dB bandwidth reduces to ~ 2.1 GHz and 100 Ω differential termination - the bandwidth can be increased by changing the input termination to 50 Ω differential. Table 7-1. Digital averaging vs Full Power Input Bandwidth (–3 dB) # of ADCs averaged ADC inputs used for averaging Input Bandwidth (-3 dB) Selected differential input termination Effective differential input termination Input Full-scale Default INx1 2.75 GHz 100 Ω 100 Ω + 2 dBm 2 INx1 2.75 GHz 100 Ω 100 Ω + 3.5 dBm 4 INx1, INx2 2.1 GHz 100 Ω 50 Ω + 6.6 dBm The full power input bandwidth plots with input RESET switch disabled (RSW0) and enabled (RSW1) are shown in Figure 7-2. Input Frequency (MHz) Normalized Gain Response (dB) 100 1000 40004000 -10 RSW1, 1x AVG RSW1, 2x AVG RSW0, 1x AVG RSW0, 2x AVG Figure 7-2. Input Bandwidth - Reset switch DIS ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 www.ti.com

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The RESET switch is enabled by default and can be disabled with the following register writes: Table 7-2. Register Write Example for Configuring the Internal Dither ADDR DATA DESCRIPTION 0x05 0x40 Select ANALOG page 0x6D 0xC0 Disable RESET Switch (to enable: 0x00) 0x6E 0x03 Disable RESET Switch (to enable: 0x00)

7.3.1.2 Input Imbalance

The AC performance is sensitive to amplitude and phase imbalance of the analog inputs, as shown in Figure 7-3 and Figure 7-4 for 1x and 2x internal averaging (FS = 2.6 GSPS, FIN = 0.9 GHz, AIN = -1 dBFS, dither = DIS) and Figure 7-5 and Figure 7-6 (FS = 3.0 GSPS, FIN = 0.9 GHz, AIN = -1 dBFS, dither = DIS). Amplitude Imbalance (dB) SNR (dBFS) HD2, Non HD23 (dBc) -1 -0.5 0 0.5 1 55 40 56 45 57 50 58 55 59 60 60 65 61 70 62 75 63 80 64 85 65 90 66 95 67 100 SNR (1x) SNR (2x) HD2 (1x) HD2 (2x) Non HD23 (1x) Non HD23 (2x) Figure 7-3. Amplitude Imbalance - 2.6 GSPS Phase Imbalance (°) SNR (dBFS) HD2, Non HD23 (dBc) -10 -5 0 5 10 55 40 56 45 57 50 58 55 59 60 60 65 61 70 62 75 63 80 64 85 65 90 66 95 67 100 SNR (1x) SNR (2x) HD2 (1x) HD2 (2x) Non HD23 (1x) Non HD23 (2x) Figure 7-4. Phase Imbalance - 2.6 GSPS Amplitude Imbalance (dB) SNR (dBFS) HD23, Non HD23 (dBc) 55 40 56 45 57 50 58 55 59 60 60 65 61 70 62 75 63 80 64 85 65 90 66 95 67 100 SNR (1x) SNR (2x) HD2 (1x) HD2 (2x) Non HD23 (1x) Non HD23 (2x) Figure 7-5. Amplitude Imbalance - 3.0 GSPS Phase Imbalance (°) SNR (dBFS) HD2, Non HD23 (dBc) -10 -5 0 5 10 55 40 56 45 57 50 58 55 59 60 60 65 61 70 62 75 63 80 64 85 65 90 SNR (1x) SNR (2x) HD2 (1x) HD2 (2x) Non HD23 (1x) Non HD23 (2x) Figure 7-6. Phase Imbalance - 3.0 GSPS www.ti.com ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 41 Product Folder Links: ADC32RF54 ADC32RF55

7.3.1.3 Overrange Indication

The ADC provides two options (configured using SPI) to indicate if input fullscale overrange occurred:

Fast Overrange on GPIO1/2 pins: indication is available after ~ 6 clock cycles and the overrange indication flag stays high (sticky) until it is cleared via SPI register writes. Note: OVRA and OVRB or OR-ed together and given on GPIO1 and 2.
Overrange embedded in JESD stream: in this configuration the overrange indicator replaces the LSB of the output data of the corresponding channel. The indicator is output ahead of the data and is updated every clock cycle. Table 7-3. JESD OVR Latency Decimation # of Bands OVR Latency (incl JESD, in sampling clock cycles) DDC Bypass - 140-144 Single (real and complex), dual 44 Quad 33 Single (real and complex), dual 80 Quad 58 Single (real and complex), dual 152 Quad 108 Single (real and complex), dual 296 Quad 208 128 Single (real and complex), dual 584 Quad 408 The overrange output flag (GPIO or JESD) is the output of individual overrange flags of all ADCs per channel being used. For example, in non-averaged mode the overrange indication per channel is for a single ADC while in 4x average mode the overrange flag of all 4 ADCs are OR-ed together. Table 7-4shows how to configure the OVR using SPI registers. Table 7-4. Programming example to configure the OVR to GPIO or JESD ADDR DATA DESCRIPTION ADDR DATA DESCRIPTION OVR on GPIO1 and GPIO2, OVR sticky OVR on JESD 0x05 0x40 Select ANALOG page 0x05 0x02 Select DIGITAL page 0xB7 0x00/01 0x00 chA, 0x01 chB 0x2E D0 Set D0 = 1 to enable OVR on JESD 0x05 0x02 Select DIGITAL page 0x05 0x00 0x237 0x05 Configures GPIO pins as outputs These extra writes are only needed using decimation 0x238 0xF0 0x05 0x18 Select DDCA/B page Clear OVR 0x20 0x06 Enable OVR on JESD 0x05 0x40 Select ANALOG page 0x74 0x04 Clear OVR flag chA 0x74 0x00 0x84 0x04 Clear OVR flag chB 0x84 0x00 Change OVR from sticky to non sticky (self clear) 0x05 0x40 Select ANALOG page 0x31 0x26 Set OVR to non-sticky ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 www.ti.com

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7.3.1.4 Analog out-of-band dither

The ADC32RF5x provides optional (enabled via SPI writes) analog out-of-band, large amplitude dither. It has a bandwidth of ~ 20 MHz located at DC and an adjustable amplitude with a maximum dither power of ~ -20 dBFS (PAR ~ 9 dB). The dither is completely rolled-off into the noise floor within ~ 100 MHz as illustrated in Figure 7-7. Since the dither is large amplitude, it is recommended for the signal input not to exceed -2.5 dBFS to avoid input saturation. The dither signal also couples to the input signal and, depending on input frequency, can degrade the close in phase noise. FS/2~ 100 MHz ~ 20 MHz Figure 7-7. Analog out-of-band dither In the frequency domain the dither signal shows up like individual tones as shown in Figure 7-8 . The dither update frequency can be adjusted with the dither divider setting. The dither update frequency is: F S / 4 / 2047 / 'Dither Divider'. In the frequency spectrum there will be 2 larger dither spurs at FIN +/- FS / 4 / 'Dither Divider'. By default, the divider is set to 50, which translates to a dither spur spacing of ~ 7 kHz. A divider setting of 32 translates to a dither spacing of ~ 11 kHz as shown in Figure 7-9. The lower the divider setting, the higher the dither tone frequency. Figure 7-9 also shows that the dither energy reduces as the offset frequency increases - less dither energy reduces the higher harmonic spur improvement. Frequency Offset (MHz) Amplitude (dBFS/Hz) 0.001 0.01 0.1 1 -180 -170 -160 -150 -140 -130 -120 -110 -100 -90 -80 Figure 7-8. Dither Close-Up Frequency Offset (MHz) Amplitude (dBFS/Hz) 0.001 0.01 0.1 1 -160 -150 -140 -130 -120 -110 -100 Dither by 32 Dither by 16 Dither by 8 Figure 7-9. Dither vs Dither Divider Setting www.ti.com ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 43 Product Folder Links: ADC32RF54 ADC32RF55

The analog dither needs to be enabled in multiple locations. Different dither amplitudes should be used depending on internal averaging used as shown in Table 7-5. Table 7-5. Recommended Dither Amplitude Settings Mode Amplitude Dither Amp1 Dither Amp2 1x AVG +/-1024 codes 0 0 1x AVG +/-768 codes 0 -4 2x/4x AVG +/-1024 codes 3 0 2x/4x AVG +/-768 codes 0 0 The internal analog dither can be enabled via the following register writes. The dither divider is set in register 0xB1 as actual -1 (e.g. a divider of 48 would be programmed as 47, default is 0x00 which is divider = 50). See Table 7-6. Table 7-6. Register Write Example for Configuring the Internal Dither ADDR DATA DESCRIPTION ADDR DATA DESCRIPTION 0x05 0x40 Select ANALOG page 0xB1 0x00 Sets dither divider. 0x00 = /50 0xA8 0x00 DITHER AMP1: 3 = 0x80, 0 = 0x00 0xB2 0x00 0xCD 0x00 DITHER AMP2: -4 = 0x40, 0 = 0x00 0xAF 0x18 0x04 0x01 0xAF 0x10 0x10 = dither ENABLED, 0x90 = dither DISABLED 0x20 0x04 0x04 0x01 0x91 0x40 0x20 0x00 0xAF 0x10 0x04 0x00 ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 www.ti.com

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7.3.2 Sampling Clock Input

The internal sampling clock path was designed for lowest residual phase noise contribution. The sampling clock circuitry requires a dedicated low noise power supply for best performance. The internal residual clock phase noise is also sensitive to clock amplitude. For best performance, the clock amplitude should be larger than 1 Vpp. The phase noise ideally improves by 3 dB per 2x averaging, however at higher input frequenices the clock path contribution reduces the improvement. Table 7-7. Internal Aperture Clock Phase Noise (FS = 3 Gsps, VIN = 1 Vpp) Frequency Offset (MHz) Amplitude (dBc/Hz) 0.001 -117 0.01 -127 0.1 -137 1 -147 10 -154 250 -160 The clock input and ADC sampling circuitry also have an amplitude noise component which modulates on to the sampled input signal. Unlike phase noise, the amplitude noise doesn't scale with input frequency, it is only affected by the sampling reset switch as shown in Figure 7-10 and Figure 7-11. This noise component can dominate the close in noise performance at lower input frequencies. Frequency (MHz) Amplitude (dBFS/Hz) 0.0001 0.001 0.01 0.1 1 10 -160 -150 -140 -130 -120 -110 -100 -90 FIN = 110 MHz, RS_SW DIS FIN = 710 MHz, RS_SW DIS FIN = 910 MHz, RS_SW DIS FIN = 110 MHz, RS_SW EN FIN = 710 MHz, RS_SW EN FIN = 910 MHz, RS_SW EN Figure 7-10. Amplitude Noise vs Input Frequency Input Frequency (MHz) Amplitude (dBFS/Hz) 100 1000 3000 -150 -145 -140 -135 -130 -125 -120 -115 Phase Noise RS_SW DIS Phase Noise RS_SW EN Amplitude Noise RS_SW DIS Amplitude Noise RS_SW EN Figure 7-11. Amplitude and Phase noise at 10 kHz offset vs Input Frequency www.ti.com ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 45 Product Folder Links: ADC32RF54 ADC32RF55

The internal aperture jitter is also dependent on the amplitude of the external clock input signal. Figure 7-12 and Figure 7-13 show the expected SNR performance with dither on/off across clock amplitude (FS = 2.6 GSPS). Figure 7-12. SNR vs Clock Amplitude (Dither OFF) Figure 7-13. SNR vs Clock Amplitude (Dither ON) The sampling clock input is internally terminated to 100 Ω differentially and provides a return loss better than 10 dB at 3 GHz (see Figure 7-14). The clock input consists of a single clock input buffer followed by a dedicated clock buffer for ADCA1/2 as well as ADCB1/2. When averaging multiple ADCs, there are some close in clock buffer noise which is correlated; and thus, does not improve with averaging. CLKP CLKM To ADCA1/2 To ADCB1/2 5 k VCM 5 k 100 VCM Buffer Figure 7-14. Internal Clock Input Routing ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 www.ti.com

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7.3.3 SYSREF

The SYSREF input signal is used to reset internal digital blocks and align them to the internal multi-frame clock in order to achieve deterministic latency subclass 1. The SYSREF input signal can be AC or DC coupled (selected via SPI register option) as shown in Figure 7-15. The ADC32RF5x has internal 100- Ω termination for DC coupling and internal biasing when using AC coupling. A register mask can be used to only give SYSREF to the NCO (see NCO section) in the decimation filter block, and leave all other blocks such as JESD interface unaffected. When giving a periodic SYSREF signal, its frequency is required to be a sub-harmonic of the internal local multi- frame clock (LMFC). The LMFC frequency is determined by the selected decimation, frames per multi-frame setting (K), samples per freame (S) and the device sampling frequency (FS). Table 7-8. LMFC and SYSREF settings for different operating modes Operating Mode LMFS Mode LMFC Clock Frequency SYSREF Frequency DDC Bypass Mode 82820 FS / (20 * K) FS / (N * 20 x K) Decimation Various FS / (D * S * K) FS / (N * D * S * K) where N is an integer value (1, 2, 3...) After enabling SYSREF input, the internal SYSREF input ignores any incoming SYSREF pulse after the first 16 pulses. SYSREFP SYSREFM 100 Buffer SYSREFP SYSREFM 5 k Buffer 5 k 0.7V 0.7V Figure 7-15. SYSREF Input Circuitry and Edge Alignment The internal synchronization using the external SYSREF signal can be enabled with the following register writes (see Table 7-9) Table 7-9. Register Write Example for Enabling SYSREF Synchronization ADDR DATA DESCRIPTION 0x05 0x02 Select DIGITAL page 0x236 0x02 Enable internal SYSREF input and clear SYSREF pulse counter 0x236 0x03 Starts internal SYSREF counter AC coupling with internal biasing of the SYSREF input can be enabled with the following SPI register writes (see Table 7-10) Table 7-10. Register Write Example for Enabling SYSREF AC Coupling ADDR DATA DESCRIPTION 0x05 0x40 Select ANALOG page 0xB4 0x01 Enable external AC coupling with internal biasing on SYSREF www.ti.com ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 47 Product Folder Links: ADC32RF54 ADC32RF55

7.3.3.1 SYSREF Capture Detection

The SYSREF input signal rising edge should be edge aligned with the rising edge of the sampling clock in order to maximize the setup and hold times. The ADC32RF5x includes an internal SYSREF monitoring circuitry to detect possible metastability resulting in a clock cycle slip; and thus, misalignment across devices. The sampling clock gets delayed by ~160 ps and then captures the SYSREF signal. The SYSREF monitoring circuitry captures the SYSREF signal ±50 ps (-50, -25, +16, +32, +48 ps) around the main SYSREF capture. In ideal conditions no SYSREF transition happens within the 100 ps SYSREF capture window and all XOR flags show "0". If a SYSREF/clock misalignment happens and the SYSREF transition falls within the SYSREF monitoring window, then one of the XOR flags (which monitor adjacent SYSREF captures within the window) shows a "1" and the SYSREF can be adjusted externally. The SYSREF monitor registers are not sticky registers, which are updated at every rising edge of SYSREF. SYSREF CLK 110 ps delay XOR XOR XOR XOR XOR SYSREF captured to ADC 25 ps delay 25 ps delay 16 ps delay 16 ps delay 16 ps delay A B C D E F Figure 7-16. SYSREF Detection Circuitry Figure 7-17 shows a misaligned SYSREF signal where the SYSREF signal arrives much later than the sampling clock rising edge. The SYSREF window feature checks if the SYSREF transition is within ±50 ps of the instant when the SYSREF signal gets captured by the sampling clock. In this example, the delayed SYSREF signal transitions between the "B" and "C" flip flop which raises the XOR2 flag. The XOR flags get reported in register 0x22F in the digital page. In this exampe, Register 0x22F reads back 0x8B, as shown in Table 7-11. SYSREF CLK CLK + 160ps +/- 50psSYSREF and sampling clock are edge aligned XOR XOR XOR XOR XOR Figure 7-17. Detection of SYSREF Transition Within Capture Window Table 7-11. SYSREF Window Register Example (0x22F) ADDR D7 D6 D5 D4 D3 D2 D1 D0 0x22F

1 SYSREF X5 SYSREF X4 SYSREF X3 SYSREF X2 SYSREF X1 SYSREF OR 1

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7.3.4 ADC Foreground Calibration

The internal ADC architecture is sensitive to temperature changes. The devices contains two additional internal ADC cores. One for channel A1/2, and one for channel B1/2 which are used when one of the ADCs is in calibration. The ADCs are calibrated as pairs where one ADC at a time is connected to the internal calibration DAC. The calibration is configured via SPI register writes and can be executed using SPI register writes or using the GPIO1 pin. When executed, the calibration takes ~ 27 ms/ADC pair (~13.5 ms/ADC). The example in Figure 7-18 shows 2x internal averaging where 4 ADC cores (#1, #2 for chA1 and #6, #7 for chB1) are used in operation and ADCs #5 and #10 for calibration. #10 CAL DAC ChA1 ChA2 ChB2 ChB1 Figure 7-18. Internal ADC setup for 2x averaging mode www.ti.com ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 49 Product Folder Links: ADC32RF54 ADC32RF55

7.3.4.1 Calibration Control

Figure 7-19 shows a timing diagram of the calibration control using GPIO1 pin. When GPIO1 transitions to LOW logic state:

an ADC pair gets swapped out within ~ 120 ns
a new calibration gets triggered immediately If GPIO1 is being held low when the calibration of an ADC pair is completed, the next ADC pair is switched and a new calibration is triggered. The order in which ADC pair gets calibrated can be configured via SPI to serial or random. When using 2x averaging for example, the calibration should be executed for 3 ADC pairs to ensure all ADCs in use have been calibrated recently. Time ADCs In use ADCs in cal 5 10ADCs O -line 1 6 5 10 27ms 5 10 1 6 5 10 1 6 2 7 27ms 5 10 1 6 2 7 GPIO1 5 10 1 6 2 7 27ms 5 10 1 6 2 7 27ms 5 10 1 6 3 8 2 7 4 9 Figure 7-19. Timing Diagram - Calibration (4x AVG Example) Figure 7-20 shows the ADC switch happens approximate 120 ns after the logic level change on GPIO1 is detected. Input GPIO 120ns Figure 7-20. Timing diagram shows the ADC switch ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 www.ti.com

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7.3.4.2 ADC Switch

During the ADC transition, the amplitude may drop less 1% for 1-2 samples as shown in Figure 7-21. The gain variation from one ADC to the next is ~ < 0.05 dB while the phase change is less 0.01 deg as shown in Figure 7-22. Figure 7-21. Output Code vs ADC Sample Time (us) Amplitude (dBFS) Phase (°) -100 -50 0 50 100 -3.06 39.28 -3.05 39.3 -3.04 39.32 -3.03 39.34 -3.02 39.36 -3.01 39.38 -3 39.4 -2.99 39.42 -2.98 39.44 -2.97 39.46 -2.96 39.48 -2.95 39.5 -2.94 39.52 Amplitude Phase Figure 7-22. Amplitude and Phase vs Time

7.3.4.3 Calibration Configuration

The ADC32RF5x provides 3 different options to configure the internal foreground calibration:

Continous calibration - see Table 7-12
Calibrate all ADCs one time using SPI trigger - see Table 7-13
Calibrate 2 ADC pairs at a time using GPIO trigger - see Table 7-14 The status of the calibration can be read back from register 0x298 (CALIBRATION page). Successful calibration reads back 0x0E. Table 7-12. Register Writes to Trigger CONTINOUS Calibration of all ADCs Using SPI ADDR DATA DESCRIPTION 0x05 0x20 Select CALIBRATION page 0x46 0x03 Table 7-13. Register Writes to Trigger SINGLE Calibration of all ADCs Using SPI ADDR DATA DESCRIPTION 0x05 0x20 Select CALIBRATION page 0x48 0x15 0x45 0x8A Toggle calibration start 0x45 0x0A wait 2 s Table 7-14. Register Writes to Trigger ADC Pair Calibration Using the GPIO Pin ADDR DATA DESCRIPTION 0x05 0x20 Select CALIBRATION page 0x46 0x02 0x45 0x4A 0x05 0x02 Select DIGITAL page 0x234 0x04 Use GPIO1 pin to freeze calibration switch www.ti.com ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 51 Product Folder Links: ADC32RF54 ADC32RF55

7.3.5 Decimation Filter

The ADC32RF5x provides up to four digital down converters per ADC channel, see Figure 7-23. The decimation filters provide a flexible option to cover a wide range of instantaneous bandwidths (IBW) as shown in Table 7-15. Single band decimation supports a wide bandwidth up to complex decimation by 4x while up to four narrow band channels with up to 128x complex decimation are supported in quad band decimation mode. N N DDCNCO N N DDCNCO N N DDCNCO N N DDCNCO ADC JESD204B 2x, 4x Averaging Figure 7-23. Digital Decimation Filter Options Table 7-15. Summary of Different Decimation Filter Band Options # of DDCs Minimum Complex Decimation Maximum Complex Decimation 1 4 128 2 8 128 4 16 128 The decimation filter can be configured to two different operating modes:

Complex Decimation: This mode provides complex output with ~ 80% passband bandwidth using a 48-bit phase coherent NCO. During the complex mixing operation the digital output is reduced by 6-dB. This reduces the fullscale from 0-dBFS to -6-dBFS. This 6-dB change applies to signals and noise and thus no dynamic range is lost.
Real Decimation: In real decimation mode, the complex mixer is bypassed (NCO is set to 0 for lowest power consumption), and the digital filter acts as a low pass filter. There is no frequency shifting and the output passband bandwidth is ~ 40%. Since the JESD204B interface is common across ADC channel A and B, the decimation ratio as well as the # of DDCs/ADC has to be the same across channels A and B. By default, the output of values of the decimation filter are rounded to 16-bit resolution. In order to avoid quantization noise limitation when using high order of decimation (that is /64 or /128), a special 20-bit output mode can be enabled (see 20-bit Output Mode). Table 7-16 provides an overview of the available complex decimation settings and resulting complex and real output bandwidths. Table 7-16. Complex Decimation Setting vs Output Bandwidth Decimation Factor N (complex) Complex Output Bandwidth per DDC FS = 3 Gsps Real Output Bandwidth per DDC FS = 3 Gsps Complex Output Rate per DDC Complex Output Bandwidth per DDC Real Output Rate per DDC Real Output Bandwidth per DDC 4 0.8 x FS / 4 750 Msps 600 MHz 0.4 x FS / 4 750 Msps 300 MHz 8 0.8 x FS / 8 375 Msps 300 MHz 0.4 x FS / 8 375 Msps 150 MHz 16 0.8 x FS / 16 187.5 Msps 150 MHz 0.4 x FS / 16 187.5 Msps 75 MHz ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 www.ti.com

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7.3.5.1 Decimation Filter Response

This section provides the different decimation filter responses with a normalized ADC sampling rate. The complex filter pass band is ~ 80% (-1 dB) with a minimum of 85 dB stop band rejection. Figure 7-24. Complex Decimation by 4 Filter Response Figure 7-25. Decimation by 4 Passband Ripple Response Normalized Frequency (Fs) Amplitude (dB) -120 -100 -80 -60 -40 -20 adc3 Passband Transition Band Alias Band Attn Spec Figure 7-26. Complex Decimation by 8 Filter Response Normalized Frequency (Fs) Amplitude (dB) -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 adc3 Passband Transition Band Alias Band Attn Spec Figure 7-27. Decimation by 8 Passband Ripple Response Normalized Frequency (Fs) Amplitude (dB) -120 -100 -80 -60 -40 -20 adc3 Passband Transition Band Alias Band Attn Spec Figure 7-28. Complex Decimation by 16 Filter Response Normalized Frequency (Fs) Amplitude (dB) -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 adc3 Passband Transition Band Alias Band Attn Spec Figure 7-29. Decimation by 16 Passband Ripple Response www.ti.com ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 53 Product Folder Links: ADC32RF54 ADC32RF55

Normalized Frequency (Fs) Amplitude (dB) -120 -100 -80 -60 -40 -20 adc3 Passband Transition Band Alias Band Attn Spec Figure 7-30. Complex Decimation by 32 Filter Response Normalized Frequency (Fs) Amplitude (dB) -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 adc3 Passband Transition Band Alias Band Attn Spec Figure 7-31. Decimation by 32 Passband Ripple Response Normalized Frequency (Fs) Amplitude (dB) -120 -100 -80 -60 -40 -20 adc3 Passband Transition Band Alias Band Attn Spec Figure 7-32. Complex Decimation by 64 Filter Response Normalized Frequency (Fs) Amplitude (dB) -120 -100 -80 -60 -40 -20 adc3 Passband Transition Band Alias Band Attn Spec Figure 7-33. Complex Decimation by 64 Filter Response Normalized Frequency (Fs) Amplitude (dB) -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 adc3 Passband Transition Band Alias Band Attn Spec Figure 7-34. Decimation by 64 Passband Ripple Response Normalized Frequency (Fs) Amplitude (dB) -120 -100 -80 -60 -40 -20 adc3 Passband Transition Band Alias Band Attn Spec Figure 7-35. Complex Decimation by 128 Filter Response ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 www.ti.com

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Normalized Frequency (Fs) Amplitude (dB) -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 adc3 Passband Transition Band Alias Band Attn Spec Figure 7-36. Complex Decimation by 128 Filter Response Normalized Frequency (Fs) Amplitude (dB) -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 adc3 Passband Transition Band Alias Band Attn Spec Figure 7-37. Decimation by 128 Passband Ripple Response

7.3.5.2 Decimation Filter Configuration

The decimation filter is configured with these register writes. Table 7-17. Register Writes to Enable the Internal Decimation Filter ADDR DATA DESCRIPTION 0x05 0x02 Select DIGITAL page 0x2C Select single/dual/quad band 0x2D Select decimation 0x05 0x04 Select JESD page 0x22 Select LMFS mode 0x24 Select DDC CLK setting 0x25 Select JESD TX CLK DIV setting 0x9F Select JESD PLL1/2 settings 0xA0 Select JESD PLL INPUT1 setting 0xA1 Select JESD PLL INPUT2 settings 0xA2 Select JESD PLL INPUT3 settings www.ti.com ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 55 Product Folder Links: ADC32RF54 ADC32RF55

7.3.5.3 20-bit Output Mode The device includes a 20-bit output resolution mode which can be used for high order decimation (that is. 64x, 128x) in order to avoid SNR degradation due to quantization noise limitation. In this mode the output data is transmitted at 2x the output rate. The 20-bit sample from the DDC gets expanded to 32-bit by adding 12x 0s, and occupies 2 consecutive 16-bit samples. This doubles the number of octets 'F' and the proper LMFS mode and JESD PLL settings have to be selected. For example, a single band complex decimation would go from LMFS = 2441 (16-bit output mode) to LMFS = 2481 (20-bit output mode) as illustrated in Table 7-18. Table 7-18. JESD Frame Assembly Comparison between 16-bit and 20-bit Output Mode LMFS = 2441 LMFS = 2481 20-bit sample I 0000 0000000 20-bit sample Q 0000 0000000 The 20-bit output mode is enabled by setting D7 in 0x2C (DIGITAL page) and selecting viable decimation and LMFS mode.

7.3.5.4 Dynamic Switching

The ADC32RF5x supports a dynamic switch mode between two decimation filter configurations without the need to resynchronize the JESD204B interface. This enables support for single, wideband DDC and 4 narrow band DDCs that can be switched in between with minimum impact on latency. Two different configurations are supported in the dynamic switching mode. Each configuration maintains the # of serdes lanes and serdes output rate during the switch. Table 7-19 shows the specific supported configurations for LMFS and decimation settings for a 2 lane and a 1 lane setup. Since the amount of output data in quad band mode is four times larger compared to single band, the decimation factor in quad band mode needs to be reduced by a factor of four compared to the single band case. Table 7-19. Dynamic switch configuration modes Single Band DDC Quad Band DDC LMFS Complex Decimation LMFS Complex Decimation 2 lanes 2-4-16-4 /16 2-16-16-1 /64 1 lane 1-4-32-4 /32 1-16-32-1 /128 There is no information in the JESD204B output data stream indicating if the output data is quad band or single band. The JESD204B receiving device controls the switching and thus needs to decode the incoming data for quad band or single band mode. The LMFS value transmitted ILA when the JESD204B link is established is always from the quad band mode in order to avoid ILA errors at the start of the link. The dynamic switch is configured with these register writes: Table 7-20. Dynamic switch configuration writes

2 Lanes: 2-4-16-4 to 2-16-16-1 1 Lane: 1-4-32-4 to 1-16-32-1

Configure ADC 2-16-16-1, Decimation by 64 Configure ADC to 1-16-32-1, Decimation by 128 0x05, 0x02 Select DIGITAL page 0x05, 0x02 Select DIGITAL page 0x373, 0x04 Configures internal clockings 0x373, 0x05 Configures internal clockings 0x388, 0x12 0x388, 0x16 0x388, 0x32 Bit D5 enables dynamic switch: 0x388, 0x36 Bit D5 enables dynamic switch: 0x16: LMFS = 1-16-32-1, /128 ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 www.ti.com

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7.3.5.4.1 2 Lane Mode JESD transmit (TX) will operate in LMFS = 2-16-16-1 in both the quad and single band modes. The JESD receiver should be configured to and switched between 2-4-16-4 and 2-16-16-1. Table 7-21. 2 Lane Dynamic Switch Frame Assembly LMFS FRAME ASSEMBLY 2-16- 16-1 A1I0 [15:8] A1I0 [7:0] A1Q0 [15:8] A1Q0 [7:0] A2I0 [15:8] A2I0 [7:0] A2Q0 [15:8] A2Q0 [7:0] A3I0 [15:8] A3I0 [7:0] A3Q0 [15:8] A3Q0 [7:0] A4I0 [15:8] A4I0 [7:0] A4Q0 [15:8] A4Q0 [7:0] B1I0 [15:8] B1I0 [7:0] B1Q0 [15:8] B1Q0 [7:0] B2I0 [15:8] B2I0 [7:0] B2Q0 [15:8] B2Q0 [7:0] B3I0 [15:8] B3I0 [7:0] B3Q0 [15:8] B3Q0 [7:0] B4I0 [15:8] B4I0 [7:0] B4Q0 [15:8] B4Q0 [7:0] 2-4- 16-4 AI0 [15:8] AI0 [7:0] AI1 [15:8] AI1 [7:0] AI2 [15:8] AI2 [7:0] AI3 [15:8] AI3 [7:0] AQ0 [15:8] AQ0 [7:0] AQ1 [15:8] AQ1 [7:0] AQ2 [15:8] AQ2 [7:0] AQ3 [15:8] AQ3 [7:0] BI0 [15:8] BI0 [7:0] BI1 [15:8] BI1 [7:0] BI2 [15:8] BI2 [7:0] BI3 [15:8] BI3 [7:0] BQ0 [15:8] BQ0 [7:0] BQ1 [15:8] BQ1 [7:0] BQ2 [15:8] BQ2 [7:0] BQ3 [15:8] BQ3 [7:0] 7.3.5.4.2 1 Lane Mode JESD transmit (TX) will operate in LMFS = 1-16-32-1 in both the quad and single band modes. The JESD receiver should be configured, and switched between 1-4-32-4 and 1-16-32-1. Table 7-22. 2 Lane Dynamic Switch Frame Assembly LMFS FRAME ASSEMBLY 1-16- 32-1 A1I0 [15:8] A1I0 [7:0] A1Q0 [15:8] A1Q0 [7:0] A2I0 [15:8] A2I0 [7:0] A2Q0 [15:8] A2Q0 [7:0] A3I0 [15:8] A3I0 [7:0] A3Q0 [15:8] A3Q0 [7:0] A4I0 [15:8] A4I0 [7:0] A4Q0 [15:8] A4Q0 [7:0] ... ... B1I0 [15:8] B1I0 [7:0] B1Q0 [15:8] B1Q0 [7:0] B2I0 [15:8] B2I0 [7:0] B2Q0 [15:8] B2Q0 [7:0] B3I0 [15:8] B3I0 [7:0] B3Q0 [15:8] B3Q0 [7:0] B4I0 [15:8] B4I0 [7:0] B4Q0 [15:8] B4Q0 [7:0] 1-4- 32-4 AI0 [15:8] AI0 [7:0] AI1 [15:8] AI1 [7:0] AI2 [15:8] AI2 [7:0] AI3 [15:8] AI3 [7:0] AQ0 [15:8] AQ0 [7:0] AQ1 [15:8] AQ1 [7:0] AQ2 [15:8] AQ2 [7:0] AQ3 [15:8] AQ3 [7:0] ... ... BI0 [15:8] BI0 [7:0] BI1 [15:8] BI1 [7:0] BI2 [15:8] BI2 [7:0] BI3 [15:8] BI3 [7:0] BQ0 [15:8] BQ0 [7:0] BQ1 [15:8] BQ1 [7:0] BQ2 [15:8] BQ2 [7:0] BQ3 [15:8] BQ3 [7:0] www.ti.com ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 57 Product Folder Links: ADC32RF54 ADC32RF55

7.3.5.5 Numerically Controlled Oscillator (NCO)

Each digital down-converter (DDC) uses a 48-bit numerically controlled oscillator (NCO) to fine tune the frequency placement prior to the digital filtering. Different NCO frequencies for each DDC are programmed using SPI register writes and the desired NCO frequency can be selected using SPI or the GPIO pins. When using the GPIO pins for NCO frequency control, frequency hopping can be achieved in less than 1 µs. The digital NCO is designed to have a SFDR of at least 100 dB. The number of available, programmable NCO frequencies depends on # of DDC bands used as illustrated in Table 7-23. ADC N I Q NCO GPIO or SPI Freq f1 Freq fX ... DDC Figure 7-38. NCO Block Diagram Table 7-23. Available # of Frequencies per NCO Depending on # of DDCs Used # of DDCs used # of Frequencies per NCO 1 8 2 4 4 4 There are two NCO operating modes (0x180 in DDC page): phase continuous and infinite phase coherent. Phase Continuous NCO : During a NCO frequency change, the NCO phase gradually adjusts to the new frequency as shown in Figure 7-39. The dashed line shows the phase of original f1 frequency. Infinite Phase Coherent NCO: With a phase coherent NCO, all frequencies are synchronized to a single event using SYSREF. This enables an infinite amount of frequency hops without the need to reset the NCO as phase coherency is maintained between frequency hops. This is illustrated in Figure 7-39 (right). When returning to the original frequency f1, the NCO phase appears as if the NCO had never changed frequencies. f1 f1 f2 f1 f1 f2 Figure 7-39. Phase Continuous (left) and Infinite Phase Coherent (right) NCO Frequency Switching ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 www.ti.com

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The oscillator generates a complex exponential sequence of: ejωn (default) or e–jωn (1) where: frequency (ω) is specified as a signed number by the 48-bit register setting The complex exponential sequence is multiplied with the real input from the ADC to mix the desired carrier to a frequency equal to f IN + f NCO. The NCO frequency can be tuned from –F S/2 to +F S/2 and is processed as a signed, 2s complement number. The NCO frequency setting is set by the 48-bit register value given and calculated as: NCO frequency (0 to + FS/2): NCO = fNCO × 248 / FS (2) NCO frequency (-FS/2 to 0): NCO = (fNCO + FS) × 248 / FS (3) where:

NCO = NCO register setting (decimal value)
fNCO = Desired NCO frequency (MHz)
FS = ADC sampling rate (MSPS) The NCO programming is illustrated with this example:
ADC sampling rate FS = 3000 MSPS
Desired NCO frequency = 920 MHz NCO frequency setting = fNCO × 248 / FS = 920 MHz x 248 / 3000 MSPS = 86,318,992,857,935 (4) Table 7-24 shows the register writes to set frequency 1 of NCO1 of DDCA to that frequency: Table 7-24. Example Register Writes to Change NCO Frequency ADDR DATA DESCRIPTION 0x05 0x08 Select DDCA page 0x105 0x4E Set frequency to 920 MHz (86,318,992,857,935) which is 0x4E81B4E81B4E starting MSB in 0x105. 0x104 0x81 0x103 0xB4 0x102 0xE8 0x101 0x1B 0x100 0x4E 0x180 0x01 Enable phase coherent NCO mode 0x181 0x00 Load and update NCO1 with the new frequency. 0x30 updates the NCO values, 0x00 clears the register for the next update. 0x181 0x30 www.ti.com ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 59 Product Folder Links: ADC32RF54 ADC32RF55

7.3.5.6 NCO Frequency Programming

There are 4 separate NCOs per channel - one for each band (such as, NCO1 = band 1) and 4 different frequencies can be programmed per NCO as shown in Figure 7-40. The NCO frequencies are located in the DDCA/B pages (0x05 0x08 for channel A and 0x05 0x10 for channel B) in registers 0x100 to 0x17D. Depending on # of bands used, the frequencies for each NCO are selected in registers 0x3B and 0x41 (DIGITAL page) as shown in Table 7-25. If the NCO frequencies are the same for channel A and channel B, they can be written to both DDCA and DDCB pages simultaneously by selecting both pages (0x05 0x18). 1: 0x160..0x165 2: 0x168..0x16D 3: 0x170..0x175 4: 0x178..0x17D 1: 0x100..0x105 2: 0x108..0x10D 3: 0x110..0x115 4: 0x118..0x11D 1: 0x120..0x125 2: 0x128..0x12D 3: 0x130..0x135 4: 0x138..0x13D Channel A Channel B 1: 0x100..0x105 2: 0x108..0x10D 3: 0x110..0x115 4: 0x118..0x11D NCO1 1: 0x120..0x125 2: 0x128..0x12D 3: 0x130..0x135 4: 0x138..0x13D 1: 0x160..0x165 2: 0x168..0x16D 3: 0x170..0x175 4: 0x178..0x17D 1: 0x140..0x145 2: 0x148..0x14D 3: 0x150..0x155 4: 0x158..0x15D 1: 0x140..0x145 2: 0x148..0x14D 3: 0x150..0x155 4: 0x158..0x15D NCO1NCO3 NCO3 NCO2 NCO2 NCO4 NCO4 Figure 7-40. Multi-Band NCO Single band DDC uses the frequencies of both NCO1 and NCO2 for a combined 8 different frequencies for NCO1 using 3 bit control (NCO2 CHx [1] and NCO1 CHx [1:0]). The NCO2 selection bit (D3) decides if frequencies from NCO1 or NCO2 are being used. In dual and quad band DDC operating mode, there are 4 frequencies per NCO available and selected using 2 register bits (NCOx CHx [1:0]). The NCO frequency selection registers are shown in Table 7-25. Table 7-25. NCO Frequency Selection SPI Interface Registers # OF BANDS ADDR D7 D6 D5 D4 D3 D2 D1 D0 SINGLE 0x3B 0 0 0 0 NCO2 CHA [1] 0 NCO1 CHA [1:0] 0x41 0 0 0 0 NCO2 CHB [1] 0 NCO1 CHB [1:0] DUAL 0x3B 0 0 0 0 NCO2 CHA [1:0] NCO1 CHA [1:0] 0x41 0 0 0 0 NCO2 CHB [1:0] NCO1 CHB [1:0] QUAD 0x3B NCO4 CHA [1:0] NCO3 CHA [1:0] NCO2 CHA [1:0] NCO1 CHA [1:0] 0x41 NCO4 CHB [1:0] NCO3 CHB [1:0] NCO2 CHB [1:0] NCO1 CHB [1:0] To select a different frequency for the NCO, two registers (0x3B and 0x41) in the DIGITAL page have to be updated. Assuming a SPI clock frequency of 10 MHz (100 ns period), programming two registers (2x (16 bit address and 8 bit data) = 48 bit) means that the NCO frequency would be updated in ~ 5 us. When updating the currently being used NCO frequency to a new frequency, the following command has to be written in order to load the new frequency into the NCO - 0x181 0x00/0x30 in each of the DDCA/B pages. Table 7-26. Example Register Writes ADDR DATA DESCRIPTION 0x05 0x02 Select DIGITAL page 0x3B 0x01 Select frequency 2 for NCO1 of channel A. 0x235 0xFF Select NCO using SPI 0x05 0x08 Select DDCA page ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 www.ti.com

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Table 7-26. Example Register Writes (continued) ADDR DATA DESCRIPTION 0x181 0x00 Update NCO with current frequencies from the register map. 0x181 0x30 The NCO phase accumulators can be reset using the external SYSREF signal. A SYSREF mask can be setup such the SYSREF signal only goes to the NCO and the remaining device remains unaffected. The following register writes configure the SYSREF mask to only affect the NCO. After completion, the SYSREF mask should be set back to default. Table 7-27. Example Register Writes to configure the SYSREF MASK ADDR DATA DESCRIPTION 0x05 0x02 Select DIGITAL page 0x357 0xA2 SYSREF mask settings (0x00 is mask default) 0x358 0x02 SYSREF mask settings (0x00 is mask default)

7.3.5.7 Fast Frequency Hopping

The ADC32RF5x supports several different options to update the NCO frequencies. Fast frequency hopping can be achieved in one of the following ways:

Using the GPIO1/2 pins to select the NCO frequency
Using the GPIO1/2, SPISEL and SCLK/SDIO pins to select the NCO frequency
Using the GPIO1/2 pins to program the NCO frequency selection (Fast SPI) NCO CONTROL SCLK SDIO SPISEL GPIO1 GPIO2 NCO SEL MODE Regular SPI (default) SPI Interface 0 used for other purpose 00 GPIO1/2 SPI Interface 0 used for NCO control 00 GPIO1/2, SPISEL, SCLK/SDIO NCO CONTROL 1 used for NCO control 00 FAST SPI SPI Interface 1 SDIO SCLK 10 The internal NCO is switched quickly; however, the switching time depends primarily on the time it takes to flush out the decimation filter as shown in Table 7-28. Table 7-28. NCO Switching Time (FS = 2.6 GSPS) vs Decimation Setting Decimation Setting NCO Switching Time /4 ~ 250 ns /8 ~ 350 ns /16 ~ 600 ns /32 ~ 1 us /64 ~ 2 us /128 ~ 4 us www.ti.com ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 61 Product Folder Links: ADC32RF54 ADC32RF55

7.3.5.7.1 Fast frequency hopping Using the GPIO1/2 pins

The NCO frequency is selected as shown in Table 7-29. This mode is enabled with the following register write: 1. Set 0x234 to 0x03 (NCO SEL MODE = 0, GPIO MODE = 3) Table 7-29. NCO Frequency Selection Using GPIO1/2 Pins # OF BANDS GPIO2 GPIO1 GPIO2 GPIO1 GPIO2 GPIO1 GPIO2 GPIO1 SINGLE 0 0 0 0 0 0 NCO1 CHA [1:0] 0 0 0 0 0 0 NCO1 CHB [1:0] DUAL 0 0 0 0 NCO2 CHA [1:0] NCO1 CHA [1:0] 0 0 0 0 NCO2 CHB [1:0] NCO1 CHB [1:0] QUAD NCO4 CHA [1:0] NCO3 CHA [1:0] NCO2 CHA [1:0] NCO1 CHA [1:0] NCO4 CHB [1:0] NCO3 CHB [1:0] NCO2 CHB [1:0] NCO1 CHB [1:0]

7.3.5.7.2 Fast frequency hopping using GPIO1/2, SEN and SDIO pins

This mode is enabled by setting the SPISEL to logic high and using the following register write: 1. Set 0x234 to 0x63 (NCO SEL MODE = 3, GPIO MODE = 3) Table 7-30. NCO Frequency Selection SPI Interface Registers # OF BANDS SDIO SEN GPIO2 GPIO1 SDIO SEN GPIO2 GPIO1 SINGLE 0 0 0 0 NCO2 CHA [1] 0 NCO1 CHA [1:0] 0 0 0 0 NCO2 CHB [1] 0 NCO1 CHB [1:0] DUAL 0 0 0 0 NCO2 CHA [1:0] NCO1 CHA [1:0] 0 0 0 0 NCO2 CHB [1:0] NCO1 CHB [1:0] QUAD NCO4 CHA [1:0] NCO3 CHA [1:0] NCO2 CHA [1:0] NCO1 CHA [1:0] NCO4 CHB [1:0] NCO3 CHB [1:0] NCO2 CHB [1:0] NCO1 CHB [1:0]

7.3.5.7.3 Fast Frequency Hopping Using the Fast SPI

In this mode, the GPIO1/2 pins are used as a "fast SPI" input which only updates the NCO selection registers. No register address information needs to be sent. GPIO1 pin is SDIO and GPIO2 pin is SCLK. This mode is enabled by setting the SPISEL to logic high and using the following register write: 1. Set 0x234 to 0x43 (NCO SEL MODE = 2, GPIO MODE = 3) The NCO frequencies are selected as shown in Table 7-31. Table 7-31. NCO Frequency Programming Using FAST SPI # OF BANDS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SINGLE 0 0 0 0 NCO1 CHB [2]

0 NCO1 CHB

[1:0] 0 0 0 0 NCO1 CHA [2]

0 NCO1 CHA

[1:0] DUAL 0 0 0 0 NCO2 CHB [1:0] NCO1 CHB [1:0] 0 0 0 0 NCO2 CHA [1:0] NCO1 CHA [1:0] QUAD NCO4 CHB [1:0] NCO3 CHB [1:0] NCO2 CHB [1:0] NCO1 CHB [1:0] NCO4 CHA [1:0] NCO3 CHA [1:0] NCO2 CHA [1:0] NCO1 CHA [1:0] ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 www.ti.com

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7.3.6 JESD204B Interface

The ADC32RF5x uses the JESD204B high-speed serial interface to transfer data from the ADC to the receiving logic device. ADC32RF5x serialized lanes are capable of operating up to 13 Gbps, slightly above the JESD204B max lane rate. A maximum of 8 lanes can be used to allow lower lane rates for interfacing with speed limited logic devices. Figure 7-41 shows a simplified block diagram of the JESD204B interface. ADC JESD204B TRANSPORT LAYER SCRAMBLER (Optional) JESD204B LINK LAYER 8B/10B ENCODER JESD204B TX ADC JESD204B BLOCK Figure 7-41. JESD204B Block Diagram

7.3.6.1 JESD204B Initial Lane Alignment (ILA)

The receiving device starts the initial lane alignment process by deasserting the SYNC signal. When a logic low state is detected on the SYNC input, the ADC starts transmitting comma characters (K28.5) in order to establish the code group synchronization, as shown in Figure 7-42. When synchronization is completed, the receiving device reasserts the SYNC signal and the ADC starts the initial lane alignment sequence with the next local multi-frame clock (LMFC) boundary. The ADC transmits four multi-frames, each containing K frame (K is SPI programmable). Each of the multi-frames contains the frame start and frame end symbols. The second multi-frame also contains the JESD204B link configuration data. SYNC SYSREF LMFC Clock LMFC Boundary xxxTransmit Data K28.5 K28.5 ILA ILA DATA DATA Multi- Frame Code Group Synchronization Initial Lane Alignment Data Transmissio n Figure 7-42. JESD204B Internal Timing Diagram

7.3.6.1.1 SYNC Signal

The SYNC signal can be issued using one of two different methods:

One of the GPIO1/2 pins can be configured via SPI to become the SYNC input pin (address 0x234 in the digital page)
The synchronization command can be issued via SPI register write (address 0x21 in the JESD page) When using the GPIO1/2 pins for the SYNC signal input, the device also supports the option to invert the signal polarity (address 0x236 in the digital page). www.ti.com ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 63 Product Folder Links: ADC32RF54 ADC32RF55

7.3.6.2 JESD204B Frame Assembly

The JESD204B standard defines the following parameters:

L: number of lanes per link
M: number of converters per device
F: number of octets per frame clock period
S: number of samples per frame

7.3.6.3 JESD204B Frame Assembly in Bypass Mode

Table 7-32 lists the available JESD204B formats and corresponding valid sampling rate ranges for the ADC32RF5x. The sampling rates are limited by the minimum and maximum SERDES line rate as well as ADC sampling clock frequencies. The JESD204B frame assembly for the different lanes is shown in Table 7-33. When internal digital averaging is used, the output resolution is automatically adjusted from 14-bit to 16-bit to avoid quantization noise limitation. Table 7-32. JESD Mode Options: Bypass Mode DECIMATION SETTING D (complex) OUTPUT RESOLUTION (Bits) L M F S MIN FS (Gsps) MAX FS (Gsps) RATIO [fSERDES/FS] Bypass 12(1) 8 2 8 20 0.5 3.0 4 14/16(2) 8 2 2 4 0.5 2.6 5 4 2 2 2 0.5 1.3 10 (1) In full rate output, two LSBs are truncated to a 12-bit output. (2) When using digital averaging the output resolution changes to 16-bit. Table 7-33. JESD Sample Frame Assembly: Bypass Mode OUTPUT LANE LMFS = 82820 LMFS = 8224 LMFS = 4222 DOUT0 A0[11:4] A0[3:0], DOUT1 A5[11:4] A5[3:0], DOUT4 B0[11:4] B0[3:0], DOUT5 B5[11:4] B5[3:0], ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 www.ti.com

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7.3.6.4 JESD204B Frame Assembly with Complex Decimation - Single Band

Table 7-34 lists the available JESD204B interface formats and corresponding valid sampling rate ranges for the ADC32RF5x with complex decimation (single band). The sampling rates are limited by the minimum and maximum SERDES line rate as well as ADC sampling clock frequencies. The JESD204B frame assembly for the different lanes is shown in Table 7-33. Table 7-34. JESD Mode Options: Complex Decimation - Single Band DECIMATION SETTING D (complex) L M F S MIN FS (Gsps) MAX FS (Gsps) RATIO [fSERDES/(FS/D)] 8 4 2 2 0.5 3.0 10 /16 0.8 /32 1.6 4 4 2 1 0.5 2.6 3.0 /16 /32 0.8 /64 1.6 2 4 4 1 0.5 2.6 /16 3.0 /32 /64 0.8 /128 1.6 1 4 8 1 0.5 1.3 /16 2.6 /32 3.0/64 /128 0.8 Table 7-35. JESD Sample Frame Assembly: Complex Decimation - Single Band OUTPUT LANE LMFS = 8422 LMFS = 4421 LMFS = 2441 LMFS = 1481 DOUT0 AI0 [15:8] AI0 [7:0] AI0 [15:8] AI0 [7:0] AI0 [15:8] AI0 [7:0] AQ0 [15:8] AQ0 [7:0] AI0 [15:8] AI0 [7:0] AQ0 [15:8] AQ0 [7:0] BI0 [15:8] BI0 [7:0] BQ0 [15:8] BQ0 [7:0] DOUT1 AI1 [15:8] AI1 [7:0] AQ0 [15:8] AQ0 [7:0] BI0 [15:8] BI0 [7:0] BQ0 [15:8] BQ0 [7:0] DOUT2 AQ0 [15:8] AQ0 [7:0] BI0 [15:8] BI0 [7:0] DOUT3 AQ1 [15:8] AQ1 [7:0] BQ0 [15:8] BQ0 [7:0] DOUT4 BI0 [15:8] BI0 [7:0] DOUT5 BI1 [15:8] BI1 [7:0] DOUT6 BQ0 [15:8] BQ0 [7:0] DOUT7 BQ1 [15:8] BQ1 [7:0] www.ti.com ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 65 Product Folder Links: ADC32RF54 ADC32RF55

7.3.6.5 JESD204B Frame Assembly with Complex Decimation - Dual Band

Table 7-36 lists the available JESD204B interface formats and corresponding valid sampling rate ranges for the ADC32RF5x with complex decimation (dual band). The sampling rates are limited by the minimum and maximum SERDES line rate as well as ADC sampling clock frequencies. The JESD204B frame assembly for the different lanes are shown in Table 7-37 and Table 7-38. Table 7-36. JESD Mode Options: Complex Decimation - Dual Band DECIMATION SETTING D (complex) L M F S MIN FS (Gsps) MAX FS (Gsps) RATIO [fSERDES/(FS/D)] 8 8 2 1 0.5 3.0 20 /16 /32 0.8 /64 1.6 4 8 4 1 0.5 2.6 /16 3.0 /32 /64 0.8 /128 1.6 2 8 8 1 0.5 1.3 /16 2.6 /32 3.0/64 /128 0.8 /16 1 8 16 1 0.5 1.3 160 /32 2.6 /64 3.0 /128 Table 7-37. JESD Sample Frame Assembly: Complex Decimation - Dual Band OUTPU T LANE LMFS = 8821 LMFS = 4841 LMFS = 2881 DOUT0 A1I0 [15:8] A1I0 [7:0] A1I0 [15:8] A1I0 [7:0] A1Q0 [15:8] A1Q0 [7:0] A1I0 [15:8] A1I0 [7:0] A1Q0 [15:8] A1Q0 [7:0] A2I0 [15:8] A2I0 [7:0] A2Q0 [15:8] A2Q0 [7:0] DOUT1 A1Q0 [15:8] A1Q0 [7:0] A2I0 [15:8] A2I0 [7:0] A2Q0 [15:8] A2Q0 [7:0] B1I0 [15:8] B1I0 [7:0] B1Q0 [15:8] B1Q0 [7:0] B2I0 [15:8] B2I0 [7:0] B2Q0 [15:8] B2Q0 [7:0] DOUT2 A2I0 [15:8] A2I0 [7:0] B1I0 [15:8] B1I0 [7:0] B1Q0 [15:8] B1Q0 [7:0] DOUT3 A2Q0 [15:8] A2Q0 [7:0] B2I0 [15:8] B2I0 [7:0] B2Q0 [15:8] B2Q0 [7:0] DOUT4 B1I0 [15:8] B1I0 [7:0] DOUT5 B1Q0 [15:8] B1Q0 [7:0] DOUT6 B2I0 [15:8] B2I0 [7:0] DOUT7 B2Q0 [15:8] B2Q0 [7:0] ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 www.ti.com

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Table 7-38. JESD Sample Frame Assembly: Complex Decimation - Dual Band OUTP UT LANE LMFS = 1-8-16-1 DOUT A1I0 [15:8] A1I0 [7:0] A1Q0 [15:8] A1Q0 [7:0] A2I0 [15:8] A2I0 [7:0] A2Q0 [15:8] A2Q0 [7:0] B1I0 [15:8] B1I0 [7:0] B1Q0 [15:8] B1Q0 [7:0] B2I0 [15:8] B2I0 [7:0] B2Q0 [15:8] B2Q0 [7:0] DOUT DOUT DOUT DOUT DOUT DOUT DOUT www.ti.com ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 67 Product Folder Links: ADC32RF54 ADC32RF55

7.3.6.6 JESD204B Frame Assembly with Complex Decimation - Quad Band

Table 7-39 lists the available JESD204B interface formats and corresponding valid sampling rate ranges for the ADC32RF5x with complex decimation (quad band). The sampling rates are limited by the minimum and maximum SERDES line rate as well as ADC sampling clock frequencies. The JESD204B frame assembly for the different lanes are shown in Table 7-40, Table 7-41 and Table 7-42. Table 7-39. JESD Mode Options: Complex Decimation - Quad Band DECIMATION SETTING D (complex) L M F S MIN FS (Gsps) MAX FS (Gsps) RATIO [fSERDES/(FS/D)] /16 8 16 4 1 0.5 3.0 40 /32 /64 0.8 /128 1.6 /16 4 16 8 1 0.5 2.6 /32 3.0/64 /128 0.8 /16 2 16 16 1 0.5 1.3 160 /32 2.6 /64 3.0 /128 /16 1 16 32 1 0.5 0.65 320 /32 1.3 /64 2.6 /128 3.0 Table 7-40. JESD Sample Frame Assembly: Complex Decimation - Quad Band OUTPUT LANE LMFS = 8-16-4-1 LMFS = 4-16-8-1 DOUT0 A1I0 [15:8] A1I0 [7:0] A1Q0 [15:8] A1Q0 [7:0] A1I0 [15:8] A1I0 [7:0] A1Q0 [15:8] A1Q0 [7:0] A2I0 [15:8] A2I0 [7:0] A2Q0 [15:8] A2Q0 [7:0] DOUT1 A2I0 [15:8] A2I0 [7:0] A2Q0 [15:8] A2Q0 [7:0] A3I0 [15:8] A3I0 [7:0] A3Q0 [15:8] A3Q0 [7:0] A4I0 [15:8] A4I0 [7:0] A4Q0 [15:8] A4Q0 [7:0] DOUT2 A3I0 [15:8] A3I0 [7:0] A3Q0 [15:8] A3Q0 [7:0] B1I0 [15:8] B1I0 [7:0] B1Q0 [15:8] B1Q0 [7:0] B2I0 [15:8] B2I0 [7:0] B2Q0 [15:8] B2Q0 [7:0] DOUT3 A4I0 [15:8] A4I0 [7:0] A4Q0 [15:8] A4Q0 [7:0] B3I0 [15:8] B3I0 [7:0] B3Q0 [15:8] B3Q0 [7:0] B4I0 [15:8] B4I0 [7:0] B4Q0 [15:8] B4Q0 [7:0] DOUT4 B1I0 [15:8] B1I0 [7:0] B1Q0 [15:8] B1Q0 [7:0] DOUT5 B2I0 [15:8] B2I0 [7:0] B2Q0 [15:8] B2Q0 [7:0] DOUT6 B3I0 [15:8] B3I0 [7:0] B3Q0 [15:8] B3Q0 [7:0] DOUT7 B4I0 [15:8] B4I0 [7:0] B4Q0 [15:8] B4Q0 [7:0] ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 www.ti.com

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Table 7-41. JESD Sample Frame Assembly: Complex Decimation - Quad Band OUTP UT LANE LMFS = 2-16-16-1 DOUT A1I0 [15:8] A1I0 [7:0] A1Q0 [15:8] A1Q0 [7:0] A2I0 [15:8] A2I0 [7:0] A2Q0 [15:8] A2Q0 [7:0] A3I0 [15:8] A3I0 [7:0] A3Q0 [15:8] A3Q0 [7:0] A4I0 [15:8] A4I0 [7:0] A4Q0 [15:8] A4Q0 [7:0] DOUT B1I0 [15:8] B1I0 [7:0] B1Q0 [15:8] B1Q0 [7:0] B2I0 [15:8] B2I0 [7:0] B2Q0 [15:8] B2Q0 [7:0] B3I0 [15:8] B3I0 [7:0] B3Q0 [15:8] B3Q0 [7:0] B4I0 [15:8] B4I0 [7:0] B4Q0 [15:8] B4Q0 [7:0] DOUT DOUT DOUT DOUT DOUT DOUT Table 7-42. JESD Sample Frame Assembly: Complex Decimation - Quad Band OUTP UT LANE LMFS = 1-16-32-1 DOUT A1I0 [15:8] A1I0 [7:0] A1Q0 [15:8] A1Q0 [7:0] A2I0 [15:8] A2I0 [7:0] A2Q0 [15:8] A2Q0 [7:0] A3I0 [15:8] A3I0 [7:0] A3Q0 [15:8] A3Q0 [7:0] A4I0 [15:8] A4I0 [7:0] A4Q0 [15:8] A4Q0 [7:0] ... ... B1I0 [15:8] B1I0 [7:0] B1Q0 [15:8] B1Q0 [7:0] B2I0 [15:8] B2I0 [7:0] B2Q0 [15:8] B2Q0 [7:0] B3I0 [15:8] B3I0 [7:0] B3Q0 [15:8] B3Q0 [7:0] B4I0 [15:8] B4I0 [7:0] B4Q0 [15:8] B4Q0 [7:0] DOUT DOUT DOUT DOUT DOUT DOUT DOUT www.ti.com ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 69 Product Folder Links: ADC32RF54 ADC32RF55

7.3.7 SERDES Output MUX

The SERDES output block contains one digital mux per SERDES output lane with a 3-bit register. This allows routing any of the 8 digital streams to any output serdes transmitter as shown in the example in Figure 7-43. The MUX can be used to reorder lanes as well as duplicate lane outputs (for example in LMFS = 1-4-8-1 mode the same output stream could be duplicated on all 8 lanes). MUX MUXMUX Stream 0 Stream 1 Stream 6 Stream 7 SPI: Lane x mux select Figure 7-43. SERDES output mux for DOUT0 By default after power, the active SERDES lanes start on lane DOUT0 as shown for the complex decimation dual band example in Table 7-43. After power up, the output is transmitted on lanes DOUT0..3. Using the digital output muxes, the output data for channel B is shifted from lanes DOUT2,3 to DOUT4,5. All SERDES transmitters are powered up and enabled by default. After configuring the output mux unused lanes can be powered down to save power consumption. Table 7-43. JESD Sample Frame Assembly: Complex Decimation - Dual Band with LMFS = 4841 OUTPUT LANE Default Using MUX DOUT0 A1I0 [15:8] A1I0 [7:0] A1Q0 [15:8] A1Q0 [7:0] A1I0 [15:8] A1I0 [7:0] A1Q0 [15:8] A1Q0 [7:0] DOUT1 A2I0 [15:8] A2I0 [7:0] A2Q0 [15:8] A2Q0 [7:0] A2I0 [15:8] A2I0 [7:0] A2Q0 [15:8] A2Q0 [7:0] DOUT2 B1I0 [15:8] B1I0 [7:0] B1Q0 [15:8] B1Q0 [7:0] DOUT3 B2I0 [15:8] B2I0 [7:0] B2Q0 [15:8] B2Q0 [7:0] DOUT4 B1I0 [15:8] B1I0 [7:0] B1Q0 [15:8] B1Q0 [7:0] DOUT5 B2I0 [15:8] B2I0 [7:0] B2Q0 [15:8] B2Q0 [7:0] DOUT6 DOUT7 Table 7-44 shows the register writes to shift the output lanes from default as illustrated in Table 7-43. Table 7-44. Example register writes to shift the output serdes lanes using the SERDES Output MUX ADDR DATA DESCRIPTION 0x05 0x04 Select JESD page 0x81 0x54 Select internal JESD streams 4 and 5 to lanes DOUT2 and DOUT3 0x82 0x32 Select internal JESD streams 2 and 3 to lanes DOUT4 and DOUT5 ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 www.ti.com

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7.3.8 Test Pattern

The ADC32RF5x provides two different options to output test patterns instead of the actual output data of the ADC in order to simplify the serial interface and system debug of the JESD204B digital interface link. The output data path is shown in \\. Transport Layer Test Pattern Data Mapping Frame Construction Scrambler 1+x14+x15 8b/10b encoding Link Layer Test Pattern Serializer ADC Section Transport Layer Link Layer PHY LayerDigital Block ADC Decimation Filter Block Figure 7-44. Test Pattern Options The available test patterns in each block are described in Table 7-45. Both test pattern blocks replace output data from the digital block, and not from the ADC; therefore, it is available in decimation or decimation bypass mode. The test patterns are synchronized with the SYSREF signal. Table 7-45. Test Pattern Overview TEST PATTERN LOCATION TYPE 8b/10b encoded REGISTER PAGE REGISTER TRANSPORT LAYER CUSTOM PATTERN Yes JESD 0x05 0x04 0x2E, D0 TOGGLE 1010 PATTERN Yes 0x2E, D1 RAMP PATTERN Yes 0x2E, D2 LINK LAYER JESD204B TEST PATTERNS Depends 0x2D, D2-D0 PRBS PATTERN (27.. 231) No 0x2F, D6-D4 The RAMP pattern provides two different output options. Internally each ADC data bus consists of parallel data streams (1 stream per serdes lane). The RAMP pattern is generated for each stream and a different starting value can be set for each stream. By default, the starting values are 0. For example, a LMFS mode using 4 lanes/ADC would show a slow ramp which increments once every 4 clock cycles with starting values set to 0 and ramp increment = 1. Also, a RAMP pattern which increments every clock cycle can be set using different starting values (such as 0, 1, 2, 3) for the 4 streams/lanes and setting the RAMP increment to 4. The follow table shows how to enable the RAMP test pattern. Table 7-46. RAMP Test Pattern ADDR DATA DESCRIPTION 0x05 0x04 Select JESD page 0x32 0x01 Set lane DOUT1 starting value = 1 0x34 0x02 Set lane DOUT2 starting value = 2 0x36 0x03 Set lane DOUT3 starting value = 3 0x42 0x01 Set lane DOUT5 starting value = 1 0x44 0x02 Set lane DOUT6 starting value = 2 0x46 0x03 Set lane DOUT7 starting value = 3 0x2E 0x34 Enable RAMP pattern, RAMP increment = 4

7.3.8.1 Transport Layer

The transport layer maps the ADC output data into 8-bit octets and constructs the JESD204B frames using the LMFS parameters. Tail bits or 0's are added when needed. Alternatively, test patterns can be substituted instead of the ADC data with the JESD frame, as shown in Table 7-45. www.ti.com ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 71 Product Folder Links: ADC32RF54 ADC32RF55

7.3.8.2 Link Layer

The link layer contains the scrambler and the 8b/10b encoding of any data passed on from the transport layer. Additionally, the link layer controls the initial lane alignment sequence that can be manually restarted. The link layer test patterns are intended for testing the quality of the link (jitter testing and so forth). The test patterns do not pass through the 8b/10b encoder and contain the options listed in Table 7-45.

7.3.8.3 Internal Capture Memory Buffer

The ADC includes a small internal capture memory buffer which can store up to 64 samples. Once a strobe is given to the memory using SPI register write, the memory will store the next continuous 64 samples of one ADC channel (selected via SPI register write) and stop. The samples are captured from the ADC cores (prior to averaging or decimation). These samples can be read back using the SPI interface without involving the JESD204B interface at all. This mode allows debug of the analog front end during the initial bring-up phase even if the JESD204B interface is not operational yet. Table 7-47. Register writes to enable the internal sample capture buffer ADDR DATA DESCRIPTION 0x05 0x02 Select DIGITAL page 0x34 Select ADC channel (D5/D4) and give strobe (D6). The 64 samples are stored in 0x800 to 0x87F in the digital page ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 www.ti.com

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7.4 Device Functional Modes

The device offers two different operating modes: bypass mode (1x AVG) and digital averaging (2x/4x AVG). Both operating modes use the same digital back end and JESD204B output configurations.

7.4.1 Digital Averaging

The ADC32RF5x provides a total of eight internal single core 3.0 Gsps ADCs. Normal bypass mode uses only two ADC cores (one ADC per channel). However, the additional six ADCs can be used to trade off further noise density improvement against additional power consumption. Figure 7-45 shows the internal block diagrams for the digital averaging modes. In averaging mode the output resolution is increased to 16-bit to avoid quantization noise limitation. In 2x averaging mode (left), one external input is connected to the INx1 input where two ADC cores internally average the input signal. In 4x averaging (right), the signal has to be split externally and connected to both the INx1 and INx2 inputs where four ADC cores internally average the signal. INx1P/M 100 ADC 2x Averaging ADC INx1P/M 100 ADC ADC INx2P/M 100 ADC ADC 4x Averaging External Figure 7-45. Internal digital averaging (left: 2x, right: 4x) Table 7-48 provides a trade-off comparison of the 3 different averaging mode options vs the default, non- averaged mode. Table 7-48. Digital Averaging vs Full Power Input Bandwidth (–3 dB) # of ADCs averaged ADC inputs used for averaging Input Bandwidth (-3 dB) Selected differential input termination Noise density Power/ch (W) Default INx1 2.75 GHz 100 Ω -156 dBFS/Hz ~2.1 2 INx1 2.75 GHz 100 Ω -158 dBFS/Hz ~2.6 4 INx1, INx2 2.1 GHz 100 Ω -160 dBFS/Hz ~3.5 Digital averaging improves decorrelated noise contributions by 3 dB per 2x AVG (ideal) while correlated noise does not improve with averaging. Some of the dominant noise sources are correlated, that is, clock jitter (external or first clock input buffer), or power supply noise. While others (such as, ADC thermal noise, clock distribution buffers) are decorrelated. Table 7-49 illustrates a performance example comparison across averaging options. SNR: When operating close to ADC fullscale, some of the SNR limitation is due to jitter and hence the SNR improvement will not reach 3 dB (2x AVG) or 6 dB (4x AVG). As the input fullscale is reduced, the clock jitter contribution to SNR becomes less and the SNR improvement is approaching the ideal 3 dB per 2x AVG. The same phenomenon can be observed when using digital decimation. As the decimation factor increases, the close-in (correlated noise) becomes the more dominating noise unless the input signal amplitude is reduced. SFDR: The amplitude of low order harmonics (HD2-HD5) and IMD3 typically is similar across ADCs; thus, the improvement with averaging is small. www.ti.com ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 73 Product Folder Links: ADC32RF54 ADC32RF55

Table 7-49. Performance Comparison Example with 1x/2x/4x Averaging with FS = 2.6 GSPS, FIN = 1 GHz and Dither EN Parameter Input Amplitude (dBFS) 1x AVG 2x AVG 4x AVG SNR (dBFS) -4 62.8 64.9 67.2 -10 63.9 66.3 68.2 -20 64.0 66.4 69.4 HD2 (dBc) -4 66 62 71 -10 74 74 75 -20 70 70 80 HD3 (dBc) -4 73 76 78 -10 80 78 80 -20 74 71 72 Non HD23 (dBFS) -4 86 84 83 -10 90 91 92 -20 96 100 97 IMD3 (dBc) -10 dBFS/tone 77 73 71 -20 dBFS/tone 78 79 72

7.5 Programming

The device is primarily configured and controlled using the serial programming interface (SPI); however, it can operate in a default configuration without requiring the SPI interface. Furthermore, the power down function as well as NCO frequency hopping or JESD synchronization are possible via pin control (GPIO1/2 pins).

7.5.1 GPIO Pin Control

There are several commands which can be executed using SPI programming or GPIO pins. Table 7-50 provides an overview of the commands available using GPIO pins. Table 7-50. GPIO Pin Command Options FEATURE DESCRIPTION JESD SYNC Support for single ended CMOS or differential LVDS NCO Control Fast frequency hopping with 3 different control options Fast Overrange GPIO1 indicates overrange for channel B and GPIO2 for channel B. In this mode the overrange indication is 'sticky' - the flag stays high until it is cleared using SPI commands. Calibration Freeze Freezes swapping of calibration ADC

7.5.2 Configuration Using the SPI Interface

The device has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial interface enable), SCLK (serial interface clock) and SDIO (serial interface data input/output) pins. Serially shifting bits into the device is enabled when SEN is low. Serial data input are latched at every SCLK rising edge when SEN is active (low). The serial data are loaded into the register at every 24th SCLK rising edge when SEN is low. When the word length exceeds a multiple of 24 bits, the excess bits are ignored. Data can be loaded in multiples of 24-bit words within a single active SEN pulse. The interface can function with SCLK frequencies from 20 MHz down to ~ 1 MHz and also with a non-50% SCLK duty cycle. ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 www.ti.com

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7.5.2.1 Register Write

The internal registers can be programmed following these steps: 1. Drive the SEN pin low 2. Set the R/W bit to 0 (bit A15 of the 16-bit address) and bits A[14:12] in address field to 0. 3. Initiate a serial interface cycle by specifying the address of the register (A[11:0]) whose content is written and 4. Write the 8-bit data that are latched in on the SCLK rising edges Figure 7-46 shows the timing requirements for the serial register write operation. A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Register Address <11:0> Register Data <7:0> SDIO SCLK tSCLK tSU(SDIO) tH(SDIO) SEN tS(SEN) tH(SEN) RESET A11 A10 A9 A8 A7 A60 0 00 R/W Figure 7-46. Serial Register Write Timing Diagram

7.5.2.2 Register Read

The device includes a mode where the contents of the internal registers can be read back using the SDIO pin. This readback mode can be useful as a diagnostic check to verify the serial interface communication between the external controller and the ADC. The procedure to read the contents of the serial registers is as follows: 1. Drive the SEN pin low 2. Set the R/W bit (A15) to 1. This setting disables any further writes to the registers. Set A[14:12] in address field to 0. 3. Initiate a serial interface cycle specifying the address of the register (A[11:0]) whose content must be read 4. The device outputs the contents (D[7:0]) of the selected register on the SDIO pin 5. The external controller can latch the contents at the SCLK falling edge A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Register Address <11:0> Register Data <7:0> SDIO SCLK SEN A11 A10 A9 A8 A7 A60 0 01 R/W tOZD tOD tODZ Figure 7-47. Serial Register Read Timing Diagram www.ti.com ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 75 Product Folder Links: ADC32RF54 ADC32RF55

7.6 Register Maps

Table 7-51. Register Map Summary PAGE REGISTER ADDRESS REGISTER DATA A[11:0] D7 D6 D5 D4 D3 D2 D1 D0 GLOBAL 0x00 0 0 0 0 0 0 0 RESET 0x05 MEM PAGE ANALOG PAGE CALIB PAGE DDCB PAGE DDCA PAGE JESD PAGE DIGITAL PAGE 0 DIGITAL 0x2C 20-BIT OUT DDC BAND SEL 0 0 0 DDC REAL BYP EN 0x2D 0 DECIMATION 0 0 0 0 0x2E 0 0 0 0 AVG EN AVG SEL(1) 0 0x33 0 0 0 1 FORMAT 0 GBL PDN 0 0x34 0 MEM STROBE MEM CH SEL 0 0 0 0 0x3B NCO4 CHA [1:0] NCO3 CHA [1:0] NCO2 CHA [1:0] NCO1 CHA [1:0] 0x41 NCO4 CHB [1:0] NCO3 CHB [1:0] NCO2 CHB [1:0] NCO1 CHB [1:0] 0x22F 1 SYSREF X5 SYSREF X4 SYSREF X3 SYSREF X2 SYSREF X1 SYSREF OR 1 0x234 0 NCO SEL MODE 0 0 GPIO MODE 0x235 NCO SEL SOURCE 0x236 0 GPIO2 INV GPIO1 INV GPIO SWAP 0 0 SYSREF RESET SYSREF EN 0x237 0 0 0 0 0 GPIO2 CFG 0 GPIO1 CFG 0x238 OVR OUTPUT CFG 0 0 0 0 JESD 0x20 K 0x21 0 SYNC SPI EN SYNC SPI 0 0 SYSREF MODE 0x22 LMFS MODE 0x24 DDC CLK DIV 0x25 JESD TX CLK DIV 0x27 0 0 DROP LSB 0 0 0 CLK BAL EN 0 0x28 JESD TX LANE EN 0x2B 0 0 0 0 0 0 0 SYNC INV 0x2D 0 0 0 0 0 TEST SEQ SEL 0x2E RAMP INCR 0 RAMP EN ALT PAT 0 0x2F 0 PRBS PAT PRBS EN 0 0 0 0 ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 www.ti.com

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Table 7-51. Register Map Summary (continued) PAGE REGISTER ADDRESS REGISTER DATA A[11:0] D7 D6 D5 D4 D3 D2 D1 D0 JESD 0x30 START VALUE JESD RAMP DOUT0 0x32 START VALUE JESD RAMP DOUT1 0x34 START VALUE JESD RAMP DOUT2 0x36 START VALUE JESD RAMP DOUT3 0x40 START VALUE JESD RAMP DOUT4 0x42 START VALUE JESD RAMP DOUT5 0x44 START VALUE JESD RAMP DOUT6 0x46 START VALUE JESD RAMP DOUT7 0x53 SCR EN 0 0 0 0 0 0 0 0x7A JESD LANE POL INV 0x80 0 LANE DOUT1 SEL 0 LANE DOUT0 SEL 0x81 0 LANE DOUT3 SEL 0 LANE DOUT2 SEL 0x82 0 LANE DOUT5 SEL 0 LANE DOUT4 SEL 0x83 0 LANE DOUT7 SEL 0 LANE DOUT6 SEL 0x84 0 0 0 0 0 0 JESD PLL FACTOR 0x89 TX EMPH DOUT1 [0] TX EMPH DOUT0 [5:0] 0 0x8A 0 0 0 TX EMPH DOUT1 [5:1] 0x8B TX EMPH DOUT3 [0] TX EMPH DOUT2 [5:0] 0 0x8C 0 0 0 TX EMPH DOUT3 [5:1] 0x8D TX EMPH DOUT5 [0] TX EMPH DOUT4 [5:0] 0 0x8E 0 0 0 TX EMPH DOUT5 [5:1] 0x8F TX EMPH DOUT7 [0] TX EMPH DOUT6 [5:0] 0 0x90 0 0 0 TX EMPH DOUT7 [5:1] 0x9D PD DOUT7 [0] PD DOUT6 [0] PD DOUT5 [0] PD DOUT4 [0] PD DOUT3 [0] PD DOUT2 [0] PD DOUT1 [0] PD DOUT0 [0] 0x9E PD DOUT7 [1] PD DOUT6 [1] PD DOUT5 [1] PD DOUT4 [1] PD DOUT3 [1] PD DOUT2 [1] PD DOUT1 [1] PD DOUT0 [1] 0x9F 0 JESD PLL1 0 JESD PLL2 0xA0 0 JESD PLL INPUT1 0 0 0 0 0xA1 0 JESD PLL INPUT2 0 0 0 0 0xA2 0 0 0 0 JESD PLL INPUT3 0 www.ti.com ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 77 Product Folder Links: ADC32RF54 ADC32RF55

Table 7-51. Register Map Summary (continued) PAGE REGISTER ADDRESS REGISTER DATA A[11:0] D7 D6 D5 D4 D3 D2 D1 D0 DDCA/B 0x180 0 0 DDC PDN DDC DITH PDN REAL DDC DB/QB DDC 0 NCO MODE 0x181 0 0 LOAD NCO 0 0 0 0 CALIBR ATION 0x34 0 0 0 0 0 AVG SEL(2) 1 0x45 CAL SPI CAL GPIO 0 0 1 0 1 0 0x298 0 0 0 0 CAL STATUS ANALOG 0x6D RESET SW [1:0] 0 0 0 0 0 0 0x6E 0 0 0 0 0 0 RESET SW [3:2] 0x7B 0 0 TERM A 0 0 0 0 TERM A 0x8B 0 0 TERM B 0 0 0 0 TERM B 0xA8 0 DITHER AMP1 0 0 0 0xAF DITHER DIS 0 0 1 0 0 0 0 0xB1 DITHER DIVIDER 0xB4 0 0 0 0 0 0 0 SYSREF AC EN 0xCD 0 DITH AMP2 0 0 0 0 0xE6 TX SWING [0] 0 0 0 0 0 0 0 0xE7 0 0 0 0 0 0 TX SWING [2:1] ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 www.ti.com

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7.6.1 Detailed Register Description

Figure 7-48. Register 0x00 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 RESET R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 7-52. Register 0x00 Field Descriptions Bit Field Type Reset Description 7-1 0 R/W 0 Must write 0 0 RESET R/W 0 This bit resets all internal registers to the default values. Does not self clear to 0. Figure 7-49. Register 0x05 7 6 5 4 3 2 1 0 MEM PAGE ANALOG PAGE CALIB PAGE DDCB PAGE DDCA PAGE JESD PAGE DIGITAL PAGE 0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 7-53. Register 0x05 Field Descriptions Bit Field Type Reset Description

7 MEM PAGE R/W 0 This bit enables access to the MEMORY page

0: MEMORY page access disabled 1: MEMORY page access enabled

6 ANALOG PAGE R/W 0 This bit enables access to the ANALOG page

0: ANALOG page access disabled 1: ANALOG page access enabled

5 CALIB PAGE R/W 0 This bit enables access to the CALIBRATION page

0: CALIBRATION page access disabled 1: CALIBRATION page access enabled 4 DDCB PAGE R/W 0 This bit enables access to the DDCB page. Contents can be written to DDCA and DDCB page simultaneously if it is identical. 0: DDCB page access disabled 1: DDCB page access enabled. 3 DDCA PAGE R/W 0 This bit enables access to the DDCA page. Contents can be written to DDCA and DDCB page simultaneously if it is identical. 0: DDCA page access disabled 1: DDCA page access enabled

2 JESD PAGE R/W 0 This bit enables access to the JESD page

0: JESD page access disabled 1: JESD page access enabled

1 DIGITAL PAGE R/W 0 This bit enables access to the DIGITAL page

0: DIGITAL page access disabled 1: DIGITAL page access enabled 0 0 R/W 0 Must write 0 www.ti.com ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 79 Product Folder Links: ADC32RF54 ADC32RF55

Figure 7-50. Register 0x2C (DIGITAL page) 7 6 5 4 3 2 1 0 20-BIT OUT DDC BAND SEL 0 0 0 DDC REAL BYP EN R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 7-54. Register 0x2C Field Descriptions Bit Field Type Reset Description 7 20-BIT OUT R/W 0 This bit enables the 20-bit output mode. It carries the output sample with 20-bit output resolution from the DDC and the sample is filled to 32-bit with 12 trailing 0s. 0: Normal operation 1: 20-bit output mode 6-5 DDC BAND SEL R/W 00 Selects 1, 2 or 4 DDC per ADC when complex decimation is enabled 0: Single band 1: Dual band 2: Quad band 3: not used 4-2 0 R 0 Must write 0 1 DDC REAL R/W 0 This bit enables real decimation filter (NCO = 0). BYP EN (D0) must be set to 0. 0: Complex decimation 1: Real decimation

0 BYP EN R/W 0 This bit enables DDC bypass mode

0: Decimation filter enabled. Complex decimation by default unless D1 is set 1: Decimation filter bypass Figure 7-51. Register 0x2D (DIGITAL page) 7 6 5 4 3 2 1 0

0 DECIMATION 0 0 0 0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 7-55. Register 0x2D Field Descriptions Bit Field Type Reset Description 7 0 R/W 0 Must write 0 6-4 DECIMATION R/W 0 Selects decimation. 0,1: not used 2: Decimation by 4 3: Decimation by 8 4: Decimation by 16 5: Decimation by 32 6: Decimation by 64 7: Decimation by 128 3-0 0 R/W 0 Must write 0 ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 www.ti.com

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Figure 7-52. Register 0x2E (DIGITAL page) 7 6 5 4 3 2 1 0 0 0 0 0 AVG EN AVG SEL (1) 0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 7-56. Register 0x2E Field Descriptions Bit Field Type Reset Description 7-4 0 R/W 0 Must write 0

3 AVG EN R/W 0 This bit enables averaging

0: no average 1: ADC averaging enabled 2-1 AVG SEL (1) R/W 00 Selects ADC averaging. Also AVG SEL (2) in CALIBRATION page needs to be set. 0: no average 1: 2 ADC average 2: 4 ADC average 0 0 R/W 0 Must write 0 Figure 7-53. Register 0x33 (DIGITAL page) 7 6 5 4 3 2 1 0 0 0 0 1 FORMAT 0 GBL PDN 0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 7-57. Register 0x33 Field Descriptions Bit Field Type Reset Description 7-5 0 R/W 0 Must write 0 4 1 R/W 0 Must write 1

3 FORMAT R/W 0 This register bit determines the output data format in DDC

bypass mode only. 0: Offset Binary 1: 2s Complement DDC mode only supports 2s complement output format. 2 0 R/W 0 Must write 0

1 GBL PDN R/W 0 This register bit enables global power down mode

0: normal operation 1: global power down mode enabled 0 0 R/W 0 Must write 0 Figure 7-54. Register 0x34 (DIGITAL page) 7 6 5 4 3 2 1 0

0 MEM STROBE MEM CH SEL 0 0 0 0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 7-58. Register 0x34 Field Descriptions Bit Field Type Reset Description 7 0 R/W 0 Must write 0

6 MEM STROBE R/W 0 This register enables fast power down mode

0: normal operation 1: fast power down mode enabled www.ti.com ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 81 Product Folder Links: ADC32RF54 ADC32RF55

Table 7-58. Register 0x34 Field Descriptions (continued) Bit Field Type Reset Description 5-4 MEM CH SEL R/W 0 This register selects which ADC channel is used to fill up the capture sample buffer. Only 1 channel can be selected at a time and the samples are captured from the ADC core without averaging or decimation. 00: capture memory is filled from chA1 input 01: capture memory is filled from chA2 input 10: capture memory is filled from chB1 input 11: capture memory is filled from chB2 input 0 0 R/W 0 Must write 0 Figure 7-55. Register 0x3B (DIGITAL page) 7 6 5 4 3 2 1 0 NCO4 CHA [1:0] NCO3 CHA [1:0] NCO2 CHA [1:0] NCO1 CHA [1:0] R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 7-59. Register 0x3B Field Descriptions Bit Field Type Reset Description 7-6 NCO4 CHA [1:0] R/W 00 This register is used when selecting the NCO frequency for channel A, band 4 with the SPI interface in quad DDC mode. 5-4 NCO3 CHA [1:0] R/W 00 This register is used when selecting the NCO frequency for channel A, band 3 with the SPI interface in quad DDC mode. 3-2 NCO2 CHA [1:0] R/W 00 In single band DDC mode this register is used to select between NCO bank 1 or 2. 00: NCO bank 1 01: NCO bank 2 In dual band DDC mode this register is used to select the NCO frequency for channel A, band 2 with the SPI interface. 1-0 NCO1 CHA [1:0] R/W 00 This register is used when selecting the NCO1 of channel A with the SPI interface. Figure 7-56. Register 0x41 (DIGITAL page) 7 6 5 4 3 2 1 0 NCO4 CHB [1:0] NCO3 CHB [1:0] NCO2 CHB [1:0] NCO1 CHB [1:0] R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 7-60. Register 0x41 Field Descriptions Bit Field Type Reset Description 7-6 NCO4 CHB [1:0] R/W 00 This register is used when selecting the NCO frequency for channel B, band 4 with the SPI interface in quad DDC mode. 5-4 NCO3 CHB [1:0] R/W 00 This register is used when selecting the NCO frequency for channel B, band 3 with the SPI interface in quad DDC mode. 3-2 NCO2 CHB [1:0] R/W 00 In single band DDC mode this register is used to select between NCO bank 1 or 2 of channel B. 00: NCO bank 1 01: NCO bank 2 In dual band DDC mode this register is used to select the NCO frequency for channel B, band 2 with the SPI interface. 1-0 NCO1 CHB [1:0] R/W 00 This register is used when selecting the NCO1 of channel B with the SPI interface. ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 www.ti.com

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Figure 7-57. Register 0x22F (DIGITAL page) 7 6 5 4 3 2 1 0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 7-61. Register 0x22F Field Descriptions Bit Field Type Reset Description 7 1 R/W 1 Must write 1 6-2 SYSREF X1..5 R/W 0 These bits are the XOR flags from the SYSREF window monitoring circuitry. The sampling clock gets delayed internally by ~ 160 ps and used to capture the SYSREF signal. If a SYSREF signal transition happens within +/- 50 ps of the SYSREF capture the appropriate XOR flag gets raised. These bits are not sticky - they get overwritten with the next SYSREF rising edge. X1: Window from 110 ps to 135 ps after the rising sampling clock edge X2: Window from 135 ps to 160 ps after the rising sampling clock edge X3: Window from 160 ps to 176 ps after the rising sampling clock edge X4: Window from 176 ps to 192 ps after the rising sampling clock edge X5: Window from 192 ps to 208 ps after the rising sampling clock edge 0: No SYSREF transition detected 1: SYSREF transition detected within given window

1 SYSREF OR R/W 0 This bit is the output of the five SYSREF XOR flags logically

OR'ed together. 0: no SYSREF flag raised 1: one of the five SYSREF XOR flags is raised. 0 1 R/W 1 Must write 1 Figure 7-58. Register 0x234 (DIGITAL page) 7 6 5 4 3 2 1 0

0 NCO SEL MODE 0 0 GPIO MODE

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 7-62. Register 0x234 Field Descriptions Bit Field Type Reset Description 7 0 R/W 0 Must write 0 6-5 NCO SEL MODE R/W 00 These bits select control of the NCO selection in complex decimation. 0: NCO selection using GPIO pins (GPIO MODE (D2-D0) needs to be set accordingly) 2: GPIO1/2 pins are used as a fast serial interface only for the NCO selection for each digital mixer 3: GPIO1/2, SCLK, SDIO pins are used for NCO selection. others: not used Register 0x235 may need to be set as well. 4-3 0 R/W 0 Must write 0 2-0 GPIO MODE R/W 000 This register sets the functionality of the two GPIO pins 0: GPIO pins are used as SYNC input (LVDS), GPIO1 = SYNCP, GPIO2 = SYNCM 1: GPIO1 is used as SYNC input (CMOS) 3: Both GPIO pins are used to select NCOs for the decimation filters 4: GPIO1 is used to disable the calibration 5: GPIO1 is used as start of SYSREF counter others: not used www.ti.com ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 83 Product Folder Links: ADC32RF54 ADC32RF55

Figure 7-59. Register 0x235 (DIGITAL page) 7 6 5 4 3 2 1 0 NCO SEL SOURCE R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 7-63. Register 0x235 Field Descriptions Bit Field Type Reset Description 7-0 NCO SEL SOURCE R/W 0 This register works in conjuction with NCO SEL MODE (0x234). 0x00: NCO selection other than regular SPI (GPIO, Fast SPI etc) 0xFF: NCO selection using regular SPI with addresses 0x3B/41. Figure 7-60. Register 0x236 (DIGITAL page) 7 6 5 4 3 2 1 0

0 GPIO2 INV GPIO1 INV GPIO SWAP 0 0 SYSREF

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 7-64. Register 0x236 Field Descriptions Bit Field Type Reset Description 7 0 R/W 0 Must write 0

6 GPIO2 INV R/W 0 This bit inverts polarity of the GPIO2 pin

0: Polarity as is 1: Polarity inverted

5 GPIO1 INV R/W 0 This bit inverts polarity of the GPIO1 pin

0: Polarity as is 1: Polarity inverted 4 GPIO SWAP R/W 0 This bit swaps GPIO1 and GPIO2 pins internally. 0: Normal operation 1: GPIO1 and GPIO2 are swapped 3-2 0 R/W 0 Must write 0

1 SYSREF RESET R/W 0 This bit enables and clears the internal SYSREF counter:

0: Normal operation 1: Enables SYSREF and clears the internal counter

0 SYSREF EN R/W 0 This bit starts the internal SYSREF counter:

0: Normal operation 1: Starts SYSREF counter Figure 7-61. Register 0x237 (DIGITAL page) 7 6 5 4 3 2 1 0 0 0 0 0 0 GPIO2 CFG 0 GPIO1 CFG R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 7-65. Register 0x237 Field Descriptions Bit Field Type Reset Description 7-3 0 R/W 0 Must write 0 2 GPIO2 CFG R/W 0 This bit configures GPIO2 pin either as input or output. 0: GPIO2 pin is input 1: GPIO2 pin is output 1 0 R/W 0 Must write 0 0 GPIO1 CFG R/W 0 This bit configures GPIO1 pin either as input or output. 0: GPIO1 pin is input 1: GPIO1 pin is output ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 www.ti.com

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Figure 7-62. Register 0x238 (DIGITAL page) 7 6 5 4 3 2 1 0 OVR OUTPUT CFG 0 0 0 0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 7-66. Register 0x238 Field Descriptions Bit Field Type Reset Description 7-4 OVR OUTPUT CFG R/W 0000 This bit configures if the overrange indication (OVR) is output on JESD output stream or on GPIO pins 0000: OVR on JESD 1111: OVR on GPIO 3-0 0 R/W 0 Must write 0 Figure 7-63. Register 0x20 (JESD page) 7 6 5 4 3 2 1 0 K R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 7-67. Register 0x20 Field Descriptions Bit Field Type Reset Description 7-0 K R/W 00000000 This is JESD204B parameter K which sets number of frames in a multi-frame. Bit value is set as K minus 1. Figure 7-64. Register 0x21 (JESD page) 7 6 5 4 3 2 1 0

0 SYNC SPI EN SYNC SPI 0 0 SYSREF MODE

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 7-68. Register 0x21 Field Descriptions Bit Field Type Reset Description 7 0 R/W 0 Must write 0

6 SYNC SPI EN R/W 0 This bit enables JESD SYNC control using SPI (ignoring SYNC

using GPIO1/2 pins) using bit D5 (SYNC SPI). 0: SPI SYNC disabled 1: SPI SYNC (using register bit D5) enabled 5 SYNC SPI R/W 0 This bit enables JESD SYNC. SYNC control via SPI must be enabled also (D6). 0: ADC outputs data (SYNC disabled) 1: SYNC enabled (ADC outputs K28.5 characters for JESD interface synchronization) 4-3 0 R/W 0 Must write 0 2-0 SYSREF MODE R/W 000 This register controls how the ADC processes incoming SYSREF pulses. 0: Ignore all SYSREF pulses 1: Use all SYSREF pulses 2: Don't use SYSREF pulses 3: Skip one SYSREF pulse then use only the next one 4: Skip one SYSREF pulse then use all pulses 5: Skip two SYSREF pulses and then use one 6: Skip two SYSREF pulses and then use all www.ti.com ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 85 Product Folder Links: ADC32RF54 ADC32RF55

Figure 7-65. Register 0x22 (JESD page) 7 6 5 4 3 2 1 0 JESD MODE R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 7-69. Register 0x22 Field Descriptions Bit Field Type Reset Description 7:0 JESD MODE R/W 00000000 This register sets the LMFS configuration 0: LMFS = 8-2-8-20 (also bit DROP LSB in 0x27 needs to be set) 1: LMFS = 8-2-2-4 3: LMFS = 8-4-2-2 4: LMFS = 8-16-4-1 5: LMFS = 4-16-8-1 8: LMFS = 8-8-2-1 9: LMFS = 4-8-4-1 10: LMFS = 2-8-8-1 12: LMFS = 4-4-2-1 13: LMFS = 2-4-4-1 14: LMFS = 1-4-8-1 15: LMFS = 2-2-2-1 16: LMFS = 1-2-4-1 others: not used Figure 7-66. Register 0x24 (JESD page) 7 6 5 4 3 2 1 0 DDC CLK DIV R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 7-70. Register 0x24 Field Descriptions Bit Field Type Reset Description 7-0 DDC CLK DIV R/W 00000000 This register sets the internal clock divider when using the decimation filter. See Table 7-72. Figure 7-67. Register 0x25 (JESD page) 7 6 5 4 3 2 1 0 JESD TX CLK DIV R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 7-71. Register 0x25 Field Descriptions Bit Field Type Reset Description 7-0 JESD TX CLK DIV R/W 0000000 This register sets the internal clock divider for the selected LMFS output mode. See Table 7-72 for 16-bit and Table 7-73 for 20-bit output. ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 www.ti.com

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Table 7-72. Register Settings for 0x24/0x25 Based on Bypass/Decimation and LMFS Mode (16-bit Output) 0x24 (DDC CLK DIV) 0x25 (JESD TX CLK DIV) LMFS BYP /4 /8 /16 /32 /64 /128 BYP /4 /8 /16 /32 /64 /128 8-2-2-4 0 0 8-2-8-20 0 4 8-4-8-10 1 4 8-4-2-2 1 0 0 0 0 0 1 1 1 1 8-8-2-1 0 0 0 0 0 0 0 0 0 0 0 0 8-16-4-1 1 1 1 1 1 1 0 0 0 0 0 0 4-2-2-2 0 0 0 0 0 0 1 1 1 1 1 1 4-4-2-1 0 0 0 0 0 0 0 0 0 0 0 0 4-8-4-1 1 1 1 1 1 1 0 0 0 0 0 0 4-16-8-1 3 3 3 3 3 3 0 0 0 0 0 0 2-2-2-1 0 0 0 0 0 0 0 0 0 0 0 0 2-4-4-1 1 1 1 1 1 1 0 0 0 0 0 0 2-8-8-1 3 3 3 3 3 3 0 0 0 0 0 0 2-16-16-1 7 7 7 7 7 0 0 0 0 0 1-2-4-1 1 1 1 1 1 1 0 0 0 0 0 0 1-4-8-1 3 3 3 3 3 3 0 0 0 0 0 0 1-8-16-1 7 7 7 7 7 0 0 0 0 0 1-16-32-1 15 15 15 15 0 0 0 0 Table 7-73. Register Settings for 0x24/0x25 Based on Decimation and LMFS Mode (20-bit Output). 0x24 (DDC CLK DIV) 0x25 (JESD TX CLK DIV) LMFS BYP /4 /8 /16 /32 /64 /128 BYP /4 /8 /16 /32 /64 /128 8-8-4-1 1 1 1 1 1 1 0 0 0 0 0 0 8-16-8-1 3 3 3 3 3 3 0 0 0 0 0 0 4-4-4-1 1 1 1 1 1 1 0 0 0 0 0 0 4-8-8-1 3 3 3 3 3 3 0 0 0 0 0 0 4-16-16-1 7 7 7 7 7 0 0 0 0 0 2-2-4-1 1 1 1 1 1 1 0 0 0 0 0 0 2-4-8-1 3 3 3 3 3 3 0 0 0 0 0 0 2-8-16-1 7 7 7 7 7 0 0 0 0 0 2-16-32-1 15 15 15 15 0 0 0 0 1-2-8-1 3 3 3 3 3 3 0 0 0 0 0 0 1-4-16-1 7 7 7 7 7 0 0 0 0 0 1-8-32-1 15 15 15 15 0 0 0 0 1-16-64-1 31 31 31 0 0 0 www.ti.com ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 87 Product Folder Links: ADC32RF54 ADC32RF55

Figure 7-68. Register 0x27 (JESD page) 7 6 5 4 3 2 1 0 0 0 DROP LSB 0 0 0 CLK BAL EN 0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 7-74. Register 0x27 Field Descriptions Bit Field Type Reset Description 7-6 0 R/W 0 Must write 0

5 DROP LSB R/W 0 This register needs to be set when using the 12-bit output LMFS

mode. 0: Drop LSB disabled 1: Drop LSB enabled when using LMFS = 8-2-8-2-20 4-2 0 R/W 0 Must write 0

1 CLK BAL EN R/W 0 This register bit needs to be enabled in bypass mode LMFS =

8-2-2-4 only in order to improve some internal clock balancing. 0: CLK BAL disabled 1: CLK BAL EN. Set for LMFS = 8-2-2-4 0 0 R/W 0 Must write 0 Figure 7-69. Register 0x28 (JESD page) 7 6 5 4 3 2 1 0 JESD LANE EN R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 7-75. Register 0x28 Field Descriptions Bit Field Type Reset Description 7-0 JESD LANE EN R/W 11111111 This register turns on individual output lanes 0: Lane powered down 1: Serdes lane enabled D0: Lane DOUT0 D1: Lane DOUT1 ... D7: Lane DOUT7 Figure 7-70. Register 0x2B 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 SYNC INV R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 7-76. Register 0x2B Field Descriptions Bit Field Type Reset Description 7-1 0 R/W 0 Must write 0

0 SYNC INV R/W 0 This register inverts the polarity from external SYNC pin

0: Polarity as is 1: Polarity inverted ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 www.ti.com

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Figure 7-71. Register 0x2D (JESD page) 7 6 5 4 3 2 1 0 0 0 0 0 0 JESD SEQ SEL R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 7-77. Register 0x2D Field Descriptions Bit Field Type Reset Description 7-3 0 R/W 0 Must write 0 2-0 JESD SEQ SEL R/W 000 This register selects the JESD test pattern sequence 0: Test sequence disabled 1: Repeat D21.5 high frequency pattern for random jitter (RJ) 2: Repeat K28.5 mixed frequency pattern for deterministic jitter (DJ) 3: Repeat initial lane alignment (ILA) sequence 4: Modified random pattern 5: Scrambled jitter pattern 6: Repeat K28.7 low frequency pattern 7: Short test pattern Figure 7-72. Register 0x2E (JESD page) 7 6 5 4 3 2 1 0 RAMP INCR 0 RAMP EN ALT PAT 0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 7-78. Register 0x2E Field Descriptions Bit Field Type Reset Description 7-4 RAMP INCR R/W 0000 This register value sets the increment step size for the ramp pattern on 16-bit output. The step size is RAMP INCR plus 1. 3 0 R/W 0 Must write 0 2 RAMP EN R/W 0 Enables RAMP output pattern in the TRANSPORT LAYER.

1 ALT PAT R/W 0 Enables a toggle pattern switching between 0x0000 and 0xFFFF

Figure 7-73. Register 0x2F (JESD page) 7 6 5 4 3 2 1 0

0 SERDES PRBS SERDES PRBS

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 7-79. Register 0x2F Field Descriptions Bit Field Type Reset Description 7 0 R/W 0 Must write 0 6-5 SERDES PRBS R/W 0 This register selects the PRBS pattern in the LINK LAYER (no 8b/10b encoding). PRBS pattern must be enabled (D4). 0: PRBS 27-1 1: PRBS 215-1 2: PRBS 223-1 3: PRBS 231-1

4 SERDES PRBS EN R/W 0 This register enables PRBS test pattern in the LINK LAYER

0: Test pattern mode disabled 1: PRBS test pattern mode enabled 3-0 0 R/W 0 Must write 0 www.ti.com ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 89 Product Folder Links: ADC32RF54 ADC32RF55

Figure 7-74. Register 0x30/32/34/36/40/42/44/46 (JESD page) 7 6 5 4 3 2 1 0 START VALUE JESD RAMP DOUT0/1/2/3/4/5/6/7 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 7-80. Register 0x30/32/34/36/40/42/44/46 Field Descriptions Bit Field Type Reset Description 7-0 START VALUE JESD RAMP R/W 00000000 The JESD RAMP test pattern is designed to act as an individual RAMP pattern on each output lane. If the starting value on each lane is set to 0 (default), each output lane shows the same RAMP code at any given time. The RAMP pattern can be configured such that the RAMP pattern is constructed across JESD output lanes using the start value registers. DOUT1=1, DOUT2=2, DOUT3=3, DOUT4=0, DOUT5=1, DOUT6=2 and DOUT7=3 as well as the RAMP increment to 4 (RAMP INCR (0x2E) = 0x30) results in a RAMP pattern across lanes for each channel in bypass mode. Figure 7-75. Register 0x53 (JESD page) 7 6 5 4 3 2 1 0 SCR EN 0 0 0 0 0 0 0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 7-81. Register 0x53 Field Descriptions Bit Field Type Reset Description

7 SCR EN R/W 0 Enables scrambling of the JESD output data

0: Output scrambling disabled 1: Output scrambling enabled 6-0 0 R/W 0 Must write 0 Figure 7-76. Register 0x7A (JESD page) 7 6 5 4 3 2 1 0 JESD LANE POL INV R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 7-82. Register 0x7A Field Descriptions Bit Field Type Reset Description 7-0 JESD LANE POL INV R/W 00000000 This register inverts the polarity of the individual SERDES output lanes. Register bit D0 corresponds to SERDES lane DOUT0, D1 to DOUT1 etc 0: Output polarity as is 1: Output polarity inverted ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 www.ti.com

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Figure 7-79. Register 0x89/8A/8B/8C/8D/8E/8F/90 (JESD page) ADDR 7 6 5 4 3 2 1 0 0x89 TX EMPH DOUT1 [0] TX EMPH DOUT0 [5:0] 0 0x8A 0 0 0 TX EMPH DOUT1 [5:1] 0x8B TX EMPH DOUT3 [0] TX EMPH DOUT2 [5:0] 0 0x8C 0 0 0 TX EMPH DOUT3 [5:1] 0x8D TX EMPH DOUT5 [0] TX EMPH DOUT4 [5:0] 0 0x8E 0 0 0 TX EMPH DOUT5 [5:1] 0x8F TX EMPH DOUT7 [0] TX EMPH DOUT6 [5:0] 0 0x90 0 0 0 TX EMPH DOUT7 [5:1] R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 7-85. Register 0x89/8A/8B/8C/8D/8E/8F/90 Field Descriptions Bit Field Type Reset Description 7-5,0 0 R/W 0 Must write 0 6-1 TX EMPH DOUT0/2/4/6 [5:0] R/W 000000 These bits select the amount of de-emphasis for the JESD output transmitter. The de-emphasis value in dB is measured as the ratio between the peak value after the signal transition to the settled value of the voltage in one bit period. 0: 0 dB 1: –1 dB 3: –2 dB 7: –4.1 dB 15: –6.2 dB 31: –8.2 dB 63: –11.5 dB 4-0,7 TX EMPH DOUT1/3/5/7 [5:0] R/W 000000 Figure 7-80. Register 0x9D/9E (JESD page) 7 6 5 4 3 2 1 0 PD DOUT7 [0,1] PD DOUT6 [0,1] PD DOUT5 [0,1] PD DOUT4 [0,1] PD DOUT3 [0,1] PD DOUT2 [0,1] PD DOUT1 [0,1] PD DOUT0 [0,1] R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 7-86. Register 0x9D/9E Field Descriptions Bit Field Type Reset Description 7-0 PD DOUTx [0,1] R/W 0 Register 0x9D and 0x9E allow power down of individual serdes output lanes. Register 0x9D (PD DOUTx [0]) covers the output driver, 0x9E (PD DOUTx [1]) covers the associated internal high-speed data clock. 0: Output lane enabled 1: Output lane powered down ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 www.ti.com

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Figure 7-81. Register 0x9F (JESD page) 7 6 5 4 3 2 1 0

0 JESD PLL1 0 JESD PLL2

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 7-87. Register 0x9F Field Descriptions Bit Field Type Reset Description 7 0 R/W 0 Must write 0 6-4 JESD PLL1 R/W 000 Internal JESD PLL input divider setting. See Table 7-89 how to configure it for the different decimation and LMFS settings. 3 0 R/W 0 Must write 0 2-0 JESD PLL2 R/W 000 Internal JESD PLL input divider setting. See Table 7-89 how to configure it for the different decimation and LMFS settings. Figure 7-82. Register 0xA0/A1/A2 (JESD page) ADDR 7 6 5 4 3 2 1 0 0xA0 0 JESD PLL INPUT1 0 0 0 0 0xA1 0 JESD PLL INPUT2 0 0 0 0 0xA2 0 0 0 0 JESD PLL INPUT3 0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 7-88. Register 0xA0/A1/A2 Field Descriptions Bit Field Type Reset Description 7-0 0 R/W 0 Must write 0 6-4 JESD PLL INPUT1/2 R/W 000 Internal JESD PLL input divider setting. See Table 7-89 (16-bit output) and Table 7-89 (20-bit output) how to configure it for the different decimation and LMFS settings. 3-1 JESD PLL INPUT3 R/W 000 Internal JESD PLL input divider setting. See Table 7-89 (16-bit output) and Table 7-89 (20-bit output)how to configure it for the different decimation and LMFS settings. Table 7-89. Register settings for 0x9F/A0/A1/A2 based on bypass/decimation and LMFS mode (16-bit output) LMFS BYP /4 /8 /16 /32 /64 /128 BYP /4 /8 /16 /32 /64 /128 BYP /4 /8 /16 /32 /64 /128 8-2-2-4 0 0 0 8-2-8-20 0 0 0 8-4-8-10 0 0 1 8-4-2-2 0 1 2 3 3 0 0 1 2 2 1 0 0 0 2 8-8-2-1 0 1 2 3 4 4 0 1 2 3 4 4 0 0 0 0 0 2 8-16-4-1 0 0 1 2 3 4 0 0 1 2 3 4 1 0 0 0 0 0 4-2-2-2 1 2 3 0 1 2 0 4-4-2-1 0 1 2 3 4 4 0 1 2 3 4 4 0 0 0 0 0 2 4-8-4-1 0 0 1 2 3 4 0 0 1 2 3 4 1 0 0 0 0 0 4-16-8-1 0 0 0 1 2 3 0 0 0 1 2 3 3 1 0 0 0 0 2-2-2-1 0 1 2 3 4 4 0 1 2 3 4 4 0 0 0 0 0 2 2-4-4-1 0 0 1 2 3 4 0 0 1 2 3 4 0 0 0 0 0 0 2-8-8-1 0 0 0 1 2 3 0 0 0 1 2 3 3 1 0 0 0 0 2-16-16-1 0 0 0 1 2 0 0 0 1 2 3 1 0 0 0 1-2-4-1 0 0 1 2 3 4 0 0 1 2 3 4 1 0 0 0 0 0 1-4-8-1 0 0 0 1 2 3 0 0 0 1 2 3 3 1 0 0 0 0 www.ti.com ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 93 Product Folder Links: ADC32RF54 ADC32RF55

Table 7-89. Register settings for 0x9F/A0/A1/A2 based on bypass/decimation and LMFS mode (16-bit output) (continued) 1-8-16-1 0 0 0 1 2 0 0 0 1 2 3 1 0 0 0 1-16-32-1 0 0 0 1 0 0 0 1 3 1 0 0 Table 7-90. Register settings for 0x9F/A0/A1/A2 based on decimation and LMFS mode (20-bit output) LMFS /4 /8 /16 /32 /64 /128 /4 /8 /16 /32 /64 /128 /4 /8 /16 /32 /64 /128 8-8-4-1 0 0 1 2 3 4 0 0 1 2 3 4 1 0 0 0 0 0 8-16-8-1 0 0 0 1 2 3 0 0 0 1 2 3 3 1 0 0 0 0 4-4-4-1 0 0 1 2 3 4 0 0 1 2 3 4 1 0 0 0 0 0 4-8-8-1 0 0 0 1 2 3 0 0 0 1 2 3 3 1 0 0 0 0 4-16-16-1 0 0 0 1 2 0 0 0 1 2 3 1 0 0 0 2-2-4-1 0 0 1 2 3 4 0 0 1 2 3 4 1 0 0 0 0 0 2-4-8-1 0 0 0 1 2 3 0 0 0 1 2 3 3 1 0 0 0 0 2-8-16-1 0 0 0 1 2 0 0 0 1 2 3 1 0 0 0 2-16-32-1 0 0 0 1 0 0 0 1 3 1 0 0 1-2-8-1 0 0 0 1 2 3 0 0 0 1 2 3 3 1 0 0 0 0 1-4-16-1 0 0 0 1 2 0 0 0 1 2 3 1 0 0 0 1-8-32-1 0 0 0 1 0 0 0 1 3 1 0 0 1-16-64-1 0 0 0 0 0 0 3 1 0 Figure 7-83. Register 0x100..0x17D (DDCA/B page) 7 6 5 4 3 2 1 0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 7-91. Register 0x100..0x17D Field Descriptions Bit Field Type Reset Description 47:0 NCOx FREQUENCYx R/W 0 The frequencies for NCOs are located in addresses 0x100 to 0x17D. Each frequency is 48-bit and the MSB starts on the highest address as illustrated in Section 7.3.5.6. ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 www.ti.com

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Figure 7-84. Register 0x180 (DDCA/B page) 7 6 5 4 3 2 1 0 0 0 DDC PDN DDC DITH PDN REAL DDC DB/QB DDC 0 NCO MODE R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 7-92. Register 0x180 Field Descriptions Bit Field Type Reset Description 7-6 0 R/W 0 Must write 0

5 DDC PDN R/W 0 This bit powers down the DDC mixer and NCO

0: DDC block enabled 1: DDC block powered down

4 DDC DITH PDN R/W 0 This bit powers down the dither in the DDC digital block

0: DDC dither enabled 1: DDC dither powered down 3 REAL DDC R/W 0 Set this bit to 1 in real decimation mode to disable the NCO. 0: Complex Decimation 1: Real Decimation 2 DB/QB DDC R/W 0 This register splits the NCOs for dual or quad band operation. 0: Dual Band 1: Quad Band 1 0 R/W 0 Must write 0

0 NCO MODE R/W 0 This register selects phase coherent or phase continuous

operation of the NCO. 0: Phase continuous 1: Phase coherent Figure 7-85. Register 0x181 (DDCA/B page) 7 6 5 4 3 2 1 0 0 0 LOAD NCO 0 0 0 0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 7-93. Register 0x181 Field Descriptions Bit Field Type Reset Description 7-6 0 R/W 0 Must write 0 5-4 LOAD NCO R/W 00 This register loads all the NCO frequencies from the memory to the NCOs. To update the NCO this register has to be set to 3 and back to 0 as shown in Table 7-94. 3-0 0 R/W 0 Must write 0 Table 7-94. NCO frequency programming example ADDR DATA DESCRIPTION 0x105 0x4E Frequency = 920 MHz with FS = 3 GSPS 86,318,992,857,935 = 0x4E81B4E81BE4 where the MSB goes to address 0x105 and the LSB to 0x100. 0x104 0x81 0x103 0xB4 0x102 0xE8 0x101 0x1B 0x100 0x4E 0x181 0x00 Load and update all NCO frequencies 0x181 0x30 www.ti.com ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 95 Product Folder Links: ADC32RF54 ADC32RF55

Figure 7-86. Register 0x34 (CALIBRATION page) 7 6 5 4 3 2 1 0 0 0 0 0 0 AVG SEL (2) 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 7-95. Register 0x34 Field Descriptions Bit Field Type Reset Description 7-3 0 R/W 0 Must write 0 2-1 AVG SEL (2) R/W 00 Selects ADC averaging. Also AVG SEL (1) in DIGITAL page needs to be set. 0: no average 01: 2 ADC average 10: not used 11: 4 ADC average 0 1 R/W 1 Must write 1 Figure 7-87. Register 0x45 (CALIBRATION page) 7 6 5 4 3 2 1 0 CAL SPI CAL GPIO 0 0 1 0 1 0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 7-96. Register 0x45 Field Descriptions Bit Field Type Reset Description 7 CAL SPI R/W 0 This register triggers the calibration using SPI write. It needs to be toggled (0=>1=>0). 6 CAL GPIO R/W 0 This register triggers the calibration using the GPIO1 pin. 5-4 0 R/W 0 Must write 0 3 1 R/W 1 Must write 1 2 0 R/W 0 Must write 0 1 1 R/W 1 Must write 1 0 0 R/W 0 Must write 0 Figure 7-88. Register 0x298 (CALIBRATION page) 7 6 5 4 3 2 1 0 0 0 0 0 CAL STATUS R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 7-97. Register 0x298 Field Descriptions Bit Field Type Reset Description 7-4 0 R/W 0 Must write 0 3-0 CAL STATUS R/W 0000 This register can be used to check if calibration state machine has finished without any errors. A value of 0xE indicates successful calibration. ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 www.ti.com

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Figure 7-92. Register 0xA8 (ANALOG page) 7 6 5 4 3 2 1 0

0 DITH AMP1 0 0 0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 7-101. Register 0xA8 Field Descriptions Bit Field Type Reset Description 7 0 R/W 0 Must write 0 6-3 DITH AMP1 R/W 0000 This register sets dither amplitude coarse gain. There are two recommended settings: 0000: Amplitude = 0 0011: Amplitude = 3 Here is a list of all the settings: 0000: Amplitude = 0 (smallest) 0001: Amplitude = 1 ... 1110: Amplitude = 14 1111: Amplitude = 15 (largest) 2-0 0 R/W 0 Must write 0 Figure 7-93. Register 0xAF (ANALOG page) 7 6 5 4 3 2 1 0 DITHER DIS 0 0 1 0 0 0 0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 7-102. Register 0xAF Field Descriptions Bit Field Type Reset Description 7 DITHER DIS R/W 0 This register disables internal dither. 0: Dither enabled 1: Dither disabled 6-5 0 R/W 0 Must write 0 4 1 R/W 0 Must write 1 3-0 0 R/W 0 Must write 0 Figure 7-94. Register 0xB1 (ANALOG page) 7 6 5 4 3 2 1 0 DITHER DIVIDER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 7-103. Register 0xB1 Field Descriptions Bit Field Type Reset Description 7-0 DITHER DIVIDER R/W 0 This register sets the dither divider frequency. SPI write is actual -1. For example a divider of 48 is 47 (0x2F). 0x00 (default) is a divide /50 ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 www.ti.com

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Figure 7-95. Register 0xB4 (ANALOG page) 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 SYSREF AC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 7-104. Register 0xB4 Field Descriptions Bit Field Type Reset Description 7-1 0 R/W 0 Must write 0

0 SYSREF AC R/W 0 This register enables external AC coupling of the SYSREF input

with internal biasing. 0: External DC coupling with internal 100 Ω termination 1: External AC coupling with internal biasing Figure 7-96. Register 0xCD (ANALOG page) 7 6 5 4 3 2 1 0

0 DITH AMP2 0 0 0 0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 7-105. Register 0xCD Field Descriptions Bit Field Type Reset Description 7 0 R/W 0 Must write 0 6-4 DITH AMP2 R/W 0 This register sets dither amplitude fine gain. There are two recommended settings: 000: Amplitude = 0 100: Amplitude = -4 Here is a list of all the settings: 000: Amplitude = 0 001: Amplitude = 1 010: Amplitude = 2 011: Amplitude = 3 (largest) 100: Amplitude = -4 (smallest) 101: Amplitude = -3 110: Amplitude = -2 111: Amplitude = -1 3-0 0 R/W 0 Must write 0 Figure 7-97. Register 0xE6/E7 (ANALOG page) ADDR 7 6 5 4 3 2 1 0 0xE6 TX SWING [0] 0 0 0 0 0 0 0 0xE7 0 0 0 0 0 0 TX SWING [2:1] R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 7-106. Register 0xE6/E7 Field Descriptions Bit Field Type Reset Description 7-0 0 R/W 0 Must write 0 1,0,7 TX SWING [2:0] R/W 000 This register adjusts the output amplitude on all 8 serdes lanes. 0: 850 mVpp 1: 825 mVpp 2: 800 mVpp 3: 775 mVpp 4: 950 mVpp 5: 925 mVpp 6: 900 mVpp 7: 875 mVpp www.ti.com ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 99 Product Folder Links: ADC32RF54 ADC32RF55

8 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

8.1 Application Information

The ADC32RF5x can be used in a wide range of applications including radar, frequency domain digitizer and spectrum analyzer, test and communications equipment and software-defined radios (SDRs). The Typical Applications section describe one configuration that meets the needs of a number of these applications.

8.2 Typical Applications

8.2.1 Wideband RF Sampling Receiver

N N N 3Gsps ADCADC 3Gsps ADCADC N N DDCNCO SPI Registers and Device Control 1x/2x/4x Averaging N N N N N DDCNCO 1x/2x/4x Averaging 3Gsps ADCADC 3Gsps ADCADC JESD204B Up to 8 lanes JESD204B SPI GPIO1/2 LMK04832 Device Clock SYSREF VCM CVCM 100 pF 100 pF 100 pF 100 pF Balun RF Input INA1 INA2 100 pF 100 pF 100 pF 100 pF Balun RF Input INB2 INB1 BPF BPF Figure 8-1. Typical Configuration for Wideband RF Sampling

8.2.1.1 Design Requirements

8.2.1.1.1 Input Signal Path

Appropriate band limiting filters should be used to reject unwanted frequencies in the receive signal path. A 1:2 (for 100 ohm effective termination impedance) or a 1:1 (for 50 ohm effective termination impedance) balun transformer is needed to convert the single ended RF input to differential for input to the ADC. The balun outputs should be AC coupled with 100 pF capacitors. The balun should have good amplitude (< 0.5 dB) and phase balance (less than 2 deg) within the frequency range of interest. A back-to-back balun configuration often times gives better SFDR performance. Table 8-1 lists a number of recommended baluns for different impedance ratios and frequency ranges. The S-parameters of the ADC input can be used in order to design the front end matching network. ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 www.ti.com

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Table 8-1. Recommended Baluns PART NUMBER MANURACTURER IMPEDANCE RATIO AMPLITUDE BALANCE (dB) PHASE BALANCE (°) FREQUENCY RANGE BAL-0009SMG Marki Microwave 1:2 0.6 5 0.5 MHz to 9 GHz TCM2-43X+ Minicircuits 1:2 0.5 7 10 MHz to 4 GHz TCM2-33WX+ Minicircuits 1:2 0.7 4 10 MHz to 3 GHz TC1-1-13M+ Minicircuits 1:1 0.5 2-3 10 MHz to 3 GHz

8.2.1.1.2 Clocking

The device clock inputs must be AC-coupled to the device to provide the rated performance. The clock source must have low jitter (integrated phase noise) for the ADC to meet the stated SNR performance, especially when operating at higher input frequencies. The clock signal may need to be filtered with a band pass filter in order to remove some of the broad band clock noise. The JESD204B data converter system (ADC and FPGA) requires additional SYSREF and device clocks. The LMK04828 or LMK04832 devices are suitable to generate these clocks. Depending on the ADC clock frequency and jitter requirements. The device may also be used as a system clock synthesizer or as a device clock and SYSREF distribution device when using multiple ADC32RF5x devices in a system.

8.2.1.2 Detailed Design Procedure

8.2.1.2.1 Sampling Clock

In order to maximize the SNR performance of the ADC a very low jitter (< 50 fs) sampling clock is required. Figure 8-2 shows the estimated SNR performance vs input frequency vs external clock jitter. The internal ADC aperture jitter also has some depenceny to the clock amplitude (gets more sensitive with higher input frequency) as shown in Figure 8-3. When using averaging and/or decimation, the SNR for a single ADC core should be estimated first before adding the SNR improvement from internal averaging and/or decimation. Figure 8-2. SNR vs TJitter vs FIN (1x AVG) Figure 8-3. SNR vs Clock Amplitude (dither off) www.ti.com ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 101 Product Folder Links: ADC32RF54 ADC32RF55

8.2.1.3 Application Curves

The following application curves demonstrate performance and results only of the ADC using a balun front end and configured to 4x internal averaging. The input frequency is 900 MHz (F S = 2.6 GSPS) and input amplitudes of -6 and -20 dBFS are shown with dither enabled/disabled. Input Frequency (MHz) Amplitude (dBFS) 0 200 400 600 800 1000 1200 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 AIN = -6 dBFS, Dither DIS SNR = 67.8 dBFS, HD23 = 81 dBFS, Non HD23 = 76 dBFS Input Frequency (MHz) Amplitude (dBFS) 0 200 400 600 800 1000 1200 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 AIN = -6 dBFS, Dither EN SNR = 67.7 dBFS, HD23 = 80 dBFS, Non HD23 = 76 dBFS AIN = -20 dBFS, Dither = DIS SNR = 70.2 dBFS, SFDR = 58 dBc, Non HD23 = 85 dBFS Input Frequency (MHz) Amplitude (dBFS) 0 200 400 600 800 1000 1200 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 AIN = -20 dBFS, Dither = EN SNR = 69.5 dBFS, HD23 = 67 dBc, Non HD23 = 88 dBFS ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 www.ti.com

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8.3 Initialization Set Up

After power-up, the internal registers must be initialized to their default values through a hardware reset by applying a low pulse on the RESET pin, as shown in Figure 8-4. 1. Apply 1.2 V DVDD digital power supply 2. Apply remaining 1.2 V power supplies (AVDD12, CLKVDD), in no specific order 3. Apply 1.8 V AVDD18 power supply 4. Apply hardware reset. After hardware reset is released, the default registers are loaded from internal fuses. 5. Begin programming the internal registers using the SPI interface. AVDD18 RESET SEN t2 t3 AVDD12 CLKVDD DVDD Figure 8-4. Initialization of Serial Registers After Power-Up Table 8-2. Power-Up Timing MIN TYP MAX UNIT t1 Power-on delay: delay from power up to active high RESET pulse 1 ms t2 Reset pulse width: active low RESET pulse width 100 ns t3 Register write delay: delay from RESET disable to SEN active 45k Clock cycles www.ti.com ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 103 Product Folder Links: ADC32RF54 ADC32RF55

8.3.1 Initial Device Configuration After Power-Up

The following section outlines the sequence of register writes for the device configuration after initial power-up. Table 8-3. Summary of Programming Steps After Initial Power-Up Step Section Description

1 RESET Hardware and software RESET in order to reset all registers to known state

2 DEVICE CONFIG Configures the digital operating modes like averaging, test pattern output, input termination, internal dither and decimation.

3 JESD Configures the JESD204B interface

4 SYSREF Enables SYSREF input and resets internal circuits based on external SYSREF signal.

5 JESD Clears and configures some of the JESD registers

6 TRIM Set trim settings for best analog performance

7 CALIB CONFIG Configure the calibration settings

8 SYSREF Issue SYSREF for trim settings to go into effect

9 RUN CALIB Run power up calibration

10 JESD Synchronize the JESD interface with the receiver

The following sections outlines the detailed register writes for the device configuration after initial power up. This includes all the register writes (fields in grey) which are not documented in the register summary table. The register examples are given for 2x internal averaging, DDC bypass mode (LMFS = 8224).

8.3.1.1 STEP 1: RESET

After the initial power up, both hardware and software reset are required. Table 8-4. Register Programming Sequence for Software RESET ADDRESS DATA DESCRIPTION 0x00 0x01 Software set and reset 0x00 0x00 0x01 0x00 0x09 0x20 These two resets are staggered in order to minimize strain on external power supply.0x09 0x80 0x09 0x00 0x08 0x01 Internal memory reset (set and reset) 0x08 0x00 0x05 0x40 Select ANALOG page 0x47 0x80 Analog reset (set and reset) 0x47 0x00 ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 www.ti.com

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8.3.1.2 STEP 2: Device Configuration

In this step, the operating mode and digital features (DDC, test pattern) are configured. Table 8-5. Register Programming Sequence for Device Configuration ADDRESS DATA DESCRIPTION 0x05 0x20 Select CALIBRATION page 0x34 0x03 Select 2x averaging (1x AVG: 0x01, 4x AVG: 0x07) 0x05 0x02 Select DIGITAL page 0x2C 0x01 Select DDC Bypass mode 0x2D 0x00 No decimation, step can be skipped 0x2E 0x0B Select 2x averaging (1x: 0x09, 4x: 0x0D) 0x23C 0x07 Set register to 0x07 0x33 0x10 Set register to 0x10 0x2F 0x11 Set register to 0x11 (1x: 0x11, 4x: 0xE1) 0x30 0x11 Set register to 0x11 (1x: 0x11, 4x: 0xE1) 0x05 0x40 Select ANALOG page 0x7B/8B 0x00 Select internal input termination (0x00 = 100 ohm) 0xA8 0x00 DITHER AMP1: 3 = 0x80, 0 = 0x00 0xCD 0x00 DITHER AMP2: -4 = 0x40, 0 = 0x00 0x04 0x01 0x20 0x04 0x91 0x40 0xAF 0x10 0xB1 0x00 Sets dither divider. 0x00 = /50 0xB2 0x00 0xAF 0x18 0xAF 0x10 0x10 = dither ENABLED, 0x90 = dither DISABLED 0x04 0x01 0x20 0x00 0x04 0x00 0x05 0x02 0x363 0x01 0x05 0x08 Select DDCA page, load non linearity correction (NLC) trims 0x224 0x00 0x223 0x00 0x21D 0x00 if FS > 2.85 GSPS 0x00, else 0x14 0x21E 0x01 if FS > 2.85 GSPS 0x00, else 0x11 0x205 0x03 0x204 0xFF 0x21A 0x3C 0x31C 0x3E 0x325 0x00 0x325 0x01 0x325 0x00 0x21C 0x00 Nyquist zone 1: 0x00, other Nyquist zone 0x02 0x225 0x00 0x225 0x01 www.ti.com ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 105 Product Folder Links: ADC32RF54 ADC32RF55

Table 8-5. Register Programming Sequence for Device Configuration (continued) ADDRESS DATA DESCRIPTION 0x225 0x00 0x05 0x10 Select DDCB page, load non linearity correction (NLC) trims 0x224 0x00 0x223 0x00 0x21D 0x00 if FS > 2.85 GSPS 0x00, else 0x14 0x21E 0x01 if FS > 2.85 GSPS 0x00, else 0x11 0x205 0x03 0x204 0xFF 0x21A 0x3C 0x21C 0x00 Nyquist zone 1: 0x00, other Nyquist zone 0x02 0x31C 0x3E 0x325 0x00 0x325 0x01 0x325 0x00 0x225 0x00 0x225 0x01 0x225 0x00 0x05 0x08 0x20 0x02 OVR MUX EN 0x203 0x30 0x303 0x30 0x180 0x30 ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 www.ti.com

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8.3.1.3 STEP 3: JESD Interface Configuration (1)

In this step, the JESD204B digital interface and the parameters are configured. Table 8-6. Register Programming Sequence for JESD204B Interface Configuration ADDRESS DATA DESCRIPTION 0x05 0x02 Select DIGITAL page 0x81 0x00 Set register to 0x00 0x80 0xF0 Set register to 0xF0 0x7F 0xFF Set register to 0xFF 0x7E 0xFF Set register to 0xFF 0x7D 0xFF Set register to 0xFF 0x7C 0xFF Set register to 0xFF 0x7B 0x3B Set register to 0x3B 0x7A 0x28 Set register to 0x28 0x79 0x51 Set register to 0x51 0x78 0x40 Set register to 0x40 0x05 0x04 Select JESD page 0x23 0x03 Set register to 0x03 0x29 0xFF Set register to 0xFF 0x20 0x0F Select K (0x0F: K=15) 0x21 0x01 SYSREF mode 0x22 0x01 Select LMFS configuration (LMFS = 8-2-2-4) 0x24 0x00 Select DDC CLK DIV 0x25 0x00 Select JESD TX CLK DIV 0x26 0x00 0x27 0x02 Select CLK BAL EN for LMFS = 8-2-2-4 0x53 0x80 Output scrambler EN/DIS (SCR EN) 0x5C 0x01 M-1 in ILA (M=2) 0x5D 0x0F K-1 in ILA (K=15) 0x6E 0x11 0xA0 0x00 Select JESD PLL INPUT divider 1/2/30xA1 0x00 0xA2 0x00 0x9F 0x00 Select JESD PLL setting 0x2A 0x0C 0x23 0x02 JESD INIT toggle 0x23 0x00

8.3.1.4 STEP 4: SYSREF Synchronization

After device and JESD204B interface configuration a synchronization using external SYSREF is necessary. Table 8-7. Device Synchronization Using External SYSREF ADDRESS DATA DESCRIPTION 0x05 0x02 Select DIGITAL page 0x236 0x02 Enable internal SYSREF input and clear SYSREF pulse counter 0x236 0x03 Starts SYSREF counter www.ti.com ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 107 Product Folder Links: ADC32RF54 ADC32RF55

8.3.1.5 STEP 5: JESD Interface Configuration (2)

Some registers of the JESD204B interface need to be set after the first SYSREF. Table 8-8. Register Programming Sequence for JESD204B Interface Configuration ADDRESS DATA DESCRIPTION 0x05 0x04 Select JESD page 0x29 0x00 0x84 0x00 JESD PLL factor

8.3.1.6 STEP 6: Analog Trim Settings

The following registers need to be set for best analog performance. The register write order is all writes in first 2 columns before moving to the next set of address/data in middle columns, and so on. Table 8-9. Analog Trim Setting Registers ADDR DATA ADDR DATA COMMENT ADDR DATA COMMENT 0x05 0x40 0x3D 0x06 Only for FS> 2.9 GSPS 0x56 0x03 0xE8 0xF0 0x104 0x60 0x56 0x07 0xE9 0x01 0x3B 0x0C Only for FS < 2.9 GSPS 0x56 0x0F 0x4B 0x1F 0xA8 0x18 Only for 1x AVG 0x6E 0x08 0x5B 0x01 0xA8 0x00 Only for 2x/4x AVG, FS<1.1 GSPS 0x102 0x02 0xEA 0x00 0xA8 0x08 Only for 2x/4x AVG, FS=1.1-1.8 GSPS 0x103 0xD9 0xEB 0x03 0xA8 0x60 Only for 2x/4x AVG, FS=1.85-2.6 GSPS 0xA7 0x00 0x95 0x00 0xA8 0x70 Only for 2x/4x AVG, FS=2.6-3.0 GSPS 0xA6 0x08 0xFC 0x28 0xCD 0x00 0x05 0x20 0xE0 0x8E 0xCE 0x00 0xC9 0x09 0xE1 0x03 0x100 See Table 8-10 for sample rate dependent trim registers 0x102 0xFE 0x4C 0x40 0x101 0x103 0x03 0x4E 0x01 0x104 0x104 0xD4 0x4E 0x00 0x105 0x105 0x03 0xA1 0x01 0x107 0x10 0x106 0xFE 0xF8 0x00 0x05 0x20 0x107 0x03 0x31 0x20 0x30 0xE8 0x108 0xBC 0xFD 0x1C 0x31 0xFF 0x109 0x1A 0xAA 0x02 0x30 0x08 0x101 0x01 0x4D 0x80 0x31 0x80 0x159 0x63 0xB3 0x30 0x32 0x03 0x05 0x40 0x64 0x10 0x05 0x02 0x31 0x00 0x62 0x12 0x243 0x02 0x4D 0x00 0xFE 0x80 0x05 0x20 0x62 0x10 0xFC 0x28 0x36 0x04 0x56 0x0E 0xFF 0x14 0x1F8 0x01 0x56 0x0C 0x106 0x00 0x1FC 0x0A 0x56 0x08 0x107 0x00 0x1F0 0x20 0x56 0x00 0x1F1 0x0C 0x6E 0x00 0x05 0x40 0xF8 0x06 ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 www.ti.com

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Table 8-9. Analog Trim Setting Registers (continued) ADDR DATA ADDR DATA COMMENT ADDR DATA COMMENT 0x39 0x40 0x102 0x42 Only for FS> 2.9 GSPS 0x56 0x01 Table 8-10. Sample rate dependent trim registers FS (GSPS) 0x100 0x101 0x104 0x105 0.6-0.7 0x48 0x00 0x01 0x01 0.7-0.9 0xC8 0x01 0x81 0x00 0.9-1.1 0x48 0x01 0x81 0x00 1.1-1.3 0xC8 0x00 0x81 0x00 1.3-1.5 0x48 0x00 0x81 0x00 1.5-1.7 0xC8 0x01 0x01 0x00 1.7-1.9 0x48 0x01 0x01 0x00 1.9-2.1 0xC8 0x00 0x01 0x00 2.1-2.3 0x48 0x00 0x01 0x00 2.3-2.5 0xC8 0x01 0x81 0x03 2.5-2.7 0x48 0x01 0x81 0x03 2.7-2.9 0xC8 0x00 0x81 0x0 2.9-3.0 0x48 0x00 0xE1 0x03 www.ti.com ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 109 Product Folder Links: ADC32RF54 ADC32RF55

8.3.1.7 STEP 7: Calibration Configuration

The following registers configure the internal foreground calibration. The register write order is all writes in first 2 columns before moving to the next set of address/data in middle columns, and so on. Table 8-11. Calibration Register Settings ADDRESS DATA ADDRESS DATA ADDRESS DATA 0x05 0x40 0xFC 0x13 0x47 0xC7 0x68 0xC0 0xFD 0x08 0x46 0x13 0x69 0xFF 0x36 0x04 0xFC 0x13 0x05 0x20 0x36 0x05 0xFD 0x00 0x46 0x03 0x36 0x04 0x36 0x04 0x47 0xC2 0xFC 0x13 0x36 0x05 0x46 0x13 0xFD 0x0A 0x36 0x04 0x1AE 0x00 0x36 0x04 0xFC 0x13 0x1E6 0x1C 0x36 0x05 0xFD 0x02 0x1AE 0x00 0x36 0x04 0x36 0x04 0x1E6 0x1C 0xFC 0x13 0x36 0x05 0x1E9 0x08 0xFD 0x0C 0x36 0x04 0x1E9 0xA8 0x36 0x04 0xFC 0x13 0x1E8 0x02 0x36 0x05 0xFD 0x04 0x1E8 0x06 0x36 0x04 0x36 0x04 0x1E8 0x04 0xFC 0x13 0x36 0x05 0x1E8 0x00 0xFD 0x0E 0x36 0x04 0x1E9 0xA0 0x36 0x04 0xFC 0x13 0x1F0 0x28 0x36 0x05 0xFD 0x06 0x1F1 0x0C 0x36 0x04 0x36 0x04 0x1F0 0x2A 0xFC 0x03 0x36 0x05 0x1F0 0x2E 0x36 0x04 0x36 0x04 0x1F0 0x2C 0x46 0x03 0xFC 0x13 0x1F0 0x28 0x47 0xC0 0xFD 0x08 0x1F0 0x08 0x46 0x13 0x36 0x04 0x1F0 0x18 0x46 0x03 0x36 0x05 0x1F0 0x38 0x47 0xC7 0x36 0x04 0x1F1 0x0C 0x46 0x13 0xFC 0x13 0x1F0 0x3A 0x1AE 0x00 0xFD 0x0A 0x1F0 0x3E 0x1E6 0x1C 0x36 0x04 0x1F0 0x3C 0x1AE 0x00 0x36 0x05 0x1F0 0x38 0x1E6 0x1C 0x36 0x04 0x1F0 0x18 0x1E9 0xA8 0xFC 0x13 0x1F0 0x10 0x1E8 0x02 0xFD 0x0C 0x1AE 0x00 0x1E8 0x06 0x36 0x04 0x1E6 0x1C 0x1E8 0x04 0x36 0x05 0x1AE 0x00 0x1E8 0x00 0x36 0x04 0x1E6 0x1C 0x1E9 0xA0 0xFC 0x13 0x47 0xC0 0x1F0 0x18 0xFD 0x0E 0x46 0x03 0x1F0 0x08 0x36 0x04 0x47 0xC2 0x1F0 0x28 0x36 0x05 0x46 0x13 0x1F1 0x0C 0x36 0x04 ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 www.ti.com

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Table 8-11. Calibration Register Settings (continued) ADDRESS DATA ADDRESS DATA ADDRESS DATA 0xFC 0x13 0x1F0 0x2A 0xFC 0x03 0xFD 0x00 0x1F0 0x2E 0x36 0x04 0x36 0x04 0x1F0 0x2C 0x46 0x03 0x36 0x05 0x1F0 0x28 0x47 0xC0 0x36 0x04 0x1F0 0x08 0x46 0x13 0xFC 0x13 0x1F0 0x18 0x05 0x40 0xFD 0x02 0x1F0 0x38 0x68 0x40 0x36 0x04 0x1F1 0x0C 0x69 0xFD 0x36 0x05 0x1F0 0x3A 0x69 0xF5 0x36 0x04 0x1F0 0x3E 0x69 0xD5 0xFC 0x13 0x1F0 0x3C 0x69 0x55 0xFD 0x04 0x1F0 0x38 0x68 0x00 0x36 0x04 0x1F0 0x18 0x69 0x54 0x36 0x05 0x1F0 0x10 0x69 0x50 0x36 0x04 0x1AE 0x00 0x69 0x40 0xFC 0x13 0x1E6 0x1C 0x69 0x00 0xFD 0x06 0x1AE 0x00 0x93 0x0E 0x36 0x04 0x1E6 0x1C 0x94 0x70 0x36 0x05 0x47 0xC0 0x94 0x77 0x36 0x04 0x46 0x03

8.3.1.8 STEP 8: SYSREF Synchronization

After setting the analog trim registers, a synchronization using external SYSREF is necessary. Table 8-12. Device Synchronization Using External SYSREF ADDRESS DATA DESCRIPTION 0x05 0x02 Select DIGITAL page 0x236 0x02 Enable internal SYSREF input and clear SYSREF pulse counter 0x236 0x03 Starts SYSREF counter

8.3.1.9 STEP 9: Run Power up Calibration

The following registers start the power up foreground calibration. The register write order is all writes in first 2 columns before moving to the next set of address and/or data in middle columns, and so on. Table 8-13. Calibration Register Settings ADDRESS DATA ADDRESS DATA ADDRESS DATA 0x05 0x20 0x93 0x20 0x58 0x30 0xE7 0x01 0x20 0x00 0x58 0x20 0x174 0x02 0x05 0x00 0x58 0x00 0x178 0x00 0x04 0x01 0x89 x020 0x17C 0x22 0x20 0x1F 0x95 0x00 0x3C 0x00 0x93 0x20 0x96 0x00 0xFC 0x03 0x04 0x01 0x97 0x10 0xFD 0x00 0x20 0x00 0x9C 0x00 0x154 0x1C 0x04 0x00 0x57 0x1E 0x155 0x03 0x05 0x20 0x46 0x02 0xFC 0x03 0xC0 0x7C 0x45 0x8A www.ti.com ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 111 Product Folder Links: ADC32RF54 ADC32RF55

Table 8-13. Calibration Register Settings (continued) ADDRESS DATA ADDRESS DATA ADDRESS DATA 0xEE 0x26 0xBC 0x3C 0x45 0x0A 0xEF 0x02 0xC9 0x01 Delay 3 seconds 0x18C 0x88 0xC9 0x00 0x89 0x00 0xAE 0xC8 0xC9 0x06 0x95 0x00 0xAF 0x00 0x38 0x01 0x96 0x00 0xB0 0x4C 0x110 0x10 0x97 0x00 0xB1 0x3F 0x111 0x42 0x9C 0x00 0x4F 0x46 0x112 0xA6 0x57 0x1A 0x50 0x2C 0x112 0xD6 0x57 0x3A 0x51 0x05 0x113 0xBB 0x57 0x7A 0x154 0x7C 0x113 0xDB 0x57 0xFA 0x158 0x7C 0x114 0xF4 0x58 0x01 0x159 0x6F 0x114 0x64 0x58 0x03 0x15C 0x7C 0x115 0x0E 0x58 0x07 0x15D 0x3F 0x115 0xFE 0x58 0x0F 0x160 0x7C 0x116 0x0D 0x58 0x1F 0x161 0x3F 0x116 0xDD 0x58 0x3F 0x164 0x7C 0x117 0x0D 0x45 0x8A 0x165 0x4F 0x117 0xDD 0x45 0x0A 0x16C 0x7C 0x46 0x03 Delay 3 seconds 0x1B0 0x1C 0x3D 0x00 0x47 0xC0 0x1B1 0x5F 0x45 0x0A 0x46 0x03 0x1D8 0x1C 0x46 0x02 0x47 0xC0 0x1D9 0xAF 0x64 0x4A 0x05 0x80 0xB2 0x1F 0x65 0x05 0x20 0x1F 0xB5 0x7F 0x68 0x28 0x9D 0x05 0x165 0xFF 0x69 0x5E 0x9E 0x08 0x38 0x01 0x6A 03D 0x8B 0x40 0xA4 0x30 0x6B 0x8F 0x20 0x00 0xC5 0x7F 0x6C 0x44 0x05 0x00 0xA8 0x00 0x57 0xDA 0x04 0x01 0xA2 0x63 0x57 0x9A 0x20 0x1F 0xA3 0x00 0x57 0x1A 0x9D 0x05 0xAD 0x02 0x58 0x3E 0x9E 0x08 0x05 0x80 0x58 0x3C 0x8B 0x40 0x20 0x1F 0x58 0x38

8.3.1.10 STEP 10: JESD Interface Synchronization

The JESD interface can be synchronized using SPI writes or the GPIO1 pin. Table 8-14. JESD Interface Synchronization Using SPI Writes ADDRESS DATA DESCRIPTION 0x05 0x04 Select JESD page 0x21 0x41 Configure ADC to control SYNC using SPI writes 0x21 0x61 Configure JESD interface to send K28.5 characters for receiver synchronization ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 www.ti.com

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Table 8-14. JESD Interface Synchronization Using SPI Writes (continued) ADDRESS DATA DESCRIPTION 0x21 0x41 Configure JESD interface to send normal ADC data

8.4 Power Supply Recommendations

The ADC32RF5x requires four different power-supplies. The AVDD18, AVDD12 and CLKVDD rail provides power for the internal analog and clocking circuits of the ADC. The DVDD rail powers the digital logic (including averaging and decimation filter) and the JESD204B digital interface. Power sequencing is required as shown in Initialization Set Up . The AVDD18, AVDD12 and especially the CLKVDD power supply must be low noise in order to achieve data sheet performance. For applications operating near DC, the 1/f noise contribution of the power supply needs to be considered as well. Power supply decoupling capacitors (0.1 µF) as close to the pins as possible on the top layer are recommended. Frequency of Signal (MHz) PSRR (dB) 0.01 0.1 1 10 100 500 AVDD12 AVDD18 CLKVDD Figure 8-5. Power Supply Rejection Ratio (PSRR) vs Frequency The recommended power supply architecture for a low noise design is to first use a high-efficiency step down switching regular, followed by a second stage of regulation using a low noise LDO for each power rail as shown in Figure 8-6. This provides additional switching noise reduction and improved voltage accuracy. TI WEBENCH ® Power Designer can be used to select and design the individual power-supply elements. Recommended switching regulators for the first stage include the LMS3635, and similar devices. Recommended low dropout (LDO) linear regulators include the TPS7A8400, and similar devices. www.ti.com ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 113 Product Folder Links: ADC32RF54 ADC32RF55

47uF 10uF 10uF 0.1uF 10uF 10uF 0.1uF 1.7V 1.2V FB = Ferrite bead filter GND GND DC/DC Regulator5V-12V LDO GND AVDD18 FB FB 47uF 47uF 10uF 10uF 0.1uF 2.3V 1.8V GND GND LDO 47uF 1.2V GND GND DVDD FB 10uF 10uF 0.1uF47uF 1.2V GND LDO Figure 8-6. Power Supply Design Example AVDD12 or CLKVDD should not be shared with the DVDD in order to prevent digital switching noise from coupling into the analog domain. ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 www.ti.com

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8.5 Layout

8.5.1 Layout Guidelines

There are several critical signals which require specific care during board design: 1. Analog input and clock signals

Traces should be as short as possible and vias should be avoided where possible to minimize impedance discontinuities.
Traces should be routed using loosely coupled 100-Ω differential traces.
Differential trace lengths should be matched as close as possible to minimize phase imbalance and HD2 degradation. 2. Digital JESD204B output interface
Traces should be routed using tightly coupled 100-Ω differential traces. 3. Power and ground connections
Provide low resistance connection paths to all power and ground pins.
Use power and ground planes instead of traces.
Avoid narrow, isolated paths which increase the connection resistance.
Use a signal/ground/power circuit board stackup to maximize coupling between the ground and power plane.

8.5.2 Layout Example

The following screen shot shows the top layer of the ADC32RF5x EVM.

The input signal traces are routed as differential signals on the top layer avoiding vias. Care is taken to maintain symmetry between positive and negative input with matched trace length in order to minimize phase imbalance. Figure 8-7 shows the layout example for 1x and 2x averaging configuration Figure 8-8 shows the layout example for 4x averaging configuration
JESD204B output interface lanes are routed differential and length matched
Bypass caps are close to the power pins on the top layer avoiding vias. JESD204B Lanes Tightly coupled traces Analog Inputs on top layer – symmetric diﬀerenal roung Figure 8-7. Layout example: top layer of ADC32RF5x EVM www.ti.com ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 115 Product Folder Links: ADC32RF54 ADC32RF55

Analog Inputs on top layer – Symmetric, di eren al rou ng to

2 ADC inputs

Figure 8-8. Layout example for 4x AVG: ADC32RF5x EVM ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 www.ti.com

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9 Device and Documentation Support

9.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

9.2 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

9.3 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

9.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

9.5 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com ADC32RF54, ADC32RF55 SBAS500A – JUNE 2022 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 117 Product Folder Links: ADC32RF54 ADC32RF55

www.ti.com 22-Dec-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples ADC32RF55IRTD ACTIVE VQFN RTD 64 168 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 AZ32RF55 Samples ADC32RF55IRTDT ACTIVE VQFN RTD 64 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 AZ32RF55 Samples PADC32RF54RTD ACTIVE VQFN RTD 64 250 TBD Call TI Call TI -40 to 85 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1

www.ti.com 22-Dec-2022 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-Dec-2022 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 23-Dec-2022 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADC32RF55IRTDT VQFN RTD 64 250 213.0 191.0 55.0 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C PIN 1 ID 6.866 0.1 0.975 0.875 7.5 64X 0.5 4X (45 X0.42) ( 8.71) 5.566 0.1 64X 0.3 0.2 64X 0.5 0.3 B 9.1 8.9 A 9.1 8.9 (0.2) 4226371/A 11/2020 VQFN - 0.9 mm max heightRTD0064N PLASTIC QUAD FLATPACK - NO LEAD NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. 3217 64 49

0.1 C B A

0.05 CPIN 1 ID

0.08 C SEATING PLANE SCALE 1.600

www.ti.com EXAMPLE BOARD LAYOUT 64X (0.6) 64X (0.25) (5.566) (8.8) 60X (0.5) 6.866 (0.63) (1.26) TYP (1.33) TYP (1.17) TYP (R0.1) TYP VIA

0.07 MAX

ALL AROUND 0.07 MIN ALL AROUND (8.8) (R0.05) TYP 4226371/A 11/2020 VQFN - 0.9 mm max heightRTD0064N PLASTIC QUAD FLATPACK - NO LEAD SYMM SYMM LAND PATTERN EXAMPLE SCALE:8X 17 32 4964 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. METAL SOLDER MASK OPENING SOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN (1.26) TYP (1.26) TYP (1.33) TYP(0.665) 20X (1.13) 20X (1.06) 64X (0.6) 64X (0.25) 60X (0.5) (8.8) (8.8) 4226371/A 11/2020 VQFN - 0.9 mm max heightRTD0064N PLASTIC QUAD FLATPACK - NO LEAD NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SYMM SYMM METAL TYP SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 65: 63% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:10X 17 32 4964

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Product Information

ADC32RF55IRTD specifications and overview.

Summary

ADC32RF5x Dual Channel 14-bit 2.6 to 3-GSPS RF Sampling Data Converter REVISED DECEMBER 2022

Description

ADC32RF5x Dual Channel 14-bit 2.6 to 3-GSPS RF Sampling Data Converter REVISED DECEMBER 2022

Source title ADC32RF55IRTD Datasheet(PDF) - Texas Instruments

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