ADC32RF45 TI | Alldatasheet
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Technical content
ADCADCADCINAP, INAM SYSREFP, SYSREFM CLKINP, CLKINM PLL Buffer INBP, INBM Buffer DB[1:0]P, DB[1:0]M DA[1:0]P, DA[1:0]M DA[3:2]P, DA[3:2]M DB[3:2]P, DB[3:2]M GPIO[4:1] ADC N N NCO CTRL SYNCBP, SYNCBM JESD204B Interface NCO FOVR FOVR NCO NCO NCO ADC Digital Block Interleave Correction Power Detection Digital Block Interleave Correction Power Detection Copyright © 2016, Texas Instruments Incorporated Clock Divider SPI and Control CM N N RESET SCLK SDATA SEN PDN SDO Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community Reference Design An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. ADC32RF45 SBAS747C –MAY 2016–REVISED DECEMBER 2016 ADC32RF45Dual-Channel,14-Bit,3.0-GSPS,Analog-to-DigitalConverter
1 Features
1• 14-Bit, Dual-Channel, 3.0-GSPS ADC
- Noise Floor: –155 dBFS/Hz
- RF Input Supports Up to 4.0 GHz
- Aperture Jitter: 90 fS
- Channel Isolation: 95 dB at fIN = 1.8 GHz
- Spectral Performance (fIN = 900 MHz, –2 dBFS): – SNR: 60.9 dBFS – SFDR: 67-dBc HD2, HD3 – SFDR: 77-dBc Worst Spur
- Spectral Performance (fIN = 1.78 GHz, –2 dBFS): – SNR: 58.8 dBFS – SFDR: 66-dBc HD2, HD3 – SFDR: 75-dBc Worst Spur
- On-Chip Digital Down-Converters: – Up to 4 DDCs (Dual-Band Mode) – Up to 3 Independent NCOs per DDC
- On-Chip Input Clamp for Overvoltage Protection
- Programmable On-Chip Power Detectors with Alarm Pins for AGC Support
- On-Chip Dither
- On-Chip Input Termination
- Input Full-Scale: 1.35 VPP
- Support for Multi-Chip Synchronization
- JESD204B Interface: – Subclass 1-Based Deterministic Latency – 4 Lanes Per Channel at 12.5 Gbps
- Power Dissipation: 3.2 W/Ch at 3.0 GSPS
- 72-Pin VQFN Package (10 mm × 10 mm)
2 Applications
- Multi-Band, Multi-Mode 2G, 3G, 4G Cellular Receivers
- Phased Array Radars
- Electronic Warfare
- Cable Infrastructure
- Broadband Wireless
- High-Speed Digitizers
- Software-Defined Radios
- Communications Test Equipment
- Microwave and Millimeter Wave Receivers
3 Description
The ADC32RF45 device is a 14-bit, 3.0-GSPS, dual- channel, analog-to-digital converter (ADC) that supports RF sampling with input frequencies up to 4 GHz and beyond. Designed for high signal-to-noise ratio (SNR), the ADC32RF45 delivers a noise spectral density of –155 dBFS/Hz as well as dynamic range and channel isolation over a large input frequency range. The buffered analog input with on- chip termination provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy. Each ADC channel can be connected to a dual-band, digital down-converter (DDC) with up to three independent, 16-bit numerically-controlled oscillators (NCOs) per DDC for phase-coherent frequency hopping. Additionally, the ADC is equipped with front- end peak and RMS power detectors and alarm functions to support external automatic gain control (AGC) algorithms. The ADC32RF45 supports the JESD204B serial interface with subclass 1-based deterministic latency using data rates up to 12.5 Gbps with up to four lanes per ADC. The device is offered in a 72-pin VQFN package (10 mm × 10 mm) and supports the industrial temperature range (–40°C to +85°C). Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) ADC32RF45 VQFN (72) 10.00 mm × 10.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Block Diagram
SBAS747C –MAY 2016–REVISED DECEMBER 2016 www.ti.com Product Folder Links: ADC32RF45 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Table of Contents
12.2 Receiving Notification of Documentation
13 Mechanical, Packaging, and Orderable
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (June 2016) to Revision C Page
72 DB2P19GPIO1
71 DB2M20GPIO2
70 DVDD21GPIO3
69 DB1P22CM
68 DB1M23GND
67 GND24AVDD19
66 DB0P25AVDD
65 DB0M26GND
64 DVDD27CLKINP
63 GPIO428CLKINM
62 DA0M29GND
61 DA0P30AVDD
60 GND31AVDD19
59 DA1M32GND
58 DA1P33SYSREFP
57 DVDD34SYSREFM
56 DA2M35SYNCBP
55 DA2P36SYNCBM
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5 Pin Configuration and Functions
NAME NO. I/O DESCRIPTION INPUT, REFERENCE INAM 41 I Differential analog input for channel A INAP 42 INBM 14 I Differential analog input for channel B INBP 13 CM 22 O Common-mode voltage for analog inputs, 1.2 V
SBAS747C –MAY 2016–REVISED DECEMBER 2016 www.ti.com Product Folder Links: ADC32RF45 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Pin Functions (continued) NAME NO. I/O DESCRIPTION CLOCK, SYNC CLKINM 28 I Differential clock input for the analog-to-digital converter (ADC). This pin has an internal differential 100-Ω termination.CLKINP 27 SYSREFM 34 I External sync input. This pin has an internal, differential 100-Ω termination and requires external biasing.SYSREFP 33 GPIO1 19 I/O GPIO control pin; configured through the SPI. This pin can be configured to be either a fast overrange output for channel A and B, a fast detect alarm signal from the peak power detect, or a numerically-controlled oscillator (NCO) control. GPIO 4 (pin 63) can also be configured as a single-ended SYNCB input. GPIO2 20 GPIO3 21 GPIO4 63 CONTROL, SERIAL RESET 48 I Hardware reset; active high. This pin has an internal 20-kΩ pulldown resistor. SCLK 6 I Serial interface clock input. This pin has an internal 20-kΩ pulldown resistor. SDIN 5 I/O Serial interface data input. This pin has an internal 20-kΩ pulldown resistor. SDIN can be data input in 4-wire mode, data input and output in 3 wire-mode. SEN 7 I Serial interface enable. This pin has an internal 20-kΩ pullup resistor to DVDD. SDOUT 11 O Serial interface data output in 4-wire mode PDN 50 I Power down; active high. This pin can be configured through an SPI register setting and can be configured to a fast overrange output channel B through the SPI. This pin has an internal 20-kΩ pulldown resistor. DATA INTERFACE DA0M 62 O JESD204B serial data output for channel A DA0P 61 DA1M 59 DA1P 58 DA2M 56 DA2P 55 DA3M 54 DA3P 53 DB0M 65 O JESD204B serial data output for channel B DB0P 66 DB1M 68 DB1P 69 DB2M 71 DB2P 72 DB3M 1 DB3P 2 SYNCBM 36 I Synchronization input for the JESD204B port. This pin has an LVDS or 1.8-V logic input, an optional on-chip 100-Ω termination, and is selectable through the SPI. This pin requires external biasing.SYNCBP 35 POWER SUPPLY AVDD19 10, 16, 24, 31, 39, 45 I Analog 1.9-V power supply AVDD 9, 12, 15, 17, 25, 30, 38, 40, 43, 44, 46 I Analog 1.15-V power supply DVDD 4, 8, 47, 51, 57, 64, 70 I Digital 1.15 V-power supply, including the JESD204B transmitter GND 3, 18, 23, 26, 29, 32, 37, 49, 52, 60, 67 I Ground; shorted to thermal pad inside device
www.ti.com SBAS747C –MAY 2016–REVISED DECEMBER 2016 Product Folder Links: ADC32RF45 Submit Documentation FeedbackCopyright © 2016, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Supply voltage range AVDD19 –0.3 2.1 VAVDD –0.3 1.4 DVDD –0.3 1.4 Voltage applied to input pins INAP, INAM and INBP, INBM –0.3 AVDD19 + 0.3 V CLKINP, CLKINM –0.3 AVDD + 0.6 SYSREFP, SYSREFM, SYNCBP, SYNCBM –0.3 AVDD + 0.6 SCLK, SEN, SDIN, RESET, PDN, GPIO1, GPIO2, GPIO3, GPIO4 –0.2 AVDD19 + 0.2 Voltage applied to output pins –0.3 2.2 V Temperature Operating free-air, TA –40 85 Storage, Tstg –65 150 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.2 ESD Ratings
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500 (1) Prolonged use above this junction temperature may increase the device failure-in-time (FIT) rate.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Supply voltage AVDD19 1.8 1.9 2.0 VAVDD 1.1 1.15 1.25 DVDD 1.1 1.15 1.2 Temperature Operating free-air, TA –40 85 Operating junction, TJ 105(1) 125 (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
6.4 Thermal Information
THERMAL METRIC(1) ADC32RF45 UNITRMP (VQFN)
72 PINS
RθJA Junction-to-ambient thermal resistance 21.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 4.4 °C/W RθJB Junction-to-board thermal resistance 2.0 °C/W ψJT Junction-to-top characterization parameter 0.1 °C/W ψJB Junction-to-board characterization parameter 2.0 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 0.2 °C/W
SBAS747C –MAY 2016–REVISED DECEMBER 2016 www.ti.com Product Folder Links: ADC32RF45 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated (1) See the Power Consumption in Different Modes section for more details. (2) Full-scale signal is applied to the analog inputs of all active channels. (3) When used in dc-coupling mode, the common-mode voltage at the analog inputs should be kept within VCM ±25 mV for best performance. (4) Crosstalk is measured with a –2-dBFS input signal on aggressor channel and no input on the victim channel. (5) See Figure 59.
6.5 Electrical Characteristics
typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient temperature range of –40°C to +85°C; and ADC sampling rate = 3 GHz, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD = 1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER CONSUMPTION(1) (Dual-Channel Operation, Both Channels A and B are Active; DDC Bypass Mode(2)) IAVDD19 1.9-V analog supply current 12-bit, bypass mode, fS = 3.0 GSPS 1792 1965 mA IAVDD 1.15-V analog supply current 12-bit, bypass mode, fS = 3.0 GSPS 972 1062 mA IDVDD 1.15-V digital supply current 12-bit, bypass mode, fS = 3.0 GSPS 1748 1892 mA PD Power dissipation 12-bit, bypass mode, fS = 3.0 GSPS 6.53 7.01 W Global power-down power dissipation 360 mW ANALOG INPUTS Resolution 14 Bits Differential input full-scale 1.35 VPP VIC Input common-mode voltage 1.2(3) V RIN Input resistance Differential resistance at dc 65 Ω CIN Input capacitance Differential capacitance at dc 2 pF VCM common-mode voltage output 1.2 V Analog input bandwidth (–3-dB point) ADC driven with 50-Ω source 3200 MHz ISOLATION Crosstalk isolation between channel A and channel B(4) fIN = 100 MHz 100 dBc fIN = 900 MHz 99 fIN = 1800 MHz 95 fIN = 2700 MHz 86 fIN = 3500 MHz 85 CLOCK INPUT(5) Input clock frequency 1.5 3 GHz Differential (peak-to-peak) input clock amplitude 0.5 1.5 2.5 VPP Input clock duty cycle 45% 50% 55% Internal clock biasing 1.0 V Internal clock termination (differential) 100 Ω
www.ti.com SBAS747C –MAY 2016–REVISED DECEMBER 2016 Product Folder Links: ADC32RF45 Submit Documentation FeedbackCopyright © 2016, Texas Instruments Incorporated (1) Minimum values are specified at AOUT = –3 dBFS. (2) Output amplitude, AOUT, refers to the signal amplitude in the ADC digital output that is same as the analog input amplitude, AIN, except when the digital gain feature is used. If digital gain is G, then AOUT = G + AIN. (3) The ADC internal resistance = 65 Ω, the driving source resistance = 50 Ω. (4) The minimum value of HD2 is specified by bench characterization.
6.6 AC Performance Characteristics
typical values specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient temperature range of –40°C to +85°C; and ADC sampling rate = 3 GHz, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD = 1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted) PARAMETER TEST CONDITIONS MIN(1) NOM MAX UNIT SNR Signal-to-noise ratio fIN = 100 MHz, AOUT = –2 dBFS 62.7 dBFS fIN = 900 MHz, AOUT = –2 dBFS 60.9 fIN = 1850 MHz, AOUT = –2 dBFS 55.4 58.8 fIN = 2100 MHz, AOUT = –2 dBFS 58.2 fIN = 2600 MHz, AOUT = –2 dBFS 56.8 fIN = 3500 MHz, AOUT(2) = –3 dBFS with 2-dB gain 54.2 NSD Noise spectral density averaged across the Nyquist zone fIN = 100 MHz, AOUT = –2 dBFS 154.5 dBFS/Hz fIN = 900 MHz, AOUT = –2 dBFS 152.7 fIN = 1850 MHz, AOUT = –2 dBFS 147.2 150.6 fIN = 2100 MHz, AOUT = –2 dBFS 150.0 fIN = 2600 MHz, AOUT = –2 dBFS 148.6 fIN = 3500 MHz, AOUT (2) = –3 dBFS with 2-dB gain 146.0 Small-signal SNR fIN = 1850 MHz, AOUT = –40 dBFS 63.0 dBFS NF(3) Input noise figure fIN = 1850 MHz, AOUT = –40 dBFS 24.7 dB SINAD Signal-to-noise and distortion ratio fIN = 100 MHz, AOUT = –2 dBFS 61.8 dBFS fIN = 900 MHz, AOUT = –2 dBFS 60.2 fIN = 1850 MHz, AOUT = –2 dBFS 58.2 fIN = 2100 MHz, AOUT = –2 dBFS 57.5 fIN = 2600 MHz, AOUT = –2 dBFS 56.0 fIN = 3500 MHz, AOUT (2) = –3 dBFS with 2-dB gain 53.6 ENOB Effective number of bits fIN = 100 MHz, AOUT = –2 dBFS 10.0 Bits fIN = 900 MHz, AOUT = –2 dBFS 9.7 fIN = 1850 MHz, AOUT = –2 dBFS 9.4 fIN = 2100 MHz, AOUT = –2 dBFS 9.3 fIN = 2600 MHz, AOUT = –2 dBFS 9.0 fIN = 3500 MHz, AOUT (2) = –3 dBFS with 2-dB gain 8.6 SFDR Spurious-free dynamic range fIN = 100 MHz, AOUT = –2 dBFS 69.0 dBc fIN = 900 MHz, AOUT = –2 dBFS 67.0 fIN = 1850 MHz, AOUT = –2 dBFS 58 66.0 fIN = 2100 MHz, AOUT = –2 dBFS 65.0 fIN = 2600 MHz, AOUT = –2 dBFS 57.0 fIN = 3500 MHz, AOUT (2) = –3 dBFS with 2-dB gain 61.0 HD2(4) Second-order harmonic distortion fIN = 100 MHz, AOUT = –2 dBFS 69.0 dBc fIN = 900 MHz, AOUT = –2 dBFS 73.0 fIN = 1850 MHz, AOUT = –2 dBFS 58 66.0 fIN = 2100 MHz, AOUT = –2 dBFS 65.0 fIN = 2700 MHz, AOUT = –2 dBFS 57.0 fIN = 3500 MHz, AOUT (2) = –3 dBFS with 2-dB gain 61.0
SBAS747C –MAY 2016–REVISED DECEMBER 2016 www.ti.com Product Folder Links: ADC32RF45 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated AC Performance Characteristics (continued) typical values specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient temperature range of –40°C to +85°C; and ADC sampling rate = 3 GHz, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD = 1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted) PARAMETER TEST CONDITIONS MIN(1) NOM MAX UNIT HD3 Third-order harmonic distortion fIN = 100 MHz, AOUT = –2 dBFS 72.0 dBc fIN = 900 MHz, AOUT = –2 dBFS 67.0 fIN = 1850 MHz, AOUT = –2 dBFS 61 70.0 fIN = 2100 MHz, AOUT = –2 dBFS 80.0 fIN = 2600 MHz, AOUT = –2 dBFS 79.0 fIN = 3500 MHz, AOUT(2) = –3 dBFS with 2-dB gain 66.0 HD4, HD5 Fourth- and fifth-order harmonic distortion fIN = 100 MHz, AOUT = –2 dBFS 83.0 dBc fIN = 900 MHz, AOUT = –2 dBFS 81.0 fIN = 1850 MHz, AOUT = –2 dBFS 61 86.0 fIN = 2100 MHz, AOUT = –2 dBFS 83.0 fIN = 2600 MHz, AOUT = –2 dBFS 76.0 fIN = 3500 MHz, AOUT (2) = –3 dBFS with 2-dB gain 82.0 IL spur Interleaving spurs: fS / 2 – fIN, fS / 4 ± fIN fIN = 100 MHz, AOUT = –2 dBFS 89.0 dBc fIN = 900 MHz, AOUT = –2 dBFS 79.0 fIN = 1850 MHz, AOUT = –2 dBFS 69 82.0 fIN = 2100 MHz, AOUT = –2 dBFS 77.0 fIN = 2600 MHz, AOUT = –2 dBFS 78.0 fIN = 3500 MHz, AOUT (2) = –3 dBFS with 2-dB gain 78.0 HD2 IL Interleaving spur for HD2: fS / 2 – HD2 fIN = 100 MHz, AOUT = –2 dBFS 82.0 dBc fIN = 900 MHz, AOUT = –2 dBFS 81.0 fIN = 1850 MHz, AOUT = –2 dBFS 62 80.0 fIN = 2100 MHz, AOUT = –2 dBFS 76.0 fIN = 2600 MHz, AOUT = –2 dBFS 65.0 fIN = 3500 MHz, AOUT (2) = –3 dBFS with 2-dB gain 77.0 Worst spur Spurious-free dynamic range (excluding HD2, HD3, HD4, HD5, and interleaving spurs IL and HD2 IL) fIN = 100 MHz, AOUT = –2 dBFS 81.0 dBc fIN = 900 MHz, AOUT = –2 dBFS 77.0 fIN = 1850 MHz, AOUT = –2 dBFS 64 75.0 fIN = 2100 MHz, AOUT = –2 dBFS 75.0 fIN = 2600 MHz, AOUT = –2 dBFS 74.0 fIN = 3500 MHz, AOUT (2) = –3 dBFS with 2-dB gain 71.0 IMD3 Two-tone, third-order intermodulation distortion fIN1 = 1770 MHz, fIN2 = 1790 MHz, AOUT = –8 dBFS (each tone) 73 dBFSfIN1 = 1800 MHz, fIN2 = 2600 MHz, AOUT = –8 dBFS (each tone) 65 fIN1 = 3490 MHz, fIN2 = 3510 MHz, AOUT = –8 dBFS (each tone) with 2-dB gain 75
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6.7 Digital Requirements
typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient temperature range of –40°C to +85°C; and ADC sampling rate = 3 GHz, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD = 1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted) PARAMETER TEST CONDITIONS MIN NOM MAX UNIT DIGITAL INPUTS (RESET, SCLK, SEN, SDIN, PDN, GPIO1, GPIO2, GPIO3, GPIO4) VIH High-level input voltage 0.8 V VIL Low-level input voltage 0.4 V IIH High-level input current 50 µA IIL Low-level input current –50 µA Ci Input capacitance 4 pF DIGITAL OUTPUTS (SDOUT, GPIO1, GPIO2, GPIO3, GPIO4) VOH High-level output voltage AVDD19 –0.1 AVDD19 V VOL Low-level output voltage 0.1 V DIGITAL INPUTS (SYSREFP and SYSREFM; SYNCBP and SYNCBM; Requires External Biasing) VID Differential input voltage 350 450 800 mVPP VCM Input common-mode voltage 1.05 1.2 1.325 V DIGITAL OUTPUTS (JESD204B Interface: DA[3:0], DB[3:0], Meets JESD204B LV-0IF-11G-SR Standard) |VOD| Output differential voltage 700 mVPP |VOCM| Output common-mode voltage 450 mV Transmitter short-circuit current Transmitter pins shorted to any voltage between –0.25 V and 1.45 V –100 100 mA zos Single-ended output impedance 50 Ω Co Output capacitance Output capacitance inside the device, from either output to ground 2 pF
SBAS747C –MAY 2016–REVISED DECEMBER 2016 www.ti.com Product Folder Links: ADC32RF45 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated (1) Overall latency = latency + tPD. (2) Latency increases when the DDC modes are used; see Table 4. (3) Common-mode voltage for the SYSREF input is kept at 1.2 V.
6.8 Timing Requirements
typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient temperature range of –40°C to +85°C; and ADC sampling rate = 3 GHz, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD = 1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted) MIN NOM MAX UNIT SAMPLE TIMING Aperture delay 250 750 ps Aperture delay matching between two channels on the same device ±15 ps Aperture delay matching between two devices at the same temperature and supply voltage ±150 ps Aperture jitter, clock amplitude = 2 VPP 90 fS Latency (1)(2) Data latency, ADC sample to digital output 12-bit bypass mode, LMFS = 82820 461 Input clock cycles 14-bit bypass mode, LMFS = 8224 424 Input clock cycles Fast overrange latency, ADC sample to FOVR indication on GPIO pins 70 tPD Propagation delay time: logic gates and output buffer delay (does not change with fS) 6 ns SYSREF TIMING(3) tSU_SYSREF SYSREF setup time: referenced to clock rising edge, 3 GSPS 140 70 ps tH_SYSREF SYSREF hold time: referenced to clock rising edge, 3 GSPS 50 20 ps Valid transition window sampling period: tSU_SYSREF – tH_SYSREF, 3 GSPS 143 ps JESD OUTPUT INTERFACE TIMING UI Unit interval: 12.5 Gbps 80 100 400 ps Serial output data rate 2.5 10.0 12.5 Gbps Rise, fall times: 1-pF, single-ended load capacitance to ground 60 ps Total jitter: BER of 1E-15 and lane rate = 12.5 Gbps 25 %UI Random jitter: BER of 1E-15 and lane rate = 12.5 Gbps 0.99 %UI, rms Deterministic jitter: BER of 1E-15 and lane rate = 12.5 Gbps 9.1 %UI, pk- pk
0 V0 V
(1) VOCM is not the same as VICM. Similarly, VOD is not the same as VID. Figure 1. Logic Levels for Digital Inputs and Outputs Figure 2. SYSREF Timing Diagram
6.9 Typical Characteristics
Figure 3. FFT for 100-MHz Input Frequency Figure 4. FFT for 900-MHz Input Frequency Figure 5. FFT for 1780-MHz Input Frequency Figure 6. FFT for 2100-MHz Input Frequency Figure 7. FFT for 2600-MHz Input Frequency Figure 8. FFT for 3500-MHz Input Frequency
Figure 57. FFT in 24X Decimation (Complex Output) Figure 58. FFT in 32X Decimation (Complex Output)
7 Parameter Measurement Information
7.1 Input Clock Diagram
Figure 59 shows the input clock diagram. Figure 59. Input Clock Diagram
ADCADCADCINAP, INAM SYSREFP, SYSREFM CLKINP, CLKINM PLL Buffer INBP, INBM Buffer DB[1:0]P, DB[1:0]M DA[1:0]P, DA[1:0]M DA[3:2]P, DA[3:2]M DB[3:2]P, DB[3:2]M GPIO[4:1] ADC N N NCO CTRL SYNCBP, SYNCBM JESD204B Interface NCO FOVR FOVR NCO NCO NCO ADC Digital Block Interleave Correction Power Detection Digital Block Interleave Correction Power Detection Copyright © 2016, Texas Instruments Incorporated Clock Divider SPI and Control CM N N RESET SCLK SDATA SEN PDN SDO ADC32RF45 SBAS747C –MAY 2016–REVISED DECEMBER 2016 www.ti.com Product Folder Links: ADC32RF45 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated
8 Detailed Description
8.1 Overview
The ADC32RF45 is a dual, 14-bit, 3-GSPS, analog-to-digital converter (ADC) followed by a multi-band digital down-converter (DDC) that can be bypassed, and a back-end JESD204B digital interface. The ADCs are preceded by an input buffer and on-chip termination to provide a uniform input impedance over a large input frequency range. Furthermore, an internal differential clamping circuit provides first-level protection against overvoltage conditions. Each ADC channel is internally interleaved four times and equipped with background, analog and digital, and interleaving correction. The on-chip DDC enables single- or dual-band internal processing to pre-select and filter smaller bands of interest and also reduces the digital output data traffic. Each DDC is equipped with up to three independent, 16-bit numerically-controlled oscillators (NCOs) for phase coherent frequency hopping; the NCOs can be controlled through the SPI or GPIO pins. The ADC32RF45 also provides three different power detectors on-chip with alarm outputs in order to support external automatic gain control (AGC) loops. The processed data are passed into the JESD204B interface where the data are framed, encoded, serialized, and output on one to four lanes per channel, depending on the ADC sampling rate and decimation. The CLKIN, SYSREF, and SYNCB inputs provide the device clock and the SYSREF and SYNCB signals to the JESD204B interface that are used to derive the internal local frame and local multiframe clocks and establish the serial link. All features of the ADC32RF45 are configurable through the SPI.
8.2 Functional Block Diagram
8.3 Feature Description
8.3.1 Analog Inputs
currents of the sampling circuit, thus resulting in a more constant SFDR performance across input frequencies. from dc to 5 GHz with a 100-Ω reference impedance. Figure 60. Equivalent Input Impedance Figure 61. SDD11 Over the Input Frequency Range
100 Ohm Source
50 Ohm Source
capacitance. Figure 62 and Figure 63 show how equivalent impedance (CIN and RIN) vary over frequency. Figure 62. Differential Input Capacitance vs Figure 63. Differential Input Resistance vs Input Frquency approximately 3.2 GHz, as shown in Figure 64. Figure 64. Input Bandwidth with a 100-Ω Source Resistance
8.3.1.1 Input Clamp Circuit
the maximum input signal to approximately 2.4 VPP, as shown in Figure 65 and Figure 66. Figure 65. Clamp Circuit in the ADC32RF45 Figure 66. Clamp Response Timing Diagram
8.3.2 Clock Input
The ADC32RF45 sampling clock input includes internal 100-Ω differential termination along with on-chip biasing. Figure 67. SDD11 of the Clock Input
Figure 68. Depending on the clock frequency, a matching circuit can be designed in order to maximize the clock Figure 68. Equivalent Aperture Jitter vs Input Clock Amplitude
8.3.3 SYSREF Input
help with skew adjustment when the sampling clock and SYSREF are not provided from the same source. Figure 69. SYSREF Internal Circuit Diagram
8.3.3.1 Using SYSREF
in the ASSERT SYSREF REG bit when using SPI registers, as shown in Figure 70. Figure 70. Using SYSREF to Reset the Clock Divider, the NCO, and the LMFC Counter disregarding the first two assertions, as shown in Table 1. Table 1. Asserting SYSREF
1 Gets reset Does not get reset Does not get reset
2 Gets reset Does not get reset Does not get reset
3 Gets reset Gets reset Gets reset
ignore further SYSREF pulses. (1) fS = sampling (device) clock frequency. (2) LCM = least-common multiple. (3) K = number of frames per multi-frame.
- SYSREF is applied as a periodic pulse.
Figure 72 shows how SYSREF can be applied as a continuous periodic waveform. (1) tSYSREF is a period of the SYSREF waveform. (2) Alternatively, the SYSREF buffer can be powered down using the PDN SYSREF bit. Figure 72. SYSREF Used as a Periodic Waveform to the NCO and JESD can be masked by setting the MASK NCO SYSREF register bit.
8.3.3.2 Frequency of the SYSREF Signal
decimation, frames per multi-frame setting (K), samples per frame (S), and device input clock frequency.
- N is an integer value (1, 2, 3, and so forth) (1) In order for the interleaving correction engine to synchronize properly, the SYSREF frequency must also be a multiple of fS / 64. Table 2 provides a summary of the valid LMFC clock settings.
Table 2. . SYSREF and LMFC Clock Frequency the signal path both on the printed circuit board (PCB) as well as internal to the device.
16 Bits
3 GSPS IQ data, 3 GSPS RX1 IQ Output
For proper device operation, disable the SYSREF signal after the JESD synchronization is established.
8.3.4 DDC Block
NOTE: Red traces show SYSREF going to the NCO blocks. Figure 73. DDC Chains Overview (One ADC Channel Shown) twice the decimated, complex output rate. The filter response with a real output is identical to a complex output.
8.3.4.1 Operating Mode: Receiver
In receiver mode, the DDC block can be configured to single- or dual-band operation, as shown in Figure 74. lanes of the JESD204B interface. NOTE: Red traces show SYSREF going to the NCO blocks. Figure 74. Decimation Filter Option for Single- or Dual-Band Operation
8.3.4.2 Operating Mode: Wide-Bandwidth Observation Receiver
NOTE: Red traces show SYSREF going to the NCO blocks. Figure 75. Decimation Filter Implementation for Single-Band and Wide-Bandwidth Mode
8.3.4.3 Decimation Filters
Table 3. Decimation Filter Summary and Maximum Available Output Bandwidth
3 GSPS IQ 3 GSPS
750 MSPS
A dual-band example with a divide-by-8 complex is shown in Figure 76. Figure 76. Dual-Band Example The decimation filters of the ADC32RF45 provide greater than 90-dB attenuation for the alias bands. Figure 77. Interpretation of the Decimation Filter Plots
8.3.4.3.1 Divide-by-4
Figure 78. Divide-by-4 Filter Response Figure 79. Divide-by-4 Filter Response (Zoomed)
8.3.4.3.2 Divide-by-6
Figure 80. Divide-by-6 Filter Response Figure 81. Divide-by-6 Filter Response (Zoomed)
8.3.4.3.3 Divide-by-8
Figure 82. Divide-by-8 Filter Response Figure 83. Divide-by-8 Filter Response (Zoomed)
8.3.4.3.4 Divide-by-9
Figure 84. Divide-by-9 Filter Response Figure 85. Divide-by-9 Filter Response (Zoomed)
8.3.4.3.5 Divide-by-10
Figure 86. Divide-by-10 Filter Response Figure 87. Divide-by-10 Filter Response (Zoomed)
8.3.4.3.6 Divide-by-12
Figure 88. Divide-by-12 Filter Response Figure 89. Divide-by-12 Filter Response (Zoomed)
8.3.4.3.7 Divide-by-16
Figure 90. Divide-by-16 Filter Response Figure 91. Divide-by-16 Filter Response (Zoomed)
8.3.4.3.8 Divide-by-18
Figure 92. Divide-by-18 Filter Response Figure 93. Divide-by-18 Filter Response (Zoomed)
8.3.4.3.9 Divide-by-20
Figure 94. Divide-by-20 Filter Response Figure 95. Divide-by-20 Filter Response (Zoomed)
8.3.4.3.10 Divide-by-24
Figure 96. Divide-by-24 Filter Response Figure 97. Divide-by-24 Filter Response (Zoomed)
8.3.4.3.11 Divide-by-32
Figure 98. Divide-by-32 Filter Response Figure 99. Divide-by-32 Filter Response (Zoomed)
8.3.4.3.12 Latency with Decimation Options
latency increases as a result of decimation filters, as described in Table 4. Table 4. Latency with different Decimation options
8.3.4.4 Digital Multiplexer (MUX)
Figure 100. In this manner, the ADC32RF45 can be configured as a single-channel ADC with up to four configurations are identical to the two ADC channel operation. Figure 100. Digital Multiplexer Option
8.3.4.5 Numerically-Controlled Oscillators (NCOs) and Mixers
a complex exponential sequence, as shown in Equation 2.
- frequency (ω) is specified as a signed number by the 16-bit register setting (2)
- x = 0, 1
- y = 1 to 4 (3) For example: If fS = 3 GSPS, then the NCO register setting = 38230 (decimal). Thus, fNCO is defined by Equation 4: (4) Any register setting changes that occur after the JESD204B interface is operational results in a non-deterministic NCO phase. If a deterministic phase is required, the JESD204B interface must be reinitialized after changing the register setting. In bypass mode (when decimation filters are not used), the NCOs are powered down in order to avoid creating unwanted spurs.
8.3.5 NCO Switching
frequency hopping. This feature is available in both single-band and dual-band mode, but only affects DDC0. based on the logic selection on the GPIO pins; see Table 7 and Figure 101. Table 5. NCO Register Configurations NCO SEL pin 500Fh, 580Fh Selects the NCO control through the SPI (default) or a GPIO pin. INSEL0, INSEL1 5438h, 5C38h Selects which two GPIO pins are used to control the NCO. NCO SEL pin 500Fh, 580Fh Selects the NCO control through the SPI (default) or a GPIO pin. NCO SEL 5010h, 5810h Selects which NCO to use for DDC0. Table 6. GPIO Pin Assignment
00 GPIO4
01 GPIO1
10 GPIO3
11 GPIO2
Table 7. NCO Selection Figure 101. NCO Switching from GPIO and SPI
8.3.6 SerDes Transmitter Interface
Figure 102. External Serial JESD204B Interface Connection
8.3.7 Eye Diagrams
Figure 103. Data Eye at 5 Gbps Figure 104. Data Eye at 12 Gbps
8.3.8 Alarm Outputs: Power Detectors for AGC Support
8.3.8.1 Absolute Peak Power Detector
block detector alarm output. Figure 105. Peak Power Detector Implementation
Figure 106. Peak Power Detector Timing Diagram operates in the fS / 8 clock domain; one peak sample is calculated over eight actual samples. (5Cxxh), although some registers are common in 54xxh (such as the GPIO pin selection). Table 8. Registers Required for the Peak Power Detector value: N is 17 bits: 1 to 216. equivalent to the peak amplitude). the DWELL value. This threshold is 16 bits and is specified in terms of fS / 8 clock cycles. 5434h, 5435h Connects the BLKPKDETH, BLKPKDETL alarms to the GPIO pins; common register. IODIR 5437h Selects the direction for the four GPIO pins; common register. RESET AGC 542Bh, 5C2Bh After configuration, reset the AGC module to start operation.
8 Samples
8.3.8.2 Crossing Detector
Figure 107. Crossing Detector Implementation Figure 108. Crossing Detector Timing Diagram
although some registers are common in 54xxh (such as the GPIO pin selection). Table 9. Registers Required for the Crossing Detector Operation Sets the block length N of number of samples (S\`). Number of actual ADC samples is 8X this value: N is 17 bits: 1 to 216. (where 256 is equivalent to the peak amplitude). identification register (IIR) filter. Sets the crossing detector time period for N = 0 to 15 as 2N × fS / 8 clock cycles. crossings, a value of 0.125 (0800h) corresponds to 12.5% crossings. 5C1Eh DWELL counter for the IIR filter hysteresis. 5C13h, 5C114h Enables 2-bit output format for the crossing detector. 5434h, 5435h Connects the IIRPKDET0, IIRPKDET1 alarms to the GPIO pins; common register. IODIR 5437h Selects the direction for the four GPIO pins; common register. RESET AGC 542Bh, 5C2Bh After configuration, reset the AGC module to start operation.
8.3.8.3 RMS Power Detector
and then compared against two sets of programmable thresholds (with hysteresis). 1-bit output provides one threshold together with hysteresis. Figure 109. RMS Power Detector Implementation (5Cxxh), although some registers are common in 54xxh (such as the GPIO pin selection). Table 10. Registers Required for Using the RMS Power Detector Feature is defined in terms of fS / 8 clocks. The block length can be programmed as 2M with M = 0 to 16. The computed average power is compared against these high and low thresholds. RMS2BIT EN 5427h, 5C27h Enables 2-bit output format for the RMS detector output. 5434h, 5435h Connects the PWRDET alarms to the GPIO pins; common register. IODIR 5437h Selects the direction for the four GPIO pins; common register. RESET AGC 542Bh, 5C2Bh After configuration, reset the AGC module to start operation.
8.3.8.4 GPIO AGC MUX
The GPIO pins can be used to control the NCO in wideband DDC mode or as alarm outputs for channel A and B. crossing detector (1 or 2 bit), faster overrange, or the RMS power output, as shown in Figure 110. pins. These pins can be configured as outputs (AGC alarm) or inputs (NCO control) through SPI programming. Figure 110. GPIO Output MUX Implementation
8.3.9 Power-Down Mode
the PDN pin or the SPI register writes.
8.3.10 ADC Test Pattern
data path is shown in Figure 111. Figure 111. Test Pattern Generator Implementation
8.3.10.1 Digital Block
for both ADC channels using the SYSREF signal. Additionally, a 12-bit ramp test pattern is available in DDC bypass mode.
The number of converters increases in dual-band DDC mode and with a complex output. Table 11. Test Pattern Options (Register 37h) Test pattern outputs on channel A and B.
0111 Double pattern: output data alternate between custom pattern 1 and
8.3.10.2 Transport Layer
pattern can be substituted instead of the ADC data with the JESD frame, as shown in Table 12. Table 12. Transport Layer Test Mode EN (Register 01h)
4 TESTMODE EN 0
to section 5.1.6.3 of the JESD204B specification.
8.3.10.3 Link Layer
The link layer contains the scrambler and the 8b, 10b encoding of any data passed on from the transport layer. Additionally, the link layer also handles the initial lane alignment sequence that can be manually restarted. patterns do not pass through the 8b, 10b encoder and contain the options listed in Table 13. Table 13. Link Layer Test Mode (Register 03h) (AAAAh) in the ADC section and running AAAAh through the 8b, 10b encoder with scrambling enabled.
8.4 Device Functional Modes
8.4.1 Device Configuration
section. In addition, the device has one dedicated parallel pin (PDN) for controlling the power-down modes.
8.4.2 JESD204B Interface
Figure 112. JESD Signal Overview
from the transport layer can be scrambled. Figure 113. JESD Digital Block Implementation
8.4.2.1 JESD204B Initial Lane Alignment (ILA)
synchronization, as shown in Figure 114. start and end symbols. The second multiframe also contains the JESD204 link configuration data. Figure 114. JESD Internal Timing Information
(1) In full rate output, the two LSBs are truncated to a 12-bit output.
8.4.2.2 JESD204B Frame Assembly
- F is the number of octets per frame clock period
- L is the number of lanes per link
- M is the number of converters for the device
- S is the number of samples per frame
8.4.2.3 JESD204B Frame Assembly in Bypass Mode
the different lanes is shown in Table 15. Table 14. JESD Mode Options: Bypass Mode (1) Blue shading indicates channel A and yellow shading indicates channel B. Table 15. JESD Sample Lane Alignments: Bypass Mode(1)
8.4.2.4 JESD204B Frame Assembly with Decimation (Single-Band DDC): Complex Output
maximum ADC sample frequency. The sample alignment on the different lanes is shown in Table 17. Table 16. JESD Mode Options: Single-Band Complex Output (1) Blue shading indicates channel A and yellow shading indicates channel B. Table 17. JESD Sample Lane Alignments: Single-Band Complex Output(1)
8.4.2.5 JESD204B Frame Assembly with Decimation (Single-Band DDC): Real Output
ADC sample frequency. The sample alignment on the different lanes is shown in Table 19. Table 18. JESD Mode Options: Single-Band Real Output (Wide Bandwidth) (1) Blue shading indicates channel A and yellow shading indicates channel B. Table 19. JESD Sample Lane Alignment: Single-Band Real Output (Wide Bandwidth)(1)
8.4.2.6 JESD204B Frame Assembly with Decimation (Single-Band DDC): Real Output
DDC) when using a complex output format. The sample alignment on the different lanes is shown in Table 21. Table 20. JESD Mode Options: Single-Band Real Output (1) Blue shading indicates channel A and yellow shading indicates channel B. Table 21. JESD Sample Lane Assignment: Single-Band Real Output(1)
4211 LMFS = 4222 LMFS = 2221 LMFS = 2242
8.4.2.7 JESD204B Frame Assembly with Decimation (Dual-Band DDC): Complex Output
ADC sample frequency. The sample alignment on the different lanes is shown in Table 23. Table 22. JESD Mode Options: Dual-Band Complex Output (1) Blue and green shading indicates the two bands for channel A; yellow and orange shading indicates the two bands for channel B. Table 23. JESD Sample Lane Assignment: Dual-Band Complex Output(1)
8.4.2.8 JESD204B Frame Assembly with Decimation (Dual-Band DDC): Real Output
sample frequency. The sample alignment on the different lanes is shown in Table 25. Table 24. JESD Mode Options: Dual-Band Real Output (1) Blue and green shading indicates the two bands for channel A; yellow and orange shading indicates the two bands for channel B. Table 25. JESD Sample Lane Assignment: Dual-Band Complex Output(1)
8.4.3 Serial Interface
speeds (of a few hertz) and also with a non-50% SCLK duty cycle, as shown in Table 26. to distinguish between read/write, page and register, and individual channel access, as described in Table 27. Figure 115. SPI Timing Diagram Table 26. SPI Timing Information
8.4.3.1 Serial Register Write: Analog Bank
- Initiating a serial interface cycle selecting the page address of the register whose content must be written. To
- Writing the register content. When a page is selected, multiple registers located in the same page can be
Figure 117. SPI Write Timing Diagram for the Analog Bank
8.4.3.2 Serial Register Readout: Analog Bank
- Selecting the page address of the register whose content must be read. Master page: write address 0012h
with 04h. ADC page: write address 0011h with FFh.
- Setting the R/W bit to 1 and writing the address to be read back.
- Reading back the register content on the SDOUT pin. When a page is selected, the contents of multiple
registers located in same page can be readback. Figure 118. SPI Read Timing Diagram for the Analog Bank
8.4.3.3 Serial Register Write: Digital Bank
- Setting the M bit to 1 and specifying the page with with the desired register. There are seven pages in Digital
begins with 4xxx when selecting a page from digital bank because the M bit must be set to 1. – To select the JESD digital page: write address 4004h with 69h, 4003h with 00h, and 4002h with 00h. Figure 119. SPI Write Timing Diagram for Digital Bank Page Selection
- Writing into the desired register by setting both the M bit and P bit to 1. Write register content. When a page
when selecting a page from the digital bank because the M bit must be set to 1, as shown in Figure 120. program registers for channel B begins with 6xxx and channel A begins with 7xxx. Figure 120. SPI Write Timing Diagram for Digital Bank Register Write
8.4.3.4 Serial Register Readout: Digital Bank
- Selecting the page in the digital page: follow step 2 in the Serial Register Write: Digital Bank section.
- Set the R/W, M, and P bits to 1, select channel A or channel B, and write the address to be read back.
– JESD digital page: use the CH bit to select channel B (CH = 0) or channel A (CH = 1).
- Read back the register content on the SDOUT pin. When a page is selected, multiple read backs from the
Figure 121. SPI Read Timing Diagram for the Digital Bank
8.4.3.5 Serial Register Write: Decimation Filter and Power Detector Pages
pages can be programmed in one SPI cycle (Figure 122).
- Directly write to the decimation filter or power detector pages. To program registers in these pages, set M = 1
detector page (A[10] = 1). Address bit A[11] selects channel A (A[11] = 0) or channel B (A[11] = 1). – Decimation filter page: write address 50xxh for channel A or 58xxh for channel B. – Power detector page: write address 54xxh for channel A or 5Cxxh for channel B. decimation factor of divide-by-8 (complex output). Figure 122. SPI Write Timing Diagram for the Decimation and Power Detector Pages
8.5 Register Maps
a page is accessed, the registers in that page can be programmed multiple times. (2) Registers in the decimation filter page and the power detector page can be directly programmed in one SPI cycle. (3) The CH bit is a don't care bit and is recommended to be kept at 0. Figure 123. SPI Registers, Two-Step Addressing
(1) Registers in the decimation filter page and the power detector page can be directly programmed in one SPI cycle. Figure 124. SPI Registers: Direct Addressing
Table 28 lists the register map for the ADC32RF45. Table 28. Register Map
000 RESET 0 0 0 0 0 0 RESET
002 DIGITAL BANK PAGE SEL[7:0]
003 DIGITAL BANK PAGE SEL[15:8]
004 DIGITAL BANK PAGE SEL[23:16]
011 ADC PAGE SEL
68 FREEZE OFFSET
Table 28. Register Map (continued)
001 CTRL K 0 0 TESTMODE EN 0 LANE ALIGN FRAME ALIGN TX LINK DIS
002 SYNC REG SYNC REG EN 0 0 12BIT MODE JESD MODE0
003 LINK LAYER TESTMODE LINK LAY RPAT LMFC MASK
006 SCRAMBLE EN 0 0 0 0 0 0 0
032 SEL EMP LANE 0 0 0
033 SEL EMP LANE 1 0 0
034 SEL EMP LANE 2 0 0
035 SEL EMP LANE 3 0 0
007 DDC0 NCO1 LSB
008 DDC0 NCO1 MSB
009 DDC0 NCO2 LSB
033 CUSTOM PATTERN1[7:0]
034 CUSTOM PATTERN1[15:8]
035 CUSTOM PATTERN2[7:0]
036 CUSTOM PATTERN2[15:8]
001 BLKPKDET [7:0]
002 BLKPKDET [15:8]
007 BLKTHHH
008 BLKTHHL
009 BLKTHLH
010 FIL0THH[15:8]
011 FIL0THL[7:0]
012 FIL0THL[15:8]
016 FIL1THH[7:0]
017 FIL1THH[15:8]
018 FIL1THL[7:0]
019 FIL1THL[15:8]
022 PWRDETH[7:0]
023 PWRDETH[15:8]
024 PWRDETL[7:0]
025 PWRDETL[15:8]
032 OUTSEL GPIO1
033 OUTSEL GPIO2
034 OUTSEL GPIO3
035 OUTSEL GPIO4
8.5.1 Example Register Writes
3 GSPS) and the JESD format configured to LMFS = 4421. Table 29. Global Power-Down Table 30. Scrambler Enable Table 31. 8X Decimation for Channel A and B
8.5.2 Register Descriptions
8.5.2.1 General Registers
8.5.2.1.1 Register 000h (address = 000h), General Registers
Figure 125. Register 000h (1) Both bits (7, 0) must be set simultaneously to perform a reset. Table 32. Register 000h Field Descriptions
7 RESET R/W 0h 0 = Normal operation
0 RESET R/W 0h 0 = Normal operation(1)
8.5.2.1.2 Register 002h (address = 002h), General Registers
Figure 126. Register 002h Table 33. Register 002h Field Descriptions desired page in the JESD bank.
8.5.2.1.3 Register 003h (address = 003h), General Registers
Figure 127. Register 003h Table 34. Register 003h Field Descriptions desired page in the JESD bank.
8.5.2.1.4 Register 004h (address = 004h), General Registers
Figure 128. Register 004h Table 35. Register 004h Field Descriptions desired page in the JESD bank.
8.5.2.1.5 Register 010h (address = 010h), General Registers
Figure 129. Register 010h Table 36. Register 010h Field Descriptions
8.5.2.1.6 Register 011h (address = 011h), General Registers
Figure 130. Register 011h Table 37. Register 011h Field Descriptions
8.5.2.1.7 Register 012h (address = 012h), General Registers
Figure 131. Register 012h Table 38. Register 012h Field Descriptions
2 MASTER PAGE SEL R/W 0h 0 = Normal operation
8.5.3 Master Page (M = 0)
8.5.3.1 Register 020h (address = 020h), Master Page
Figure 132. Register 020h Table 39. Register 020h Field Descriptions 4 PDN SYSREF R/W 0h This bit powers down the SYSREF input buffer. 1 PDN CHB R/W 0h This bit powers down channel B. 0 GLOBAL PDN R/W 0h This bit enables the global power-down.
8.5.3.2 Register 032h (address = 032h), Master Page
Figure 133. Register 032h Table 40. Register 032h Field Descriptions
5 INCR CM IMPEDANCE R/W 0h Only use this bit when analog inputs are dc-coupled to the
8.5.3.3 Register 039h (address = 039h), Master Page
Figure 134. Register 039h
0 ALWAYS
Table 41. Register 039h Field Descriptions
6 ALWAYS WRITE 1 W 0h Always set this bit to 1
4 ALWAYS WRITE 1 W 0h Always set this bit to 1
1 PDN CHB EN R/W 0h This bit enables the power-down control of channel B through
0 SYNC TERM DIS R/W 0h This bit disables the on-chip, 100-Ω termination resistors on the
8.5.3.4 Register 03Ch (address = 03Ch), Master Page
Figure 135. Register 03Ch
0 SYSREF DEL EN 0 0 0 0 SYSREF DEL[4:3]
Table 42. Register 03Ch Field Descriptions
6 SYSREF DEL EN R/W 0h This bit allows an internal delay to be added to the SYSREF
delay can be adjusted in 25-ps steps; the first step is 175 ps.
8.5.3.5 Register 05Ah (address = 05Ah), Master Page
Figure 136. Register 05Ah Table 43. Register 05Ah Field Descriptions
7 SYSREF DEL2 W 0h When the SYSREF delay feature is enabled (3Ch, bit 6) the
delay can be adjusted in 25-ps steps; the first step is 175 ps.
6 SYSREF DEL1 R/W
5 SYSREF DEL0 W
Table 44. SYSREF DEL[2:0] Bit Settings
8.5.3.6 Register 03Dh (address = 3Dh), Master Page
Figure 137. Register 03Dh Table 45. Register 03Dh Field Descriptions
8.5.3.7 Register 057h (address = 057h), Master Page
Figure 138. Register 057h Table 46. Register 057h Field Descriptions 3 ASSERT SYSREF REG R/W 0h Set this bit to use the SPI register to assert SYSREF.
8.5.3.8 Register 058h (address = 058h), Master Page
Figure 139. Register 058h Table 47. Register 058h Field Descriptions 5 SYNCB POL R/W 0h This bit inverts the SYNCB polarity.
8.5.4 ADC Page (FFh, M = 0)
8.5.4.1 Register 03Fh (address = 03Fh), ADC Page
Figure 140. Register 03Fh Table 48. Register 03Fh Field Descriptions 2 SLOW SP EN1 R/W 0h This bit must be enabled for clock rates below 2.5 GSPS.
8.5.4.2 Register 042h (address = 042h), ADC Page
Figure 141. Register 042h Table 49. Register 042h Field Descriptions 4 SLOW SP EN2 R/W 0h This bit must be enabled for clock rates below 2.5 GSPS.
8.5.5 Digital Function Page (610000h, M = 1 for Channel A and 610100h, M = 1 for Channel B)
8.5.5.1 Register A6h (address = 0A6h), Digital Function Page
Figure 142. Register 0A6h Table 50. Register 0A6h Field Descriptions decimation up to 11 dB; see Table 51. Table 51. DIG GAIN Bit Settings
8.5.6 Offset Corr Page Channel A (610000h, M = 1)
8.5.6.1 Register 034h (address = 034h), Offset Corr Page Channel A
Figure 143. Register 034h Table 52. Register 034h Field Descriptions
0 SEL EXT EST R/W 0h This bit selects the external estimate for the offset correction
block; see the Using DC Coupling in the ADC32RF45 section.
8.5.6.2 Register 068h (address = 068h), Offset Corr Page Channel A
Figure 144. Register 068h Table 53. Register 068h Field Descriptions
7 FREEZE OFFSET CORR R/W 0h Use this bit and bits 5 and 1 to freeze the offset estimation
anymore, and applies the last computed value.
5 ALWAYS WRITE 1 R/W 0h Always write this bit as 1 for the offset correction block to work
2 DIS OFFSET CORR R/W 0h 0 = Offset correction block works and removes fS/8, fS/4, 3fS/8,
1 ALWAYS WRITE 1 R/W 0h Always write this bit as 1 for the offset correction block to work
8.5.7 Offset Corr Page Channel B (610000h, M = 1)
8.5.7.1 Register 068h (address = 068h), Offset Corr Page Channel B
Figure 145. Register 068h Table 54. Register 068h Field Descriptions anymore, and applies the last computed value.
8.5.8 Digital Gain Page (610005h, M = 1 for Channel A and 610105h, M = 1 for Channel B)
8.5.8.1 Register 0A6h (address = 0A6h), Digital Gain Page
Figure 146. Register 0A6h Table 55. Register 0A6h Field Descriptions
8.5.9 Main Digital Page Channel A (680000h, M = 1)
8.5.9.1 Register 000h (address = 000h), Main Digital Page Channel A
Figure 147. Register 000h Table 56. Register 000h Field Descriptions
0 DIG CORE RESET GBL R/W 0h Pulse this bit (0 →1 →0) to reset the digital core (applies to both
All Nyquist zone settings take effect when this bit is pulsed.
8.5.9.2 Register 0A2h (address = 0A2h), Main Digital Page Channel A
Figure 148. Register 0A2h Table 57. Register 0A2h Field Descriptions 3 NQ ZONE EN R/W 0h This bit allows for specification of the operating Nyquist zone. Set the NQ ZONE EN bit before programming these bits.
8.5.10 Main Digital Page Channel B (680001h, M = 1)
8.5.10.1 Register 000h (address = 000h), Main Digital Page Channel B
Figure 149. Register 000h Table 58. Register 000h Field Descriptions All Nyquist zone settings take effect when this bit is pulsed.
8.5.10.2 Register 0A2h (address = 0A2h), Main Digital Page Channel B
Figure 150. Register 0A2h Table 59. Register 0A2h Field Descriptions 3 NQ ZONE EN R/W 0h This bit allows for specification of the operating Nyquist zone. Set the NQ ZONE EN bit before programming these bits.
8.5.11 JESD Digital Page (6900h, M = 1)
8.5.11.1 Register 001h (address = 001h), JESD Digital Page
Figure 151. Register 001h Table 60. Register 001h Field Descriptions
7 CTRL K R/W 0h This bit is the enable bit for the number of frames per
4 TESTMODE EN 0 This bit generates a long transport layer test pattern mode
according to section 5.1.6.3 of the JESD204B specification.
0 TX LINK DIS R/W 0h This bit disables sending the initial link alignment (ILA) sequence
8.5.11.2 Register 002h (address = 002h ), JESD Digital Page
Figure 152. Register 002h Table 61. Register 002h Field Descriptions 7 SYNC REG R/W 0h This bit provides SYNC control through the SPI. 6 SYNC REG EN R/W 0h This bit is the enable bit for SYNC control through the SPI.
8.5.11.3 Register 003h (address = 003h), JESD Digital Page
Figure 153. Register 003h Table 62. Register 003h Field Descriptions
4 LINK LAY RPAT R/W 0h This bit changes the running disparity in a modified RPAT
pattern test mode (only when link layer test mode = 100).
3 LMFC MASK RESET R/W 0h 0 = Normal operation
2 JESD MODE1 R/W 1h These bits select the configuration register to configure the
1 JESD MODE2 R/W 0h These bits select the configuration register to configure the
0 RAMP 12BIT R/W 0h This bit enables the RAMP test pattern for 12-bit mode only
8.5.11.4 Register 004h (address = 004h), JESD Digital Page
Figure 154. Register 004h Table 63. Register 004h Field Descriptions by 0, 1, 2, or 3 multiframes after the code group synchronization.
8.5.11.5 Register 006h (address = 006h), JESD Digital Page
Figure 155. Register 006h Table 64. Register 006h Field Descriptions 7 SCRAMBLE EN R/W 0h This bit is the scramble enable bit in the JESD204B interface.
8.5.11.6 Register 007h (address = 007h), JESD Digital Page
Figure 156. Register 007h Table 65. Register 007h Field Descriptions 4-0 FRAMES PER MULTIFRAME (K) R/W 0h These bits set the number of multiframes. Actual K is the value in hex + 1 (that is, 0Fh is K = 16).
8.5.11.7 Register 016h (address = 016h), JESD Digital Page
Figure 157. Register 016h Table 66. Register 016h Field Descriptions 6-4 40x MODE R/W 0h This register must be set for 40X mode operation.
8.5.11.8 Register 017h (address = 017h), JESD Digital Page
Figure 158. Register 017h Table 67. Register 017h Field Descriptions 3-0 Lane[3:0] POL W 0h These bits set the polarity of the individual JESD output lanes.
8.5.11.9 Register 032h-035h (address = 032h-035h), JESD Digital Page
Figure 159. Register 032h Figure 160. Register 033h Figure 161. Register 034h Figure 162. Register 035h
Table 68. Register 032h-035h Field Descriptions settled value of the voltage in one bit period.
8.5.11.10 Register 036h (address = 036h), JESD Digital Page
Figure 163. Register 036h
0 CMOS SYNCB 0 0 0 0 0 0
Table 69. Register 036h Field Descriptions
6 CMOS SYNCB R/W 0h This bit enables single-ended control of SYNCB using the
GPIO4 pin (pin 63). The differential SYNCB input is ignored.
8.5.11.11 Register 037h (address = 037h), JESD Digital Page
Figure 164. Register 037h Table 70. Register 037h Field Descriptions tables in the JESD204B Frame Assembly section for settings.
8.5.11.12 Register 03Eh (address = 03Eh), JESD Digital Page
Figure 165. Register 03Eh
0 MASK CLKDIV SYSREF MASK NCO SYSREF 0 0 0 0 0
Table 71. Register 03Eh Field Descriptions
6 MASK CLKDIV SYSREF R/W 0h Use this bit to mask the SYSREF going to the input clock
5 MASK NCO SYSREF R/W 0h Use this bit to mask the SYSREF going to the NCO in the DDC
block and LMFC counter of the JESD interface.
8.5.12 Decimation Filter Page
8.5.12.1 Register 000h (address = 000h), Decimation Filter Page
Figure 166. Register 000h Table 72. Register 000h Field Descriptions
0 DDC EN R/W 0h This bit enables the decimation filter and disables the bypass
8.5.12.2 Register 001h (address = 001h), Decimation Filter Page
Figure 167. Register 001h Table 73. Register 001h Field Descriptions 3-0 DECIM FACTOR R/W 0h These bits configure the decimation filter setting.
8.5.12.3 Register 002h (address = 2h), Decimation Filter Page
Figure 168. Register 002h Table 74. Register 002h Field Descriptions
0 DUAL BAND EN R/W 0h This bit enables the dual-band DDC filter for the corresponding
8.5.12.4 Register 005h (address = 005h), Decimation Filter Page
Figure 169. Register 005h Table 75. Register 005h Field Descriptions
0 REAL OUT EN R/W 0h This bit converts the complex output to real output at 2x the
8.5.12.5 Register 006h (address = 006h), Decimation Filter Page
Figure 170. Register 006h Table 76. Register 006h Field Descriptions
0 DDC MUX R/W 0h This bit connects the DDC to the alternate channel ADC to
8.5.12.6 Register 007h (address = 007h), Decimation Filter Page
Figure 171. Register 007h Table 77. Register 007h Field Descriptions
8.5.12.7 Register 008h (address = 008h), Decimation Filter Page
Figure 172. Register 008h Table 78. Register 008h Field Descriptions
8.5.12.8 Register 009h (address = 009h), Decimation Filter Page
Figure 173. Register 009h Table 79. Register 009h Field Descriptions
8.5.12.9 Register 00Ah (address = 00Ah), Decimation Filter Page
Figure 174. Register 00Ah Table 80. Register 00Ah Field Descriptions
8.5.12.10 Register 00Bh (address = 00Bh), Decimation Filter Page
Figure 175. Register 00Bh Table 81. Register 00Bh Field Descriptions
8.5.12.11 Register 00Ch (address = 00Ch), Decimation Filter Page
Figure 176. Register 00Ch Table 82. Register 00Ch Field Descriptions
8.5.12.12 Register 00Dh (address = 00Dh), Decimation Filter Page
Figure 177. Register 00Dh Table 83. Register 00Dh Field Descriptions DDC1 (band 2, only when dual-band mode is enabled).
8.5.12.13 Register 00Eh (address = 00Eh), Decimation Filter Page
Figure 178. Register 00Eh Table 84. Register 00Eh Field Descriptions DDC1 (band 2, only when dual-band mode is enabled).
8.5.12.14 Register 00Fh (address = 00Fh), Decimation Filter Page
Figure 179. Register 00Fh Table 85. Register 00Fh Field Descriptions 0 NCO SEL PIN R/W 0h This bit enables NCO selection through the GPIO pins.
8.5.12.15 Register 010h (address = 010h), Decimation Filter Page
Figure 180. Register 010h Table 86. Register 010h Field Descriptions 1-0 NCO SEL R/W 0h These bits enable NCO selection through register setting.
8.5.12.16 Register 011h (address = 011h), Decimation Filter Page
Figure 181. Register 011h Table 87. Register 011h Field Descriptions 1-0 LMFC RESET MODE R/W 0h These bits reset the configuration for all DDCs and NCOs. reset only when analog clock dividers are resynchronized. operation. Deterministic latency is not ensured.
8.5.12.17 Register 014h (address = 014h), Decimation Filter Page
Figure 182. Register 014h Table 88. Register 014h Field Descriptions
0 DDC0 6DB GAIN R/W 0h This bit scales the output of DDC0 by 2 (6 dB) to compensate
by-4 and -6); see register 1Fh.
8.5.12.18 Register 016h (address = 016h), Decimation Filter Page
Figure 183. Register 016h Table 89. Register 016h Field Descriptions
0 DDC1 6DB GAIN R/W 0h This bit scales the output of DDC0 by 2 (6 dB) to compensate
by-4 and -6); see register 1Fh.
8.5.12.19 Register 01Eh (address = 01Eh), Decimation Filter Page
Figure 184. Register 01Eh
0 DDC DET LAT 0 0 0 0
Table 90. Register 01Eh Field Descriptions Table 91. DDC DET LAT Bit Settings
8.5.12.20 Register 01Fh (address = 01Fh), Decimation Filter Page
Figure 185. Register 01Fh Table 92. Register 01Fh Field Descriptions
0 WBF 6DB GAIN R/W 0h This bit scales the output of the wide bandwidth DDC filter by 2
8.5.12.21 Register 033h-036h (address = 033h-036h), Decimation Filter Page
Figure 186. Register 033h Figure 187. Register 034h Figure 188. Register 035h Figure 189. Register 036h Table 93. Register 033h-036h Field Descriptions
8.5.12.22 Register 037h (address = 037h), Decimation Filter Page
Figure 190. Register 037h Table 94. Register 037h Field Descriptions 3-0 TEST PATTERN SEL R/W 0h These bits select the test pattern output on the channel.
8.5.12.23 Register 03Ah (address = 03Ah), Decimation Filter Page
Figure 191. Register 03Ah Table 95. Register 03Ah Field Descriptions must be enabled first (bit D0). 0 TP RES EN R/W 0h This bit enables the test pattern reset.
8.5.13 Power Detector Page
8.5.13.1 Register 000h (address = 000h), Power Detector Page
Figure 192. Register 000h Table 96. Register 000h Field Descriptions 0 PKDET EN R/W 0h This bit enables the peak power and crossing detector.
8.5.13.2 Register 001h-002h (address = 001h-002h), Power Detector Page
Figure 193. Register 001h Figure 194. Register 002h Table 97. Register 001h-002h Field Descriptions The divide-by-8 to -32 complex: length = 10 × decimation factor.
8.5.13.3 Register 003h (address = 003h), Power Detector Page
Figure 195. Register 003h Table 98. Register 003h Field Descriptions
0 BLKPKDET[16] R/W 0h This register specifies the block length in terms of number of
The divide-by-8 to -32 complex: length = 10 × decimation factor.
8.5.13.4 Register 007h-00Ah (address = 007h-00Ah), Power Detector Page
Figure 196. Register 007h Figure 197. Register 008h Figure 198. Register 009h Figure 199. Register 00Ah Table 99. Register 007h-00Ah Field Descriptions 256 is equivalent to the peak amplitude.
8.5.13.5 Register 00Bh-00Ch (address = 00Bh-00Ch), Power Detector Page
Figure 200. Register 00Bh Figure 201. Register 00Ch Table 100. Register 00Bh-00Ch Field Descriptions 7-0 DWELL R/W 0h DWELL time counter. BLKTHHH or BLKTHLH, the peak detector output flags are set.
8.5.13.6 Register 00Dh (address = 00Dh), Power Detector Page
Figure 202. Register 00Dh Table 101. Register 00Dh Field Descriptions
0 FILT0LPSEL R/W 0h This bit selects either the block detector output or 2-bit output as
the input to the IIR filter.
8.5.13.7 Register 00Eh (address = 00Eh), Power Detector Page
Figure 203. Register 00Eh Table 102. Register 00Eh Field Descriptions fS / 8 clock cycles (approximately 87 µs at 3 GSPS).
8.5.13.8 Register 00Fh, 010h-012h, and 016h-019h (address = 00Fh, 010h-012h, and 016h-019h), Power
Figure 204. Register 00Fh Figure 205. Register 010h Figure 206. Register 011h Figure 207. Register 012h Figure 208. Register 016h
Figure 209. Register 017h Figure 210. Register 018h Figure 211. Register 019h Table 103. Register 00Fh, 010h, 011h, 012h, 016h, 017h, 018h, and 019h Field Descriptions corresponds to 12.5% crossings.
8.5.13.9 Register 013h-01Ah (address = 013h-01Ah), Power Detector Page
Figure 212. Register 013h Figure 213. Register 01Ah Table 104. Register 013h and 01Ah Field Descriptions
0 IIR0 2BIT EN
8.5.13.10 Register 01Dh-01Eh (address = 01Dh-01Eh), Power Detector Page
Figure 214. Register 01Dh Figure 215. Register 01Eh Table 105. Register 01Dh-01Eh Field Descriptions bits and is specified in terms of fS / 8 clock cycles.
8.5.13.11 Register 020h (address = 020h), Power Detector Page
Figure 216. Register 020h Table 106. Register 020h Field Descriptions 0 RMSDET EN R/W 0h This bit enables the RMS power detector.
8.5.13.12 Register 021h (address = 021h), Power Detector Page
Figure 217. Register 021h Table 107. Register 021h Field Descriptions programmed as 2M, where M = 0 to 16.
8.5.13.13 Register 022h-025h (address = 022h-025h), Power Detector Page
Figure 218. Register 022h Figure 219. Register 023h Figure 220. Register 024h Figure 221. Register 025h Table 108. Register 022h-025h Field Descriptions thresholds. One LSB of the thresholds represents 1 / 216.
8.5.13.14 Register 027h (address = 027h), Power Detector Page
Figure 222. Register 027h Table 109. Register 027h Field Descriptions
0 RMS 2BIT EN R/W 0h This bit enables 2-bit output format on the RMS output
8.5.13.15 Register 02Bh (address = 02Bh), Power Detector Page
Figure 223. Register 02Bh Table 110. Register 02Bh Field Descriptions
4 RESET AGC R/W 0h After configuration, the AGC module must be reset and then
brought out of reset to start operation. Example: set 542Bh to 10h and then to 00h.
8.5.13.16 Register 032h-035h (address = 032h-035h), Power Detector Page
Figure 224. Register 032h Figure 225. Register 033h Figure 226. Register 034h Figure 227. Register 035h Table 111. Register 032h-035h Field Descriptions R/W 0h These bits set the function or signal for each GPIO pin.
8.5.13.17 Register 037h (address = 037h), Power Detector Page
Figure 228. Register 037h Table 112. Register 037h Field Descriptions 3-0 IODIRGPIO[4:1] R/W 0h These bits select the output direction for the GPIO[4:1] pins.
8.5.13.18 Register 038h (address = 038h), Power Detector Page
Figure 229. Register 038h Table 113. Register 038h Field Descriptions 5-4 INSEL1 R/W 0h These bits select which GPIO pin is used for the INSEL1 bit. 1-0 INSEL0 R/W 0h These bits select which GPIO pin is used for the INSEL0 bit. Table 114. INSEL Bit Settings
9 Application and Implementation
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.1.1 Start-Up Sequence
with a 12-bit output (LMFS = 82820). Table 115. Initialization Sequence
3 Pulse a hardware reset (low-to-high-to-low) on
4 Write the register addresses described in the
registers every time after power up. the Nyquist zone information to the device. reducing interleaving mismatch errors.
6.1 Wait for 50 ms for the device to estimate the
optimized by this step for channel A. optimized by this step for channel B.
9.1.2 Hardware Reset
Timing information for the hardware reset is shown in Figure 230 and Table 116. Figure 230. Hardware Reset Timing Diagram Table 116. Hardware Reset Timing Information
9.1.3 SNR and Clock Jitter
SNR for higher input frequencies. filters at the clock input. A faster clock slew rate also improves the ADC aperture jitter. SNR, depending on the amount of external jitter for different input frequencies, is shown in Figure 231. Figure 231. ADC SNR vs Input Frequency and External Clock Jitter
9.1.3.1 External Clock Phase Noise Consideration
Figure 232. Integration Bandwidth for Extracting Jitter from Clock Phase Noise frequency, as shown in Figure 233. Figure 233. Small Wanted Signal in Presence of Interferer signal band of interest is too large, the wanted signal cannot not be recovered. frequency of the input signal. The ADC sampling rate scales the clock phase noise, as shown in Equation 8.
9.1.4 Power Consumption in Different Modes
with a 12-bit, 3-GSPS output (bypass mode). Table 117 shows power consumption in different DDC modes for dual-channel and single-channel operation. Table 117. Power Consumption in Different DDC Modes (Sampling Clock Frequency, fS = 3 GSPS)
9.1.5 Using DC Coupling in the ADC32RF45
- Ensure that the correct common-mode voltage is used at the ADC analog inputs.
common-mode voltage track the required common-mode voltage of the ADC. (1) Set the INCR CM IMPEDANCE bit to increase the RCM from 0 Ω to > 5000 Ω. (2) RDC is approximately 65 Ω. Figure 234. The ADC32RF45 in a DC-Coupling Application
- Ensure that the correct SPI settings are written to the ADC.
among four interleaving ADC cores for a given channel. Figure 235. Offset Corrector in the ADC32RF45 present at these frequencies, the offset corrector block can be bypassed.
9.1.5.1 Bypassing the Offset Corrector Block
is frozen so that the last estimated value is held. Required register writes are provided in Table 118. Table 118. Freezing and Bypassing the Offset Corrector Block 1 — Signal source is turned off. The device detects an idle channel at its input.
9.1.5.1.1 Effect of Temperature
corrector block is frozen or disabled. Figure 236. Offset Corrector Block Frozen at Room Figure 237. Offset Corrector Block Disabled
55 DA2P
9.2 Typical Application
input frequency range. A typical schematic for an ac-coupled receiver is shown in Figure 238. Figure 238. Additional capacitors can be placed on the remaining power pins. Figure 238. Typical Application Implementation Diagram
9.2.1 Design Requirements
9.2.1.1 Transformer-Coupled Circuits
designing the driving circuits, the ADC input impedance (or SDD11) must be considered. switching currents of the sampling circuit. Figure 239. Input Drive Circuit
9.2.2 Detailed Design Procedure
pin is recommended to damp out ringing caused by package parasitics, as shown in Figure 239.
9.2.3 Application Curves
Figure 240 and Figure 241 show the typical performance at 100 MHz and 1780 MHz, respectively. Figure 240. FFT for 100-MHz Input Frequency Figure 241. FFT for 1780-MHz Input Frequency
10 Power Supply Recommendations
supply for AVDD19. There is no specific sequence for power-supply requirements during device power-up. AVDD, DVDD, and AVDD19 can power-up in any order.
11 Layout
11.1 Layout Guidelines
- Analog inputs are located on opposite sides of the device pinout to ensure minimum crosstalk on the package level. To minimize crosstalk onboard, the analog inputs must exit the pinout in opposite directions, as shown in the reference layout of Figure 242 as much as possible.
- In the device pinout, the sampling clock is located on a side perpendicular to the analog inputs in order to minimize coupling. This configuration is also maintained on the reference layout of Figure 242 as much as possible.
- Keep digital outputs away from the analog inputs. When these digital outputs exit the pinout, the digital output traces must not be kept parallel to the analog input traces because this configuration can result in coupling from the digital outputs to the analog inputs and degrade performance. All digital output traces to the receiver [such as field-programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs)] must be matched in length to avoid skew among outputs.
- At each power-supply pin (AVDD, DVDD, or AVDD19), keep a 0.1-µF decoupling capacitor close to the device. A separate decoupling capacitor group consisting of a parallel combination of 10-µF, 1-µF, and 0.1-µF capacitors can be kept close to the supply source.
11.2 Layout Example
Figure 242. ADC32RF45EVM Layout
SBAS747C –MAY 2016–REVISED DECEMBER 2016 www.ti.com Product Folder Links: ADC32RF45 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
- ADC32RF45/RF80 EVM Quick Startup Guide (SLAU620)
- Configuration Files for the ADC32RF45 (SBAA226)
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
www.ti.com 7-Oct-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) ADC32RF45IRMP Active Production VQFN (RMP) | 72 168 | JEDEC TRAY (5+1) Yes NIPDAU Level-3-260C-168 HR -40 to 85 AZ32RF45 ADC32RF45IRMP.A Active Production VQFN (RMP) | 72 168 | JEDEC TRAY (5+1) Yes NIPDAU Level-3-260C-168 HR -40 to 85 AZ32RF45 ADC32RF45IRMPG4 Active Production VQFN (RMP) | 72 168 | JEDEC TRAY (5+1) Yes NIPDAU Level-3-260C-168 HR -40 to 85 AZ32RF45 ADC32RF45IRMPG4.A Active Production VQFN (RMP) | 72 168 | JEDEC TRAY (5+1) Yes NIPDAU Level-3-260C-168 HR -40 to 85 AZ32RF45 ADC32RF45IRMPT Active Production VQFN (RMP) | 72 250 | SMALL T&R Yes NIPDAU Level-3-260C-168 HR -40 to 85 AZ32RF45 ADC32RF45IRMPT.A Active Production VQFN (RMP) | 72 250 | SMALL T&R Yes NIPDAU Level-3-260C-168 HR -40 to 85 AZ32RF45 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative Addendum-Page 1
www.ti.com 7-Oct-2025 and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 15-Jul-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 15-Jul-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADC32RF45IRMPT VQFN RMP 72 250 213.0 191.0 55.0 Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 15-Jul-2025 TRAY L - Outer tray length without tabs KO - Outer tray height W - Outer tray width P1 - Tray unit pocket pitch CW - Measurement for tray edge (Y direction) to corner pocket center CL - Measurement for tray edge (X direction) to corner pocket center Text Chamfer on Tray corner indicates Pin 1 orientation of packed units. *All dimensions are nominal Device Package Name Package Type Pins SPQ Unit array matrix Max temperature (°C) L (mm) W (mm) (µm) (mm) CL (mm) CW (mm) ADC32RF45IRMP RMP VQFNP 72 168 8 X 21 150 315 135.9 7620 14.65 11 11.95 ADC32RF45IRMP.A RMP VQFNP 72 168 8 X 21 150 315 135.9 7620 14.65 11 11.95 ADC32RF45IRMPG4 RMP VQFNP 72 168 8 X 21 150 315 135.9 7620 14.65 11 11.95 ADC32RF45IRMPG4.A RMP VQFNP 72 168 8 X 21 150 315 135.9 7620 14.65 11 11.95 Pack Materials-Page 3
www.ti.com PACKAGE OUTLINE C PIN 1 ID 8.5 0.1 0.9 MAX 0.05 0.00 8.5 72X 0.30 0.1868X 0.5 72X 0.5 0.3 4X (45 X0.42) B 10.1 9.9 A 10.1 9.9 (0.2) 4221047/B 02/2014 VQFN - 0.9 mm max heightRMP0072A VQFN NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. 3619 72 55
0.1 C B A
0.05 C PIN 1 ID (R0.2) SYMM SYMM
0.08 C SEATING PLANE
SCALE 1.700
www.ti.com EXAMPLE BOARD LAYOUT 72X (0.6) 72X (0.24) ( 8.5) (9.8) 68X (0.5) (0.25) TYP
0.07 MAX
ALL AROUND 0.07 MIN ALL AROUND ( ) TYP VIA 0.2 (9.8) (1.315) TYP (1.315) TYP 4221047/B 02/2014 VQFN - 0.9 mm max heightRMP0072A VQFN SYMM SYMM SEE DETAILS LAND PATTERN EXAMPLE SCALE:8X 19 36 5572 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see QFN/SON PCB application report in literature No. SLUA271 (www.ti.com/lit/slua271). METAL SOLDER MASK OPENING SOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK OPENING METAL SOLDER MASK DEFINED
www.ti.com EXAMPLE STENCIL DESIGN (9.8) 72X (0.6) 72X (0.24) (0.25) TYP 68X (0.5) 36X ( 1.115) (1.315) TYP (1.315) TYP (9.8)(1.315) TYP (1.315) TYP ( ) TYP VIA 0.2 4221047/B 02/2014 VQFN - 0.9 mm max heightRMP0072A VQFN NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SYMM SYMM METAL TYP SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 62% PRINTED SOLDER COVERAGE BY AREA SCALE:8X 19 36 5572
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