ADC32J44IRGZT

Texas Instruments

Dual-Channel, 14-Bit, 50-MSPS to 160-MSPS, Analog-to-Digital Converters

Manufacturer: Texas Instruments

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Frequency (MHz) Amplitude (dBFS) 0 16 32 48 64 80 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 D101 Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community ADC32J42,ADC32J43,ADC32J44,ADC32J45 SBAS663A –MAY 2014–REVISED JUNE 2015 ADC32J4xDual-Channel,14-Bit,50-MSPSto160-MSPS,Analog-to-DigitalConverters withJESD204BInterface

1 Features 3 Description

The ADC32J4x are a high-linearity, ultra-low power, 1• Dual Channel dual-channel, 14-bit, 50-MSPS to 160-MSPS, analog-• 14-Bit Resolution to-digital converter (ADC) family. The devices are

Single Supply: 1.8 V designed specifically to support demanding, high input frequency signals with large dynamic range• Flexible Input Clock Buffer with Divide-by-1, -2, -4 requirements. A clock input divider allows more• SNR = 72.2 dBFS, SFDR = 87 dBc at flexibility for system clock architecture design and thefIN = 70 MHz SYSREF input enables complete system
Ultralow Power Consumption: synchronization. The ADC32J4x family supports JESD204B interface in order to reduce the number of– 227 mW/Ch at 160 MSPS interface lines, thus allowing high system integration• Channel Isolation: 105 dB density. The JESD204B interface is a serial interface,• Internal Dither where the data of each ADC are serialized and output
JESD204B Serial Interface: over only one differential pair. An internal phase- locked loop (PLL) multiplies the incoming ADC– Subclass 0, 1, 2 Compliant up to 3.2 Gbps sampling clock by 20 to derive the bit clock, which is– Supports One Lane per ADC up to 160 MSPS used to serialize the 14-bit data from each channel.
Support for Multichip Synchronization The devices support subclass 1 with interface speeds up to 3.2 Gbps.• Pin-to-Pin Compatible with 12-Bit Version (ADC32J2X) Device Information(1)
Package: VQFN-48 (7 mm × 7 mm) PART NUMBER PACKAGE BODY SIZE (NOM) ADC32J4x VQFN (48) 7.00 mm × 7.00 mm2 Applications (1) For all available packages, see the package option addendum• Multi-Carrier, Multi-Mode Cellular Base Stations at the end of the datasheet.
Radar and Smart Antenna Arrays
Munitions Guidance Performance at fS = 160 MSPS, fIN = 10 MHz• Motor Control Feedback (SNR = 72.5 dBFS, SFDR = 92 dBc)
Network and Vector Analyzers
Communications Test Equipment
Nondestructive Testing
Microwave Receivers
Software-Defined Radios (SDRs)
Quadrature and Diversity Radio Receivers An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

ADC32J42,ADC32J43,ADC32J44,ADC32J45 SBAS663A –MAY 2014–REVISED JUNE 2015 www.ti.com Table of Contents

4 Revision History

Changes from Original (May 2014) to Revision A Page

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13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 NC SYNCP~ DAM DAPSDATA AVDD CLKM SCLK OVRB NCVCM NC AVDD NC AVDD AVDD INAP AVDD INAM GND Pad (Back Side) NC PDN AVDD NC AVDD NC DVDD NC NC NC AVDD AVDD INBP INBM AVDD SYSREFM SYSREFP RESET SDOUT CLKP SEN AVDD DBM SYNCM~ AVDD DBP OVRA DVDD AVDD ADC32J42,ADC32J43,ADC32J44,ADC32J45 www.ti.com SBAS663A –MAY 2014–REVISED JUNE 2015

5 Device Comparison Table

INTERFACE (Bits) 25 MSPS 50 MSPS 80 MSPS 125 MSPS 160 MSPS

12 ADC3221 ADC3222 ADC3223 ADC3224 —

14 ADC3241 ADC3242 ADC3243 ADC3244 —

12 — ADC32J22 ADC32J23 ADC32J24 ADC32J25 JESD204B 14 — ADC32J42 ADC32J43 ADC32J44 ADC32J45

6 Pin Configuration and Functions

ADC32J42,ADC32J43,ADC32J44,ADC32J45 SBAS663A –MAY 2014–REVISED JUNE 2015 www.ti.com Pin Functions PIN I/O DESCRIPTION NAME NO. 4, 5, 8, 9, 12, 17, 20,AVDD I Analog 1.8-V power supply25, 28, 29, 32, 39, 46 CLKM 18 I Negative differential clock input for the ADC CLKP 19 I Positive differential clock input for the ADC DAM 48 O Negative serial JESD204B output for channel A DAP 47 O Positive serial JESD204B output for channel A DBM 45 O Negative serial JESD204B output for channel B DBP 44 O Positive serial JESD204B output for channel B DVDD 3,34 I Digital 1.8-V power supply GND PowerPAD™ I Ground, 0 V INAM 11 I Negative differential analog input for channel A INAP 10 I Positive differential analog input for channel A INBM 26 I Negative differential analog input for channel B INBP 27 I Positive differential analog input for channel B 2, 6, 7, 30, 31, 35,NC — Do not connect37, 38, 40, 41 OVRA 1 O Overrange indicator for channel A OVRB 36 O Overrange indicator for channel B PDN 33 I Power-down control. This pin has an internal 150-kΩ pulldown resistor. RESET 21 I Hardware reset; active high. This pin has an internal 150-kΩ pulldown resistor. SCLK 13 I Serial interface clock input. This pin has an internal 150-kΩ pulldown resistor. SDATA 14 I Serial Interface data input. This pin has an internal 150-kΩ pulldown resistor. SDOUT 16 O Serial interface data output SEN 15 I Serial interface enable. This pin has an internal 150-kΩ pullup resistor to AVDD. SYNCM~ 42 I Positive JESD204B SYNC~ input SYNCP~ 43 I Negative JESD204B SYNC~ input SYSREFM 23 I Negative external SYSREF input SYSREFP 22 I Positive external SYSREF input VCM 24 O Common-mode voltage output for analog inputs

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7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Supply voltage range, AVDD –0.3 2.1 V Supply voltage range, DVDD –0.3 2.1 V MinimumINAP, INBP, INCP, INDP, INAM, INBM, INCM, INDM –0.3 V(AVDD + 0.3, 2.1) MinimumCLKP, CLKM(2) –0.3 VVoltage applied to (AVDD + 0.3, 2.1) input pins: MinimumSYSREFP, SYSREFM, SYNCP~, SYNCM~ –0.3 V(AVDD + 0.3, 2.1) SCLK, SEN, SDATA, RESET, PDN –0.3 3.6 V Operating free-air, TA –40 85 °C Temperature Operating junction, TJ 125 °C Storage, Tstg –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) When AVDD is turned off, TI recommends switching off the input clock (or ensuring the voltage on CLKP, CLKM is less than |0.3 V|). This configuration prevents the ESD protection diodes at the clock input pins from turning on.

7.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions(1)

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT SUPPLIES AVDD Analog supply voltage range 1.7 1.8 1.9 V DVDD Digital supply voltage range 1.7 1.8 1.9 V ANALOG INPUT For input frequencies < 450 MHz 2 VPP VID Differential input voltage For input frequencies < 600 MHz 1 VPP VIC Input common-mode voltage VCM ± 0.025 V CLOCK INPUT Input clock frequency Sampling clock frequency 15 160(2) MSPS Sine wave, ac-coupled 0.2 1.5 V Input clock amplitude (differential) LVPECL, ac-coupled 1.6 V LVDS, ac-coupled 0.7 V Input clock duty cycle 35% 50% 65% Input clock common-mode voltage 0.95 V DIGITAL OUTPUTS CLOAD Maximum external load capacitance from each output pin to GND 3.3 pF RLOAD Single-ended load resistance 50 Ω (1) After power-up, to reset the device for the first time, only use the RESET pin; see the Register Initialization section. (2) With the clock divider enabled by default for divide-by-1. Maximum sampling clock frequency for the divide-by-4 option is 640 MSPS. Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: ADC32J42 ADC32J43 ADC32J44 ADC32J45

ADC32J42,ADC32J43,ADC32J44,ADC32J45 SBAS663A –MAY 2014–REVISED JUNE 2015 www.ti.com

7.4 Thermal Information

THERMAL METRIC(1) RGZ (VQFN) UNIT

48 PINS

RθJA Junction-to-ambient thermal resistance 25.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 18.9 °C/W RθJB Junction-to-board thermal resistance 3.0 °C/W ψJT Junction-to-top characterization parameter 0.2 °C/W ψJB Junction-to-board characterization parameter 3 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 0.5 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, maximum sampling rate, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUT Differential input full-scale 2.0 VPP ri Input resistance Differential at dc 6.5 kΩ ci Input capacitance Differential at dc 5.2 pF VOC(VCM) VCM common-mode voltage output 0.95 V VCM output current capability 10 mA Input common-mode current Per analog input pin 1.5 µA/MSPS 50-Ω differential source driving aAnalog input bandwidth (3 dB) 450 MHz50-Ω termination across INP, INM DC ACCURACY EO Offset error –20 20 mV Gain error as a result of internalEG(REF) –3 3 %FSreference inaccuracy alone EG(CHAN) Gain error of channel alone ±1 %FS α(EGCHAN) Temperature coefficient of EG(CHAN) –0.017 Δ%FS/Ch CHANNEL-TO-CHANNEL ISOLATION fIN = 10 MHz 105 dB fIN = 100 MHz 105 dB Crosstalk(1) fIN = 200 MHz 105 dB fIN = 230 MHz 105 dB fIN = 300 MHz 105 dB (1) Crosstalk is measured with a –1-dBFS input signal on aggressor channel and no input on victim channel.

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7.6 Electrical Characteristics: ADC32J44, ADC32J45

7.7 Electrical Characteristics: ADC32J42, ADC32J43

ADC32J42,ADC32J43,ADC32J44,ADC32J45 SBAS663A –MAY 2014–REVISED JUNE 2015 www.ti.com

7.8 AC Performance: ADC32J45

Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 160 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted. ADC32J45 (fS = 160 MSPS) DITHER ON DITHER OFF PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNIT DYNAMIC AC CHARACTERISTICS fIN = 10 MHz 72.5 72.8 fIN = 70 MHz 70.2 71.7 72.0 SNR Signal-to-noise ratio fIN = 100 MHz 71.3 71.6 dBFS fIN = 170 MHz 70.1 70.7 fIN = 230 MHz 68.9 69.5 fIN = 10 MHz 151.5 151.8 fIN = 70 MHz –149.5 150.7 151.0 Noise spectral densityNSD fIN = 100 MHz 150.3 150.6 dBFS/Hz(averaged across Nyquist zone) fIN = 170 MHz 149.1 149.7 fIN = 230 MHz 147.9 148.5 fIN = 10 MHz 72.3 72.6 fIN = 70 MHz 68.3 71.5 71.8 SINAD Signal-to-noise and distortion ratio fIN = 100 MHz 71.0 71.2 dBFS fIN = 170 MHz 69.6 70.1 fIN = 230 MHz 68.3 68.4 fIN = 10 MHz 11.7 11.8 fIN = 70 MHz 11.1 11.6 11.6 ENOB Effective number of bits fIN = 100 MHz 11.5 11.5 Bits fIN = 170 MHz 11.3 11.3 fIN = 230 MHz 11.0 11.1 fIN = 10 MHz 90 88 fIN = 70 MHz 81 85 85 SFDR Spurious-free dynamic range fIN = 100 MHz 85 84 dBc fIN = 170 MHz 84 83 fIN = 230 MHz 81 80 fIN = 10 MHz 90 91 fIN = 70 MHz 81 91 92 HD2 Second-order harmonic distortion fIN = 100 MHz 88 86 dBc fIN = 170 MHz 84 83 fIN = 230 MHz 81 80 fIN = 10 MHz 91 88 fIN = 70 MHz 81 85 84 HD3 Third-order harmonic distortion fIN = 100 MHz 85 84 dBc fIN = 170 MHz 91 86 fIN = 230 MHz 86 87 fIN = 10 MHz 98 95 fIN = 70 MHz 87 99 95 Non Spurious-free dynamic range fIN = 100 MHz 97 94 dBcHD2, HD3 (excluding HD2, HD3) fIN = 170 MHz 92 91 fIN = 230 MHz 91 89

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ADC32J42,ADC32J43,ADC32J44,ADC32J45 www.ti.com SBAS663A –MAY 2014–REVISED JUNE 2015 AC Performance: ADC32J45 (continued) Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 160 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted. ADC32J45 (fS = 160 MSPS) DITHER ON DITHER OFF PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNIT fIN = 10 MHz 87 84 fIN = 70 MHz 78 84 83 THD Total harmonic distortion fIN = 100 MHz 83 82 dBc fIN = 170 MHz 82 80 fIN = 230 MHz 79 77 fIN1 = 45 MHz, 90 90 fIN2 = 50 MHzTwo-tone, third-orderIMD3 dBFSintermodulation distortion fIN1 = 185 MHz, 86 86fIN2 = 190 MHz DNL Differential nonlinearity fIN = 70 MHz ±0.3 ±0.3 LSBs INL Integrated nonlinearity fIN = 70 MHz ±1.5 ±1.5 LSBs Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: ADC32J42 ADC32J43 ADC32J44 ADC32J45

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7.9 AC Performance: ADC32J44

Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted. ADC32J44 (fS = 125 MSPS) DITHER ON DITHER OFF PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNIT DYNAMIC AC CHARACTERISTICS fIN = 10 MHz 72.6 72.8 fIN = 70 MHz 70.8 72.3 72.5 SNR Signal-to-noise ratio fIN = 100 MHz 72.1 72.3 dBFS fIN = 170 MHz 70.1 71.7 fIN = 230 MHz 70.0 70.8 fIN = 10 MHz 150.6 150.8 fIN = 70 MHz –148.8 150.3 150.5 Noise spectral densityNSD fIN = 100 MHz 150.1 150.3 dBFS/Hz(averaged across Nyquist zone) fIN = 170 MHz 148.1 149.7 fIN = 230 MHz 148.0 148.8 fIN = 10 MHz 72.5 72.7 fIN = 70 MHz 68.6 72.2 72.4 SINAD Signal-to-noise and distortion ratio fIN = 100 MHz 72.0 72.2 dBFS fIN = 170 MHz 70.7 71.4 fIN = 230 MHz 69.5 70.2 fIN = 10 MHz 11.8 11.8 fIN = 70 MHz 11.1 11.7 11.7 ENOB Effective number of bits fIN = 100 MHz 11.7 11.7 Bits fIN = 170 MHz 11.4 11.6 fIN = 230 MHz 11.2 11.4 fIN = 10 MHz 94 92 fIN = 70 MHz 81 93 91 SFDR Spurious-free dynamic range fIN = 100 MHz 93 90 dBc fIN = 170 MHz 85 84 fIN = 230 MHz 82 81 fIN = 10 MHz 95 92 fIN = 70 MHz 81 94 94 HD2 Second-order harmonic distortion fIN = 100 MHz 93 91 dBc fIN = 170 MHz 85 84 fIN = 230 MHz 82 81 fIN = 10 MHz 96 92 fIN = 70 MHz 82 93 90 HD3 Third-order harmonic distortion fIN = 100 MHz 93 90 dBc fIN = 170 MHz 88 88 fIN = 230 MHz 91 93 fIN = 10 MHz 99 96 fIN = 70 MHz 87 99 96 Non Spurious-free dynamic range fIN = 100 MHz 98 96 dBcHD2, HD3 (excluding HD2, HD3) fIN = 170 MHz 98 95 fIN = 230 MHz 96 91

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ADC32J42,ADC32J43,ADC32J44,ADC32J45 www.ti.com SBAS663A –MAY 2014–REVISED JUNE 2015 AC Performance: ADC32J44 (continued) Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted. ADC32J44 (fS = 125 MSPS) DITHER ON DITHER OFF PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNIT fIN = 10 MHz 91 87 fIN = 70 MHz 78 90 87 THD Total harmonic distortion fIN = 100 MHz 90 87 dBc fIN = 170 MHz 83 82 fIN = 230 MHz 80 79 fIN1 = 45 MHz, 91 91 fIN2 = 50 MHzTwo-tone, third-orderIMD3 dBFSintermodulation distortion fIN1 = 185 MHz, 86 86fIN2 = 190 MHz DNL Differential nonlinearity fIN = 70 MHz ±0.3 ±0.3 LSBs INL Integrated nonlinearity fIN = 70 MHz ±1.5 ±1.5 LSBs Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: ADC32J42 ADC32J43 ADC32J44 ADC32J45

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7.10 AC Performance: ADC32J43

Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted. ADC32J43 (fS = 80 MSPS) DITHER ON DITHER OFF PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNIT DYNAMIC AC CHARACTERISTICS fIN = 10 MHz 72.3 72.6 fIN = 70 MHz 70.8 72.2 72.4 SNR Signal-to-noise ratio fIN = 100 MHz 72.0 72.2 dBFS fIN = 170 MHz 71.4 71.8 fIN = 230 MHz 70.6 71.0 fIN = 10 MHz 148.4 148.7 fIN = 70 MHz –146.8 148.2 148.4 Noise spectral densityNSD fIN = 100 MHz 148.0 148.2 dBFS/Hz(averaged across Nyquist zone) fIN = 170 MHz 147.4 147.8 fIN = 230 MHz 146.6 147.0 fIN = 10 MHz 72.3 72.5 fIN = 70 MHz 68.6 72.2 72.2 SINAD Signal-to-noise and distortion ratio fIN = 100 MHz 71.9 72.0 dBFS fIN = 170 MHz 71.0 71.4 fIN = 230 MHz 69.9 70.2 fIN = 10 MHz 11.7 11.8 fIN = 70 MHz 11.1 11.7 11.7 ENOB Effective number of bits fIN = 100 MHz 11.6 11.7 Bits fIN = 170 MHz 11.5 11.6 fIN = 230 MHz 11.3 11.4 fIN= 10 MHz 96 91 fIN = 70 MHz 82 95 90 SFDR Spurious-free dynamic range fIN = 100 MHz 91 88 dBc fIN = 170 MHz 85 84 fIN = 230 MHz 81 80 fIN = 10 MHz 96 95 fIN = 70 MHz 81 98 96 HD2 Second-order harmonic distortion fIN = 100 MHz 93 91 dBc fIN = 170 MHz 85 84 fIN = 230 MHz 81 80 fIN = 10 MHz 95 93 fIN = 70 MHz 83 92 92 HD3 Third-order harmonic distortion fIN = 100 MHz 91 88 dBc fIN = 170 MHz 92 91 fIN = 230 MHz 83 83 fIN = 10 MHz 99 93 fIN = 70 MHz 87 99 93 Non Spurious-free dynamic range fIN = 100 MHz 97 92 dBcHD2, HD3 (excluding HD2, HD3) fIN = 170 MHz 97 93 fIN = 230 MHz 95 92

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ADC32J42,ADC32J43,ADC32J44,ADC32J45 www.ti.com SBAS663A –MAY 2014–REVISED JUNE 2015 AC Performance: ADC32J43 (continued) Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted. ADC32J43 (fS = 80 MSPS) DITHER ON DITHER OFF PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNIT fIN = 10 MHz 93 87 fIN = 70 MHz 78 93 87 THD Total harmonic distortion fIN = 100 MHz 87 85 dBc fIN = 170 MHz 83 82 fIN = 230 MHz 79 77 fIN1 = 45 MHz, 90 90 fIN2 = 50 MHzTwo-tone, third-orderIMD3 dBFSintermodulation distortion fIN1 = 185 MHz, 89 89fIN2 = 190 MHz DNL Differential nonlinearity fIN = 70 MHz ±0.3 ±0.3 LSBs INL Integrated nonlinearity fIN = 70 MHz ±1.5 ±1.5 LSBs Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 13 Product Folder Links: ADC32J42 ADC32J43 ADC32J44 ADC32J45

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7.11 AC Performance: ADC32J42

Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted. ADC32J42 (fS = 50 MSPS) DITHER ON DITHER OFF PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNIT DYNAMIC AC CHARACTERISTICS fIN = 10 MHz 71.3 72.2 72.5 fIN = 70 MHz 71.8 72.1 SNR Signal-to-noise ratio fIN = 100 MHz 71.8 72.0 dBFS fIN = 170 MHz 71.1 71.5 fIN = 230 MHz 69.1 69.4 fIN = 10 MHz 146.1 146.5 fIN = 70 MHz 145.8 146.1 Noise spectral densityNSD fIN = 100 MHz 145.8 146.0 dBFS/Hz(averaged across Nyquist zone) fIN = 170 MHz 145.1 145.5 fIN = 230 MHz 143.1 143.4 fIN = 10 MHz 69.1 72.1 72.3 fIN = 70 MHz 71.8 71.9 SINAD Signal-to-noise and distortion ratio fIN = 100 MHz 71.7 71.8 dBFS fIN = 170 MHz 70.8 71.1 fIN = 230 MHz 68.4 68.7 fIN = 10 MHz 11.2 11.7 11.7 fIN = 70 MHz 11.6 11.7 ENOB Effective number of bits fIN = 100 MHz 11.6 11.6 Bits fIN = 170 MHz 11.5 11.5 fIN = 230 MHz 11.1 11.1 fIN = 10 MHz 84.5 95 93 fIN = 70 MHz 95 90 SFDR Spurious-free dynamic range fIN = 100 MHz 91 89 dBc fIN = 170 MHz 85 84 fIN = 230 MHz 81 80 fIN = 10 MHz 84.5 95 94 fIN = 70 MHz 97 96 HD2 Second-order harmonic distortion fIN = 100 MHz 92 92 dBc fIN = 170 MHz 85 84 fIN = 230 MHz 81 80 fIN = 10 MHz 84.5 102 93 fIN = 70 MHz 95 90 HD3 Third-order harmonic distortion fIN = 100 MHz 91 89 dBc fIN = 170 MHz 88 88 fIN = 230 MHz 82 83 fIN = 10 MHz 87 98 91 fIN = 70 MHz 94 92 Non Spurious-free dynamic range fIN = 100 MHz 91 91 dBcHD2, HD3 (excluding HD2, HD3) fIN = 170 MHz 96 92 fIN = 230 MHz 93 91

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ADC32J42,ADC32J43,ADC32J44,ADC32J45 www.ti.com SBAS663A –MAY 2014–REVISED JUNE 2015 AC Performance: ADC32J42 (continued) Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted. ADC32J42 (fS = 50 MSPS) DITHER ON DITHER OFF PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNIT fIN = 10 MHz 79.5 92 90 fIN = 70 MHz 91 87 THD Total harmonic distortion fIN = 100 MHz 88 85 dBc fIN = 170 MHz 83 82 fIN = 230 MHz 78 78 fIN1 = 45 MHz, 90 90 fIN2 = 50 MHzTwo-tone, third-orderIMD3 dBFSintermodulation distortion fIN1 = 185 MHz, 86 86fIN2 = 190 MHz DNL Differential nonlinearity fIN = 70 MHz ±0.3 ±0.3 LSBs INL Integrated nonlinearity fIN = 70 MHz ±1.5 ±1.5 LSBs Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 15 Product Folder Links: ADC32J42 ADC32J43 ADC32J44 ADC32J45

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7.12 Digital Characteristics

The dc specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level 0 or 1. AVDD = DVDD = 1.8 V and –1-dBFS differential input, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL INPUTS (RESET, SCLK, SEN, SDATA, PDN)(1) VIH High-level input voltage All digital inputs support 1.8-V and 3.3-V logic levels 1.2 V VIL Low-level input voltage All digital inputs support 1.8-V and 3.3-V logic levels 0.4 V SEN 0 µA IIH High-level input current RESET, SCLK, SDATA, PDN 10 µA SEN 10 µA IIL Low-level input current RESET, SCLK, SDATA, PDN 0 µA DIGITAL INPUTS (SYNCP~, SYNCM~, SYSREFP, SYSREFM) VIH High-level input voltage 1.3 V VIL Low-level input voltage 0.5 V Common-mode voltage for SYNC~V(CM_DIG) 0.95 Vand SYSREF DIGITAL OUTPUTS (SDOUT, OVRA, OVRB) DVDD –VOH High-level output voltage DVDD V0.1 VOL Low-level output voltage 0.1 V DIGITAL OUTPUTS (JESD204B Interface: DxP, DxM)(2) VOH High-level output voltage AVDD V VOL Low-level output voltage AVDD – 0.4 V VOD Output differential voltage 0.4 V VOC Output common-mode voltage AVDD – 0.2 V Transmitter pins shorted to any voltage betweenTransmitter short-circuit current –100 100 mA–0.25 V and 1.45 V zos Single-ended output impedance 50 Ω Output capacitance inside the device,Output capacitance 2 pFfrom either output to ground (1) The RESET, SCLK, SDATA, and PDN pins have a 150-kΩ (typical) internal pulldown resistor to ground, and the SEN pin has a 150-kΩ (typical) pullup resistor to AVDD. (2) 50-Ω, single-ended external termination to 1.8 V.

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7.13 Timing Requirements

maximum values are across the full temperature range: TMIN = –40°C to TMAX = 85°C. See Figure 143. Table 1. Latency in Different Modes(1)(2) (1) Overall latency = latency + tD. (2) tS is the time period of the ADC conversion clock. 11 clock cycles in 20X mode.

7.14 Typical Characteristics: ADC32J45

differential input, 2-VPP full-scale, 32k-point FFT, dither enabled, and special modes written, unless otherwise noted. Figure 1. FFT for 10-MHz Input Signal (Dither On) Figure 2. FFT for 10-MHz Input Signal (Dither Off) Figure 3. FFT for 70-MHz Input Signal (Dither On) Figure 4. FFT for 70-MHz Input Signal (Dither Off) Figure 5. FFT for 170-MHz Input Signal (Dither On) Figure 6. FFT for 170-MHz Input Signal (Dither Off)

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differential input, 2-VPP full-scale, 32k-point FFT, dither enabled, and special modes written, unless otherwise noted. Figure 13. FFT for Two-Tone Input Signal Figure 14. FFT for Two-Tone Input Signal Figure 15. Intermodulation Distortion vs Input Amplitude Figure 16. Intermodulation Distortion vs Input Amplitude Figure 17. Signal-to-Noise Ratio vs Input Frequency Figure 18. Spurious-Free Dynamic Range vs

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10 MHz

70 MHz

100 MHz

170 MHz

230 MHz

270 MHz

400 MHz

differential input, 2-VPP full-scale, 32k-point FFT, dither enabled, and special modes written, unless otherwise noted. Figure 19. Signal-to-Noise Ratio vs Figure 20. Spurious-Free Dynamic Range vs Figure 21. Performance vs Input Amplitude (30 MHz) Figure 22. Performance vs Input Amplitude (170 MHz) Figure 23. Performance vs Input Common-Mode Voltage Figure 24. Performance vs Input Common-Mode Voltage

differential input, 2-VPP full-scale, 32k-point FFT, dither enabled, and special modes written, unless otherwise noted. Figure 25. Spurious-Free Dynamic Range vs Figure 26. Signal-to-Noise Ratio vs Figure 27. Spurious-Free Dynamic Range vs Figure 28. Signal-to-Noise Ratio vs Figure 29. Performance vs Clock Amplitude (40 MHz) Figure 30. Performance vs Clock Amplitude (150 MHz)

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7.15 Typical Characteristics: ADC32J44

differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted. Figure 34. FFT for 10-MHz Input Signal (Dither On) Figure 35. FFT for 10-MHz Input Signal (Dither Off) Figure 36. FFT for 70-MHz Input Signal (Dither On) Figure 37. FFT for 70-MHz Input Signal (Dither Off) Figure 38. FFT for 170-MHz Input Signal (Dither On) Figure 39. FFT for 170-MHz Input Signal (Dither Off)

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differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted. Figure 46. FFT for Two-Tone Input Signal Figure 47. FFT for Two-Tone Input Signal Figure 48. Intermodulation Distortion vs Input Amplitude Figure 49. Intermodulation Distortion vs Input Amplitude Figure 50. Signal-to-Noise Ratio vs Input Frequency Figure 51. Spurious-Free Dynamic Range vs

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differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted. Figure 52. Signal-to-Noise Ratio vs Figure 53. Spurious-Free Dynamic Range vs Figure 54. Performance vs Input Amplitude (30 MHz) Figure 55. Performance vs Input Amplitude (170 MHz) Figure 56. Performance vs Input Common-Mode Voltage Figure 57. Performance vs Input Common-Mode Voltage

differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted. Figure 58. Spurious-Free Dynamic Range vs Figure 59. Signal-to-Noise Ratio vs Figure 60. Spurious-Free Dynamic Range vs Figure 61. Signal-to-Noise Ratio vs Figure 62. Performance vs Clock Amplitude (40 MHz) Figure 63. Performance vs Clock Amplitude (150 MHz)

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7.16 Typical Characteristics: ADC32J43

differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted. Figure 67. FFT for 10-MHz Input Signal (Dither On) Figure 68. FFT for 10-MHz Input Signal (Dither Off) Figure 69. FFT for 70-MHz Input Signal (Dither On) Figure 70. FFT for 70-MHz Input Signal (Dither Off) Figure 71. FFT for 170-MHz Input Signal (Dither On) Figure 72. FFT for 170-MHz Input Signal (Dither Off)

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differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted. Figure 79. FFT for Two-Tone Input Signal Figure 80. FFT for Two-Tone Input Signal Figure 81. Intermodulation Distortion vs Input Amplitude Figure 82. Intermodulation Distortion vs Input Amplitude Figure 83. Signal-to-Noise Ratio vs Input Frequency Figure 84. Spurious-Free Dynamic Range vs Input

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differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted. Figure 85. Signal-to-Noise Ratio vs Figure 86. Spurious-Free Dynamic Range vs Figure 87. Performance vs Input Amplitude (30 MHz) Figure 88. Performance vs Input Amplitude (170 MHz) Figure 89. Performance vs Input Common-Mode Voltage Figure 90. Performance vs Input Common-Mode Voltage

differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted. Figure 91. Spurious-Free Dynamic Range vs Figure 92. Signal-to-Noise Ratio vs Figure 93. Spurious-Free Dynamic Range vs Figure 94. Signal-to-Noise Ratio vs Figure 95. Performance vs Clock Amplitude (40 MHz) Figure 96. Performance vs Clock Amplitude (150 MHz)

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7.17 Typical Characteristics: ADC32J42

differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted. Figure 100. FFT for 10-MHz Input Signal (Dither On) Figure 101. FFT for 10-MHz Input Signal (Dither Off) Figure 102. FFT for 70-MHz Input Signal (Dither On) Figure 103. FFT for 70-MHz Input Signal (Dither Off) Figure 104. FFT for 170-MHz Input Signal (Dither On) Figure 105. FFT for 170-MHz Input Signal (Dither Off)

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differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted. Figure 112. FFT for Two-Tone Input Signal Figure 113. FFT for Two-Tone Input Signal Figure 114. Intermodulation Distortion vs Input Amplitude Figure 115. Intermodulation Distortion vs Input Amplitude Figure 116. Signal-to-Noise Ratio vs Input Frequency Figure 117. Spurious-Free Dynamic Range vs

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differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted. Figure 118. Signal-to-Noise Ratio vs Figure 119. Spurious-Free Dynamic Range vs Figure 120. Performance vs Input Amplitude (30 MHz) Figure 121. Performance vs Input Amplitude (170 MHz) Figure 122. Performance vs Input Common-Mode Voltage Figure 123. Performance vs Input Common-Mode Voltage

differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted. Figure 124. Spurious-Free Dynamic Range vs Figure 125. Signal-to-Noise Ratio vs Figure 126. Spurious-Free Dynamic Range vs Figure 127. Signal-to-Noise Ratio vs Figure 128. Performance vs Clock Amplitude (40 MHz) Figure 129. Performance vs Clock Amplitude (150 MHz)

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7.18 Typical Characteristics: Common Plots

differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted. Figure 134. CMRR vs Test Signal FrequencyFigure 133. CMRR FFT Figure 136. PSRR vs Test Signal FrequencyFigure 135. PSRR FFT for AVDD Supply Figure 137. Power vs Sampling Frequency 20X Mode Figure 138. Power vs Sampling Frequency 40X Mode

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7.19 Typical Characteristics: Contour Plots

32k-point FFT, unless otherwise noted. Figure 139. Spurious-Free Dynamic Range (SFDR) for Figure 140. Spurious-Free Dynamic Range (SFDR) for Figure 141. Signal-to-Noise Ratio (SNR) for Figure 142. Signal-to-Noise Ratio (SNR) for

8 Parameter Measurement Information

8.1 Timing Diagrams

(1) Overall latency = ADC latency + tD. (2) x = A for channel A and B for channel B. Figure 143. ADC Latency (1) x = A for channel A and B for channel B. Figure 144. SYNC~ Latency in CGS Phase

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CLKP, CLKM Configuration Registers SCLK SEN SDATA SDOUT RESET Common ModeVCM DAP, DAM SYSREFP, SYSREFM Divide by 1,2,4 INAP, INAM SYNCP, SYNCM DBP, DBM 14-Bit ADC 14-Bit ADC INBP, INBM Digital Encoder and JESD204B OVRA Digital Encoder and JESD204B OVRD PDN PLL ADC32J42,ADC32J43,ADC32J44,ADC32J45 SBAS663A –MAY 2014–REVISED JUNE 2015 www.ti.com

9 Detailed Description

9.1 Overview

The ADC32J4x are a high-linearity, ultra-low power, dual-channel, 14-bit, 50-MSPS to 160-MSPS, analog-to- digital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. A clock input divider allows more flexibility for system clock architecture design ans the SYSREF input enables complete system synchronization. The ADC32J4x family supports JESD204B interface in order to reduce the number of interface lines, thus allowing for high system integration density. The JESD204B interface is a serial interface, where the data of each ADC are serialized and output over only one differential pair. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock by 20 to derive the bit clock, which is used to serialize the 14-bit data from each channel. The ADC32J4x devices support subclass 0, 1, and 2 with interface data rates up to 3.2 Gbps.

9.2 Functional Block Diagram

9.3 Feature Description

9.3.1 Analog Inputs

The ADC32J4x analog signal inputs are designed to be driven differentially. Each input pin (INP, INM) must swing symmetrically between (VCM + 0.5 V) and (VCM – 0.5 V), resulting in a 2-VPP (default) differential input swing. The input sampling circuit has a 3-dB bandwidth that extends up to 450 MHz (50-Ω source driving a 50-Ω termination between INP and INM).

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Product Folder Links: ADC32J42 ADC32J43 ADC32J44 ADC32J45

0.1 F/c109Zo

0.1 F/c109

9.3.2 Clock Input

Figure 148, Figure 149, and Figure 150. See Figure 151 for details regarding the internal clock buffer. NOTE: RT = termination resistor, if necessary. Figure 148. Differential Sine-Wave Clock Driving Figure 149. LVDS Clock Driving Circuit Figure 150. LVPECL Clock Driving Circuit NOTE: CEQ is 1 pF to 3 pF and is the equivalent input capacitance of the clock buffer. Figure 151. Internal Clock Buffer

a clock source with very low jitter. Band-pass filtering of the clock source can help reduce the effects of jitter. There is no change in performance with a non-50% duty cycle clock input. Figure 152. Single-Ended Clock Driving Circuit

9.3.2.1 SNR and Clock Jitter

external jitter for different input frequencies, is shown in Figure 153. Figure 153. SNR vs Frequency and Jitter

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9.3.2.2 Input Clock Divider

divide-by-4 option supports a maximum input clock frequency of 640 MHz.

9.3.3 Power-Down Control

down or standby functionality, as shown in Table 2. Table 2. Power-Down Modes

9.3.4 Internal Dither Algorithm

Figure 155. FFT with Dither OffFigure 154. FFT with Dither On

9.3.5 JESD204B Interface

process allows synchronization of multiple devices in a system and minimizes timing and alignment uncertainty. Figure 156. JESD204B Interface the transport layer can be scrambled. Figure 157. JESD204B Block

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9.3.5.1 JESD204B Initial Lane Alignment (ILA)

9.3.5.2 JESD204B Test Patterns

9.3.5.3 JESD204B Frame Assembly

L is the number of lanes per link,
M is the number of converters per device,
F is the number of octets per frame clock period, and
S is the number of samples per frame. Table 3 lists the available JESD204B format and valid range for the ADC32J4x. The ranges are limited by the SERDES line rate and the maximum ADC sample frequency.

Table 3. LMFS Values and Interface Rate can be changed from 20X (default) to 40X by setting the registers listed in Table 4. Figure 158. JESD Frame Assembly Table 4. Configuring 40X Mode

9.3.5.4 Digital Outputs

Figure 159. CML Output Connections transmitter mask at 3.125 Gbps (156.25 MSPS, 20X mode), respectively. Figure 160. Eye Diagram: 3.125 Gbps

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9.4 Device Functional Modes

9.4.1 Digital Gain

Table 5. Digital Gain versus Full-Scale Amplitude

9.4.2 Overrange Indication

OVR indication can be presented on the overrange pins instead by using the SPI register map.

ADC32J42,ADC32J43,ADC32J44,ADC32J45 SBAS663A –MAY 2014–REVISED JUNE 2015 www.ti.com

9.5 Programming

The ADC32J4x can be configured using a serial programming interface, as described in this section.

9.5.1 Serial Interface

The device has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial interface enable), SCLK (serial interface clock), SDATA (serial interface data), and SDOUT (serial interface data output) pins. Serially shifting bits into the device is enabled when SEN is low. Serial data SDATA are latched at every SCLK rising edge when SEN is active (low). Serial data are loaded into the register at every 24th SCLK rising edge when SEN is low. When the word length exceeds a multiple of 24 bits, the excess bits are ignored. Data can be loaded in multiples of 24-bit words within a single active SEN pulse. The interface can function with SCLK frequencies from 20 MHz down to very low speeds (of a few hertz) and also with a non-50% SCLK duty cycle.

9.5.1.1 Register Initialization

After power-up, the internal registers must be initialized to their default values through a hardware reset by applying a high pulse on the RESET pin (of durations greater than 10 ns); see Figure 161. If required, the serial interface registers can be cleared during operation either: 1. Through a hardware reset, or 2. By applying a software reset. When using the serial interface, set the RESET bit (D0 in register address 06h) high. This setting initializes the internal registers to the default values and then self-resets the RESET bit low. In this case, the RESET pin is kept low.

9.5.1.1.1 Serial Register Write

The device internal register can be programmed with these steps: 1. Drive the SEN pin low, 2. Set the R/W bit to 0 (bit A15 of the 16-bit address), 3. Set bit A14 in the address field to 1, 4. Initiate a serial interface cycle by specifying the address of the register (A13 to A0) whose content must be written, and 5. Write the 8-bit data that are latched in on the SCLK rising edge.

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Product Folder Links: ADC32J42 ADC32J43 ADC32J44 ADC32J45

9.5.1.1.2 Serial Register Readout

The device includes a mode where the contents of the internal registers can be read back using the SDOUT pin.

Set the R/W bit (A15) to 1. This setting disables any further writes to the registers.
Set bit A14 in the address field to 1.
Initiate a serial interface cycle specifying the address of the register (A13 to A0) whose content must be read.
The device outputs the contents (D7 to D0) of the selected register on the SDOUT pin.
The external controller can latch the contents at the SCLK rising edge.
To enable register writes, reset the R/W register bit to 0.

the SDOUT pin at the SCLK falling edge with an approximate delay (tSD_DELAY) of 20 ns, as shown in Figure 163. Figure 162. Serial Register Read Timing Diagram Figure 163. SDOUT Timing Diagram

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9.5.2 Register Initialization

applying a high pulse on the RESET pin, as shown in Figure 164 and Table 7. Figure 164. Initialization of Serial Registers after Power-Up Table 7. Power-Up Timing

Through hardware reset, or
By applying a software reset. When using the serial interface, set the RESET bit (D0 in register address 06h)

high. This setting initializes the internal registers to the default values and then self-resets the RESET bit low. In this case, the RESET pin is kept low.

9.5.3 Start-Up Sequence

After power-up, the sequence described in Table 8 can be used to set up the ADC32J4x for basic operation. Table 8. Start-Up Settings Provide all supply voltages. There is no required power-supply sequence for1 —AVDD and DVDD.

2 Pulse a hardware reset (low to high to low) on pin 24 —

9.6 Register Maps

Table 9. Register Map Summary

13 LOW SPEED MODE 0 0 0 0 0 0 0

27 CLK DIV 0 0 0 0 0 0

30 OCTETS PER FRAME

34 SUBCLASSV 0 0 0 0 0

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9.6.1 Summary of Special Mode Registers

Table 10 lists the location, value, and functions of special mode registers in the device. Table 10. Special Modes Summary SPECIAL MODE 1 CHA 07h (bits 4-2) Use for improved HD3. SPECIAL MODE 2 CHA 422h (bits 1-0) Helps improve HD2.

9.6.2 Serial Register Descriptions

9.6.2.1 Register 01h (address = 01h)

Figure 165. Register 01h Table 11. Register 01h Field Descriptions bits with bits 5 and 3 of register 434h. bits with bits 5 and 3 of register 534h.

9.6.2.2 Register 03h (address = 03h)

Figure 166. Register 03h Table 12. Register 03h Field Descriptions Digital gain enable bit for channel A.

1 CHA GAINEN R/W 0h 0 = Digital gain disabled

9.6.2.3 Register 04h (address = 04h)

Figure 167. Register 04h Table 13. Register 04h Field Descriptions Digital gain enable bit for channel B.

1 CHB GAINEN R/W 0h 0 = Digital gain disabled

9.6.2.4 Register 06h (address = 06h)

Figure 168. Register 06h Table 14. Register 06h Field Descriptions This bit enables the test pattern selection for the digital outputs.

1 TEST PATTERN EN R/W 0h 0 = Normal operation

0 RESET R/W 0h This bit resets all internal registers to the default values and self-

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9.6.2.5 Register 07h (address = 07h)

Figure 169. Register 07h Table 15. Register 07h Field Descriptions

9.6.2.6 Register 08h (address = 08h)

Figure 170. Register 08h Table 16. Register 08h Field Descriptions

9.6.2.7 Register 09h (address = 09h)

Figure 171. Register 09h Table 17. Register 09h Field Descriptions This bit sets the digital output data format.

0 DATA FORMAT R/W 0h 0 = Twos complement

9.6.2.8 Register 0Ah (address = 0Ah)

Figure 172. Register 0Ah Table 18. Register 0Ah Field Descriptions programmed by the CUSTOM PATTERN register bits. 0110 = Deskew pattern: data are 3AAAh.

9.6.2.9 Register 0Bh (address = 0Bh)

Figure 173. Register 0Bh Table 19. Register 0Bh Field Descriptions programmed by the CUSTOM PATTERN register bits. 0110 = Deskew pattern: data are 3AAAh.

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9.6.2.10 Register 0Ch (address = 0Ch)

Figure 174. Register 0Ch Table 20. Register 0Ch Field Descriptions These bits set the digital gain for individual channels. Register3-0 CHA DIGITAL GAIN R/W 0h settings are listed in Table 21. Table 21. Channel Digital Gain

9.6.2.11 Register 0Dh (address = 0Dh)

Figure 175. Register 0Dh Table 22. Register 0Dh Field Descriptions These bits set the digital gain for the individual channels.7-4 CHB DIGITAL GAIN R/W 0h Register settings are listed in Table 21.

9.6.2.12 Register 0Eh (address = 0Eh)

Figure 176. Register 0Eh Table 23. Register 0Eh Field Descriptions 7-0 CUSTOM PATTERN[13:6] R/W 0h These bits set the custom pattern[13:6] for all channels.

9.6.2.13 Register 0Fh (address = 0Fh)

Figure 177. Register 0Fh Table 24. Register 0Fh Field Descriptions 7-2 CUSTOM PATTERN[5:0] R/W 0h These bits set the custom pattern[5:0] for all channels.

9.6.2.14 Register 13h (address = 13h)

Figure 178. Register 13h Table 25. Register 13h Field Descriptions Use this bit for sampling frequencies < 25 MSPS.

7 LOW SPEED MODE R/W 0h 0 = Normal operation

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9.6.2.15 Register 15h (address = 15h)

Figure 179. Register 15h Table 26. Register 15h Field Descriptions ADCs of both channels enter standby.

3 STANDBY R/W 0h 0 = Normal operation

2 GLOBAL PDN R/W 0h 0 = Normal operation

This bit disables the power-down control from the pin.

9.6.2.16 Register 27h (address = 27h)

Figure 180. Register 27h Table 27. Register 27h Field Descriptions Internal clock divider for the input sample clock.

9.6.2.17 Register 2Ah (address = 2Ah)

Figure 181. Register 2Ah Table 28. Register 2Ah Field Descriptions This bit sets the output pattern when SYNC~ is high. 2 LANE ALIGN R/W 0h JESD204B specification. 1 FRAME ALIGN R/W 0h JESD204B specification.

9.6.2.18 Register 2Bh (address = 2Bh)

Figure 182. Register 2Bh Table 29. Register 2Bh Field Descriptions Enable bit for the number of frames per multiframe.

1 CTRL K R/W 0h 0 = Default is 9 (20X mode) frames per multiframe

Enable bit for the number of octets per frame.

0 CTRL F R/W 0h 0 = 20X mode using one lane per ADC (default is F = 2)

9.6.2.19 Register 2Fh (address = 2Fh)

Figure 183. Register 2Fh Table 30. Register 2Fh Field Descriptions Scramble enable bit in the JESD204B interface.

7 SCRAMBLE EN R/W 0h 0 = Scrambling disabled

9.6.2.20 Register 30h (address = 30h)

Figure 184. Register 30h Table 31. Register 30h Field Descriptions These bits set the number of octets per frame (F).

9.6.2.21 Register 31h (address = 31h)

Figure 185. Register 31h Table 32. Register 31h Field Descriptions These bits set the number of frames per multiframe. For each mode, K must not be set to a lower value.

9.6.2.22 Register 34h (address = 34h)

Figure 186. Register 34h Table 33. Register 34h Field Descriptions

9.6.2.23 Register 3Ah (address = 3Ah)

Figure 187. Register 3Ah Table 34. Register 3Ah Field Descriptions JESD output buffer current selection.

9.6.2.24 Register 3Bh (address = 3Bh)

Figure 188. Register 3Bh Table 35. Register 3Bh Field Descriptions Table 36. PULSE DET MODES Register Settings

0 Don’t care 0 Allow all pulses to reset input clock dividers

1 Don’t care 0 Do not allow reset of analog clock dividers

9.6.2.25 Register 3Ch (address = 3Ch)

Figure 189. Register 3Ch Table 37. Register 3Ch Field Descriptions

7 FORCE LMFC COUNT R/W 0h 1 = Enables using a different starting value for the LMFC

9.6.2.26 Register 422h (address = 422h)

Figure 190. Register 422h Table 38. Register 422h Field Descriptions 1 SPECIAL MODE2 CHA W 1h Always write 1 for improved HD2 performance.

9.6.2.27 Register 434h (address = 434h)

Figure 191. Register 434h Table 39. Register 434h Field Descriptions Set this bit along with bits 5 and 4 of register 01h. improves by 0.5 dB at 70 MHz. Set this bit along with bits 5 and 4 of register 01h. improves by 0.5 dB at 70 MHz.

9.6.2.28 Register 522h (address = 522h)

Figure 192. Register 522h Table 40. Register 522h Field Descriptions 1 SPECIAL MODE2 CHB W 1h Always write 1 for better HD2 performance.

9.6.2.29 Register 534h (address = 534h)

Figure 193. Register 534 Table 41. Register 534 Field Descriptions Set this bit along with bits 3 and 2 of register 01h. improves by 0.5 dB at 70 MHz. Set this bit along with bits 3 and 2 of register 01h. improves by 0.5 dB at 70 MHz. validate and test their design implementation to confirm system functionality.

10.1 Application Information

Figure 195 show the impedance (Zin = Rin || Cin) across the ADC input pins. Figure 194. Differential Input Resistance, Rin Figure 195. Differential Input Capacitance, Cin

10.2 Typical Applications

10.2.1 Driving Circuit Design: Low Input Frequencies

Figure 196. Driving Circuit for Low Input Frequencies

10.2.1.1 Design Requirements

10.2.1.2 Detailed Design Procedure

optimized for low input frequencies. An external R-C-R filter using 50-Ω resistors and a 22-pF capacitor is used. With the series inductor (39 nH), this combination helps absorb the sampling glitches.

10.2.1.3 Application Curves

Figure 197 shows the performance obtained by using the circuit illustrated in Figure 196. Figure 197. FFT for 10-MHz Input Signal (Dither On)

10.2.2 Driving Circuit Design: Input Frequencies Between 100 MHz to 230 MHz

Figure 198. Driving Circuit for Mid-Range Input Frequencies (100 MHz < fIN < 230 MHz)

10.2.2.1 Design Requirements

See the Design Requirements section for further details.

10.2.2.2 Detailed Design Procedure

performance, as shown in Figure 198.

10.2.2.3 Application Curve

Figure 199 shows the performance obtained by using the circuit shown in Figure 198. Figure 199. FFT for 170-MHz Input Signal (Dither On)

10.2.3 Driving Circuit Design: Input Frequencies Greater than 230 MHz

Figure 200. Driving Circuit for High Input Frequencies (fIN > 230 MHz)

10.2.3.1 Design Requirements

See the Design Requirements section for further details.

10.2.3.2 Detailed Design Procedure

improvement in performance. However, a series resistance of 10 Ω can be used, as shown in Figure 200.

10.2.3.3 Application Curve

Figure 201 shows the performance obtained by using the circuit shown in Figure 200. Figure 201. FFT for 450-MHz Input Signal (Dither On)

11 Power-Supply Recommendations

requirements during device power-up. AVDD and DVDD can power up in any order.

12 Layout

12.1 Layout Guidelines

Analog inputs are located on opposite sides of the device pin out to ensure minimum crosstalk on the

as much as possible, as shown in the reference layout of Figure 202.

In the device pin out, the sampling clock is located on a side perpendicular to the analog inputs in order to
Keep digital outputs away from the analog inputs. When these digital outputs exit the pin out, the digital

must be matched in length to avoid skew among outputs.

At each power-supply pin (AVDD and DVDD), a 0.1-µF decoupling capacitor must be kept close to the

µF capacitors can be kept close to the supply source.

12.2 Layout Example

Figure 202. Typical Layout of the ADC32J4x Board

13 Device and Documentation Support

13.1 Related Links

tools and software, and quick access to sample or buy. Table 42. Related Links

13.2 Community Resources

solve problems with fellow engineers. contact information for technical support.

13.3 Trademarks

E2E is a trademark of Texas Instruments. PowerPAD is a trademark of Texas Instruments, Inc. All other trademarks are the property of their respective owners.

13.4 Electrostatic Discharge Caution

during storage or handling to prevent electrostatic damage to the MOS gates.

13.5 Glossary

This glossary lists and explains terms, acronyms, and definitions.

14 Mechanical, Packaging, and Orderable Information

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www.ti.com 21-Jul-2015 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples ADC32J42IRGZ25 ACTIVE VQFN RGZ 48 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 AZ32J42 ADC32J42IRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 AZ32J42 ADC32J42IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 AZ32J42 ADC32J42RGZT PREVIEW VQFN RGZ 48 TBD Call TI Call TI -40 to 85 ADC32J43IRGZ25 ACTIVE VQFN RGZ 48 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 AZ32J43 ADC32J43IRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 AZ32J43 ADC32J43IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 AZ32J43 ADC32J44IRGZ25 ACTIVE VQFN RGZ 48 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 AZ32J44 ADC32J44IRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 AZ32J44 ADC32J44IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 AZ32J44 ADC32J45IRGZ25 ACTIVE VQFN RGZ 48 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 AZ32J45 ADC32J45IRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 AZ32J45 ADC32J45IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 AZ32J45 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details.

www.ti.com 21-Jul-2015 Addendum-Page 2 TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 1-Jul-2015 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADC32J42IRGZR VQFN RGZ 48 2500 336.6 336.6 28.6 ADC32J42IRGZT VQFN RGZ 48 250 213.0 191.0 55.0 ADC32J43IRGZR VQFN RGZ 48 2500 336.6 336.6 28.6 ADC32J43IRGZT VQFN RGZ 48 250 213.0 191.0 55.0 ADC32J44IRGZR VQFN RGZ 48 2500 336.6 336.6 28.6 ADC32J44IRGZT VQFN RGZ 48 250 213.0 191.0 55.0 ADC32J45IRGZR VQFN RGZ 48 2500 336.6 336.6 28.6 ADC32J45IRGZT VQFN RGZ 48 250 213.0 191.0 55.0 PACKAGE MATERIALS INFORMATION www.ti.com 1-Jul-2015 Pack Materials-Page 2

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Product Information

ADC32J44IRGZT specifications and overview.

Summary

Dual-Channel, 14-Bit, 50-MSPS to 160-MSPS, Analog-to-Digital Converters

Description

Dual-Channel, 14-Bit, 50-MSPS to 160-MSPS, Analog-to-Digital Converters

Source title ADC32J44IRGZT Datasheet(PDF) - Texas Instruments

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