ADC3223IRGZT

ADC3221 TI | Alldatasheet

Document overview

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Technical content

Frequency (MHz) Amplitude (dBFS) 0 12.5 25 37.5 50 62.5 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 D201 Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. ADC3221,ADC3222,ADC3223,ADC3224 SBAS672B –JULY 2014–REVISED MARCH 2016 ADC322x Dual-Channel,12-Bit,25-MSPSto125-MSPS,Analog-to-DigitalConverters

1 Features

1• Dual Channel

• 12-Bit Resolution
• Single Supply: 1.8 V
• Serial LVDS Interface (SLVDS)
• Flexible Input Clock Buffer with Divide-by-1, -2, -4
• SNR = 70.2 dBFS, SFDR = 87 dBc at fIN = 70 MHz
• Ultra-Low Power Consumption: – 116 mW/Ch at 125 MSPS
• Channel Isolation: 105 dB
• Internal Dither and Chopper
• Support for Multi-Chip Synchronization
• Pin-to-Pin Compatible with 14-Bit Version
• Package: VQFN-48 (7 mm × 7 mm)

2 Applications

• Multi-Carrier, Multi-Mode Cellular Base Stations
• Radar and Smart Antenna Arrays
• Munitions Guidance
• Motor Control Feedback
• Network and Vector Analyzers
• Communications Test Equipment
• Nondestructive Testing
• Microwave Receivers
• Software-Defined Radios (SDRs)
• Quadrature and Diversity Radio Receivers
• Handheld Radio and Instrumentation

3 Description

The ADC322x are a high-linearity, ultra-low power, dual-channel, 12-bit, 25-MSPS to 125-MSPS, analog- to-digital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. An input clock divider allows more flexibility for system clock architecture design and the SYSREF input enables complete system synchronization. The ADC322x family supports serial low-voltage differential signaling (LVDS) in order to reduce the number of interface lines, thus allowing for high system integration density. The serial LVDS interface is two-wire, where each ADC data are serialized and output over two LVDS pairs. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock that is used to serialize the 12-bit output data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) ADC322x VQFN (48) 7.00 mm × 7.00 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. space space space space space space Performance at fS = 125 MSPS, fIN = 10 MHz (SNR = 70.6 dBFS, SFDR = 100 dBc)

ADC3221,ADC3222,ADC3223,ADC3224 SBAS672B –JULY 2014–REVISED MARCH 2016 www.ti.com Product Folder Links: ADC3221 ADC3222 ADC3223 ADC3224 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Table of Contents

14 Mechanical, Packaging, and Orderable

4 Revision History

Changes from Revision A (March 2015) to Revision B Page

• Changed SNR and Clock Jitter section: changed typical thermal noise value in description of and changed
• Changed Register Map Summary table: changed FLIP BITS to FLIP WIRE in register 04h, changed bit 7 in register

ADC3221,ADC3222,ADC3223,ADC3224 www.ti.com SBAS672B –JULY 2014–REVISED MARCH 2016 Product Folder Links: ADC3221 ADC3222 ADC3223 ADC3224 Submit Documentation FeedbackCopyright © 2014–2016, Texas Instruments Incorporated Changes from Original (July 2014) to Revision A Page

13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 FCLKP DCLKP DA0M DA0PSDATA AVDD CLKP SCLK GND DB1PVCM AVDD GND AVDD AVDD AVDD INAP AVDD INAM GND Pad (Back Side) GND DVDD GND DB1M DB0P DB0M GND DVDD PDN AVDD AVDD AVDD INBP INBM AVDD SYSREFM SYSREFP RESET SDOUT CLKM SEN AVDD DA1P FCLKM DA1M DCLKM DVDD GND DVDD ADC3221,ADC3222,ADC3223,ADC3224 SBAS672B –JULY 2014–REVISED MARCH 2016 www.ti.com Product Folder Links: ADC3221 ADC3222 ADC3223 ADC3224 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated

5 Device Comparison Table

(Bits) 25 MSPS 50 MSPS 80 MSPS 125 MSPS 160 MSPS Serial LVDS

12 ADC3221 ADC3222 ADC3223 ADC3224 —

14 ADC3241 ADC3242 ADC3243 ADC3244 —

12 — ADC32J22 ADC32J23 ADC32J24 ADC32J2x5 14 — ADC32J42 ADC32J43 ADC32J44 ADC32J45

6 Pin Configuration and Functions

ADC3221,ADC3222,ADC3223,ADC3224 www.ti.com SBAS672B –JULY 2014–REVISED MARCH 2016 Product Folder Links: ADC3221 ADC3222 ADC3223 ADC3224 Submit Documentation FeedbackCopyright © 2014–2016, Texas Instruments Incorporated Pin Functions PIN I/O DESCRIPTION NAME NO. AVDD 6-9, 12, 17, 20, 25, 28-30 I Analog 1.8-V power supply CLKM 18 I Negative differential clock input for the ADC CLKP 19 I Positive differential clock input for the ADC DA0M 48 O Negative serial LVDS output for channel A0 DA0P 47 O Positive serial LVDS output for channel A0 DA1M 46 O Negative serial LVDS output for channel A1 DA1P 45 O Positive serial LVDS output for channel A1 DB0M 40 O Negative serial LVDS output for channel B0 DB0P 39 O Positive serial LVDS output for channel B0 DB1M 38 O Negative serial LVDS output for channel B1 DB1P 37 O Positive serial LVDS output for channel B1 DCLKM 44 O Negative bit clock output DCLKP 43 O Positive bit clock output DVDD 2, 4, 33, 35 I Digital 1.8-V power supply FCLKM 42 O Negative frame clock output FCLKP 41 O Positive frame clock output GND 1, 3, 5, 32, 34, 36, PowerPAD™ I Ground, 0 V INAM 11 I Negative differential analog input for channel A INAP 10 I Positive differential analog input for channel A INBM 26 I Negative differential analog input for channel B INBP 27 I Positive differential analog input for channel B PDN 31 I Power-down control. This pin can be configured via the SPI. This pin has an internal 150-kΩ pull-down resistor. RESET 21 I Hardware reset; active high. This pin has an internal 150-kΩ pull-down resistor. SCLK 13 I Serial interface clock input. This pin has an internal 150-kΩ pull-down resistor. SDATA 14 I Serial interface data input. This pin has an internal 150-kΩ pull-down resistor. SDOUT 16 O Serial interface data output SEN 15 I Serial interface enable; active low. This pin has an internal 150-kΩ pull-up resistor to AVDD. SYSREFM 23 I Negative external SYSREF input SYSREFP 22 I Positive external SYSREF input VCM 24 O Common-mode voltage for analog inputs

ADC3221,ADC3222,ADC3223,ADC3224 SBAS672B –JULY 2014–REVISED MARCH 2016 www.ti.com Product Folder Links: ADC3221 ADC3222 ADC3223 ADC3224 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Analog supply voltage range, AVDD –0.3 2.1 V Digital supply voltage range, DVDD –0.3 2.1 V Voltage applied to input pins INAP, INBP, INAM, INBM –0.3 min (1.9, AVDD + 0.3) V CLKP, CLKM –0.3 AVDD + 0.3 SYSREFP, SYSREFM –0.3 AVDD + 0.3 SCLK, SEN, SDATA, RESET, PDN –0.3 3.9 Temperature Operating free-air, TA –40 85 °COperating junction, TJ 125 Storage, Tstg –65 150 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

7.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V (1) To reset the device for the first time after power-up, only use the RESET pin; see the Register Initialization section. (2) See Table 3 for details. (3) With the clock divider enabled by default for divide-by-1. Maximum sampling clock frequency for the divide-by-4 option is 500 MSPS.

7.3 Recommended Operating Conditions(1)

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT SUPPLIES AVDD Analog supply voltage range 1.7 1.8 1.9 V DVDD Digital supply voltage range 1.7 1.8 1.9 V ANALOG INPUT VID Differential input voltage For input frequencies < 450 MHz 2 VPP For input frequencies < 600 MHz 1 VIC Input common-mode voltage VCM ± 0.025 V CLOCK INPUT Input clock frequency Sampling clock frequency 15(2) 125(3) MSPS Input clock amplitude (differential) Sine wave, ac-coupled 0.2 1.5 VPPLVPECL, ac-coupled 1.6 LVDS, ac-coupled 0.7 Input clock duty cycle 35% 50% 65% Input clock common-mode voltage 0.95 V DIGITAL OUTPUTS CLOAD Maximum external load capacitance from each output pin to GND 3.3 pF RLOAD Differential load resistance placed externally 100 Ω

ADC3221,ADC3222,ADC3223,ADC3224 www.ti.com SBAS672B –JULY 2014–REVISED MARCH 2016 Product Folder Links: ADC3221 ADC3222 ADC3223 ADC3224 Submit Documentation FeedbackCopyright © 2014–2016, Texas Instruments Incorporated (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.4 Thermal Information

THERMAL METRIC(1) ADC322x UNITRGZ (VQFN)

48 PINS

RθJA Junction-to-ambient thermal resistance 25.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 18.9 °C/W RθJB Junction-to-board thermal resistance 3.0 °C/W ψJT Junction-to-top characterization parameter 0.2 °C/W ψJB Junction-to-board characterization parameter 3 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 0.5 °C/W

7.5 Electrical Characteristics: ADC3221, ADC3222

typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, maximum sampling rate, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input (unless otherwise noted) PARAMETER ADC3241 ADC3242 UNITMIN TYP MAX MIN TYP MAX ADC clock frequency 125 125 MSPS 1.8-V analog supply current 31 71 39 81 mA 1.8-V digital supply current 35 65 43 75 mA Total power dissipation 118 205 147 245 mW Global power-down dissipation 5 17 5 17 mW Standby power-down dissipation 78 103 78 103 mW

7.6 Electrical Characteristics: ADC3223, ADC3224

typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, maximum sampling rate, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input (unless otherwise noted) PARAMETER ADC3243 ADC3244 UNITMIN TYP MAX MIN TYP MAX ADC clock frequency 80 125 MSPS 1.8-V analog supply current 50 91 65 106 mA 1.8-V digital supply current 52 85 64 95 mA Total power dissipation 183 285 233 325 mW Global power-down dissipation 5 17 5 17 mW Standby power-down dissipation 72 103 78 103 mW

ADC3221,ADC3222,ADC3223,ADC3224 SBAS672B –JULY 2014–REVISED MARCH 2016 www.ti.com Product Folder Links: ADC3221 ADC3222 ADC3223 ADC3224 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated (1) Crosstalk is measured with a –1-dBFS input signal on one channel and no input on the other channel.

7.7 Electrical Characteristics: General

typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, maximum sampling rate, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RESOLUTION Resolution 12 Bits ANALOG INPUT Differential input full-scale 2.0 VPP RIN Input resistance Differential at dc 6.6 kΩ CIN Input capacitance Differential at dc 3.7 pF VOC(VCM) VCM common-mode voltage output 0.95 V VCM output current capability 10 mA Input common-mode current Per analog input pin 1.5 µA/MSPS Analog input bandwidth (3 dB) 50-Ω differential source driving 50-Ω termination across INP and INM 540 MHz DC ACCURACY EO Offset error –25 25 mV αEO Temperature coefficient of offset error ±0.024 mV/C EG(REF) Gain error as a result of internal reference inaccuracy alone –2% 2% EG(CHAN) Gain error of channel alone –2 %FS α(EGCHAN) Temperature coefficient of EG(CHAN) ±0.008 Δ%FS/°C CHANNEL-TO-CHANNEL ISOLATION Crosstalk(1) fIN = 10 MHz 105 dB fIN = 100 MHz 105 fIN = 200 MHz 105 fIN = 230 MHz 105 fIN = 300 MHz 105

ADC3221,ADC3222,ADC3223,ADC3224 www.ti.com SBAS672B –JULY 2014–REVISED MARCH 2016 Product Folder Links: ADC3221 ADC3222 ADC3223 ADC3224 Submit Documentation FeedbackCopyright © 2014–2016, Texas Instruments Incorporated (1) Reported from a 1-MHz offset.

7.8 AC Performance: ADC3221

typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 25 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input (unless otherwise noted) PARAMETER TEST CONDITIONS ADC3221 (fS = 25 MSPS) UNIT DITHER ON DITHER OFF MIN TYP MAX MIN TYP MAX DYNAMIC AC CHARACTERISTICS SNR Signal-to-noise ratio (from 1-MHz offset) fIN = 10 MHz 70.9 71.2 dBFS fIN = 20 MHz 68.5 70.8 71.1 fIN = 70 MHz 70.6 70.9 fIN = 100 MHz 70.3 70.6 fIN = 170 MHz 69.7 69.9 fIN = 230 MHz 68.8 69 Signal-to-noise ratio (full Nyquist band) fIN = 10 MHz 70.2 70.6 dBFS fIN = 20 MHz 70.2 70.5 fIN = 70 MHz 69.9 70.2 fIN = 100 MHz 69.6 69.9 fIN = 170 MHz 69.2 69.3 fIN = 230 MHz 68.2 68.4 NSD(1) Noise spectral density (averaged across Nyquist zone) fIN = 10 MHz –141.9 –142.2 dBFS/Hz fIN = 20 MHz –141.8 –139.5 –142.1 fIN = 70 MHz –141.6 –141.9 fIN = 100 MHz –141.3 –141.6 fIN = 170 MHz –140.7 –140.9 fIN = 230 MHz –139.8 –140.0 SINAD(1) Signal-to-noise and distortion ratio fIN = 10 MHz 70.9 71.1 dBFS fIN = 20 MHz 68.1 70.8 71 fIN = 70 MHz 70.6 70.7 fIN = 100 MHz 70.2 70.3 fIN = 170 MHz 69.6 69.6 fIN = 230 MHz 68.5 68.5 ENOB(1) Effective number of bits fIN = 10 MHz 11.5 11.5 Bits fIN = 20 MHz 11 11.5 11.5 fIN = 70 MHz 11.4 11.5 fIN = 100 MHz 11.4 11.4 fIN = 170 MHz 11.3 11.3 fIN = 230 MHz 11.1 11.1 SFDR Spurious-free dynamic range fIN = 10 MHz 96 88 dBc fIN = 20 MHz 82 93 89 fIN = 70 MHz 93 87 fIN = 100 MHz 85 82 fIN = 170 MHz 86 83 fIN = 230 MHz 81 80

ADC3221,ADC3222,ADC3223,ADC3224 SBAS672B –JULY 2014–REVISED MARCH 2016 www.ti.com Product Folder Links: ADC3221 ADC3222 ADC3223 ADC3224 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated AC Performance: ADC3221 (continued) typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 25 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input (unless otherwise noted) PARAMETER TEST CONDITIONS ADC3221 (fS = 25 MSPS) UNIT DITHER ON DITHER OFF MIN TYP MAX MIN TYP MAX HD2 Second-order harmonic distortion fIN = 10 MHz 106 97 dBc fIN = 20 MHz 82 102 95 fIN = 70 MHz 101 95 fIN = 100 MHz 95 93 fIN = 170 MHz 88 87 fIN = 230 MHz 81 81 HD3 Third-order harmonic distortion fIN = 10 MHz 96 88 dBc fIN = 20 MHz 82 93 92 fIN = 70 MHz 93 87 fIN = 100 MHz 85 82 fIN = 170 MHz 87 83 fIN = 230 MHz 82 80 Non HD2, HD3 Spurious-free dynamic range (excluding HD2, HD3) fIN = 10 MHz 99 92 dBc fIN = 20 MHz 87 101 91 fIN = 70 MHz 99 93 fIN = 100 MHz 98 92 fIN = 170 MHz 99 92 fIN = 230 MHz 97 93 THD Total harmonic distortion fIN = 10 MHz 94 85 dBc fIN = 20 MHz 80 92 85 fIN = 70 MHz 91 85 fIN = 100 MHz 86 82 fIN = 170 MHz 84 81 fIN = 230 MHz 78 77 IMD3 Two-tone, third-order intermodulation distortion fIN1 = 45 MHz, fIN2 = 50 MHz –95 –94 dBFS fIN1 = 185 MHz, fIN2 = 190 MHz –90 –89

ADC3221,ADC3222,ADC3223,ADC3224 www.ti.com SBAS672B –JULY 2014–REVISED MARCH 2016 Product Folder Links: ADC3221 ADC3222 ADC3223 ADC3224 Submit Documentation FeedbackCopyright © 2014–2016, Texas Instruments Incorporated (1) Reported from a 1-MHz offset.

7.9 AC Performance: ADC3222

typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input (unless otherwise noted) PARAMETER TEST CONDITIONS ADC3222 (fS = 50 MSPS) UNIT DITHER ON DITHER OFF MIN TYP MAX MIN TYP MAX DYNAMIC AC CHARACTERISTICS SNR Signal-to-noise ratio (from 1-MHz offset) fIN = 10 MHz 70.9 71.1 dBFS fIN = 20 MHz 68.5 70.9 71.1 fIN = 70 MHz 70.7 70.9 fIN = 100 MHz 70.5 70.7 fIN = 170 MHz 70 70.1 fIN = 230 MHz 69.3 69.6 Signal-to-noise ratio (full Nyquist band) fIN = 10 MHz 70.3 70.5 fIN = 20 MHz 70.1 70.3 fIN = 70 MHz 70.1 70.3 fIN = 100 MHz 69.9 70.2 fIN = 170 MHz 69.5 69.5 fIN = 230 MHz 68.7 69 NSD(1) Noise spectral density (averaged across Nyquist zone) fIN = 10 MHz –144.9 –145.1 dBFS/Hz fIN = 20 MHz –144.9 –142.5 –145.1 fIN = 70 MHz –144.7 –144.9 fIN = 100 MHz –144.5 –144.7 fIN = 170 MHz –144.0 –144.1 fIN = 230 MHz –143.3 –143.6 SINAD(1) Signal-to-noise and distortion ratio fIN = 10 MHz 70.8 71 dBFS fIN = 20 MHz 68 70.8 71 fIN = 70 MHz 70.6 70.8 fIN = 100 MHz 70.4 70.6 fIN = 170 MHz 69.8 69.9 fIN = 230 MHz 69 69.1 ENOB(1) Effective number of bits fIN = 10 MHz 11.5 11.5 Bits fIN = 20 MHz 11 11.5 11.5 fIN = 70 MHz 11.4 11.5 fIN = 100 MHz 11.4 11.4 fIN = 170 MHz 11.3 11.3 fIN = 230 MHz 11.2 11.2 SFDR Spurious-free dynamic range fIN = 10 MHz 89 95 dBc fIN = 20 MHz 82 95 91 fIN = 70 MHz 95 93 fIN = 100 MHz 88 86 fIN = 170 MHz 85 83 fIN = 230 MHz 82 81

ADC3221,ADC3222,ADC3223,ADC3224 SBAS672B –JULY 2014–REVISED MARCH 2016 www.ti.com Product Folder Links: ADC3221 ADC3222 ADC3223 ADC3224 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated AC Performance: ADC3222 (continued) typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input (unless otherwise noted) PARAMETER TEST CONDITIONS ADC3222 (fS = 50 MSPS) UNIT DITHER ON DITHER OFF MIN TYP MAX MIN TYP MAX HD2 Second-order harmonic distortion fIN = 10 MHz 103 97 dBc fIN = 20 MHz 82 100 94 fIN = 70 MHz 97 94 fIN = 100 MHz 94 93 fIN = 170 MHz 89 89 fIN = 230 MHz 83 83 HD3 Third-order harmonic distortion fIN = 10 MHz 89 96 dBc fIN = 20 MHz 82 94 95 fIN = 70 MHz 95 93 fIN = 100 MHz 88 86 fIN = 170 MHz 85 83 fIN = 230 MHz 83 81 Non HD2, HD3 Spurious-free dynamic range (excluding HD2, HD3) fIN = 10 MHz 99 95 dBc fIN = 20 MHz 87 101 93 fIN = 70 MHz 99 94 fIN = 100 MHz 100 94 fIN = 170 MHz 99 93 fIN = 230 MHz 97 93 THD Total harmonic distortion fIN = 10 MHz 89 89 dBc fIN = 20 MHz 80 93 87 fIN = 70 MHz 92 88 fIN = 100 MHz 90 86 fIN = 170 MHz 83 81 fIN = 230 MHz 80 78 IMD3 Two-tone, third-order intermodulation distortion fIN1 = 45 MHz, fIN2 = 50 MHz –95 –92 dBFS fIN1 = 185 MHz, fIN2 = 190 MHz –92 –92

ADC3221,ADC3222,ADC3223,ADC3224 www.ti.com SBAS672B –JULY 2014–REVISED MARCH 2016 Product Folder Links: ADC3221 ADC3222 ADC3223 ADC3224 Submit Documentation FeedbackCopyright © 2014–2016, Texas Instruments Incorporated (1) Reported from a 1-MHz offset.

7.10 AC Performance: ADC3223

typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input (unless otherwise noted) PARAMETER TEST CONDITIONS ADC3223 (fS = 80 MSPS) UNIT DITHER ON DITHER OFF MIN TYP MAX MIN TYP MAX DYNAMIC AC CHARACTERISTICS SNR Signal-to-noise ratio (from 1-MHz offset) fIN = 10 MHz 70.7 70.9 dBFS fIN = 70 MHz 68.5 70.6 70.8 fIN = 100 MHz 70.5 70.7 fIN = 170 MHz 70.1 70.3 fIN = 230 MHz 69.7 69.9 Signal-to-noise ratio (full Nyquist band) fIN = 10 MHz 70.3 70.5 fIN = 70 MHz 70.2 70.5 fIN = 100 MHz 70.1 70.4 fIN = 170 MHz 69.7 69.9 fIN = 230 MHz 69.4 69.6 NSD(1) Noise spectral density (averaged across Nyquist zone) fIN = 10 MHz –146.7 –146.9 dBFS/Hz fIN = 70 MHz –146.6 –144.5 –146.8 fIN = 100 MHz –146.5 –146.7 fIN = 170 MHz –146.1 –146.3 fIN = 230 MHz –145.7 –145.9 SINAD(1) Signal-to-noise and distortion ratio fIN = 10 MHz 70.7 70.9 dBFS fIN = 70 MHz 68.1 70.6 70.8 fIN = 100 MHz 70.5 70.6 fIN = 170 MHz 70 70.2 fIN = 230 MHz 69.5 69.6 ENOB(1) Effective number of bits fIN = 10 MHz 11.4 11.5 Bits fIN = 70 MHz 11.02 11.4 11.5 fIN = 100 MHz 11.4 11.4 fIN = 170 MHz 11.3 11.4 fIN = 230 MHz 11.3 11.3 SFDR Spurious-free dynamic range fIN = 10 MHz 88 95 dBc fIN = 70 MHz 82 94 93 fIN = 100 MHz 93 92 fIN = 170 MHz 88 87 fIN = 230 MHz 85 84

ADC3221,ADC3222,ADC3223,ADC3224 SBAS672B –JULY 2014–REVISED MARCH 2016 www.ti.com Product Folder Links: ADC3221 ADC3222 ADC3223 ADC3224 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated AC Performance: ADC3223 (continued) typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input (unless otherwise noted) PARAMETER TEST CONDITIONS ADC3223 (fS = 80 MSPS) UNIT DITHER ON DITHER OFF MIN TYP MAX MIN TYP MAX HD2 Second-order harmonic distortion fIN = 10 MHz 104 99 dBc fIN = 70 MHz 82 95 94 fIN = 100 MHz 95 93 fIN = 170 MHz 88 87 fIN = 230 MHz 85 85 HD3 Third-order harmonic distortion fIN = 10 MHz 89 95 dBc fIN = 70 MHz 82 94 94 fIN = 100 MHz 95 96 fIN = 170 MHz 93 90 fIN = 230 MHz 89 85 Non HD2, HD3 Spurious-free dynamic range (excluding HD2, HD3) fIN = 10 MHz 94 93 dBc fIN = 70 MHz 87 100 95 fIN = 100 MHz 99 96 fIN = 170 MHz 99 95 fIN = 230 MHz 98 95 THD Total harmonic distortion fIN = 10 MHz 88 91 dBc fIN = 70 MHz 79.5 91 89 fIN = 100 MHz 91 88 fIN = 170 MHz 86 84 fIN = 230 MHz 83 81 IMD3 Two-tone, third-order intermodulation distortion fIN1 = 45 MHz, fIN2 = 50 MHz –94 –94 dBFS fIN1 = 185 MHz, fIN2 = 190 MHz –92 –90

ADC3221,ADC3222,ADC3223,ADC3224 www.ti.com SBAS672B –JULY 2014–REVISED MARCH 2016 Product Folder Links: ADC3221 ADC3222 ADC3223 ADC3224 Submit Documentation FeedbackCopyright © 2014–2016, Texas Instruments Incorporated (1) Reported from a 1-MHz offset.

7.11 AC Performance: ADC3224

typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input (unless otherwise noted) PARAMETER TEST CONDITIONS ADC3224 (fS = 125 MSPS) UNIT DITHER ON DITHER OFF MIN TYP MAX MIN TYP MAX DYNAMIC AC CHARACTERISTICS SNR Signal-to-noise ratio (from 1-MHz offset) fIN = 10 MHz 70.5 70.8 dBFS fIN = 70 MHz 68.5 70.4 70.7 fIN = 100 MHz 70.3 70.6 fIN = 170 MHz 69.9 70.2 fIN = 230 MHz 69.4 69.8 Signal-to-noise ratio (full Nyquist band) fIN = 10 MHz 70.3 70.6 fIN = 70 MHz 70.2 70.5 fIN = 100 MHz 70.2 70.4 fIN = 170 MHz 69.7 70.0 fIN = 230 MHz 69.2 69.6 NSD(1) Noise spectral density (averaged across Nyquist zone) fIN = 10 MHz –148.5 –148.8 dBFS/Hz fIN = 70 MHz –148.4 –146.5 –148.7 fIN = 100 MHz –148.3 –148.6 fIN = 170 MHz –147.9 –148.2 fIN = 230 MHz –147.4 –147.8 SINAD(1) Signal-to-noise and distortion ratio fIN = 10 MHz 70.5 70.6 dBFS fIN = 70 MHz 68 70.4 70.6 fIN = 100 MHz 70.2 70.3 fIN = 170 MHz 69.7 69.9 fIN = 230 MHz 69.2 69.5 ENOB(1) Effective number of bits fIN = 10 MHz 11.4 11.4 Bits fIN = 70 MHz 11 11.4 11.4 fIN = 100 MHz 11.4 11.4 fIN = 170 MHz 11.3 11.3 fIN = 230 MHz 11.2 11.2 SFDR Spurious-free dynamic range fIN = 10 MHz 93 87 dBc fIN = 70 MHz 82 95 89 fIN = 100 MHz 89 86 fIN = 170 MHz 86 85 fIN = 230 MHz 83 83

ADC3221,ADC3222,ADC3223,ADC3224 SBAS672B –JULY 2014–REVISED MARCH 2016 www.ti.com Product Folder Links: ADC3221 ADC3222 ADC3223 ADC3224 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated AC Performance: ADC3224 (continued) typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input (unless otherwise noted) PARAMETER TEST CONDITIONS ADC3224 (fS = 125 MSPS) UNIT DITHER ON DITHER OFF MIN TYP MAX MIN TYP MAX HD2 Second-order harmonic distortion fIN = 10 MHz 96 96 dBc fIN = 70 MHz 84 96 96 fIN = 100 MHz 91 91 fIN = 170 MHz 86 85 fIN = 230 MHz 83 83 HD3 Third-order harmonic distortion fIN = 10 MHz 94 87 dBc fIN = 70 MHz 82 95 89 fIN = 100 MHz 91 86 fIN = 170 MHz 96 89 fIN = 230 MHz 88 85 Non HD2, HD3 Spurious-free dynamic range (excluding HD2, HD3) fIN = 10 MHz 99 96 dBc fIN = 70 MHz 87 99 95 fIN = 100 MHz 99 95 fIN = 170 MHz 99 92 fIN = 230 MHz 97 92 THD Total harmonic distortion fIN = 10 MHz 91 85 dBc fIN = 70 MHz 80 91 86 fIN = 100 MHz 87 83 fIN = 170 MHz 85 82 fIN = 230 MHz 82 80 IMD3 Two-tone, third-order intermodulation distortion fIN1 = 45 MHz, fIN2 = 50 MHz –96 –95 dBFS fIN1 = 185 MHz, fIN2 = 190 MHz –92 –88

ADC3221,ADC3222,ADC3223,ADC3224 www.ti.com SBAS672B –JULY 2014–REVISED MARCH 2016 Product Folder Links: ADC3221 ADC3222 ADC3223 ADC3224 Submit Documentation FeedbackCopyright © 2014–2016, Texas Instruments Incorporated (1) SEN has an internal 150-kΩ pull-up resistor to AVDD. SPI pins (SEN, SCLK, SDATA) can be driven by 1.8-V or 3.3-V CMOS buffers.

7.12 Digital Characteristics

the dc specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level 0 or 1; AVDD = DVDD = 1.8 V, and –1-dBFS differential input (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL INPUTS (RESET, SCLK, SDATA, SEN, PDN) VIH High-level input voltage All digital inputs support 1.8-V and 3.3-V CMOS logic levels 1.3 V VIL Low-level input voltage All digital inputs support 1.8-V and 3.3-V CMOS logic levels 0.4 V IIH High-level input current RESET, SDATA, SCLK, PDN VHIGH = 1.8 V 10 µA SEN(1) VHIGH = 1.8 V 0 IIL Low-level input current RESET, SDATA, SCLK, PDN VLOW = 0 V 0 µA SEN VLOW = 0 V 10 DIGITAL INPUTS (SYSREFP, SYSREFM) VIH High-level input voltage 1.3 V VIL Low-level input voltage 0.5 V Common-mode voltage for SYSREF 0.9 V DIGITAL OUTPUTS, CMOS INTERFACE (SDOUT) VOH High-level output voltage DVDD – 0.1 DVDD V VOL Low-level output voltage 0 0.1 V DIGITAL OUTPUTS, LVDS INTERFACE VODH High-level output differential voltage With an external 100-Ω termination 280 350 460 mV VODL Low-level output differential voltage With an external 100-Ω termination –460 –350 –280 mV VOCM Output common-mode voltage 1.05 V (1) Overall latency = ADC latency + tPDI.

7.13 Timing Requirements: General

typical values are at TA = 25°C, AVDD = DVDD = 1.8 V, and –1-dBFS differential input (unless otherwise noted); minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = 85°C MIN TYP MAX UNIT tA Aperture delay 1.24 1.44 1.64 ns Aperture delay matching between two channels of the same device ±70 ps Aperture delay variation between two devices at same temperature and supply voltage ±150 ps tJ Aperture jitter 130 fS rms Wake-up time Time to valid data after exiting standby power-down mode 35 65 µsTime to valid data after exiting global power-down mode (in this mode, both channels power down) 85 140 ADC latency(1) 2-wire mode (default) 9 Clock cycles1-wire mode 8 tSU_SYSREF SYSREF reference time Setup time for SYSREF referenced to input clock rising edge 1000 ps tH_SYSREF Hold time for SYSREF referenced to input clock rising edge 100

(1) CLOAD is the effective external single-ended load capacitance between each output pin and ground. (2) RLOAD is the differential load resistance between the LVDS output pair. specifications take into account the effect of jitter on the output data and clock. (4) Timing parameters are ensured by design and characterization and are not tested in production. (5) Data valid refers to a logic high of 100 mV and a logic low of –100 mV.

7.14 Timing Requirements: LVDS Output

Table 1. LVDS Timing at Lower Sampling Frequencies: 6X Serialization (2-Wire Mode) Table 2. LVDS Timings at Lower Sampling Frequencies: 12X Serialization (1-Wire Mode)

7.15 Typical Characteristics: ADC3221

Figure 1. FFT for 10-MHz Input Signal (Dither On) Figure 2. FFT for 10-MHz Input Signal (Dither Off) Figure 3. FFT for 70-MHz Input Signal (Dither On) Figure 4. FFT for 70-MHz Input Signal (Dither Off) Figure 5. FFT for 170-MHz Input Signal (Dither On) Figure 6. FFT for 170-MHz Input Signal (Dither Off)

7.16 Typical Characteristics: ADC3222

Figure 31. FFT for 10-MHz Input Signal (Dither On) Figure 32. FFT for 10-MHz Input Signal (Dither Off) Figure 33. FFT for 70-MHz Input Signal (Dither On) Figure 34. FFT for 70-MHz Input Signal (Dither Off) Figure 35. FFT for 170-MHz Input Signal (Dither On) Figure 36. FFT for 170-MHz Input Signal (Dither Off)

7.17 Typical Characteristics: ADC3223

Figure 61. FFT for 10-MHz Input Signal (Dither On) Figure 62. FFT for 10-MHz Input Signal (Dither Off) Figure 63. FFT for 70-MHz Input Signal (Dither On) Figure 64. FFT for 70-MHz Input Signal (Dither Off) Figure 65. FFT for 170-MHz Input Signal (Dither On) Figure 66. FFT for 170-MHz Input Signal (Dither Off)

7.18 Typical Characteristics: ADC3224

Figure 91. FFT for 10 MHz Input Signal Figure 92. FFT for 10-MHz Input Signal Figure 93. FFT for 70-MHz Input Signal (Dither On) Figure 94. FFT for 70-MHz Input Signal (Dither Off) Figure 95. FFT for 170-MHz Input Signal (Dither On) Figure 96. FFT for 170 MHz Input Signal (Dither Off)

7.19 Typical Characteristics: Common

Figure 121. Common-Mode Rejection Ratio vs Figure 122. Common-Mode Rejection Ratio Spectrum Figure 123. Power-Supply Rejection Ratio vs Figure 124. Power-Supply Rejection Ratio Spectrum Figure 125. Power vs Sampling Speed

7.20 Typical Characteristics: Contour

Figure 126. Spurious-Free Dynamic Range (SFDR) Figure 127. Signal-to-Noise Ratio (SNR)

8 Parametric Measurement Information

8.1 Timing Diagrams

(1) With an external 100-Ω termination. Figure 128. Serial LVDS Output Voltage Levels Figure 129. Output Timing Diagram

1,2,4 INBP INBM 12-Bit ADC PLL 12-Bit ADC FCLKP FCLKM DCLKP DCLKM Bit Clock Frame Clock DB1P DB1M DB0P DB0M Digital Encoder and Serializer Configuration Registers SCLK SEN SDATA SDOUT RESET Common ModeVCM PDN ADC3221,ADC3222,ADC3223,ADC3224 www.ti.com SBAS672B –JULY 2014–REVISED MARCH 2016 Product Folder Links: ADC3221 ADC3222 ADC3223 ADC3224 Submit Documentation FeedbackCopyright © 2014–2016, Texas Instruments Incorporated

9 Detailed Description

9.1 Overview

The ADC322x are a high-linearity, ultra-low power, dual-channel, 12-bit, 25-MSPS to 125-MSPS, analog-to- digital converter (ADC) family. The ADC322x runs off of a single 1.8-V supply and supports system synchronization though the SYSREF pin. Output data are available in standard LVDS format accompanied with bit-clock and frame-clock outputs.

9.2 Functional Block Diagram

0.1 F/c109Zo

0.1 F/c109

9.3 Feature Description

9.3.1 Analog Inputs

symmetrically between (VCM + 0.5 V) and (VCM – 0.5 V), resulting in a 2-VPP (default) differential input swing. termination between INP and INM).

9.3.2 Clock Input

Figure 132, Figure 133, and Figure 134. See Figure 135 for details regarding the internal clock buffer. RT = termination resistor, if necessary. Figure 132. Differential Sine-Wave Clock Driving Figure 133. LVDS Clock Driving Circuit Figure 134. LVPECL Clock Driving Circuit

NOTE: CEQ is 1 pF to 3 pF and is the equivalent input capacitance of the clock buffer. Figure 135. Internal Clock Buffer a clock source with very low jitter. Band-pass filtering of the clock source can help reduce the effects of jitter. There is no change in performance with a non-50% duty cycle clock input. Figure 136. Single-Ended Clock Driving Circuit

9.3.2.1 SNR and Clock Jitter

SNR for higher input frequencies. The SNR limitation resulting from sample clock jitter can be calculated with Equation 2. the noise of the clock input buffer, and the external clock. TJitter can be calculated with Equation 3.

(1) Use the LOW SPEED ENABLE register bits for low speed operation; see Table 22. noise) for different jitter of clock driver. Figure 137. SNR vs Frequency for Different Clock Jitter

9.3.3 Digital Output Interface

• One-wire, 1X frame clock, 12X serialization with the DDR bit clock and
• Two-wire, 1X frame clock, 6X serialization with the DDR bit clock.

Table 3. Interface Rates

9.3.3.1 One-Wire Interface: 12X Serialization

9.3.3.2 Two-Wire Interface: 6X Serialization

Figure 138. Output Timing Diagram

9.4 Device Functional Modes

9.4.1 Input Clock Divider

divide-by-4 option provides a maximum input clock frequency of 500 MHz.

9.4.2 Chopper Functionality

function creates a spur at fS / 2 that must be filtered out digitally. Figure 139. Chopper Off Figure 140. Chopper On

9.4.3 Power-Down Control

power-down or standby functionality, as shown in Table 4. Table 4. Power-Down Modes

9.4.3.1 Improving Wake-Up Time From Global Power-Down

from a global power-down from 85 µs to 55 µs. Table 5. Wake-Up Time From Global Power-Down

9.4.4 Internal Dither Algorithm

Figure 141. FFT with Dither On Figure 142. FFT Dither Off

9.5 Programming

The ADC322x can be configured using a serial programming interface, as described in this section.

9.5.1 Serial Interface

9.5.1.1 Register Initialization

1. Through a hardware reset, or
2. By applying a software reset. When using the serial interface, set the RESET bit (D0 in register address 06h)

high. This setting initializes the internal registers to the default values and then self-resets the RESET bit low. In this case, the RESET pin is kept low.

9.5.1.1.1 Serial Register Write

1. Set the R/W bit to 0 (bit A15 of the 16-bit address),
2. Set bit A14 in the address field to 1,
3. Initiate a serial interface cycle by specifying the address of the register (A13 to A0) whose content must be
4. Write the 8-bit data that are latched in on the SCLK rising edge.

Figure 143 and Table 6 show the timing requirements for the serial register write operation. Figure 143. Serial Register Write Timing Diagram Table 6. Serial Interface Timing(1)

9.5.1.1.2 Serial Register Readout

The device includes a mode where the contents of the internal registers can be read back using the SDOUT pin.

1. Set the R/W bit (A15) to 1. This setting disables any further writes to the registers.
2. Set bit A14 in the address field to 1.
3. Initiate a serial interface cycle specifying the address of the register (A[13:0]) whose content must be read.
4. The device outputs the contents (D[7:0]) of the selected register on the SDOUT pin.
5. The external controller can latch the contents at the SCLK rising edge.
6. To enable register writes, reset the R/W register bit to 0.

the SDOUT pin at the SCLK falling edge with an approximate delay (tSD_DELAY) of 20 ns, as shown in Figure 145. Figure 144. Serial Register Read Timing Diagram Figure 145. SDOUT Timing Diagram

9.5.2 Register Initialization

applying a high pulse on the RESET pin, as shown in Figure 146 and Table 7. Figure 146. Initialization of Serial Registers after Power-Up Table 7. Power-Up Timing

1. Through a hardware reset, or
2. By applying a software reset. When using the serial interface, set the RESET bit (D0 in register address 06h)

high. This setting initializes the internal registers to the default values and then self-resets the RESET bit low. In this case, the RESET pin is kept low.

9.6 Register Maps

Table 8. Register Map Summary

9.6.1 Summary of Special Mode Registers

Table 9 lists the location, value, and functions of special mode registers in the device. Table 9. Special Modes Summary

9.6.2 Serial Register Description

9.6.2.1 Register 01h

Figure 147. Register 01h Table 10. Register 01h Description These bits enable or disable the on-chip dither. Control this bit with bits 5 and 3 of register 434h. improves by 0.2 dB at 70 MHz. These bits enable or disable the on-chip dither. Control this bit with bits 5 and 3 of register 434h. improves by 0.2 dB at 70 MHz.

9.6.2.2 Register 03h

Figure 148. Register 03h Table 11. Register 03h Description

0 ODD EVEN R/W 0h

9.6.2.3 Register 04h

Figure 149. Register 04h Table 12. Register 04h Description

0 FLIP WIRE R/W 0h

9.6.2.4 Register 05h

Figure 150. Register 05h Table 13. Register 05h Description This bit transmits output data on either one or two wires. mode, the recommended fS is less than 62.5 MSPS.

9.6.2.5 Register 06h

Figure 151. Register 06h Table 14. Register 06h Description

1 TEST PATTERN EN R/W 0h

This bit enables test pattern selection for the digital outputs.

0 RESET W 0h

This bit applies a software reset.

9.6.2.6 Register 07h

Figure 152. Register 07h Table 15. Register 07h Description

0 OVR ON LSB R/W 0h

This bit provides the overrange (OVR) information on the LSB bits. 1 = Output data bit 0 carries the OVR information.

9.6.2.7 Register 09h

Figure 153. Register 09h Table 16. Register 09h Description

1 ALIGN TEST PATTERN R/W 0h

This bit aligns the test patterns across the outputs of both channels.

0 DATA FORMAT R/W 0h

This bit programs the digital output data format.

9.6.2.8 Register 0Ah

Figure 154. Register 0Ah Table 17. Register 0Ah Description

9.6.2.9 Register 0Bh

Figure 155. Register 0Bh Table 18. Register 0Bh Description

9.6.2.10 Register 0Eh

Figure 156. Register 0Eh Table 19. Register 0Eh Description 7-0 CUSTOM PATTERN[11:4] R/W 0h These bits set the 12-bit custom pattern (bits 11-4) for all channels.

9.6.2.11 Register 0Fh

Figure 157. Register 0Fh Table 20. Register 0Fh Description 7-4 CUSTOM PATTERN[3:0] R/W 0h These bits set the 12-bit custom pattern (bits 3-0) for all channels.

9.6.2.12 Register 13h

Figure 158. Register 13h Table 21. Register 13h Description upon sampling frequency, write this bit as per Table 22. Table 22. LOW SPEED ENABLE Register Bit Settings Across fS

9.6.2.13 Register 15h

Figure 159. Register 15h

0 CHA PDN CHB PDN 0 STANDBY GLOBAL PDN 0 CONFIG PDN PIN

Table 23. Register 15h Description

6 CHA PDN R/W 0h 0 = Normal operation

5 CHB PDN R/W 0h 0 = Normal operation

3 STANDBY R/W 0h

The ADCs of both channels enter standby.

2 GLOBAL PDN R/W 0h 0 = Normal operation

0 CONFIG PDN PIN R/W 0h

9.6.2.14 Register 25h

Figure 160. Register 25h Table 24. Register 25h Description Table 25. LVDS Output Swing

9.6.2.15 Register 27h

Figure 161. Register 27h Table 26. Register 27h Description These bits set the internal clock divider for the input sampling clock.

9.6.2.16 Register 41Dh

Figure 162. Register 41Dh Table 27. Register 41Dh Description

1 HIGH IF MODE0 R/W 0h

This bit improves HD3 for IF > 100 MHz. For best HD3 at IF > 100 MHz, set HIGH IF MODE[3:0] to 1111.

9.6.2.17 Register 422h

Figure 163. Register 422h Table 28. Register 422h Description

1 DIS CHOP CHA R/W 0h

Set this bit to shift a 1/f noise floor at dc.

9.6.2.18 Register 434h

Figure 164. Register 434h Table 29. Register 434h Description

5 DIS DITH CHA R/W 0h

Set this bit with bits 5 and 4 of register 01h. improves by 0.5 dB at 70 MHz.

3 DIS DITH CHA R/W 0h

Set this bit with bits 5 and 4 of register 01h. improves by 0.5 dB at 70 MHz.

9.6.2.19 Register 439h

Figure 165. Register 439h Table 30. Register 439h Description 3 SP1 CHA R/W 0h Special mode for best performance on channel A.

9.6.2.20 Register 51Dh

Figure 166. Register 51Dh Table 31. Register 51Dh Description

1 HIGH IF MODE1 R/W 0h

This bit improves HD3 for IF > 100 MHz. For best HD3 at IF > 100 MHz, set HIGH IF MODE[3:0] to 1111.

9.6.2.21 Register 522h

Figure 167. Register 522h Table 32. Register 522h Description

1 DIS CHOP CHB R/W 0h

Set this bit to shift a 1/f noise floor at dc.

9.6.2.22 Register 534h

Figure 168. Register 534h Table 33. Register 534h Description Set this bit with bits 3 and 2 of register 01h. improves by 0.5 dB at 70 MHz. Set this bit with bits 3 and 2 of register 01h. improves by 0.5 dB at 70 MHz.

9.6.2.23 Register 539h

Figure 169. Register 539h Table 34. Register 539h Description 3 SP1 CHB R/W 0h Special mode for best performance on channel B.

9.6.2.24 Register 608h

Figure 170. Register 608h Table 35. Register 608h Description This bit improves HD3 for IF > 100 MHz. For best HD3 at IF > 100 MHz, set HIGH IF MODE[3:0] to 1111.

9.6.2.25 Register 70Ah

Figure 171. Register 70Ah Table 36. Register 70Ah Description

7 DIS CLK FILT R/W 0h

0 PDN SYSREF R/W 0h

buffer must be powered down by setting this bit.

10 Applications and Implementation

validate and test their design implementation to confirm system functionality.

10.1 Application Information

Figure 173 show the impedance (Zin = Rin || Cin) across the ADC input pins. Figure 172. Differential Input Resistance (RIN) Figure 173. Differential Input Capacitance (CIN)

10.2 Typical Applications

10.2.1 Driving Circuit Design: Low Input Frequencies

Figure 174. Driving Circuit for Low Input Frequencies

10.2.1.1 Design Requirements

10.2.1.2 Detailed Design Procedure

with the series inductor (39 nH); this combination helps absorb the sampling glitches.

10.2.1.3 Application Curve

Figure 175 shows the performance obtained by using the circuit shown in Figure 174. Figure 175. Performance FFT at 10 MHz (Low Input Frequency)

10.2.2 Driving Circuit Design: Input Frequencies Between 100 MHz to 230 MHz

Figure 176. Driving Circuit for Mid-Range Input Frequencies (100 MHz < fIN < 230 MHz)

10.2.2.1 Design Requirements

See the Design Requirements section for further details.

10.2.2.2 Detailed Design Procedure

performance, as shown in Figure 176.

10.2.2.3 Application Curve

Figure 177 shows the performance obtained by using the circuit shown in Figure 176. Figure 177. Performance FFT at 170 MHz (Mid Input Frequency)

0.1 PF 10 Ÿ

10.2.3 Driving Circuit Design: Input Frequencies Greater than 230 MHz

Figure 178. Driving Circuit for High Input Frequencies (fIN > 230 MHz)

10.2.3.1 Design Requirements

See the Design Requirements section for further details.

10.2.3.2 Detailed Design Procedure

improvement in performance. However, a series resistance of 10 Ω can be used as shown in Figure 178.

10.2.3.3 Application Curve

Figure 179 shows the performance obtained by using the circuit shown in Figure 178. Figure 179. Performance FFT at 450 MHz (High Input Frequency)

11 Power-Supply Recommendations

requirements during device power-up. AVDD and DVDD can power up in any order.

12 Layout

12.1 Layout Guidelines

1. Analog inputs are located on opposite sides of the device pin out to ensure minimum crosstalk on the

as shown in the reference layout of Figure 180 as much as possible.

1. In the device pin out, the sampling clock is located on a side perpendicular to the analog inputs in order to
2. Keep digital outputs away from analog inputs. When these digital outputs exit the pin out, the digital output

as an FPGA or an ASIC) must be matched in length to avoid skew among outputs.

1. At each power-supply pin (AVDD and DVDD), a 0.1-µF decoupling capacitor must be kept close to the

0.1-µF capacitors can be kept close to the supply source.

12.2 Layout Example

Figure 180. Typical Layout of the ADC322x Board

13 Device and Documentation Support

13.1 Related Links

resources, tools and software, and quick access to sample or buy. Table 37. Related Links

13.2 Community Resources

solve problems with fellow engineers. contact information for technical support.

13.3 Trademarks

E2E is a trademark of Texas Instruments. PowerPAD is a trademark of Texas Instruments, Inc. All other trademarks are the property of their respective owners.

13.4 Electrostatic Discharge Caution

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

13.5 Glossary

This glossary lists and explains terms, acronyms, and definitions.

14 Mechanical, Packaging, and Orderable Information

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 23-Apr-2015 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples ADC3221IRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 AZ3221 ADC3221IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 AZ3221 ADC3222IRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 AZ3222 ADC3222IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 AZ3222 ADC3223IRGZ25 ACTIVE VQFN RGZ 48 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 AZ3223 ADC3223IRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 AZ3223 ADC3223IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 AZ3223 ADC3224IRGZ25 ACTIVE VQFN RGZ 48 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 AZ3224 ADC3224IRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 AZ3224 ADC3224IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 AZ3224 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

www.ti.com 23-Apr-2015 Addendum-Page 2 (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 3-Apr-2015 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADC3221IRGZR VQFN RGZ 48 2500 336.6 336.6 28.6 ADC3221IRGZT VQFN RGZ 48 250 213.0 191.0 55.0 ADC3222IRGZR VQFN RGZ 48 2500 336.6 336.6 28.6 ADC3222IRGZT VQFN RGZ 48 250 213.0 191.0 55.0 ADC3223IRGZR VQFN RGZ 48 2500 336.6 336.6 28.6 ADC3223IRGZT VQFN RGZ 48 250 213.0 191.0 55.0 ADC3224IRGZR VQFN RGZ 48 2500 336.6 336.6 28.6 ADC3224IRGZT VQFN RGZ 48 250 213.0 191.0 55.0 PACKAGE MATERIALS INFORMATION www.ti.com 3-Apr-2015 Pack Materials-Page 2

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