ADC31RF80IRMP

Texas Instruments

3-GSPS Telecom Receiver and Feedback Device

Manufacturer: Texas Instruments

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ADCADCADCINP, INM SYSREFP, SYSREFM CLKINP, CLKINM PLL Buffer D[1:0]P, D[1:0]M D[3:2]P, D[3:2]M GPIO[4:1] N NCO CTRL SYNCBP, SYNCBM JESD204B Interface FOVR NCO NCO ADC Digital Block (Interleave Correction Power Detection) Copyright © 2017, Texas Instruments Incorporated Clock Divider SPI and Control CM N RESET SCLK SDATA SEN PDN SDO Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. ADC31RF80 SBAS860 – AUGUST 2017 ADC31RF803-GSPSTelecomReceiverandFeedbackDevice

1 Features

1• 14-Bit, 3-GSPS ADC

Noise Floor: –155 dBFS/Hz
RF Input Supports Up To 4.0 GHz
Aperture Jitter: 90 fS
Spectral Performance (fIN = 900 MHz, –2 dBFS): – SNR: 61.4 dBFS – SFDR: 71-dBc HD2, HD3 – SFDR: 76-dBc Worst Spur
Spectral Performance (fIN = 1.85 GHz, –2 dBFS): – SNR: 58.5 dBFS – SFDR: 65-dBc HD2, HD3 – SFDR: 75-dBc Worst Spur
On-Chip Digital Down-Converters: – Up to 2 DDCs (Dual-Band Mode) – Up to 3 Independent NCOs per DDC
On-Chip Input Clamp for Overvoltage Protection
Programmable On-Chip Power Detectors With Alarm Pins for AGC Support
On-Chip Dither
On-Chip Input Termination
Input Full-Scale: 1.35 VPP
Support for Multi-Chip Synchronization
JESD204B Interface: – Subclass 1-Based Deterministic Latency – 4 Lanes Support at 12.5 Gbps
Total Power Dissipation: 3.2 W at 3.0 GSPS
72-Pin VQFN Package (10 mm × 10 mm)

2 Applications

Multi-Carrier GSM Cellular Infrastructure Base Stations
Telecommunications Receivers
DPD Observation Receivers
Backhaul Receivers
RF Repeaters and Distributed Antenna Systems

3 Description

The ADC31RF80 device is a 14-bit, 3-GSPS, single- channel telecom receiver and feedback device that supports RF sampling with input frequencies up to 4 GHz and beyond. Designed for high signal-to-noise ratio (SNR), the ADC31RF80 delivers a noise spectral density of –155 dBFS/Hz as well as dynamic range over a large input frequency range. The buffered analog input with on-chip termination provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy. The ADC31RF80 comes with a dual-band, digital down-converter (DDC) with up to three independent, 16-bit numerically-controlled oscillators (NCOs) per DDC for phase-coherent frequency hopping. Additionally, the ADC is equipped with front-end peak and RMS power detectors and alarm functions to support external automatic gain control (AGC) algorithms. The ADC31RF80 supports the JESD204B serial interface with subclass 1-based deterministic latency using data rates up to 12.5 Gbps with up to four lanes. The device is offered in a 72-pin VQFN package (10 mm × 10 mm) and supports the industrial temperature range (–40°C to +85°C). Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) ADC31RF80 VQFN (72) 10.00 mm × 10.00 mm (1) For all available packages, see the package option addendum at the end of the data sheet. Simplified Block Diagram

SBAS860 – AUGUST 2017 www.ti.com Product Folder Links: ADC31RF80 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Table of Contents 6.6 AC Performance Characteristics: fS = 2949.12 6.7 AC Performance Characteristics: fS = 2457.6 MSPS 6.8 AC Performance Characteristics: fS = 2457.6 MSPS

12.2 Receiving Notification of Documentation

13 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES August 2017 * Initial release.

72 NC19GPIO1

71 NC20GPIO2

70 DVDD21GPIO3

69 NC22CM

68 NC23GND

67 GND24AVDD19

66 NC25AVDD

65 NC26GND

64 DVDD27CLKINP

63 GPIO428CLKINM

62 D0M29GND

61 D0P30AVDD

60 GND31AVDD19

59 D1M32GND

58 D1P33SYSREFP

57 DVDD34SYSREFM

56 D2M35SYNCBP

55 D2P36SYNCBM

5 Pin Configuration and Functions

NAME NO. I/O DESCRIPTION INPUT, REFERENCE INM 41 I Differential analog input INP 42 CM 22 O Common-mode voltage for analog inputs, 1.2 V NC 1, 2, 13, 14, 65, 66, 68, 69, 71, 72 — Do not connect these pins.

SBAS860 – AUGUST 2017 www.ti.com Product Folder Links: ADC31RF80 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Pin Functions (continued) NAME NO. I/O DESCRIPTION CLOCK, SYNC CLKINM 28 I Differential clock input for the analog-to-digital converter (ADC). This pin has an internal differential 100-Ω termination.CLKINP 27 SYSREFM 34 I External SYSREF input. This pin has an internal, differential 100-Ω termination and requires external biasing.SYSREFP 33 GPIO1 19 I/O GPIO control pin; configured through the SPI. This pin can be configured to be either a fast overrange output, a fast detect alarm signal from the peak power detect, or a numerically-controlled oscillator (NCO) control. GPIO 4 (pin 63) can also be configured as a single-ended SYNCB input. GPIO2 20 GPIO3 21 GPIO4 63 CONTROL, SERIAL RESET 48 I Hardware reset; active high. This pin has an internal 20-kΩ pulldown resistor. SCLK 6 I Serial interface clock input. This pin has an internal 20-kΩ pulldown resistor. SDIN 5 I/O Serial interface data input. This pin has an internal 20-kΩ pulldown resistor. SDIN can be data input in 4-wire mode, data input and output in 3 wire-mode. SEN 7 I Serial interface enable. This pin has an internal 20-kΩ pullup resistor to DVDD. SDOUT 11 O Serial interface data output in 4-wire mode PDN 50 I Power down; active high. This pin has an internal 20-kΩ pulldown resistor. DATA INTERFACE D0M 62 O JESD204B serial data output D0P 61 D1M 59 D1P 58 D2M 56 D2P 55 D3M 54 D3P 53 SYNCBM 36 I Synchronization input for the JESD204B port. This pin has an LVDS or 1.8-V logic input, an optional on-chip 100-Ω termination, and is selectable through the SPI. This pin requires external biasing.SYNCBP 35 POWER SUPPLY AVDD19 10, 16, 24, 31, 39, 45 I Analog 1.9-V power supply AVDD 9, 12, 15, 17, 25, 30, 38, 40, 43, 44, 46 I Analog 1.15-V power supply DVDD 4, 8, 47, 51, 57, 64, 70 I Digital 1.15 V-power supply, including the JESD204B transmitter GND 3, 18, 23, 26, 29, 32, 37, 49, 52, 60, 67 I Ground; shorted to thermal pad inside device

www.ti.com SBAS860 – AUGUST 2017 Product Folder Links: ADC31RF80 Submit Documentation FeedbackCopyright © 2017, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Supply voltage range AVDD19 –0.3 2.1 VAVDD –0.3 1.4 DVDD –0.3 1.4 Voltage applied to input pins INP, INM –0.3 AVDD19 + 0.3 V CLKINP, CLKINM –0.3 AVDD + 0.6 SYSREFP, SYSREFM, SYNCBP, SYNCBM –0.3 AVDD + 0.6 SCLK, SEN, SDIN, RESET, PDN, GPIO1, GPIO2, GPIO3, GPIO4 –0.2 AVDD19 + 0.2 Voltage applied to output pins –0.3 2.2 V Temperature Operating free-air, TA –40 85 Storage, Tstg –65 150 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500 (2) Prolonged use above this junction temperature may increase the device failure-in-time (FIT) rate.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Supply voltage(1) AVDD19 1.8 1.9 2.0 VAVDD 1.1 1.15 1.25 DVDD 1.1 1.15 1.2 Temperature Operating free-air, TA –40 85 Operating junction, TJ 105(2) 125 (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.4 Thermal Information

THERMAL METRIC(1) ADC31RF80 UNITRMP (VQFN)

72 PINS

RθJA Junction-to-ambient thermal resistance 21.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 4.4 °C/W RθJB Junction-to-board thermal resistance 2.0 °C/W ψJT Junction-to-top characterization parameter 0.1 °C/W ψJB Junction-to-board characterization parameter 2.0 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 0.2 °C/W

SBAS860 – AUGUST 2017 www.ti.com Product Folder Links: ADC31RF80 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated (1) Full-scale signal is applied to the analog input; see the Power Consumption in Different Modes section for more details. (2) When used in dc-coupling mode, the common-mode voltage at the analog inputs should be kept within VCM ±25 mV for best performance. (3) See Figure 79.

6.5 Electrical Characteristics

typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient temperature range of –40°C to +85°C; and chip sampling rate = 2949.12 MSPS, 50% clock duty cycle, DDC-bypassed performance, AVDD19 = 1.9 V, AVDD = 1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER CONSUMPTION (Divide-by-4, Complex Output Mode(1)) IAVDD19 1.9-V analog supply current fS = 2949.12 MSPS 956 1439 mA IAVDD 1.15-V analog supply current fS = 2949.12 MSPS 499 813 mA IDVDD 1.15-V digital supply current fS = 2949.12 MSPS 975 1164 mA PD Power dissipation fS = 2949.12 MSPS 3.51 4.71 W Global power-down power dissipation 245 mW ANALOG INPUTS Resolution 14 Bits Differential input full-scale 1.35 VPP VIC Input common-mode voltage 1.2(2) V RIN Input resistance Differential resistance at dc 65 Ω CIN Input capacitance Differential capacitance at dc 2 pF VCM common-mode voltage output 1.2 V Analog input bandwidth (–3-dB point) ADC driven with 50-Ω source 3200 MHz CLOCK INPUT(3) Input clock frequency 1.5 3 GSPS Differential (peak-to-peak) input clock amplitude 0.5 1.5 2.5 VPP Input clock duty cycle 45% 50% 55% Internal clock biasing 1.0 V Internal clock termination (differential) 100 Ω

www.ti.com SBAS860 – AUGUST 2017 Product Folder Links: ADC31RF80 Submit Documentation FeedbackCopyright © 2017, Texas Instruments Incorporated (1) Performance is shown with DDC bypassed. When DDC is enabled, performance improves by the decimation filtering process. (2) Minimum values are specified at AOUT = –3 dBFS. (3) Output amplitude, AOUT, refers to the signal amplitude in the ADC digital output that is same as the analog input amplitude, AIN, except when the digital gain feature is used. If digital gain is G, then AOUT = G + AIN. (4) The ADC internal resistance = 65 Ω, the driving source resistance = 50 Ω. (5) The minimum value of HD2 is specified by bench characterization. 6.6 AC Performance Characteristics: fS = 2949.12 MSPS typical values specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient temperature range of –40°C to +85°C; and chip sampling rate = 2949.12 MSPS, 50% clock duty cycle, DDC-bypassed performance(1), AVDD19 = 1.9 V, AVDD = 1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted) PARAMETER TEST CONDITIONS MIN(2) NOM MAX UNIT SNR Signal-to-noise ratio fIN = 100 MHz, AOUT = –2 dBFS 63.2 dBFS fIN = 900 MHz, AOUT = –2 dBFS 61.4 fIN = 1850 MHz, AOUT = –2 dBFS 56 58.5 fIN = 2100 MHz, AOUT = –2 dBFS 57.7 fIN = 2600 MHz, AOUT = –2 dBFS 56.6 fIN = 3500 MHz, AOUT(3) = –3 dBFS with 2-dB gain 54.6 NSD Noise spectral density averaged across the Nyquist zone fIN = 100 MHz, AOUT = –2 dBFS 154.9 dBFS/Hz fIN = 900 MHz, AOUT = –2 dBFS 153.1 fIN = 1850 MHz, AOUT = –2 dBFS 147.7 150.2 fIN = 2100 MHz, AOUT = –2 dBFS 149.4 fIN = 2600 MHz, AOUT = –2 dBFS 148.3 fIN = 3500 MHz, AOUT (3) = –3 dBFS with 2-dB gain 146.3 Small-signal SNR fIN = 1850 MHz, AOUT = –40 dBFS 63.1 dBFS NF(4) Noise figure fIN = 1850 MHz, AOUT = –40 dBFS 24.7 dB SINAD Signal-to-noise and distortion ratio fIN = 100 MHz, AOUT = –2 dBFS 62.1 dBFS fIN = 900 MHz, AOUT = –2 dBFS 61.0 fIN = 1850 MHz, AOUT = –2 dBFS 57.8 fIN = 2100 MHz, AOUT = –2 dBFS 56.9 fIN = 2600 MHz, AOUT = –2 dBFS 55.7 fIN = 3500 MHz, AOUT (3) = –3 dBFS with 2-dB gain 54.5 ENOB Effective number of bits fIN = 100 MHz, AOUT = –2 dBFS 10.0 Bits fIN = 900 MHz, AOUT = –2 dBFS 9.8 fIN = 1850 MHz, AOUT = –2 dBFS 9.3 fIN = 2100 MHz, AOUT = –2 dBFS 9.2 fIN = 2600 MHz, AOUT = –2 dBFS 9.0 fIN = 3500 MHz, AOUT (3) = –3 dBFS with 2-dB gain 8.8 SFDR Spurious-free dynamic range fIN = 100 MHz, AOUT = –2 dBFS 68.0 dBc fIN = 900 MHz, AOUT = –2 dBFS 71 fIN = 1850 MHz, AOUT = –2 dBFS 58 65 fIN = 2100 MHz, AOUT = –2 dBFS 65 fIN = 2600 MHz, AOUT = –2 dBFS 63 fIN = 3500 MHz, AOUT (3) = –3 dBFS with 2-dB gain 68 HD2(5) Second-order harmonic distortion fIN = 100 MHz, AOUT = –2 dBFS 68 dBc fIN = 900 MHz, AOUT = –2 dBFS 71 fIN = 1850 MHz, AOUT = –2 dBFS 58 65 fIN = 2100 MHz, AOUT = –2 dBFS 65 fIN = 2700 MHz, AOUT = –2 dBFS 63 fIN = 3500 MHz, AOUT (3) = –3 dBFS with 2-dB gain 68

SBAS860 – AUGUST 2017 www.ti.com Product Folder Links: ADC31RF80 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated AC Performance Characteristics: fS = 2949.12 MSPS (continued) typical values specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient temperature range of –40°C to +85°C; and chip sampling rate = 2949.12 MSPS, 50% clock duty cycle, DDC-bypassed performance(1), AVDD19 = 1.9 V, AVDD = 1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted) PARAMETER TEST CONDITIONS MIN(2) NOM MAX UNIT HD3 Third-order harmonic distortion fIN = 100 MHz, AOUT = –2 dBFS 73 dBc fIN = 900 MHz, AOUT = –2 dBFS 80 fIN = 1850 MHz, AOUT = –2 dBFS 62 71 fIN = 2100 MHz, AOUT = –2 dBFS 77 fIN = 2600 MHz, AOUT = –2 dBFS 79 fIN = 3500 MHz, AOUT(3) = –3 dBFS with 2-dB gain 76 HD4, HD5 Fourth- and fifth-order harmonic distortion fIN = 100 MHz, AOUT = –2 dBFS 78 dBc fIN = 900 MHz, AOUT = –2 dBFS 81.0 fIN = 1850 MHz, AOUT = –2 dBFS 69 76 fIN = 2100 MHz, AOUT = –2 dBFS 77 fIN = 2600 MHz, AOUT = –2 dBFS 77 fIN = 3500 MHz, AOUT (3) = –3 dBFS with 2-dB gain 84 IL spur Interleaving spurs: fS / 2 – fIN, fS / 4 ± fIN fIN = 100 MHz, AOUT = –2 dBFS 89 dBc fIN = 900 MHz, AOUT = –2 dBFS 88 fIN = 1850 MHz, AOUT = –2 dBFS 68 82 fIN = 2100 MHz, AOUT = –2 dBFS 79 fIN = 2600 MHz, AOUT = –2 dBFS 81 fIN = 3500 MHz, AOUT (3) = –3 dBFS with 2-dB gain 75 HD2 IL Interleaving spur for HD2: fS / 2 – HD2 fIN = 100 MHz, AOUT = –2 dBFS 85.0 dBc fIN = 900 MHz, AOUT = –2 dBFS 79.0 fIN = 1850 MHz, AOUT = –2 dBFS 62 80.0 fIN = 2100 MHz, AOUT = –2 dBFS 74.0 fIN = 2600 MHz, AOUT = –2 dBFS 74.0 fIN = 3500 MHz, AOUT (3) = –3 dBFS with 2-dB gain 80.0 Worst spur Spurious-free dynamic range (excluding HD2, HD3, HD4, HD5, and interleaving spurs IL and HD2 IL) fIN = 100 MHz, AOUT = –2 dBFS 83.0 dBc fIN = 900 MHz, AOUT = –2 dBFS 76.0 fIN = 1850 MHz, AOUT = –2 dBFS 64 75.0 fIN = 2100 MHz, AOUT = –2 dBFS 75.0 fIN = 2600 MHz, AOUT = –2 dBFS 75.0 fIN = 3500 MHz, AOUT (3) = –3 dBFS with 2-dB gain 72.0 IMD3 Two-tone, third-order intermodulation distortion fIN1 = 900 MHz, fIN2 = 950 MHz, AOUT = –8 dBFS (each tone) 79 dBFS fIN1 = 1770 MHz, fIN2 = 1790 MHz, AOUT = –8 dBFS (each tone) 70 fIN1 = 1800 MHz, fIN2 = 2600 MHz, AOUT = –8 dBFS (each tone) 73 fIN1 = 3490 MHz, fIN2 = 3510 MHz, AOUT = –8 dBFS (each tone) with 2-dB gain 67

www.ti.com SBAS860 – AUGUST 2017 Product Folder Links: ADC31RF80 Submit Documentation FeedbackCopyright © 2017, Texas Instruments Incorporated (1) F-band = 1880 MHz to 1920 MHz, A-band = 2010 MHz to 2025 MHz, and D-band = 2570 MHz to 2620 MHz. 6.7 AC Performance Characteristics: fS = 2457.6 MSPS (Performance Optimized for F + A + D Band(1)) typical values specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient temperature range of –40°C to +85°C; and chip sampling rate = 2949.12 MSPS, 50% clock duty cycle, DDC-bypassed performance, AVDD19 = 1.9 V, AVDD = 1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted) PARAMETER TEST CONDITIONS MIN NOM MAX UNIT SNR Signal-to-noise ratio fIN = 1850 MHz, AOUT = –2 dBFS 58.5 dBFS fIN = 2600 MHz, AOUT = –2 dBFS 55.8 SFDR Spurious-free dynamic range fIN = 1850 MHz, AOUT = –2 dBFS 60.0 dBc fIN = 2600 MHz, AOUT = –2 dBFS 57.0 HD2 Second-order harmonic distortion fIN = 1850 MHz, AOUT = –2 dBFS 59.0 dBc fIN = 2600 MHz, AOUT = –2 dBFS 57.0 HD3 Third-order harmonic distortion fIN = 1850 MHz, AOUT = –2 dBFS 75.0 dBc fIN = 2600 MHz, AOUT = –2 dBFS 65.0 IL spur Interleaving spurs: fS / 2 – fIN, fS / 4 ± fIN fIN = 1850 MHz, AOUT = –2 dBFS 84.0 dBc fIN = 2600 MHz, AOUT = –2 dBFS 76.0 HD2 IL Interleaving spur for HD2: fS / 2 – HD2 fIN = 1850 MHz, AOUT = –2 dBFS 76.0 dBc fIN = 2600 MHz, AOUT = –2 dBFS 67.0 IMD3 Two-tone, third-order intermodulation distortion fIN1 = 1800 MHz, fIN2 = 2600 MHz, AOUT = –8 dBFS (each tone) 67.0 dBFS (1) F-band = 1880 MHz to 1920 MHz, A-band = 2010 MHz to 2025 MHz, and D-band = 2570 MHz to 2620 MHz. 6.8 AC Performance Characteristics: fS = 2457.6 MSPS (Performance Optimized for F + A Band(1)) typical values specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient temperature range of –40°C to +85°C; and chip sampling rate = 2949.12 MSPS, 50% clock duty cycle, DDC-bypassed performance, AVDD19 = 1.9 V, AVDD = 1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted) PARAMETER TEST CONDITIONS MIN NOM MAX UNIT SNR Signal-to-noise ratio fIN = 1850 MHz, AOUT = –2 dBFS 58.7 dBFS fIN = 2100 MHz, AOUT = –2 dBFS 57.9 SFDR Spurious-free dynamic range fIN = 1850 MHz, AOUT = –2 dBFS 71.0 dBc fIN = 2100 MHz, AOUT = –2 dBFS 69.0 HD2 Second-order harmonic distortion fIN = 1850 MHz, AOUT = –2 dBFS 71.0 dBc fIN = 2100 MHz, AOUT = –2 dBFS 69.0 HD3 Third-order harmonic distortion fIN = 1850 MHz, AOUT = –2 dBFS 75.0 dBc fIN = 2100 MHz, AOUT = –2 dBFS 76.0 IL spur Interleaving spurs: fS / 2 – fIN, fS / 4 ± fIN fIN = 1850 MHz, AOUT = –2 dBFS 82.0 dBc fIN = 2100 MHz, AOUT = –2 dBFS 84.0 HD2 IL Interleaving spur for HD2: fS / 2 – HD2 fIN = 1850 MHz, AOUT = –2 dBFS 80.0 dBc fIN = 2100 MHz, AOUT = –2 dBFS 80.0

6.9 Digital Requirements

typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient temperature range of –40°C to +85°C; and chip sampling rate = 2949.12 MSPS, DDC bypassed performance, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD = 1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted) PARAMETER TEST CONDITIONS MIN NOM MAX UNIT DIGITAL INPUTS (RESET, SCLK, SEN, SDIN, PDN, GPIO1, GPIO2, GPIO3, GPIO4) VIH High-level input voltage 0.8 V VIL Low-level input voltage 0.4 V IIH High-level input current 50 µA IIL Low-level input current –50 µA Ci Input capacitance 4 pF DIGITAL OUTPUTS (SDOUT, GPIO1, GPIO2, GPIO3, GPIO4) VOH High-level output voltage AVDD19 –0.1 AVDD19 V VOL Low-level output voltage 0.1 V DIGITAL INPUTS (SYSREFP and SYSREFM; SYNCBP and SYNCBM; Requires External Biasing) VID Differential input voltage 350 450 800 mVPP VCM Input common-mode voltage 1.05 1.2 1.325 V DIGITAL OUTPUTS (JESD204B Interface: D[3:0], Meets JESD204B LV-0IF-11G-SR Standard) |VOD| Output differential voltage 700 mVPP |VOCM| Output common-mode voltage 450 mV Transmitter short-circuit current Transmitter pins shorted to any voltage between –0.25 V and 1.45 V –100 100 mA zos Single-ended output impedance 50 Ω Co Output capacitance Output capacitance inside the device, from either output to ground 2 pF

0 V0 V

(1) Overall latency = latency + tPD. (2) Latency increases when the DDC modes are used; see Table 4. (3) Common-mode voltage for the SYSREF input is kept at 1.2 V.

6.10 Timing Requirements

VOCM is not the same as VICM. Similarly, VOD is not the same as VID. Figure 1. Logic Levels for Digital Inputs and Outputs

Figure 2. SYSREF Timing Diagram

6.11 Typical Characteristics

Figure 3. FFT for 100-MHz Input Frequency Figure 4. FFT for 100-MHz Input Signal (fS = 2457.6 MSPS) Figure 5. FFT for 900-MHz Input Signal Figure 6. FFT for 900-MHz Input Signal (fS = 2457.6 MSPS) Figure 7. FFT for 1850-MHz Input Signal Figure 8. FFT for 1850-MHz Input Signal (fS = 2457.6 MSPS)

7 Parameter Measurement Information

7.1 Input Clock Diagram

Figure 79 shows the input clock diagram. Figure 79. Input Clock Diagram

8 Detailed Description

8.1 Overview

The ADC31RF80 is a single-channel, 14-bit, 2949.12-MSPS, telecom receiver and feedback device containing an analog-to-digital converter (ADC) followed by multi-band digital down-converters (DDCs), and a back-end JESD204B digital interface. The ADC is preceded by an input buffer and on-chip termination to provide a uniform input impedance over a large input frequency range. Furthermore, an internal differential clamping circuit provides first-level protection against overvoltage conditions. The ADC is internally interleaved four times and equipped with background, analog and digital, and interleaving correction. The on-chip DDC enables single- or dual-band internal processing to pre-select and filter smaller bands of interest and also reduces the digital output data traffic. Each DDC is equipped with up to three independent, 16-bit numerically-controlled oscillators (NCOs) for phase coherent frequency hopping; the NCOs can be controlled through the SPI or GPIO pins. The ADC31RF80 also provides three different power detectors on-chip with alarm outputs in order to support external automatic gain control (AGC) loops. The processed data are passed into the JESD204B interface where the data are framed, encoded, serialized, and output on one to four lanes, depending on the ADC sampling rate and decimation. The CLKIN, SYSREF, and SYNCB inputs provide the device clock and the SYSREF and SYNCB signals to the JESD204B interface that are used to derive the internal local frame and local multiframe clocks and establish the serial link. All features of the ADC31RF80 are configurable through the SPI.

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Analog Inputs

currents of the sampling circuit, thus resulting in a more constant SFDR performance across input frequencies. from dc to 5 GHz with a 100-Ω reference impedance. Figure 80. Equivalent Input Impedance Figure 81. SDD11 Over the Input Frequency Range

100 Ohm Source

50 Ohm Source

capacitance. Figure 82 and Figure 83 show how equivalent impedance (CIN and RIN) vary over frequency. Figure 82. Differential Input Capacitance vs Figure 83. Differential Input Resistance vs Input Frquency that extends up to approximately 3.2 GHz. Figure 84. Input Bandwidth with a 100-Ω Source Resistance

8.3.1.1 Input Clamp Circuit

Figure 85 and Figure 86, effectively limiting the maximum input signal to approximately 2.4 VPP. Figure 85. Clamp Circuit in the ADC31RF80 Figure 86. Clamp Response Timing Diagram

8.3.2 Clock Input

The ADC31RF80 sampling clock input includes internal 100-Ω differential termination along with on-chip biasing. approximately 3 GHz; Figure 87 shows the clock input impedance with a 100-Ω reference impedance. Figure 87. SDD11 of the Clock Input

The analog-to-digital converter (ADC) aperture jitter is a function of the clock amplitude applied to the pins. the clock frequency, a matching circuit can be designed in order to maximize the clock amplitude. Figure 88. Equivalent Aperture Jitter vs Input Clock Amplitude

8.3.3 SYSREF Input

help with skew adjustment when the sampling clock and SYSREF are not provided from the same source. Figure 89. SYSREF Internal Circuit Diagram

8.3.3.1 Using SYSREF

in the ASSERT SYSREF REG bit, as shown in Figure 90, when using SPI registers. Figure 90. Using SYSREF to Reset the Clock Divider, the NCO, and the LMFC Counter SYSREF assertion after disregarding the first two assertions. Table 1. Asserting SYSREF

1 Gets reset Does not get reset Does not get reset

2 Gets reset Does not get reset Does not get reset

3 Gets reset Gets reset Gets reset

ignore further SYSREF pulses. (1) fS = sampling (device) clock frequency. (3) K = number of frames per multi-frame. (4) LCM = least-common multiple.

SYSREF is applied as a periodic pulse.

Figure 92 shows how SYSREF can be applied as a continuous periodic waveform. tSYSREF is a period of the SYSREF waveform. Alternatively, the SYSREF buffer can be powered down using the PDN SYSREF bit. Figure 92. SYSREF Used as a Periodic Waveform to the NCO and JESD can be masked by setting the MASK NCO SYSREF register bit.

8.3.3.2 Frequency of the SYSREF Signal

decimation, frames per multi-frame setting (K), samples per frame (S), and device input clock frequency.

N is an integer value (1, 2, 3, and so forth) (1) In order for the interleaving correction engine to synchronize properly, the SYSREF frequency must also be a multiple of fS / 64. Table 2 provides a summary of the valid LMFC clock settings.

Table 2. . SYSREF and LMFC Clock Frequency the signal path both on the printed circuit board (PCB) as well as internal to the device.

16 Bits

3 GSPS IQ data, 3 GSPS RX1 IQ Output

For proper device operation, disable the SYSREF signal after the JESD synchronization is established.

8.3.4 DDC Block

NOTE: Red traces show SYSREF going to the NCO blocks. Figure 93. DDC Chains Overview twice the decimated, complex output rate. The filter response with a real output is identical to a complex output.

8.3.4.1 Operating Mode: Receiver

NOTE: Red traces show SYSREF going to the NCO blocks. Figure 94. Decimation Filter Option for Single- or Dual-Band Operation

8.3.4.2 Operating Mode: Wide-Bandwidth Observation Receiver

NOTE: Red traces show SYSREF going to the NCO blocks. Figure 95. Decimation Filter Implementation for Single-Band and Wide-Bandwidth Mode

8.3.4.3 Decimation Filters

Table 3. Decimation Filter Summary and Maximum Available Output Bandwidth

3 GSPS IQ 3 GSPS

375 MSPS

Figure 96 shows a dual-band example with a divide-by-8 complex. Figure 96. Dual-Band Example The decimation filters of the ADC31RF80 provide greater than 90-dB attenuation for the alias bands. Figure 97. Interpretation of the Decimation Filter Plots

8.3.4.3.1 Divide-by-4

Figure 98. Divide-by-4 Filter Response Figure 99. Divide-by-4 Filter Response (Zoomed)

8.3.4.3.2 Divide-by-6

Figure 100. Divide-by-6 Filter Response Figure 101. Divide-by-6 Filter Response (Zoomed)

8.3.4.3.3 Divide-by-8

Figure 102. Divide-by-8 Filter Response Figure 103. Divide-by-8 Filter Response (Zoomed)

8.3.4.3.4 Divide-by-9

Figure 104. Divide-by-9 Filter Response Figure 105. Divide-by-9 Filter Response (Zoomed)

8.3.4.3.5 Divide-by-10

Figure 106. Divide-by-10 Filter Response Figure 107. Divide-by-10 Filter Response (Zoomed)

8.3.4.3.6 Divide-by-12

Figure 108. Divide-by-12 Filter Response Figure 109. Divide-by-12 Filter Response (Zoomed)

8.3.4.3.7 Divide-by-16

Figure 110. Divide-by-16 Filter Response Figure 111. Divide-by-16 Filter Response (Zoomed)

8.3.4.3.8 Divide-by-18

Figure 112. Divide-by-18 Filter Response Figure 113. Divide-by-18 Filter Response (Zoomed)

8.3.4.3.9 Divide-by-20

Figure 114. Divide-by-20 Filter Response Figure 115. Divide-by-20 Filter Response (Zoomed)

8.3.4.3.10 Divide-by-24

Figure 116. Divide-by-24 Filter Response Figure 117. Divide-by-24 Filter Response (Zoomed)

8.3.4.3.11 Divide-by-32

Figure 118. Divide-by-32 Filter Response Figure 119. Divide-by-32 Filter Response (Zoomed)

8.3.4.3.12 Latency With Decimation Options

because of the increase in number of taps in the decimation filter. Table 4. Latency With Different Decimation Options

8.3.4.4 Numerically-Controlled Oscillators (NCOs) and Mixers

generates a complex exponential sequence.

frequency (ω) is specified as a signed number by the 16-bit register setting (2) The complex exponential sequence is multiplied by the real input from the ADC to mix the desired carrier down to 0 Hz. The ADC has two DDCs. The first DDC has three NCOs and the second DDC has one NCO. The first DDC can dynamically select one of the three NCOs based on the GPIO pin or SPI selection. In wide-bandwidth mode (lower decimation factors, for example, 4 and 6), there can only be one active DDC. The NCO frequencies can be programmed independently through the DDCx, NCO[4:1], and the MSB and LSB register settings. Equation 3 gives the NCO frequency setting that is set by the 16-bit register: where
x = 0, 1
y = 1 to 4 (3) For example: If fS = 2949.12 MSPS, then the NCO register setting = 38230 (decimal). Thus, Equation 4 defines fNCO: (4) Any register setting changes that occur after the JESD204B interface is operational results in a non-deterministic NCO phase. If a deterministic phase is required, the JESD204B interface must be reinitialized after changing the register setting.

8.3.5 NCO Switching

The first DDC (DDC0) provides three different NCOs that can be used for phase-coherent frequency hopping. This feature is available in both single-band and dual-band mode, but only affects DDC0.

Table 5. NCO Register Configurations NCO SEL PIN 500Fh Selects the NCO control through the SPI (default) or a GPIO pin. INSEL0[1:0], INSEL1[1:0] 5438h Selects which two GPIO pins are used to control the NCO. NCO SEL PIN 500Fh Selects the NCO control through the SPI (default) or a GPIO pin. NCO SEL[1:0] 5010h Selects which NCO to use for DDC0. Table 6. GPIO Pin Assignment

00 GPIO4

01 GPIO1

10 GPIO3

11 GPIO2

Table 7. NCO Selection

00 NCO1

01 NCO2

10 NCO3

Figure 120. NCO Switching from GPIO and SPI

8.3.6 SerDes Transmitter Interface

Figure 121. External Serial JESD204B Interface Connection

8.3.7 Eye Diagrams

Figure 122. Data Eye at 5 Gbps Figure 123. Data Eye at 12 Gbps

8.3.8 Alarm Outputs: Power Detectors for AGC Support

the ADC. The power detectors operate off the full-rate ADC output prior to the decimation filters.

8.3.8.1 Absolute Peak Power Detector

block detector alarm output. Figure 124. Peak Power Detector Implementation Figure 125. Peak Power Detector Timing Diagram

operates in the fS / 8 clock domain; one peak sample is calculated over eight actual samples. The automatic gain control (AGC) modes can be configured using registers in the power-detector page (54xxh). Table 8. Registers Required for the Peak Power Detector value: N is 17 bits: 1 to 216. equivalent to the peak amplitude). the DWELL value. This threshold is 16 bits and is specified in terms of fS / 8 clock cycles. 5434h, 5435h Connects the BLKPKDETH, BLKPKDETL alarms to the GPIO pins; common register. IODIR 5437h Selects the direction for the four GPIO pins; common register. RESET AGC 542Bh After configuration, reset the AGC module to start operation.

8 Samples

8.3.8.2 Crossing Detector

Figure 126. Crossing Detector Implementation Figure 127. Crossing Detector Timing Diagram

Table 9. Registers Required for the Crossing Detector Operation BLKPKDET 5401h, 5402h, 5403h Sets the block length N of number of samples (S\`). Number of actual ADC samples is 8x this value: N is 17 bits: 1 to 216. (where 256 is equivalent to the peak amplitude). identification register (IIR) filter. Sets the crossing detector time period for N = 0 to 15 as 2N × fS / 8 clock cycles. crossings, a value of 0.125 (0800h) corresponds to 12.5% crossings. DWELLIIR 541Dh, 541Eh DWELL counter for the IIR filter hysteresis. IIR1 2BIT EN 5413h, 54114h Enables 2-bit output format for the crossing detector. 5434h, 5435h Connects the IIRPKDET0, IIRPKDET1 alarms to the GPIO pins; common register. IODIR 5437h Selects the direction for the four GPIO pins; common register. RESET AGC 542Bh After configuration, reset the AGC module to start operation.

8.3.8.3 RMS Power Detector

and then compared against two sets of programmable thresholds (with hysteresis). 1-bit output provides one threshold together with hysteresis. Figure 128. RMS Power Detector Implementation Table 10. Registers Required for Using the RMS Power Detector Feature is defined in terms of fS / 8 clocks. The block length can be programmed as 2M with M = 0 to 16. The computed average power is compared against these high and low thresholds. RMS2BIT EN 5427h Enables 2-bit output format for the RMS detector output. 5434h, 5435h Connects the PWRDET alarms to the GPIO pins; common register. IODIR 5437h Selects the direction for the four GPIO pins; common register. RESET AGC 542Bh After configuration, reset the AGC module to start operation.

8.3.8.4 GPIO AGC MUX

crossing detector (1 or 2 bit), faster overrange, or the RMS power output. pins. These pins can be configured as outputs (AGC alarm) or inputs (NCO control) through SPI programming. Figure 129. GPIO Output MUX Implementation

8.3.9 Power-Down Mode

the PDN pin or the SPI register writes.

8.3.10 ADC Test Pattern

Figure 130. Test Pattern Generator Implementation

8.3.10.1 Digital Block

when complex (I, Q) output or dual-band DDC is selected. Additionally, a 12-bit test pattern is also available.

The number of converters increases in dual-band DDC mode and with a complex output. Table 11. Test Pattern Options (Register 37h and 38h in Decimation Filter Page) Test pattern outputs on when the I and Q stream DDC option is chosen.

0111 Double pattern: output data alternate between custom pattern 1 and

8.3.10.2 Transport Layer

pattern can be substituted, as shown in Table 12, instead of the ADC data with the JESD frame. Table 12. Transport Layer Test Mode EN (Register 01h)

4 TESTMODE EN 0

to section 5.1.6.3 of the JESD204B specification.

8.3.10.3 Link Layer

The link layer contains the scrambler and the 8b, 10b encoding of any data passed on from the transport layer. Additionally, the link layer also handles the initial lane alignment sequence that can be manually restarted. patterns do not pass through the 8b, 10b encoder and contain the options listed in Table 13. Table 13. Link Layer Test Mode (Register 03h) (AAAAh) in the ADC section and running AAAAh through the 8b, 10b encoder with scrambling enabled.

8.4 Device Functional Modes

8.4.1 Device Configuration

section. In addition, the device has one dedicated parallel pin (PDN) for controlling the power-down modes.

8.4.2 JESD204B Interface

Figure 131. JESD Signal Overview from the transport layer can be scrambled. Figure 132. JESD Digital Block Implementation

8.4.2.1 JESD204B Initial Lane Alignment (ILA)

establish the code group synchronization. start and end symbols. The second multiframe also contains the JESD204 link configuration data. Figure 133. JESD Internal Timing Information

8.4.2.2 JESD204B Frame Assembly

F is the number of octets per frame clock period
L is the number of lanes per link
M is the number of converters for the device
S is the number of samples per frame

8.4.2.3 JESD204B Frame Assembly with Decimation (Single-Band DDC): Complex Output

maximum ADC sample frequency. Table 15 shows the sample alignment on the different lanes. Table 14. JESD Mode Options: Single-Band Complex Output Table 15. JESD Sample Lane Alignments: Single-Band Complex Output

8.4.2.4 JESD204B Frame Assembly with Decimation (Single-Band DDC): Real Output

ADC sample frequency. Table 17 shows the sample alignment on the different lanes. Table 16. JESD Mode Options: Single-Band Real Output (Wide Bandwidth) Table 17. JESD Sample Lane Alignment: Single-Band Real Output (Wide Bandwidth)

8.4.2.5 JESD204B Frame Assembly with Decimation (Single-Band DDC): Real Output

DDC) when using a complex output format. Table 19 shows the sample alignment on the different lanes. Table 18. JESD Mode Options: Single-Band Real Output Table 19. JESD Sample Lane Assignment: Single-Band Real Output

4211 LMFS = 4222 LMFS = 2221 LMFS = 2242

8.4.2.6 JESD204B Frame Assembly with Decimation (Dual-Band DDC): Complex Output

ADC sample frequency. Table 21 shows the sample alignment on the different lanes. Table 20. JESD Mode Options: Dual-Band Complex Output (1) Blue and green shading indicates the output of the two DDC bands. Table 21. JESD Sample Lane Assignment: Dual-Band Complex Output(1)

8.4.2.7 JESD204B Frame Assembly with Decimation (Dual-Band DDC): Real Output

sample frequency. Table 23 shows the sample alignment on the different lanes. Table 22. JESD Mode Options: Dual-Band Real Output (1) Blue and green shading indicates the output of the two DDC bands. Table 23. JESD Sample Lane Assignment: Dual-Band Complex Output(1)

8.4.3 Serial Interface

20 MHz down to low speeds (of a few hertz) and also with a non-50% SCLK duty cycle. to distinguish between read/write, page and register, and individual channel access, as described in Table 25. Figure 134. SPI Timing Diagram Table 24. SPI Timing Information

8.4.3.1 Serial Register Write: Analog Bank

Initiating a serial interface cycle selecting the page address of the register whose content must be written. To
Writing the register content. When a page is selected, multiple registers located in the same page can be

Figure 136. SPI Write Timing Diagram for the Analog Bank

8.4.3.2 Serial Register Readout: Analog Bank

Selecting the page address of the register whose content must be read. Master page: write address 0012h

with 04h. ADC page: write address 0011h with FFh.

Setting the R/W bit to 1 and writing the address to be read back.
Reading back the register content on the SDOUT pin. When a page is selected, the contents of multiple

registers located in same page can be readback. Figure 137. SPI Read Timing Diagram for the Analog Bank

8.4.3.3 Serial Register Write: Digital Bank

Setting the M bit to 1 and specifying the page with with the desired register. There are seven pages in Digital

begins with 4xxx when selecting a page from digital bank because the M bit must be set to 1. – To select the offset corrector page: write address 4004h with 61h, 4003h with 00h, and 4002h with 00h. – To select the digital gain page: write address 4004h with 61h, 4003h with 00h, and 4002h with 05h. – To select the main digital page: write address 4004h with 68h, 4003h with 00h, and 4002h with 00h. – To select the JESD digital page: write address 4004h with 69h, 4003h with 00h, and 4002h with 00h. Figure 138. SPI Write Timing Diagram for Digital Bank Page Selection

Writing into the desired register by setting both the M bit and P bit to 1. Write register content. When a page

cycle begins with 6xxx when selecting a page from the digital bank because the M bit must be set to 1. JESD digital page begins with 7xxx. Figure 139. SPI Write Timing Diagram for Digital Bank Register Write

8.4.3.4 Serial Register Readout: Digital Bank

Selecting the page in the digital page: follow step 2 in the Serial Register Write: Digital Bank section.
Set the R/W, M, P, and CH bits to 1, and write the address to be read back.
Read back the register content on the SDOUT pin. When a page is selected, multiple read backs from the

Figure 140. SPI Read Timing Diagram for the Digital Bank

8.4.3.5 Serial Register Write: Decimation Filter and Power Detector Pages

pages can be programmed in one SPI cycle (Figure 141).

Directly write to the decimation filter or power detector pages. To program registers in these pages, set M = 1

– Decimation filter page: SPI cycle begins with 50xxh. – Power detector page: SPI cycle begins with 54xxh. divide-by-8 (complex output). Figure 141. SPI Write Timing Diagram for the Decimation and Power Detector Pages

8.5 Register Maps

a page is accessed, the registers in that page can be programmed and read back multiple times. (2) Registers in the decimation filter page and the power detector page can be directly programmed in one SPI cycle. (3) The CH bit is a don't care bit and is recommended to be kept at 0. Figure 142. SPI Registers, Two-Step Addressing

(1) Registers in the decimation filter page and the power detector page can be directly programmed in one SPI cycle. (2) To program registers in the decimation filter page. (3) To program registers in power detector page. Figure 143. SPI Registers: Direct Addressing

Table 26 lists the register map for the ADC31RF80. Table 26. Register Map

000 RESET 0 0 0 0 0 0 RESET

002 DIGITAL BANK PAGE SEL[7:0]

003 DIGITAL BANK PAGE SEL[15:8]

004 DIGITAL BANK PAGE SEL[23:16]

011 ADC PAGE SEL

68 FREEZE OFFSET

Table 26. Register Map (continued)

001 CTRL K 0 0 TESTMODE EN 0 LANE ALIGN FRAME ALIGN TX LINK DIS

002 SYNC REG SYNC REG EN 0 0 12BIT MODE JESD MODE0

003 LINK LAYER TESTMODE LINK LAY RPAT LMFC MASK

006 SCRAMBLE EN 0 0 0 0 0 0 0

032 SEL EMP LANE 0 0 0

033 SEL EMP LANE 1 0 0

034 SEL EMP LANE 2 0 0

035 SEL EMP LANE 3 0 0

007 DDC0 NCO1 LSB

008 DDC0 NCO1 MSB

009 DDC0 NCO2 LSB

033 CUSTOM PATTERN1[7:0]

034 CUSTOM PATTERN1[15:8]

035 CUSTOM PATTERN2[7:0]

036 CUSTOM PATTERN2[15:8]

037 TEST PATTERN DDC1 Q-DATA TEST PATTERN DDC1 I-DATA

038 TEST PATTERN DDC2 Q-DATA TEST PATTERN DDC2 I -DATA

001 BLKPKDET [7:0]

002 BLKPKDET [15:8]

007 BLKTHHH

008 BLKTHHL

009 BLKTHLH

010 FIL0THH[15:8]

011 FIL0THL[7:0]

012 FIL0THL[15:8]

016 FIL1THH[7:0]

017 FIL1THH[15:8]

018 FIL1THL[7:0]

019 FIL1THL[15:8]

022 PWRDETH[7:0]

023 PWRDETH[15:8]

024 PWRDETL[7:0]

025 PWRDETL[15:8]

032 OUTSEL GPIO4

033 OUTSEL GPIO1

034 OUTSEL GPIO3

035 OUTSEL GPIO2

8.5.1 Example Register Writes

JESD format configured to LMFS = 4421. Table 27. Global Power-Down Table 28. Scrambler Enable Table 29. 8x Decimation

8.5.2 Register Descriptions

Table 30 lists the access codes for the ADC31RF80 registers. Table 30. ADC31RF80 Access Type Codes

8.5.2.1 General Registers

8.5.2.1.1 Register 000h (address = 000h), General Registers

Figure 144. Register 000h (1) Both bits (7, 0) must be set simultaneously to perform a reset. Table 31. Register 000h Field Descriptions

7 RESET R/W 0h 0 = Normal operation

0 RESET R/W 0h 0 = Normal operation(1)

8.5.2.1.2 Register 002h (address = 002h), General Registers

Figure 145. Register 002h Table 32. Register 002h Field Descriptions desired page in the JESD bank.

8.5.2.1.3 Register 003h (address = 003h), General Registers

Figure 146. Register 003h Table 33. Register 003h Field Descriptions desired page in the JESD bank.

8.5.2.1.4 Register 004h (address = 004h), General Registers

Figure 147. Register 004h Table 34. Register 004h Field Descriptions desired page in the JESD bank.

8.5.2.1.5 Register 010h (address = 010h), General Registers

Figure 148. Register 010h Table 35. Register 010h Field Descriptions

8.5.2.1.6 Register 011h (address = 011h), General Registers

Figure 149. Register 011h Table 36. Register 011h Field Descriptions

8.5.2.1.7 Register 012h (address = 012h), General Registers

Figure 150. Register 012h Table 37. Register 012h Field Descriptions

2 MASTER PAGE SEL R/W 0h 0 = Normal operation

8.5.3 Master Page (M = 0)

8.5.3.1 Register 020h (address = 020h), Master Page

Figure 151. Register 020h Table 38. Register 020h Field Descriptions 4 PDN SYSREF R/W 0h This bit powers down the SYSREF input buffer. 0 GLOBAL PDN R/W 0h This bit enables the global power-down.

8.5.3.2 Register 032h (address = 032h), Master Page

Figure 152. Register 032h Table 39. Register 032h Field Descriptions

5 INCR CM IMPEDANCE R/W 0h Only use this bit when analog inputs are dc-coupled to the

8.5.3.3 Register 039h (address = 039h), Master Page

Figure 153. Register 039h

0 ALWAYS

Table 40. Register 039h Field Descriptions

6 ALWAYS WRITE 1 R/W 0h Always set this bit to 1

4 ALWAYS WRITE 1 R/W 0h Always set this bit to 1

0 SYNC TERM DIS R/W 0h This bit disables the on-chip, 100-Ω termination resistors on the

8.5.3.4 Register 03Ch (address = 03Ch), Master Page

Figure 154. Register 03Ch

0 SYSREF DEL EN 0 0 0 0 SYSREF DEL[4:3]

Table 41. Register 03Ch Field Descriptions

6 SYSREF DEL EN R/W 0h This bit allows an internal delay to be added to the SYSREF

delay can be adjusted in 25-ps steps; the first step is 175 ps.

8.5.3.5 Register 05Ah (address = 05Ah), Master Page

Figure 155. Register 05Ah Table 42. Register 05Ah Field Descriptions

7 SYSREF DEL2 R/W 0h When the SYSREF delay feature is enabled (3Ch, bit 6) the

delay can be adjusted in 25-ps steps; the first step is 175 ps.

6 SYSREF DEL1

5 SYSREF DEL0

Table 43. SYSREF DEL[2:0] Bit Settings

8.5.3.6 Register 03Dh (address = 3Dh), Master Page

Figure 156. Register 03Dh Table 44. Register 03Dh Field Descriptions

8.5.3.7 Register 057h (address = 057h), Master Page

Figure 157. Register 057h Table 45. Register 057h Field Descriptions 3 ASSERT SYSREF REG R/W 0h Set this bit to use the SPI register to assert SYSREF.

8.5.3.8 Register 058h (address = 058h), Master Page

Figure 158. Register 058h Table 46. Register 058h Field Descriptions 5 SYNCB POL R/W 0h This bit inverts the SYNCB polarity.

8.5.4 ADC Page (FFh, M = 0)

8.5.4.1 Register 03Fh (address = 03Fh), ADC Page

Figure 159. Register 03Fh Table 47. Register 03Fh Field Descriptions 2 SLOW SP EN1 R/W 0h This bit must be enabled for clock rates below 2.5 GSPS.

8.5.4.2 Register 042h (address = 042h), ADC Page

Figure 160. Register 042h Table 48. Register 042h Field Descriptions 4 SLOW SP EN2 R/W 0h This bit must be enabled for clock rates below 2.5 GSPS.

8.5.5 Digital Function Page (610000h, M = 1)

8.5.5.1 Register A6h (address = 0A6h), Digital Function Page

Figure 161. Register 0A6h Table 49. Register 0A6h Field Descriptions decimation up to 11 dB; see Table 50. Table 50. DIG GAIN Bit Settings

8.5.6 Offset Corr Page (610000h, M = 1)

8.5.6.1 Register 034h (address = 034h), Offset Corr Page

Figure 162. Register 034h Table 51. Register 034h Field Descriptions

0 SEL EXT EST R/W 0h This bit selects the external estimate for the offset correction

block; see the Using DC Coupling in the ADC31RF80 section.

8.5.6.2 Register 068h (address = 068h), Offset Corr Page

Figure 163. Register 068h Table 52. Register 068h Field Descriptions

7 FREEZE OFFSET CORR R/W 0h Use this bit and bits 5 and 1 to freeze the offset estimation

anymore, and applies the last computed value.

6 ALWAYS WRITE 1 R/W 0h Always write this bit as 1 for the offset correction block to work

2 DIS OFFSET CORR R/W 0h 0 = Offset correction block works and removes fS / 8, fS / 4,

1 ALWAYS WRITE 1 R/W 0h Always write this bit as 1 for the offset correction block to work

8.5.7 Digital Gain Page (610005h, M = 1)

8.5.7.1 Register 0A6h (address = 0A6h), Digital Gain Page

Figure 164. Register 0A6h Table 53. Register 0A6h Field Descriptions

8.5.8 Main Digital Page (680000h, M = 1)

8.5.8.1 Register 000h (address = 000h), Main Digital Page

Figure 165. Register 000h Table 54. Register 000h Field Descriptions 0 DIG CORE RESET GBL R/W 0h Pulse this bit (0 →1 →0) to reset the digital core. All Nyquist zone settings take effect when this bit is pulsed.

8.5.8.2 Register 0A2h (address = 0A2h), Main Digital Page

Figure 166. Register 0A2h Table 55. Register 0A2h Field Descriptions 3 NQ ZONE EN R/W 0h This bit allows for specification of the operating Nyquist zone. Set the NQ ZONE EN bit before programming these bits.

8.5.8.3 Register 0A5h (address = 0A5h), Main Digital Page

Figure 167. Register 0A5h Table 56. Register 0A5h Field Descriptions 7-0 Sampling Frequency R/W 0h These bits specify the ADC sampling frequency .

8.5.8.4 Register 0A9h (address = 0A9h), Main Digital Page

Figure 168. Register 0A9h Table 57. Register 0A9h Field Descriptions 3 Sampling Frequency Enable R/W 0h This bit allows for specification of operating sampling frequency.

8.5.8.5 Register 0B0h (address = 0B0h), Main Digital Page

Figure 169. Register 0B0h Table 58. Register 0B0h Field Descriptions

1 LSB = 1 MHz

the aliased frequency values.

8.5.8.6 Register 0B1h (address = 0B1h), Main Digital Page

Figure 170. Register 0B1h Table 59. Register 0B1h Field Descriptions

8.5.8.7 Register 0B2h (address = 0B2h), Main Digital Page

Figure 171. Register 0B2h Table 60. Register 0B2h Field Descriptions the aliased frequency values.

8.5.8.8 Register 0B3h (address = 0B3h), Main Digital Page

Figure 172. Register 0B3h Table 61. Register 0B3h Field Descriptions 5 Band1 Frequency Range Enable R/W 0h This bit enables the Band1 frequency range settings. are used only if this bit is set to 1.

8.5.8.9 Register 0B4h (address = 0B4h), Main Digital Page

Figure 173. Register 0B4h Table 62. Register 0B4h Field Descriptions the aliased frequency values.

8.5.8.10 Register 0B5h (address = 0B5h), Main Digital Page

Figure 174. Register 0B5h Table 63. Register 0B5h Field Descriptions

8.5.8.11 Register 0B6h (address = 0B6h), Main Digital Page

Figure 175. Register 0B6h Table 64. Register 0B6h Field Descriptions the aliased frequency values.

8.5.8.12 Register 0B7h (address = 0B7h), Main Digital Page

Figure 176. Register 0B7h Table 65. Register 0B7h Field Descriptions 5 Band2 Frequency Range Enable R/W 0h This bit enables the Band2 frequency range settings. are used only if this bit is set to 1.

8.5.8.13 Register 0B8h (address = 0B8h), Main Digital Page

Figure 177. Register 0B8h Table 66. Register 0B8h Field Descriptions the aliased frequency values.

8.5.8.14 Register 0B9h (address = 0B9h), Main Digital Page

Figure 178. Register 0B9h Table 67. Register 0B9h Field Descriptions

8.5.8.15 Register 0BAh (address = 0BAh), Main Digital Page

Figure 179. Register 0BAh Table 68. Register 0BAh Field Descriptions the aliased frequency values.

8.5.8.16 Register 0BBh (address = 0BBh), Main Digital Page

Figure 180. Register 0BBh Table 69. Register 0BBh Field Descriptions 5 Band3 Frequency Range Enable R/W 0h This bit enables the Band3 frequency range settings. are used only if this bit is set to 1.

8.5.9 JESD Digital Page (6900h, M = 1)

8.5.9.1 Register 001h (address = 001h), JESD Digital Page

Figure 181. Register 001h Table 70. Register 001h Field Descriptions

7 CTRL K R/W 0h This bit is the enable bit for the number of frames per

4 TESTMODE EN R/W 0h This bit generates a long transport layer test pattern mode

according to section 5.1.6.3 of the JESD204B specification.

0 TX LINK DIS R/W 0h This bit disables sending the initial link alignment (ILA) sequence

8.5.9.2 Register 002h (address = 002h ), JESD Digital Page

Figure 182. Register 002h Table 71. Register 002h Field Descriptions 7 SYNC REG R/W 0h This bit provides SYNC control through the SPI. 6 SYNC REG EN R/W 0h This bit is the enable bit for SYNC control through the SPI.

8.5.9.3 Register 003h (address = 003h), JESD Digital Page

Figure 183. Register 003h Table 72. Register 003h Field Descriptions

4 LINK LAY RPAT R/W 0h This bit changes the running disparity in a modified RPAT

pattern test mode (only when link layer test mode = 100).

3 LMFC MASK RESET R/W 0h 0 = Normal operation

2 JESD MODE1 R/W 1h These bits select the configuration register to configure the

1 JESD MODE2 R/W 0h These bits select the configuration register to configure the

0 RAMP 12BIT R/W 0h 12-bit RAMP test pattern.

8.5.9.4 Register 004h (address = 004h), JESD Digital Page

Figure 184. Register 004h Table 73. Register 004h Field Descriptions by 0, 1, 2, or 3 multiframes after the code group synchronization.

8.5.9.5 Register 006h (address = 006h), JESD Digital Page

Figure 185. Register 006h Table 74. Register 006h Field Descriptions 7 SCRAMBLE EN R/W 0h This bit is the scramble enable bit in the JESD204B interface.

8.5.9.6 Register 007h (address = 007h), JESD Digital Page

Figure 186. Register 007h Table 75. Register 007h Field Descriptions 4-0 FRAMES PER MULTIFRAME (K) R/W 0h These bits set the number of multiframes. Actual K is the value in hex + 1 (that is, 0Fh is K = 16).

8.5.9.7 Register 016h (address = 016h), JESD Digital Page

Figure 187. Register 016h Table 76. Register 016h Field Descriptions 6-4 40x MODE R/W 0h This register must be set for 40x mode operation.

8.5.9.8 Register 017h (address = 017h), JESD Digital Page

Figure 188. Register 017h Table 77. Register 017h Field Descriptions 3-0 Lane[3:0] POL R/W 0h These bits set the polarity of the individual JESD output lanes.

8.5.9.9 Register 032h-035h (address = 032h-035h), JESD Digital Page

Figure 189. Register 032h Figure 190. Register 033h Figure 191. Register 034h Figure 192. Register 035h Table 78. Register 032h-035h Field Descriptions settled value of the voltage in one bit period.

8.5.9.10 Register 036h (address = 036h), JESD Digital Page

Figure 193. Register 036h

0 CMOS SYNCB 0 0 0 0 0 0

Table 79. Register 036h Field Descriptions

6 CMOS SYNCB R/W 0h This bit enables single-ended control of SYNCB using the

8.5.9.11 Register 037h (address = 037h), JESD Digital Page

Figure 194. Register 037h Table 80. Register 037h Field Descriptions tables in the JESD204B Frame Assembly section for settings.

8.5.9.12 Register 03Ch (address = 03Ch), JESD Digital Page

Figure 195. Register 03Ch Table 81. Register 03Ch Field Descriptions

0 EN CMOS SYNCB R/W 0h Set this bit and the CMOS SYNCB bit high to provide a single-

Select the JESD digital page.
Write address 7036h with value 40h.
Write address 703Ch with value 01h.

8.5.9.13 Register 03Eh (address = 03Eh), JESD Digital Page

Figure 196. Register 03Eh

0 MASK CLKDIV SYSREF MASK NCO SYSREF 0 0 0 0 0

Table 82. Register 03Eh Field Descriptions

6 MASK CLKDIV SYSREF R/W 0h Use this bit to mask the SYSREF going to the input clock

5 MASK NCO SYSREF R/W 0h Use this bit to mask the SYSREF going to the NCO in the DDC

block and LMFC counter of the JESD interface.

8.5.10 Decimation Filter Page

8.5.10.1 Register 000h (address = 000h), Decimation Filter Page

Figure 197. Register 000h Table 83. Register 000h Field Descriptions 0 DDC EN R/W 0h This bit enables the decimation filter.

8.5.10.2 Register 001h (address = 001h), Decimation Filter Page

Figure 198. Register 001h Table 84. Register 001h Field Descriptions 3-0 DECIM FACTOR R/W 0h These bits configure the decimation filter setting.

8.5.10.3 Register 002h (address = 2h), Decimation Filter Page

Figure 199. Register 002h Table 85. Register 002h Field Descriptions

0 DUAL BAND EN R/W 0h This bit enables the dual-band DDC filter for the corresponding

8.5.10.4 Register 005h (address = 005h), Decimation Filter Page

Figure 200. Register 005h Table 86. Register 005h Field Descriptions

0 REAL OUT EN R/W 0h This bit converts the complex output to real output at 2x the

8.5.10.5 Register 007h (address = 007h), Decimation Filter Page

Figure 201. Register 007h Table 87. Register 007h Field Descriptions

8.5.10.6 Register 008h (address = 008h), Decimation Filter Page

Figure 202. Register 008h Table 88. Register 008h Field Descriptions

8.5.10.7 Register 009h (address = 009h), Decimation Filter Page

Figure 203. Register 009h Table 89. Register 009h Field Descriptions

8.5.10.8 Register 00Ah (address = 00Ah), Decimation Filter Page

Figure 204. Register 00Ah Table 90. Register 00Ah Field Descriptions

8.5.10.9 Register 00Bh (address = 00Bh), Decimation Filter Page

Figure 205. Register 00Bh Table 91. Register 00Bh Field Descriptions

8.5.10.10 Register 00Ch (address = 00Ch), Decimation Filter Page

Figure 206. Register 00Ch Table 92. Register 00Ch Field Descriptions

8.5.10.11 Register 00Dh (address = 00Dh), Decimation Filter Page

Figure 207. Register 00Dh Table 93. Register 00Dh Field Descriptions DDC1 (band 2, only when dual-band mode is enabled).

8.5.10.12 Register 00Eh (address = 00Eh), Decimation Filter Page

Figure 208. Register 00Eh Table 94. Register 00Eh Field Descriptions DDC1 (band 2, only when dual-band mode is enabled).

8.5.10.13 Register 00Fh (address = 00Fh), Decimation Filter Page

Figure 209. Register 00Fh Table 95. Register 00Fh Field Descriptions 0 NCO SEL PIN R/W 0h This bit enables NCO selection through the GPIO pins.

8.5.10.14 Register 010h (address = 010h), Decimation Filter Page

Figure 210. Register 010h Table 96. Register 010h Field Descriptions 1-0 NCO SEL R/W 0h These bits enable NCO selection through register setting.

8.5.10.15 Register 011h (address = 011h), Decimation Filter Page

Figure 211. Register 011h Table 97. Register 011h Field Descriptions 1-0 LMFC RESET MODE R/W 0h These bits reset the configuration for all DDCs and NCOs. reset only when analog clock dividers are resynchronized. operation. Deterministic latency is not ensured.

8.5.10.16 Register 014h (address = 014h), Decimation Filter Page

Figure 212. Register 014h Table 98. Register 014h Field Descriptions

0 DDC0 6DB GAIN R/W 0h This bit scales the output of DDC0 by 2 (6 dB) to compensate

by-4 and -6); see register 1Fh.

8.5.10.17 Register 016h (address = 016h), Decimation Filter Page

Figure 213. Register 016h Table 99. Register 016h Field Descriptions

0 DDC1 6DB GAIN R/W 0h This bit scales the output of DDC1 by 2 (6 dB) to compensate

by-4 and -6); see register 1Fh.

8.5.10.18 Register 01Eh (address = 01Eh), Decimation Filter Page

Figure 214. Register 01Eh

0 DDC DET LAT 0 0 0 0

Table 100. Register 01Eh Field Descriptions Table 101. DDC DET LAT Bit Settings

8.5.10.19 Register 01Fh (address = 01Fh), Decimation Filter Page

Figure 215. Register 01Fh Table 102. Register 01Fh Field Descriptions

0 WBF 6DB GAIN R/W 0h This bit scales the output of the wide bandwidth DDC filter by 2

8.5.10.20 Register 033h-036h (address = 033h-036h), Decimation Filter Page

Figure 216. Register 033h Figure 217. Register 034h Figure 218. Register 035h Figure 219. Register 036h Table 103. Register 033h-036h Field Descriptions

8.5.10.21 Register 037h (address = 037h), Decimation Filter Page

Figure 220. Register 037h Table 104. Register 037h Field Descriptions 7-4 TEST PATTERN DDC1 Q-DATA W 0h These bits select the test patten for the Q stream of the DDC1.

0111 Double pattern: output data alternate between custom

3-0 TEST PATTERN DDC1 I-DATA R/W 0h These bits select the test patten for the I stream of the DDC1.

8.5.10.22 Register 038h (address = 038h), Decimation Filter Page

Figure 221. Register 038h Table 105. Register 038h Field Descriptions 7-4 TEST PATTERN DDC2 Q-DATA R/W 0h These bits select the test patten for the Q stream of the DDC2. 3-0 TEST PATTERN DDC2 I -DATA R/W 0h These bits select the test patten for the I stream of the DDC2.

8.5.10.23 Register 039h (address = 039h), Decimation Filter Page

Figure 222. Register 039h Table 106. Register 039h Field Descriptions

0 USE COMMON TEST PATTERN R/W 0h 0 = Each data stream sends test patterns programmed by

8.5.10.24 Register 03Ah (address = 03Ah), Decimation Filter Page

Figure 223. Register 03Ah Table 107. Register 03Ah Field Descriptions must be enabled first (bit D0). 0 TP RES EN R/W 0h This bit enables the test pattern reset.

8.5.11 Power Detector Page

8.5.11.1 Register 000h (address = 000h), Power Detector Page

Figure 224. Register 000h Table 108. Register 000h Field Descriptions 0 PKDET EN R/W 0h This bit enables the peak power and crossing detector.

8.5.11.2 Register 001h-002h (address = 001h-002h), Power Detector Page

Figure 225. Register 001h Figure 226. Register 002h Table 109. Register 001h-002h Field Descriptions The divide-by-8 to -32 complex: length = 10 × decimation factor.

8.5.11.3 Register 003h (address = 003h), Power Detector Page

Figure 227. Register 003h Table 110. Register 003h Field Descriptions

0 BLKPKDET[16] R/W 0h This register specifies the block length in terms of number of

The divide-by-8 to -32 complex: length = 10 × decimation factor.

8.5.11.4 Register 007h-00Ah (address = 007h-00Ah), Power Detector Page

Figure 228. Register 007h Figure 229. Register 008h Figure 230. Register 009h Figure 231. Register 00Ah Table 111. Register 007h-00Ah Field Descriptions 256 is equivalent to the peak amplitude.

8.5.11.5 Register 00Bh-00Ch (address = 00Bh-00Ch), Power Detector Page

Figure 232. Register 00Bh Figure 233. Register 00Ch Table 112. Register 00Bh-00Ch Field Descriptions 7-0 DWELL R/W 0h DWELL time counter. BLKTHHH or BLKTHLH, the peak detector output flags are set.

8.5.11.6 Register 00Dh (address = 00Dh), Power Detector Page

Figure 234. Register 00Dh Table 113. Register 00Dh Field Descriptions

0 FILT0LPSEL R/W 0h This bit selects either the block detector output or 2-bit output as

the input to the IIR filter.

8.5.11.7 Register 00Eh (address = 00Eh), Power Detector Page

Figure 235. Register 00Eh Table 114. Register 00Eh Field Descriptions fS / 8 clock cycles (approximately 87 µs at 3 GSPS).

8.5.11.8 Register 00Fh, 010h-012h, and 016h-019h (address = 00Fh, 010h-012h, and 016h-019h), Power

Figure 236. Register 00Fh Figure 237. Register 010h Figure 238. Register 011h Figure 239. Register 012h Figure 240. Register 016h Figure 241. Register 017h

Figure 242. Register 018h Figure 243. Register 019h Table 115. Register 00Fh, 010h, 011h, 012h, 016h, 017h, 018h, and 019h Field Descriptions corresponds to 12.5% crossings.

8.5.11.9 Register 013h-01Ah (address = 013h-01Ah), Power Detector Page

Figure 244. Register 013h Figure 245. Register 01Ah Table 116. Register 013h and 01Ah Field Descriptions

0 IIR0 2BIT EN

8.5.11.10 Register 01Dh-01Eh (address = 01Dh-01Eh), Power Detector Page

Figure 246. Register 01Dh Figure 247. Register 01Eh Table 117. Register 01Dh-01Eh Field Descriptions bits and is specified in terms of fS / 8 clock cycles.

8.5.11.11 Register 020h (address = 020h), Power Detector Page

Figure 248. Register 020h Table 118. Register 020h Field Descriptions 0 RMSDET EN R/W 0h This bit enables the RMS power detector.

8.5.11.12 Register 021h (address = 021h), Power Detector Page

Figure 249. Register 021h Table 119. Register 021h Field Descriptions programmed as 2M, where M = 0 to 16.

8.5.11.13 Register 022h-025h (address = 022h-025h), Power Detector Page

Figure 250. Register 022h Figure 251. Register 023h Figure 252. Register 024h Figure 253. Register 025h Table 120. Register 022h-025h Field Descriptions thresholds. One LSB of the thresholds represents 1 / 216.

8.5.11.14 Register 027h (address = 027h), Power Detector Page

Figure 254. Register 027h Table 121. Register 027h Field Descriptions

0 RMS 2BIT EN R/W 0h This bit enables 2-bit output format on the RMS output

8.5.11.15 Register 02Bh (address = 02Bh), Power Detector Page

Figure 255. Register 02Bh Table 122. Register 02Bh Field Descriptions

4 RESET AGC R/W 0h After configuration, the AGC module must be reset and then

brought out of reset to start operation. Example: set 542Bh to 10h and then to 00h.

8.5.11.16 Register 032h-035h (address = 032h-035h), Power Detector Page

Figure 256. Register 032h Figure 257. Register 033h Figure 258. Register 034h Figure 259. Register 035h Table 123. Register 032h-035h Field Descriptions R/W 0h These bits set the function or signal for each GPIO pin.

8.5.11.17 Register 037h (address = 037h), Power Detector Page

Figure 260. Register 037h Table 124. Register 037h Field Descriptions 3-0 IODIRGPIO[4:1] R/W 0h These bits select the output direction for the GPIO[4:1] pins.

8.5.11.18 Register 038h (address = 038h), Power Detector Page

Figure 261. Register 038h Table 125. Register 038h Field Descriptions 5-4 INSEL1 R/W 0h These bits select which GPIO pin is used for the INSEL1 bit. the INSEL pins; see the section NCO Switching for details. 1-0 INSEL0 R/W 0h These bits select which GPIO pin is used for the INSEL0 bit. the INSEL pins; see the section NCO Switching for details. Table 126. INSEL Bit Settings

9 Application and Implementation

validate and test their design implementation to confirm system functionality.

9.1 Application Information

9.1.1 Start-Up Sequence

decimation-by-4 complex output mode. Table 127. Initialization Sequence

3 Pulse a hardware reset (low-to-high-to-low) on

4 Write the register addresses described in the

registers every time after power up.

5 Write the register addresses mentioned in the

ILConfigNyqX file, where X is the Nyquist zone. the Nyquist zone information to the device.

6.1 Wait for 50 ms for the device to estimate the

optimized by this step for channel A.

9.1.2 Hardware Reset

Figure 262 and Table 128 provide the timing information for the hardware reset. Figure 262. Hardware Reset Timing Diagram

Table 128. Hardware Reset Timing Information

9.1.3 SNR and Clock Jitter

clock jitter sets the SNR for higher input frequencies. filters at the clock input. A faster clock slew rate also improves the ADC aperture jitter. The ADC31RF80 has a thermal noise of approximately 63 dBFS and an internal aperture jitter of 90 fS. Figure 263 shows the SNR in relation to the amount of external jitter for different input frequencies. Figure 263. ADC SNR vs Input Frequency and External Clock Jitter

9.1.3.1 External Clock Phase Noise Consideration

Figure 264. Integration Bandwidth for Extracting Jitter From Clock Phase Noise contribution at a certain offset frequency. Figure 265. Small Wanted Signal in Presence of Interferer signal band of interest is too large, the wanted signal cannot not be recovered. frequency of the input signal. Equation 8 shows how the ADC sampling rate scales the clock phase noise.

9.1.4 Power Consumption in Different Modes

Table 129 and Table 130 show power consumption in different DDC modes. Table 129. Power Consumption in Different DDC Modes (Sampling Clock Frequency, fS = 2457.6 MSPS) Table 130. Power Consumption in Different DDC Modes (Sampling Clock Frequency, fS = 2949.12 MSPS)

9.1.5 Using DC Coupling in the ADC31RF80

Ensure that the correct common-mode voltage is used at the ADC analog inputs.

common-mode voltage track the required common-mode voltage of the ADC. (1) Set the INCR CM IMPEDANCE bit to increase the RCM from 0 Ω to > 5000 Ω. (2) RDC is approximately 65 Ω. Figure 266. The ADC31RF80 in a DC-Coupling Application

Ensure that the correct SPI settings are written to the ADC.

among four interleaving ADC cores. Figure 267. Offset Corrector in the ADC31RF80 present at these frequencies, the offset corrector block can be bypassed.

9.1.5.1 Bypassing the Offset Corrector Block

is frozen so that the last estimated value is held. Required register writes are provided in Table 131. Table 131. Freezing and Bypassing the Offset Corrector Block 1 — Signal source is turned off. The device detects an idle channel at its input.

9.1.5.1.1 Effect of Temperature

corrector block is frozen or disabled. Figure 268. Offset Corrector Block Frozen at Room Figure 269. Offset Corrector Block Disabled

55 D2P

9.2 Typical Application

input frequency range. Figure 270 shows a typical schematic for an ac-coupled receiver. Figure 270. Additional capacitors can be placed on the remaining power pins. Figure 270. Typical Application Implementation Diagram

9.2.1 Design Requirements

9.2.1.1 Transformer-Coupled Circuits

designing the driving circuits, the ADC input impedance (or SDD11) must be considered. switching currents of the sampling circuit. Figure 271. Input Drive Circuit

9.2.2 Detailed Design Procedure

pin, as shown in Figure 271, is recommended to damp out ringing caused by package parasitics.

9.2.3 Application Curves

Figure 272 and Figure 273 show the typical performance at 100 MHz and 1780 MHz, respectively. Figure 272. FFT for 100-MHz Input Frequency Figure 273. FFT for 1780-MHz Input Frequency

10 Power Supply Recommendations

Figure 274. Power Sequencing for the ADC31RF80 Family of Devices

11 Layout

11.1 Layout Guidelines

Analog inputs are located on opposite sides of the device pinout to ensure minimum crosstalk on the package level. To minimize crosstalk onboard, the analog inputs must exit the pinout in opposite directions, as shown in the reference layout of Figure 275 as much as possible.
In the device pinout, the sampling clock is located on a side perpendicular to the analog inputs in order to minimize coupling. This configuration is also maintained on the reference layout of Figure 275 as much as possible.
Keep digital outputs away from the analog inputs. When these digital outputs exit the pinout, the digital output traces must not be kept parallel to the analog input traces because this configuration can result in coupling from the digital outputs to the analog inputs and degrade performance. All digital output traces to the receiver [such as field-programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs)] must be matched in length to avoid skew among outputs.
At each power-supply pin (AVDD, DVDD, or AVDD19), keep a 0.1-µF decoupling capacitor close to the device. A separate decoupling capacitor group consisting of a parallel combination of 10-µF, 1-µF, and 0.1-µF capacitors can be kept close to the supply source.

11.2 Layout Example

ADC31RF80, the unused channel is not required to be connected to the board and can be left floating. Figure 275. ADC32RF80EVM Layout

12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation see the following:

ADC32RF45/RF80 EVM Quick Startup Guide
Configuration Files for the ADC32RF45

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

12.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

12.4 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

12.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.6 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 23-Aug-2017 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples ADC31RF80IRMP PREVIEW VQFN RMP 72 168 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 AZ31RF80 ADC31RF80IRMPT PREVIEW VQFN RMP 72 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 AZ31RF80 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

www.ti.com 23-Aug-2017 Addendum-Page 2

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Product Information

ADC31RF80IRMP specifications and overview.

Summary

3-GSPS Telecom Receiver and Feedback Device

Description

3-GSPS Telecom Receiver and Feedback Device

Source title ADC31RF80IRMP Datasheet(PDF) - Texas Instruments

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