ADC10158

ADC10154 NSC | Alldatasheet

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Features

n 4- or 8- channel configurable multiplexer n Analog input track/hold function n 0V to 5V analog input range with single +5V power supply n −5V to +5V analog input voltage range with±5V supplies n Fully tested in unipolar (single +5V supply) and bipolar (dual±5V supplies) operation n Programmable resolution/speed and output data format n Ratiometric or Absolute voltage reference operation n No zero or full scale adjustment required n No missing codes over temperature n Easy microprocessor interface Key Specifications n Resolution 10-bit plus sign n Integral linearity error ±1 LSB (max) n Unipolar power dissipation 33 mW (max) n Conversion time (10-bit + sign) 4.4 µs (max) n Conversion time (8-bit) 3.2 µs (max) n Sampling rate (10-bit + sign) 166 kHz n Sampling rate (8-bit) 207 kHz n Band-gap reference 2.5V ±2.0% (max) ADC10158 Simplified Block Diagram TRI-STATE® is a registered trademark of National Semiconductor Corporation. DS011225-1 November 1999 ADC10154/ADC10158 10-Bit Plus Sign 4 µs ADCs with 4- or 8-Channel MUX, Track/Hold and Reference © 1999 National Semiconductor Corporation DS011225 www.national.com

AV + This is the positive analog supply. This pin should be bypassed with a 0.1 µF ceramic ca- pacitor and a 10 µF tantalum capacitor to the system analog ground. DV + This is the positive digital supply. This supply pin also needs to be bypassed with 0.1 µF ce- ramic and 10 µF tantalum capacitors to the system digital ground. AV + and DV+ should be bypassed separately and tied to same power supply. DGND This is the digital ground. All logic levels are re- ferred to this ground. V − This is the negative analog supply. For unipolar operation this pin may be tied to the system analog ground or to a negative supply source. It should not go above DGND by more than 50 mV. When bipolar operation is required, the voltage on this pin will limit the analog input’s negative voltage level. In bipolar operation this supply pin needs to be bypassed with 0.1 µF ceramic and 10 µF tantalum capacitors to the system analog ground. V REF VREF These are the positive and negative reference inputs. The voltage difference between VREF and VREF − will set the analog input voltage span. VREF Out This is the internal band-gap voltage reference output. For proper operation of the voltage ref- erence, this pin needs to be bypassed with a 330 µF tantalum or electrolytic capacitor. CS This is the chip select input. When a logic low is applied to this pin the WR and RD pins are enabled. RD This is the read control input. When a logic low is applied to this pin the digital outputs are en- abled and the INT output is reset high. WR This is the write control input. The rising edge of the signal applied to this pin selects the mul- tiplexer channel and initiates a conversion. INT This is the interrupt output. A logic low at this output indicates the completion of a conver- sion. CLK This is the clock input. The clock frequency di- rectly controls the duration of the conversion time (for example, in the 10-bit bipolar mode t C = 22/fCLK ) and the acquisition time (tA = 6/fCLK ). DB0(MA0) –DB7 (L/R) These are the digital data inputs/outputs. DB0 is the least significant bit of the digital output word; DB7 is the most significant bit in the digi- tal output word (see the Output Data Configu- ration table). MA0 through MA4 are the digital inputs for the multiplexer channel selection (see the Multiplexer Addressing tables). U/S (Unsigned/Signed), 8/10, (8/10-bit resolution) and L/R (Left/Right justification) are the digital input bits that set the A/D’s output word format and resolution (see the Output Data Configura- tion table). The conversion time is modified by the chosen resolution (see Electrical AC Char- acteristics table). The lower the resolution, the faster the conversion will be. CH0–CH7 These are the analog input multiplexer chan- nels. They can be configured as single-ended inputs, differential input pairs, or pseudo-differential inputs (see the Multiplexer Addressing tables for the input polarity assignments). Dual-in-Line and SO Packages DS011225-2 Top View Order Number ADC10154 Dual-in-Line and SO Packages DS011225-3 Top View Order Number ADC10158 M28B or N28B ADC10154/ADC10158 www.national.com 2

Absolute Maximum Ratings(Notes 1, 3) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Positive Supply Voltage Negative Supply Voltage (V−) −6.5V Total Supply Voltage (V+ −V −) 13V Total Reference Voltage (VREF + −V REF −) 6.6V Voltage at Inputs and Outputs V − − 0.3V to V+ + 0.3V Input Current at Any Pin (Note 4) ±5m A Package Input Current (Note 4) ±20 mA Package Dissipation at TA = 25˚C (Note 5) 500 mW ESD Susceptibility (Note 6) 2000V Soldering Information N Packages (10 Sec) 260˚C J Packages (10 Sec) 300˚C Vapor Phase (60 Sec) 215˚C Infrared (15 Sec) 220˚C Storage Temperature Ceramic DIP Packages Plastic DIP and SO Packages −65˚C to +150˚C −40˚C to +150˚C Operating Ratings(Notes 2, 3) Temperature Range T MIN ≤ TA ≤ TMAX ADC10154CIWM, ADC10158CIN, ADC10158CIWM −40˚C ≤ T A ≤ +85˚C Positive Supply Voltage + = AV + = DV +) 4.5 V DC to 5.5 VDC Unipolar Negative Supply Voltage −) DGND Bipolar Negative Supply Voltage −) −4.5V to −5.5V V+ −V − 11V VREF + AV + + 0.05 VDC to V− − 0.05 VDC VREF − AV + + 0.05 VDC to V− − 0.05 VDC VREF (VREF + −V REF −) 0.5 V DC to V+

Electrical Characteristics

The following specifications apply for V+ = AV + = DV + = + 5.0 VDC ,V REF + = 5.000 VDC ,V REF − = GND, V − = GND for unipo- lar operation or V− = −5.0 VDC for bipolar operation, and fCLK = 5.0 MHz unless otherwise specified.Boldface limits apply for TA = TJ = TMIN to TMAX ;all other limits TA = TJ = 25˚C. (Notes 8, 9, 12) Symbol Parameter Conditions Typical (Note 10) CIN and CIWM Units (Limit)Suffixes Limits (Note 11) UNIPOLAR CONVERTER AND MULTIPLEXER STATIC CHARACTERISTICS Resolution 10 + Sign Bits Unipolar Integral V REF + = 2.5V ±0.5 LSB Linearity Error V REF + = 5.0V ±1 LSB (Max) Unipolar Full-Scale Error V REF + = 2.5V ±0.5 LSB VREF + = 5.0V ±1.5 LSB (Max) Unipolar Offset Error V REF + = 2.5V ±1 LSB VREF + = 5.0V ±2 LSB (Max) Unipolar Total Unadjusted V REF + = 2.5V ±1.5 LSB Error (Note 13) V REF + = 5.0V ±2.5 LSB (Max) Unipolar Power Supply V + = +5V ±10% Sensitivity V REF + = 4.5V Offset Error ±0.25 ±1 LSB (Max) Full-Scale Error ±0.25 ±1 LSB (Max) Integral Linearity Error ±0.25 LSB BIPOLAR CONVERTER AND MULTIPLEXER STATIC CHARACTERISTICS Resolution 10 + Sign Bits Bipolar Integral V REF + = 5.0V ±1 LSB (Max) Linearity Error Bipolar Full-Scale Error V REF + = 5.0V ±1.25 LSB (Max) ADC10154/ADC10158 www.national.com3

Electrical Characteristics(Continued) The following specifications apply for V+ = AV + = DV + = + 5.0 VDC ,V REF + = 5.000 VDC ,V REF − = GND, V − = GND for unipo- lar operation or V− = −5.0 VDC for bipolar operation, and fCLK = 5.0 MHz unless otherwise specified.Boldface limits apply for TA = TJ = TMIN to TMAX ;all other limits TA = TJ = 25˚C. (Notes 8, 9, 12) Symbol Parameter Conditions Typical (Note 10) CIN and CIWM Units (Limit)Suffixes Limits (Note 11) BIPOLAR CONVERTER AND MULTIPLEXER STATIC CHARACTERISTICS Bipolar Negative Full-Scale V REF + = 5.0V Error with Positive-Full ±1.25 LSB (Max) Scale Adjusted Bipolar Offset Error V REF + = 5.0V ±2.5 LSB (Max) Bipolar Total Unadjusted V REF + = 5.0V ±3 LSB (Max) Error (Note 13) Bipolar Power Supply Sensitivity Offset Error V Full-Scale Error VREF + = 4.5V ±0.5 ±1.5 LSB (Max) Integral Linearity Error ±0.25 LSB Offset Error V− = −5V ±10% ±0.25 ±0.75 LSB (Max) Full-Scale Error VREF Integral Linearity Error ±0.25 LSB UNIPOLAR AND BIPOLAR CONVERTER AND MULTIPLEXER STATIC CHARACTERISTICS Missing Codes 0 DC Common Mode V IN + = VIN Error (Note 14) = VIN where Bipolar +5.0V ≥ VIN ≥ −5.0V ±0.25 ±0.75 LSB (Max) Unipolar +5.0V ≥ VIN ≥ 0V ±0.25 ±0.5 LSB (Max) R REF Reference Input Resistance 7 4.5 kΩ (Max) 9.5 kΩ (Max) C REF Reference Input Capacitance 70 pF VAI Analog Input Voltage (V++0.05) V (Max) (V−−0.05) V (Min) C AI Analog Input Capacitance 30 pF Off Channel Leakage On Channel = 5V −400 −1000 nA (Max) Current Off Channel = 0V (Note 15) On Channel = 0V 400 1000 nA (Max) Off Channel= 5V The following specifications apply for V+ = AV + = DV + = + 5.0 VDC ,V REF + = 5.000 VDC ,V REF − = GND, V − = GND for unipolar operation or V− = −5.0 VDC for bipolar operation, and fCLK = 5.0 MHz unless otherwise specified.Boldface limits apply for TA = TJ = TMIN to TMAX ;all other limits TA = TJ = 25˚C. (Notes 8, 9, 12) Symbol Parameter Conditions Typical Limits (Note 11) Units (Limit)(Note 10) DYNAMIC CONVERTER AND MULTIPLEXER CHARACTERISTICS S/(N+D) Unipolar Signal-to-Noise+ f IN = 10 kHz, VIN = 4.85 Vp–p 60 dB Distortion Ratio f IN = 150 kHz, VIN = 4.85 Vp-p 58 dB S/(N+D) Bipolar Signal-to-Noise+ f IN = 10 kHz, VIN = ±4.85V 60 dB Distortion Ratio f IN = 150 kHz, VIN = ±4.85V 58 dB ADC10154/ADC10158 www.national.com 4

Electrical Characteristics(Continued) The following specifications apply for V+ = AV + = DV + = + 5.0 VDC ,V REF + = 5.000 VDC ,V REF − = GND, V − = GND for unipolar operation or V− = −5.0 VDC for bipolar operation, and fCLK = 5.0 MHz unless otherwise specified.Boldface limits apply for TA = TJ = TMIN to TMAX ;all other limits TA = TJ = 25˚C. (Notes 8, 9, 12) Symbol Parameter Conditions Typical Limits (Note 11) Units (Limit)(Note 10) DYNAMIC CONVERTER AND MULTIPLEXER CHARACTERISTICS −3 dB Unipolar Full V IN = 4.85 Vp–p 200 kHz Power Bandwidth −3 dB Bipolar Full V IN = ±4.85V 200 kHz Power Bandwidth REFERENCE CHARACTERISTICS (Unipolar Operation V− = GND Only) VREFOut Reference Output Voltage 2.5 ±1% 2.5± 2% V (Max) ΔVREF /Δt VREFOut Temperature Coefficient 40 ppm/˚C ΔVREF /ΔIL Load Regulation Sourcing 0 mA ≤ IL ≤ +4 mA 0.003 0.1 % /mA (Max) Sinking 0 mA ≥ IL ≥ −1 mA 0.2 0.6 % /mA (Max) Line Regulation 4.5V ≤ V+ ≤ 5.5V 0.5 6 mV (Max) ISC Short Circuit Current VREFOut = 0V 14 25 mA (Max) ΔVREF /Δt Long-Term Stability 200 ppm/1 kHr tSU Start-Up Time C L = 330 µF 20 ms DIGITAL AND DC CHARACTERISTICS V IN(1) Logical “1” Input Voltage V + = 5.5V 2.0 V (Min) VIN(0) Logical “0” Input Voltage V + = 4.5V 0.8 V (Max) IIN(1) Logical “1” Input Current V IN = 5.0V 0.005 2.5 µA (Max) IIN(0) Logical “0” Input Current V IN = 0V −0.005 −2.5 µA (Max) VOUT(1) Logical “1” Output Voltage V + = 4.5V: IOUT = −360 µA 2.4 V (Min) IOUT = −10 µA 4.25 V (Min) VOUT(0) Logical “0” Output Voltage V + = 4.5V 0.4 V (Max) IOUT = 1.6 mA IOUT TRI-STATE ® Output Current V OUT = 0V −0.01 −3 µA (Max) VOUT = 5V 0.01 3 µA (Max) +ISC Output Short Circuit Source Current VOUT = 0V −40 −10 mA (Min) −ISC Output Short Circuit V OUT = DV + 30 10 mA (Min) Sink Current DI+ Digital Supply Current CS = HIGH 0.75 2 mA (Max) CS = HIGH, fCLK = 0H z 0.15 mA (Max) AI+ Analog Supply Current CS = HIGH 3 4.5 mA (Max) CS = HIGH, fCLK = 0H z 3 mA (Max) I− Negative Supply Current CS = HIGH 3.5 4.5 mA (Max) CS = HIGH, fCLK = 0H z 3.5 mA (Max) IREF Reference Input Current V REF + = 5V 0.7 1.1 mA (Max) ADC10154/ADC10158 www.national.com5

The following specifications apply for V+ = AV + = DV + = + 5.0 VDC ,V REF + = 5.000 VDC ,V REF − = GND, V − = GND for unipolar operation or V− = −5.0 VDC for bipolar operation, and fCLK = 5.0 MHz unless otherwise specified.Boldface limits apply for TA = TJ = TMIN to TMAX ;all other limits TA = TJ = 25˚C. (Note 16) Symbol Parameter Conditions Typical Limits (Note 11) Units (Limit)(Note 10) AC CHARACTERISTICS f CLK Clock Frequency 8 5.0 MHz (Max) 10 kHz (Min) Clock Duty Cycle 20 % (Min) 80 % (Max) tC Conversion 8-Bit Unipolar Mode 16 1/fCLK Time f CLK = 5.0 MHz 3.2 µs (Max) 8-Bit Bipolar Mode 18 1/fCLK fCLK = 5.0 MHz 3.6 µs (Max) 10-Bit Unipolar Mode 20 1/fCLK fCLK = 5.0 MHz 4.0 µs (Max) 10-Bit Bipolar Mode 22 1/fCLK fCLK = 5.0 MHz 4.4 µs (Max) tA Acquisition Time 6 1/fCLK fCLK = 5.0 MHz 1.2 µs tCR Delay between Falling Edge of 0 5 ns (Min) CS and Falling Edge of RD tRC Delay betwee Rising Edge 0 5 ns (Min) RD and Rising Edge of CS tCW Delay between Falling Edge 0 5 ns (Min) of CS and Falling Edge of WR tWC Delay between Rising Edge 0 5 ns (Min) of WR and Rising Edge of CS tRW Delay between Falling Edge 0 5 ns (Min) of RD and Falling Edge of WR tW(WR) WR Pulse Width 25 50 ns (Min) tWS WR High to CLK÷2 Low Set-Up Time 5 ns (Max) tDS Data Set-Up Time 6 15 ns (Max) tDH Data Hold Time 0 5 ns (Max) tWR Delay from Rising Edge 0 5 ns (Min) of WR to Rising Edge RD tACC Access Time (Delay from Falling C L = 100 pF 25 45 ns (Max) Edge of RD to Output Data Valid) tWI,tRI Delay from Falling Edge C L = 100 pF 25 40 ns (Max) of WR or RD to Reset of INT tINTL Delay from Falling Edge of CLK÷2t o Falling Edge of INT 40 ns t1H ,t0H TRI-STATE Control (Delay from C L = 10 pF, RL = 1k Ω 20 35 ns (Max) Rising Edge of RD to Hi-Z State) tRR Delay between Successive 25 50 ns (Min) RD Pulses tP Delay between Last Rising Edge of RD and the Next Falling 20 50 ns (Min) Edge of WR C IN Capacitance of Logic Inputs 5 pF C OUT Capacitance of Logic Outputs 5 pF Note 1:Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. ADC10154/ADC10158 www.national.com 6

Electrical Characteristics(Continued) Note 2:Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may de- grade when the device is not operated under the listed test conditions. Note 3:All voltages are measured with respect to GND, unless otherwise specified. Note 4:When the input voltage (VIN) at any pin exceeds the power supplies (VIN < V− or VIN > AV + or DV+), the current at that pin should be limited to 5 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 5 mA to four. Note 5:The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax ,θJA and the ambient temperature, TA. The maximum allowable power dissipation at any temperature is PD = (TJmax −T A)/θJA or the number given in the Absolute Maximum Ratings, whichever is lower. For this device, TJmax = 150˚C. The typical thermal resistance (θJA) of these parts when board mounted follow: ADC10154 with BIN and CIN suffixes 65˚C/W, ADC10154 with BIJ, CIJ and CMJ suffixes 49˚C/W, ADC10154 with BIWM and CIWM suffixes 72˚C/W, ADC10158 with BIN and CIN suffixes 59˚C/W, ADC10158 with BIJ, CIJ, and CMJ suffixes 46˚C/W, ADC10158 with BIWM and CIWM suffixes 68˚C/W. Note 6:Human body model, 100 pF capacitor discharged through a 1.5 kΩ resistor. Note 7:See AN-450 “Surface Mounting Methods and Their Effect on Product Reliability” or the section titled “Surface Mount” found in any post-1986 National Semi- conductor Linear Data Book for other methods of soldering surface mount devices. Note 8:Two on-chip diodes are tied to each analog input as shown below. They will forward-conduct for analog input voltages one diode drop below V − supply or one diode drop greater than V+ supply. Be careful during testing at low V+ levels (4.5V), as high level analog inputs (5V) can cause an input diode to conduct, es- pecially at elevated temperatures, which will cause errors for analog inputs near full-scale. The specification allows 50 mV forward bias of either diode; this means that as long as the analog VIN does not exceed the supply voltage by more than 50 mV, the output code will be correct. Exceeding this range on an unselected chan- nel will corrupt the reading of a selected channel. This means that if AV+ and DV+ are minimum (4.5 VDC ) and V− is a maximum (−4.5 VDC ) full scale must be≤ ±4.55 VDC . Note 9:A diode exists between AV+ and DV+ as shown below. Note 10:Typicals are at TJ = TA = 25˚C and represent most likely parametric norm. Note 11:Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). Note 12: One LSB is referenced to 10 bits of resolution. Note 13:Total unadjusted error includes offset, full-scale, linearity, multiplexer, and hold step errors. Note 14:For DC Common Mode Error the only specification that is measured is offset error. Note 15:Channel leakage current is measured after the channel selection. Note 16:All the timing specifications are tested at the TTL logic levels, VIL = 0.8V for a falling edge and VIH = 2.0V for a rising. DS011225-4 DS011225-5 To guarantee accuracy, it is required that the AV+ and DV+ be connected together to a power supply with separate bypass filter at each V+ pin. ADC10154/ADC10158 www.national.com7

Typical Converter Performance Characteristics Total Positive Supply Current (DI+ +A I+) vs Temperature DS011225-27 Total Positive Power Supply Current (DI + +A I+) vs Clock Frequency DS011225-28 Offset Error vs Temperature DS011225-29 Offset Error vs Reference Voltage DS011225-30 Linearity Error vs Temperature DS011225-31 Linearity Error vs Reference Voltage DS011225-32 Linearity Error vs Clock Frequency DS011225-33 Spectral Response with 50 kHz Sine Wave DS011225-34 10-Bit Unsigned Signal-to-Noise + THD Ratio vs Input Signal Level DS011225-35 ADC10154/ADC10158 www.national.com9

Typical Reference Performance Characteristics Leakage Current Test Circuit Load Regulation DS011225-36 Line Regulation (3 Typical Parts) DS011225-37 Output Drift vs Temperature (3 Typical Parts) DS011225-38 Available Output Current vs Supply Voltage DS011225-39 DS011225-10 ADC10154/ADC10158 www.national.com 10

TRI-STATE Test Circuits and Waveforms Timing Diagrams DS011225-11 DS011225-12 DS011225-13 DS011225-14 DS011225-15 DIAGRAM 1. Starting a Conversion with New MUX Channel and Output Configuration ADC10154/ADC10158 www.national.com11

Timing Diagrams (Continued) DS011225-16 DIAGRAM 2. Starting a Conversion without Changing the MUX Channel or Output Configuration DS011225-17 DIAGRAM 3. Reading the Conversion Result ADC10154/ADC10158 www.national.com 12

TABLE 1. ADC10154 and ADC10158 Output Data Configuration

8765432 L S B Second Byte Read

32 L S B LLLLL Second Byte Read

2 L S B LLLLLL Second Byte Read

TABLE 2. ADC10158 Multiplexer Addressing

TABLE 3. ADC10154 Multiplexer Addressing

www.national.com15

1.0 Functional Description

erence is also provided on the ADC10154 and ADC10158.

1.1 DIGITAL INTERFACE

the A/D conversion resolution and the output data format. data bits zero through four (MA0–MA4). tion. DB7 selects left or right justification of the output data. be completed before a new conversion is started. FIGURE 3. Starting a Conversion without Updating the Channel Configuration, Resolution, or Data Format

1.0 Functional Description(Continued)

Digital Interface Hints:

• Reads and writes can be completely asynchronous to CLK.
• In addition to the timing indicated in Diagrams 1–3, CS can be tied low permanently or taken low for entire con- versions, eliminating all the CS guardbands (t CR ,tRC , tCW ,tWC ).
• If CS is used as shown in Diagrams 1–-3, the CS guard- bands (tCR ,tRC ,tCW ,tWC ) between CS and the RD and WR signals can safely be ignored as long as the follow- ing two conditions are met: 1) When initiating a write, CS and WR must be simulta- neously low for at least tW(WR) ns (see Diagram 1). The “start” conversion” bit will be set on the rising edge of WR or CS, whichever is first. 2) When reading data, understand that data will not be valid until tACC ns afterbothCS and RD go low. The output data will enter TRI-STATE t1H ns or t0H ns aftereitherCS or RD goes high (see Diagrams 2 and 3).

1.2 ARCHITECTURE

Before a conversion is started, during the analog input sam- pling period, the sampled data comparator is zeroed. As the comparator is being zeroed the channel assigned to be the positive input is connected to the A/D’s input capacitor. (See the Digital Interface section for a description of the assign- ment procedure.) This charges the input 32C capacitor of the DAC to the positive analog input voltage. The switches shown in the DAC portion of the detailed block diagram are set for this zeroing/acquisition period. The voltage at the in- put and output of the comparator are at equilibrium at this point in time. When the conversion is started the comparator feedback switches are opened and the 32C input capacitor is then switched to the assigned negative input voltage. When the comparator feedback switch opens a fixed amount of charge is trapped on the common plates of the capacitors. The voltage at the input of the comparator moves away from equilibrium when the 32C capacitor is switched to the as- signed negative input voltage, causing the output of the com- parator to go high (“1”) or low (“0”). The SAR next goes through an algorithm, controlled by the output state of the comparator, that redistributes the charge on the capacitor ar- ray by switching the voltage on one side of the capacitors in the array. The objective of the SAR algorithm is to return the voltage at the input of the comparator as close as possible to equilibrium. The switch position information at the completion of the suc- cessive approximation routine is a direct representation of the digital output. This information is then manipulated by the Digital Output decoder to the programmed format. The refor- matted data is then available to be strobed onto the data bus (DB0–DB7) via the digital output buffers by taking CS and RD low.

2.0 Applications Information

2.1 MULTIPLEXER CONFIGURATION

The design of these converters utilizes a sampled-data com- parator structure which allows a differential analog input to be converted by the successive approximation routine. The actual voltage converted is always the difference be- tween an assigned “+” input terminal and a “−” input terminal. The polarity of each input terminal or pair of input terminals being converted indicates which line the converter expects to be the most positive. If the assigned “+” input is less than the “−” input the converter responds with an all zeros output code when configured for unsigned operation. When config- ured for signed operation the A/D responds with the appro- priate output digital code. A unique input multiplexing scheme has been utilized to pro- vide multiple analog channels. The input channels can be software configured into three modes: differential, single-ended, or pseudo-differential. Figure 4 shows the three modes using the 4-channel MUX of the ADC10154. The eight inputs of the ADC10158 can also be configured in any of the three modes. The single-ended mode has CH0–CH3 assigned as the positive input with the negative input being the V REF − of the device. In the differential mode, the ADC10154 channel inputs are grouped in pairs, CH0 with CH1 and CH2 with CH3. The polarity assignment of each channel in the pair is interchangeable. Finally, in the pseudo-differential mode CH0–CH2 are positive inputs re- ferred to CH3 which is now a pseudo-ground. This pseudo-ground input can be set to any potential within the in- put common-mode range of the converter. The analog signal conditioning required in transducer-based data acquisition systems is significantly simplified with this type of input flex- ibility. One converter package can now handle ground-referred inputs and true differential inputs as well as signals referred to a specific voltage. The analog input voltages for each channel can range from 50 mV below V − (typically ground for unipolar operation or −5V for bipolar operation) to 50 mV above V+ = DV + = AV + (typically 5V) without degrading conversion accuracy. If the voltage on an unselected channel exceeds these limits it may corrupt the reading of the selected channel. ADC10154/ADC10158 www.national.com17

2.0 Applications Information(Continued)

2.2 REFERENCE CONSIDERATIONS

the AV+ and V−. Only the difference voltage is of importance. mum reference input resistance of 4.5 kΩ . age is proportional to the voltage used for the A/D reference. put code for a given input condition.

4 Single-Ended

2 Differential

3 Pseudo-Differential

2 Single Ended and 1 Differential

FIGURE 4. Analog Input Multiplexer Options

2.3 THE ANALOG INPUTS

any degradation in performance. is sampled before each decision in the SAR sequence. conversion time (tC = 22/fCLK for 10-bit plus sign resolution). peak value would have to be approximately 731 mV.

2.4 OPTIONAL ADJUSTMENTS

2.4.1 Zero Error

FIGURE 5. Different Reference Configurations

mV for VREF = + 5.000V and 10-bit plus sign resolution). pseudo-differential input channel configurations.

2.4.2 Full-Scale

signed operation this only adjusts the positive full scale error. trical Characteristics after a positive full-scale adjustment.

2.4.3 Adjusting for an Arbitrary Analog Input

HEX to 001HEX code transition.

2.5 INPUT SAMPLE-AND-HOLD

will not effect the A/D conversion result. Figure 6. The values shown yield an time, thereby allowing a larger external source resistance.

0 LSB would have a signal-to-noise ratio of about 68 dB,

where S/N is in dB and n is the number of bits. FIGURE 6. Analog Input Model FIGURE 7. ADC10154/ADC10158

(Continued) gain error sample/hold specs are included in the ADC10154/ ADC10158’s total unadjusted, linearity, gain and offset error specifications, while the hold settling time is included in the A/D’s maximum conversion time specification. The hold droop rate can be thought of as being zero since an unlim- ited amount of time can pass between a conversion and the reading of data. The data is lost after a new conversion has been completed. Protecting the Analog Inputs DS011225-25 Diodes are 1N914. The protection diodes should be able to withstand the output current of the op amp under current limit. Zero-Shift and Span-Adjust for Signed or Unsigned, Unipolar, Single-Ended Multiplexer Assignment, Analog Input Range of 2V≤ VIN ≤ 4.5V DS011225-26 *1% resistors ADC10154/ADC10158 www.national.com21

Physical Dimensionsinches (millimeters) unless otherwise noted Dual-In-Line Package (M) Order Number ADC10154CIWM Dual-In-Line Package (M) Order Number ADC10158CIWM ADC10154/ADC10158 www.national.com 22

Physical Dimensionsinches (millimeters) unless otherwise noted (Continued) LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: sea.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 www.national.com Dual-In-Line Package (N) Order Number ADC10158BIN or ADC10158CIN ADC10154/ADC10158 10-Bit Plus Sign 4 µs ADCs with 4- or 8-Channel MUX, Track/Hold and Reference National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.